From nobody Wed Nov 12 02:04:59 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1567511396; cv=none; d=zoho.com; s=zohoarc; b=YVZ9Ugkz+fVWkKkH9kieLdraeFaIEmzTFM8OeIti6yyeHoSfVmR3Z+cs8mbxxvEnFVUQ6CNasmTEtW+sQVK5w2aZR8TVRT9542QUWbgcz8YMgvbTtl5o51i7biWo1dhm+ze0HIwPNapoLN8mtTqfOEdo3t2hJCVk+GvlMXcvK3Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567511396; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=tCLeVpbzcwj7JOaHQloyX+K6EcgVYwv+zhudsMAKWsk=; b=oAVJlSwMxngOzP6tdktQgiMKnfTTm/hka1gwGn0801VJOqOeahqniJd53hhiga9Thqvd9nRVDtGz3kqPl+/QBCbv7mlfYoq6EBZzSGGOruYglcyNgdYvNs713F0XgmF30uDG9RAkm//HRDmjCp3I3fW5JXWeg0AKa6Sr996F0pA= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567511396049962.22174174075; Tue, 3 Sep 2019 04:49:56 -0700 (PDT) Received: from localhost ([::1]:44424 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i57Jq-00072s-91 for importer@patchew.org; Tue, 03 Sep 2019 07:49:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55110) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i57Hn-00053S-N2 for qemu-devel@nongnu.org; Tue, 03 Sep 2019 07:47:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i57Hm-0005x0-ID for qemu-devel@nongnu.org; Tue, 03 Sep 2019 07:47:47 -0400 Received: from mx1.redhat.com ([209.132.183.28]:45190) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i57Hj-0005uh-UT; Tue, 03 Sep 2019 07:47:44 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3F17830603AA; Tue, 3 Sep 2019 11:47:43 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-102.brq.redhat.com [10.40.204.102]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 038345DAAC; Tue, 3 Sep 2019 11:47:40 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 13:47:26 +0200 Message-Id: <20190903114729.3400-3-philmd@redhat.com> In-Reply-To: <20190903114729.3400-1-philmd@redhat.com> References: <20190903114729.3400-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.41]); Tue, 03 Sep 2019 11:47:43 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 2/5] target/arm: Restrict pre-ARMv7 cpus to TCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" KVM requires a cpu based on (at least) the ARMv7 architecture. The following CPUs are disabled: * ARMv4 - StrongARM (SA1100/1110) - OMAP1510 (TI925T) * ARMv5 - ARM926 - ARM946 - ARM1026 - XScale (PXA250/255/260/261/262/270) * ARMv6 - ARM1136 - ARM1176 - ARM11MPCore - Cortex-M0 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: fixed misplaced #endif (rth), list cpus --- target/arm/cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2399c14471..f69780147c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1678,6 +1678,8 @@ static ObjectClass *arm_cpu_class_by_name(const char = *cpu_model) /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 +#ifdef CONFIG_TCG + static void arm926_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -1900,6 +1902,8 @@ static void cortex_m0_initfn(Object *obj) cpu->midr =3D 0x410cc200; } =20 +#endif + static void cortex_m3_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -2283,6 +2287,8 @@ static void cortex_a15_initfn(Object *obj) define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } =20 +#ifdef CONFIG_TCG + static void ti925t_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -2451,6 +2457,8 @@ static void pxa270c5_initfn(Object *obj) cpu->reset_sctlr =3D 0x00000078; } =20 +#endif + #ifndef TARGET_AARCH64 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); * otherwise, a CPU with as many features enabled as our emulation support= s. @@ -2523,6 +2531,7 @@ struct ARMCPUInfo { =20 static const ARMCPUInfo arm_cpus[] =3D { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) +#ifdef CONFIG_TCG { .name =3D "arm926", .initfn =3D arm926_initfn }, { .name =3D "arm946", .initfn =3D arm946_initfn }, { .name =3D "arm1026", .initfn =3D arm1026_initfn }, @@ -2536,6 +2545,7 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "arm11mpcore", .initfn =3D arm11mpcore_initfn }, { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, .class_init =3D arm_v7m_class_init }, +#endif { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, @@ -2548,6 +2558,7 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, +#ifdef CONFIG_TCG { .name =3D "ti925t", .initfn =3D ti925t_initfn }, { .name =3D "sa1100", .initfn =3D sa1100_initfn }, { .name =3D "sa1110", .initfn =3D sa1110_initfn }, @@ -2564,6 +2575,7 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "pxa270-b1", .initfn =3D pxa270b1_initfn }, { .name =3D "pxa270-c0", .initfn =3D pxa270c0_initfn }, { .name =3D "pxa270-c5", .initfn =3D pxa270c5_initfn }, +#endif #ifndef TARGET_AARCH64 { .name =3D "max", .initfn =3D arm_max_initfn }, #endif --=20 2.20.1