From nobody Wed Nov 12 02:07:54 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1567348122; cv=none; d=zoho.com; s=zohoarc; b=KZrmoHlxkW2Kas8rysL8itEUrOf4irPj/fyRMmna3q6GZdaefGOFEvrOO1QOfslGgVmsm/W2oq073rYaa+6hjkBTaPsCTXE1UtG/HAy9hZ38x3XB/5QrOAtA/zCyuesGZZLj2TWY/T5Bcv+jXbpnmMDr2fiV2LCZbUJSPhuW8gs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567348122; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=k/gXDuBhQJyim/gjlUOVIdOtwMWRyEeEWlzfyf7HRMk=; b=ckoSRTZmvFhUOeR7I3AqMjmYVsfVW9XZJpDZnbiWCBaskTJXpbCICsvXc2U0BptFZTWi/psvT5u6FGWPHWV8XKn13yyaExvymVIL1O463SqVzYuu5h27shx7JXXSPwQyVK+qFKrV5fOaoxszX2qoCXmk64F5s7pIJGNIO5QSwhk= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567348122549149.81752435905787; Sun, 1 Sep 2019 07:28:42 -0700 (PDT) Received: from localhost ([::1]:57782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i4QqP-0002iZ-CY for importer@patchew.org; Sun, 01 Sep 2019 10:28:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39580) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i4Qjk-0004mg-9o for qemu-devel@nongnu.org; Sun, 01 Sep 2019 10:21:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i4Qjh-0004uE-Rz for qemu-devel@nongnu.org; Sun, 01 Sep 2019 10:21:47 -0400 Received: from mga12.intel.com ([192.55.52.136]:16719) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i4Qjh-0004jJ-Ax for qemu-devel@nongnu.org; Sun, 01 Sep 2019 10:21:45 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Sep 2019 07:21:45 -0700 Received: from tao-optiplex-7060.sh.intel.com ([10.239.159.36]) by fmsmga002.fm.intel.com with ESMTP; 01 Sep 2019 07:21:43 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,455,1559545200"; d="scan'208";a="211453142" From: Tao Xu To: imammedo@redhat.com, eblake@redhat.com, ehabkost@redhat.com Date: Sun, 1 Sep 2019 22:21:18 +0800 Message-Id: <20190901142119.20482-11-tao3.xu@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190901142119.20482-1-tao3.xu@intel.com> References: <20190901142119.20482-1-tao3.xu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.136 Subject: [Qemu-devel] [PATCH v10 10/11] numa: Extend CLI to provide memory side cache information X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jingqi.liu@intel.com, tao3.xu@intel.com, fan.du@intel.com, qemu-devel@nongnu.org, daniel@linux.ibm.com, jonathan.cameron@huawei.com, dan.j.williams@intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Liu Jingqi Add -numa hmat-cache option to provide Memory Side Cache Information. These memory attributes help to build Memory Side Cache Information Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT). Reviewed-by: Daniel Black Signed-off-by: Liu Jingqi Signed-off-by: Tao Xu --- No changes in v10. --- hw/core/numa.c | 67 +++++++++++++++++++++++++++++++++++ include/sysemu/numa.h | 2 ++ qapi/machine.json | 81 +++++++++++++++++++++++++++++++++++++++++-- qemu-options.hx | 16 +++++++-- 4 files changed, 162 insertions(+), 4 deletions(-) diff --git a/hw/core/numa.c b/hw/core/numa.c index 7387547793..6e4f6169cb 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -333,6 +333,67 @@ void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOp= tions *node, } } =20 +void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node, + Error **errp) +{ + int nb_numa_nodes =3D ms->numa_state->num_nodes; + HMAT_Cache_Info *hmat_cache =3D NULL; + + if (node->node_id >=3D nb_numa_nodes) { + error_setg(errp, "Invalid node-id=3D%" PRIu32 + ", it should be less than %d.", + node->node_id, nb_numa_nodes); + return; + } + + if (node->total > MAX_HMAT_CACHE_LEVEL) { + error_setg(errp, "Invalid total=3D%" PRIu8 + ", it should be less than or equal to %d.", + node->total, MAX_HMAT_CACHE_LEVEL); + return; + } + if (node->level > node->total) { + error_setg(errp, "Invalid level=3D%" PRIu8 + ", it should be less than or equal to" + " total=3D%" PRIu8 ".", + node->level, node->total); + return; + } + if (ms->numa_state->hmat_cache[node->node_id][node->level]) { + error_setg(errp, "Duplicate configuration of the side cache for " + "node-id=3D%" PRIu32 " and level=3D%" PRIu8 ".", + node->node_id, node->level); + return; + } + + if ((node->level > 1) && + ms->numa_state->hmat_cache[node->node_id][node->level - 1] && + (node->size >=3D + ms->numa_state->hmat_cache[node->node_id][node->level - 1]->si= ze)) { + error_setg(errp, "Invalid size=3D0x%" PRIx64 + ", the size of level=3D%" PRIu8 + " should be less than the size(0x%" PRIx64 + ") of level=3D%" PRIu8 ".", + node->size, node->level, + ms->numa_state->hmat_cache[node->node_id] + [node->level - 1]->size, + node->level - 1); + return; + } + + hmat_cache =3D g_malloc0(sizeof(*hmat_cache)); + + hmat_cache->mem_proximity =3D node->node_id; + hmat_cache->size =3D node->size; + hmat_cache->total_levels =3D node->total; + hmat_cache->level =3D node->level; + hmat_cache->associativity =3D node->assoc; + hmat_cache->write_policy =3D node->policy; + hmat_cache->line_size =3D node->line; + + ms->numa_state->hmat_cache[node->node_id][node->level] =3D hmat_cache; +} + void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp) { Error *err =3D NULL; @@ -377,6 +438,12 @@ void set_numa_options(MachineState *ms, NumaOptions *o= bject, Error **errp) goto end; } break; + case NUMA_OPTIONS_TYPE_HMAT_CACHE: + parse_numa_hmat_cache(ms, &object->u.hmat_cache, &err); + if (err) { + goto end; + } + break; default: abort(); } diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h index c18e939395..700d7c0392 100644 --- a/include/sysemu/numa.h +++ b/include/sysemu/numa.h @@ -77,6 +77,8 @@ void set_numa_options(MachineState *ms, NumaOptions *obje= ct, Error **errp); void parse_numa_opts(MachineState *ms); void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node, Error **errp); +void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node, + Error **errp); void numa_complete_configuration(MachineState *ms); void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms); extern QemuOptsList qemu_numa_opts; diff --git a/qapi/machine.json b/qapi/machine.json index b6019335e8..088be81920 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -428,10 +428,12 @@ # # @hmat-lb: memory latency and bandwidth information (Since: 4.2) # +# @hmat-cache: memory side cache information (Since: 4.2) +# # Since: 2.1 ## { 'enum': 'NumaOptionsType', - 'data': [ 'node', 'dist', 'cpu', 'hmat-lb' ] } + 'data': [ 'node', 'dist', 'cpu', 'hmat-lb', 'hmat-cache' ] } =20 ## # @NumaOptions: @@ -447,7 +449,8 @@ 'node': 'NumaNodeOptions', 'dist': 'NumaDistOptions', 'cpu': 'NumaCpuOptions', - 'hmat-lb': 'NumaHmatLBOptions' }} + 'hmat-lb': 'NumaHmatLBOptions', + 'hmat-cache': 'NumaHmatCacheOptions' }} =20 ## # @NumaNodeOptions: @@ -648,6 +651,80 @@ '*latency': 'time', '*bandwidth': 'size' }} =20 +## +# @HmatCacheAssociativity: +# +# Cache associativity in the Memory Side Cache +# Information Structure of HMAT +# +# For more information of @HmatCacheAssociativity see +# the chapter 5.2.27.5: Table 5-143 of ACPI 6.3 spec. +# +# @none: None +# +# @direct: Direct Mapped +# +# @complex: Complex Cache Indexing (implementation specific) +# +# Since: 4.2 +## +{ 'enum': 'HmatCacheAssociativity', + 'data': [ 'none', 'direct', 'complex' ] } + +## +# @HmatCacheWritePolicy: +# +# Cache write policy in the Memory Side Cache +# Information Structure of HMAT +# +# For more information of @HmatCacheWritePolicy see +# the chapter 5.2.27.5: Table 5-143: Field "Cache Attributes" of ACPI 6.3 = spec. +# +# @none: None +# +# @write-back: Write Back (WB) +# +# @write-through: Write Through (WT) +# +# Since: 4.2 +## +{ 'enum': 'HmatCacheWritePolicy', + 'data': [ 'none', 'write-back', 'write-through' ] } + +## +# @NumaHmatCacheOptions: +# +# Set the memory side cache information for a given memory domain. +# +# For more information of @NumaHmatCacheOptions see +# the chapter 5.2.27.5: Table 5-143: Field "Cache Attributes" of ACPI 6.3 = spec. +# +# @node-id: the memory proximity domain to which the memory belongs. +# +# @size: the size of memory side cache in bytes. +# +# @total: the total cache levels for this memory proximity domain. +# +# @level: the cache level described in this structure. +# +# @assoc: the cache associativity, none/direct-mapped/complex(complex cach= e indexing). +# +# @policy: the write policy, none/write-back/write-through. +# +# @line: the cache Line size in bytes. +# +# Since: 4.2 +## +{ 'struct': 'NumaHmatCacheOptions', + 'data': { + 'node-id': 'uint32', + 'size': 'size', + 'total': 'uint8', + 'level': 'uint8', + 'assoc': 'HmatCacheAssociativity', + 'policy': 'HmatCacheWritePolicy', + 'line': 'uint16' }} + ## # @HostMemPolicy: # diff --git a/qemu-options.hx b/qemu-options.hx index 252495c288..f30cf27559 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -169,7 +169,8 @@ DEF("numa", HAS_ARG, QEMU_OPTION_numa, "-numa node[,memdev=3Did][,cpus=3Dfirstcpu[-lastcpu]][,nodeid=3Dnode][= ,initiator=3Dnode]\n" "-numa dist,src=3Dsource,dst=3Ddestination,val=3Ddistance\n" "-numa cpu,node-id=3Dnode[,socket-id=3Dx][,core-id=3Dy][,thread-id=3Dz= ]\n" - "-numa hmat-lb,initiator=3Dnode,target=3Dnode,hierarchy=3Dmemory|first= -level|second-level|third-level,data-type=3Daccess-latency|read-latency|wri= te-latency[,latency=3Dlat][,bandwidth=3Dbw]\n", + "-numa hmat-lb,initiator=3Dnode,target=3Dnode,hierarchy=3Dmemory|first= -level|second-level|third-level,data-type=3Daccess-latency|read-latency|wri= te-latency[,latency=3Dlat][,bandwidth=3Dbw]\n" + "-numa hmat-cache,node-id=3Dnode,size=3Dsize,total=3Dtotal,level=3Dlev= el[,assoc=3Dnone|direct|complex][,policy=3Dnone|write-back|write-through][,= line=3Dsize]\n", QEMU_ARCH_ALL) STEXI @item -numa node[,mem=3D@var{size}][,cpus=3D@var{firstcpu}[-@var{lastcpu}]= ][,nodeid=3D@var{node}][,initiator=3D@var{initiator}] @@ -177,6 +178,7 @@ STEXI @itemx -numa dist,src=3D@var{source},dst=3D@var{destination},val=3D@var{di= stance} @itemx -numa cpu,node-id=3D@var{node}[,socket-id=3D@var{x}][,core-id=3D@va= r{y}][,thread-id=3D@var{z}] @itemx -numa hmat-lb,initiator=3D@var{node},target=3D@var{node},hierarchy= =3D@var{str},data-type=3D@var{str}[,latency=3D@var{lat}][,bandwidth=3D@var{= bw}] +@itemx -numa hmat-cache,node-id=3D@var{node},size=3D@var{size},total=3D@va= r{total},level=3D@var{level}[,assoc=3D@var{str}][,policy=3D@var{str}][,line= =3D@var{size}] @findex -numa Define a NUMA node and assign RAM and VCPUs to it. Set the NUMA distance from a source node to a destination node. @@ -282,11 +284,19 @@ if NUM is 0, means the corresponding latency or bandw= idth information is not pro And if input numbers without any unit, the latency unit will be 'ps' and t= he bandwidth will be MB/s. =20 +In @samp{hmat-cache} option, @var{node-id} is the NUMA-id of the memory be= longs. +@var{size} is the size of memory side cache in bytes. @var{total} is the t= otal cache levels. +@var{level} is the cache level described in this structure. @var{assoc} is= the cache associativity, +the possible value is 'none/direct(direct-mapped)/complex(complex cache in= dexing)'. +@var{policy} is the write policy. @var{line} is the cache Line size in byt= es. + For example, the following option assigns NUMA node 0 and 1. Node 0 has 2 = cpus and a ram, node 1 has only a ram. The processors in node 0 access memory in no= de 0 with access-latency 5 nanoseconds, access-bandwidth is 200 MB/s; The processors in NUMA node 0 access memory in NUMA node 1 with access-lat= ency 10 nanoseconds, access-bandwidth is 100 MB/s. +And for memory side cache information, NUMA node 0 and 1 both have 1 level= memory +cache, size is 0x20000 bytes, policy is write-back, the cache Line size is= 8 bytes: @example -machine hmat=3Don \ -m 2G \ @@ -300,7 +310,9 @@ nanoseconds, access-bandwidth is 100 MB/s. -numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmemory,data-type=3Dacce= ss-latency,latency=3D5ns \ -numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D200M \ -numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmemory,data-type=3Dacce= ss-latency,latency=3D10ns \ --numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D100M +-numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D100M \ +-numa hmat-cache,node-id=3D0,size=3D0x20000,total=3D1,level=3D1,assoc=3Ddi= rect,policy=3Dwrite-back,line=3D8 \ +-numa hmat-cache,node-id=3D1,size=3D0x20000,total=3D1,level=3D1,assoc=3Ddi= rect,policy=3Dwrite-back,line=3D8 @end example =20 ETEXI --=20 2.20.1