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X-Received-From: 192.55.52.136 Subject: [Qemu-devel] [PATCH v10 09/11] numa: Extend CLI to provide memory latency and bandwidth information X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jingqi.liu@intel.com, tao3.xu@intel.com, fan.du@intel.com, qemu-devel@nongnu.org, daniel@linux.ibm.com, jonathan.cameron@huawei.com, dan.j.williams@intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Liu Jingqi Add -numa hmat-lb option to provide System Locality Latency and Bandwidth Information. These memory attributes help to build System Locality Latency and Bandwidth Information Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT). Signed-off-by: Liu Jingqi Signed-off-by: Tao Xu --- Changes in v10: - use new builtin type 'time' as qapi input. --- hw/core/numa.c | 164 ++++++++++++++++++++++++++++++++++++++++++ include/sysemu/numa.h | 2 + qapi/machine.json | 95 +++++++++++++++++++++++- qemu-options.hx | 49 ++++++++++++- 4 files changed, 307 insertions(+), 3 deletions(-) diff --git a/hw/core/numa.c b/hw/core/numa.c index 1e75c26e49..7387547793 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -42,6 +42,7 @@ #include "qemu/option.h" #include "qemu/config-file.h" #include "qemu/cutils.h" +#include "hw/acpi/hmat.h" =20 QemuOptsList qemu_numa_opts =3D { .name =3D "numa", @@ -186,6 +187,152 @@ void parse_numa_distance(MachineState *ms, NumaDistOp= tions *dist, Error **errp) ms->numa_state->have_numa_distance =3D true; } =20 +static uint64_t hmat_get_base(uint64_t lb_data, int unit) +{ + uint64_t base =3D 1; + + while (lb_data >=3D UINT16_MAX && QEMU_IS_ALIGNED(lb_data, unit)) { + lb_data /=3D unit; + base *=3D unit; + } + + if (lb_data < UINT16_MAX) { + return base; + } else { + return 0; + } +} + +void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node, + Error **errp) +{ + int nb_numa_nodes =3D ms->numa_state->num_nodes; + NodeInfo *numa_info =3D ms->numa_state->nodes; + HMAT_LB_Info *hmat_lb =3D NULL; + uint64_t base_lat =3D 0, base_bw =3D 0, bw_mb; + + if (node->data_type <=3D HMATLB_DATA_TYPE_WRITE_LATENCY) { + if (!node->has_latency) { + error_setg(errp, "Missing 'latency' option."); + return; + } + if (node->has_bandwidth) { + error_setg(errp, "Invalid option 'bandwidth' since " + "the data type is latency."); + return; + } + } + + if (node->data_type >=3D HMATLB_DATA_TYPE_ACCESS_BANDWIDTH) { + if (!node->has_bandwidth) { + error_setg(errp, "Missing 'bandwidth' option."); + return; + } + if (node->has_latency) { + error_setg(errp, "Invalid option 'latency' since " + "the data type is bandwidth."); + return; + } + } + + if (node->initiator >=3D nb_numa_nodes) { + error_setg(errp, "Invalid initiator=3D%" + PRIu16 ", it should be less than %d.", + node->initiator, nb_numa_nodes); + return; + } + if (!numa_info[node->initiator].has_cpu) { + error_setg(errp, "Invalid initiator=3D%" + PRIu16 ", it isn't an initiator proximity domain.", + node->initiator); + return; + } + + if (node->target >=3D nb_numa_nodes) { + error_setg(errp, "Invalid target=3D%" + PRIu16 ", it should be less than %d.", + node->target, nb_numa_nodes); + return; + } + if (!numa_info[node->target].present) { + error_setg(errp, "Invalid target=3D%" + PRIu16 ", it hasn't a valid NUMA node.", + node->target); + return; + } + + if (node->has_latency) { + hmat_lb =3D ms->numa_state->hmat_lb[node->hierarchy][node->data_ty= pe]; + + if (!hmat_lb) { + hmat_lb =3D g_malloc0(sizeof(*hmat_lb)); + ms->numa_state->hmat_lb[node->hierarchy][node->data_type] =3D = hmat_lb; + } else if (hmat_lb->latency[node->initiator][node->target]) { + error_setg(errp, "Duplicate configuration of the latency for " + "initiator=3D%" PRIu16 " and target=3D%" PRIu16 ".", + node->initiator, node->target); + return; + } + + base_lat =3D hmat_get_base(node->latency, 1000); + if (base_lat =3D=3D 0) { + error_setg(errp, "Latency value %" PRIu64 " overflow, max valu= e" + " is %" PRIu16, node->latency, UINT16_MAX - 1); + return; + } + + /* Only the first time of setting the base unit is valid. */ + if (hmat_lb->base_lat =3D=3D 0) { + hmat_lb->base_lat =3D base_lat; + } else if (hmat_lb->base_lat !=3D base_lat) { + error_setg(errp, "Invalid base latency unit %" PRIu64 ", all " + "latencies must be specified in the same units.", base_lat); + return; + } + + hmat_lb->latency[node->initiator][node->target] =3D + node->latency / base_lat; + } + + if (node->has_bandwidth) { + hmat_lb =3D ms->numa_state->hmat_lb[node->hierarchy][node->data_ty= pe]; + bw_mb =3D node->bandwidth / 1024 / 1024; + + if (!hmat_lb) { + hmat_lb =3D g_malloc0(sizeof(*hmat_lb)); + ms->numa_state->hmat_lb[node->hierarchy][node->data_type] =3D = hmat_lb; + } else if (hmat_lb->bandwidth[node->initiator][node->target]) { + error_setg(errp, "Duplicate configuration of the bandwidth for= " + "initiator=3D%" PRIu16 " and target=3D%" PRIu16 ".", + node->initiator, node->target); + return; + } + + base_bw =3D hmat_get_base(bw_mb, 1024); + if (base_bw =3D=3D 0) { + error_setg(errp, "Bandwidth value %" PRIu64 " overflow, max va= lue" + " is %" PRIu16, bw_mb, UINT16_MAX - 1); + return; + } + + /* Only the first time of setting the base unit is valid. */ + if (hmat_lb->base_bw =3D=3D 0) { + hmat_lb->base_bw =3D base_bw; + } else if (hmat_lb->base_bw !=3D base_bw) { + error_setg(errp, "Invalid base bandwidth unit %" PRIu64 ", all= " + "bandwidths must be specified in the same units.", base_bw); + return; + } + + hmat_lb->bandwidth[node->initiator][node->target] =3D bw_mb; + } + + if (hmat_lb) { + hmat_lb->hierarchy =3D node->hierarchy; + hmat_lb->data_type =3D node->data_type; + } +} + void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp) { Error *err =3D NULL; @@ -224,6 +371,12 @@ void set_numa_options(MachineState *ms, NumaOptions *o= bject, Error **errp) machine_set_cpu_numa_node(ms, qapi_NumaCpuOptions_base(&object->u.= cpu), &err); break; + case NUMA_OPTIONS_TYPE_HMAT_LB: + parse_numa_hmat_lb(ms, &object->u.hmat_lb, &err); + if (err) { + goto end; + } + break; default: abort(); } @@ -251,6 +404,17 @@ static int parse_numa(void *opaque, QemuOpts *opts, Er= ror **errp) qemu_strtosz_MiB(mem_str, NULL, &object->u.node.mem); } =20 + if (object->type =3D=3D NUMA_OPTIONS_TYPE_HMAT_LB) { + if (object->u.hmat_lb.has_latency) { + const char *lat_str =3D qemu_opt_get(opts, "latency"); + qemu_strtotime_ps(lat_str, NULL, &object->u.hmat_lb.latency); + } + if (object->u.hmat_lb.has_bandwidth) { + const char *bw_str =3D qemu_opt_get(opts, "bandwidth"); + qemu_strtosz_MiB(bw_str, NULL, &object->u.hmat_lb.bandwidth); + } + } + set_numa_options(ms, object, &err); =20 end: diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h index dc48d39439..c18e939395 100644 --- a/include/sysemu/numa.h +++ b/include/sysemu/numa.h @@ -75,6 +75,8 @@ typedef struct NumaState NumaState; =20 void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp); void parse_numa_opts(MachineState *ms); +void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node, + Error **errp); void numa_complete_configuration(MachineState *ms); void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms); extern QemuOptsList qemu_numa_opts; diff --git a/qapi/machine.json b/qapi/machine.json index 3c2914cd1c..b6019335e8 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -426,10 +426,12 @@ # # @cpu: property based CPU(s) to node mapping (Since: 2.10) # +# @hmat-lb: memory latency and bandwidth information (Since: 4.2) +# # Since: 2.1 ## { 'enum': 'NumaOptionsType', - 'data': [ 'node', 'dist', 'cpu' ] } + 'data': [ 'node', 'dist', 'cpu', 'hmat-lb' ] } =20 ## # @NumaOptions: @@ -444,7 +446,8 @@ 'data': { 'node': 'NumaNodeOptions', 'dist': 'NumaDistOptions', - 'cpu': 'NumaCpuOptions' }} + 'cpu': 'NumaCpuOptions', + 'hmat-lb': 'NumaHmatLBOptions' }} =20 ## # @NumaNodeOptions: @@ -557,6 +560,94 @@ 'base': 'CpuInstanceProperties', 'data' : {} } =20 +## +# @HmatLBMemoryHierarchy: +# +# The memory hierarchy in the System Locality Latency +# and Bandwidth Information Structure of HMAT (Heterogeneous +# Memory Attribute Table) +# +# For more information of @HmatLBMemoryHierarchy see +# the chapter 5.2.27.4: Table 5-142: Field "Flags" of ACPI 6.3 spec. +# +# @memory: the structure represents the memory performance +# +# @first-level: first level memory of memory side cached memory +# +# @second-level: second level memory of memory side cached memory +# +# @third-level: third level memory of memory side cached memory +# +# Since: 4.2 +## +{ 'enum': 'HmatLBMemoryHierarchy', + 'data': [ 'memory', 'first-level', 'second-level', 'third-level' ] } + +## +# @HmatLBDataType: +# +# Data type in the System Locality Latency +# and Bandwidth Information Structure of HMAT (Heterogeneous +# Memory Attribute Table) +# +# For more information of @HmatLBDataType see +# the chapter 5.2.27.4: Table 5-142: Field "Data Type" of ACPI 6.3 spec. +# +# @access-latency: access latency (nanoseconds) +# +# @read-latency: read latency (nanoseconds) +# +# @write-latency: write latency (nanoseconds) +# +# @access-bandwidth: access bandwidth (MB/s) +# +# @read-bandwidth: read bandwidth (MB/s) +# +# @write-bandwidth: write bandwidth (MB/s) +# +# Since: 4.2 +## +{ 'enum': 'HmatLBDataType', + 'data': [ 'access-latency', 'read-latency', 'write-latency', + 'access-bandwidth', 'read-bandwidth', 'write-bandwidth' ] } + +## +# @NumaHmatLBOptions: +# +# Set the system locality latency and bandwidth information +# between Initiator and Target proximity Domains. +# +# For more information of @NumaHmatLBOptions see +# the chapter 5.2.27.4: Table 5-142 of ACPI 6.3 spec. +# +# @initiator: the Initiator Proximity Domain. +# +# @target: the Target Proximity Domain. +# +# @hierarchy: the Memory Hierarchy. Indicates the performance +# of memory or side cache. +# +# @data-type: presents the type of data, access/read/write +# latency or hit latency. +# +# @latency: the value of latency from @initiator to @target proximity doma= in, +# the latency units are "ps(picosecond)", "ns(nanosecond)" or +# "us(microsecond)". +# +# @bandwidth: the value of bandwidth between @initiator and @target proxim= ity +# domain, the bandwidth units are "MB(/s)","GB(/s)" or "TB(/s)= ". +# +# Since: 4.2 +## +{ 'struct': 'NumaHmatLBOptions', + 'data': { + 'initiator': 'uint16', + 'target': 'uint16', + 'hierarchy': 'HmatLBMemoryHierarchy', + 'data-type': 'HmatLBDataType', + '*latency': 'time', + '*bandwidth': 'size' }} + ## # @HostMemPolicy: # diff --git a/qemu-options.hx b/qemu-options.hx index 9f568c58d1..252495c288 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -168,16 +168,19 @@ DEF("numa", HAS_ARG, QEMU_OPTION_numa, "-numa node[,mem=3Dsize][,cpus=3Dfirstcpu[-lastcpu]][,nodeid=3Dnode][,= initiator=3Dnode]\n" "-numa node[,memdev=3Did][,cpus=3Dfirstcpu[-lastcpu]][,nodeid=3Dnode][= ,initiator=3Dnode]\n" "-numa dist,src=3Dsource,dst=3Ddestination,val=3Ddistance\n" - "-numa cpu,node-id=3Dnode[,socket-id=3Dx][,core-id=3Dy][,thread-id=3Dz= ]\n", + "-numa cpu,node-id=3Dnode[,socket-id=3Dx][,core-id=3Dy][,thread-id=3Dz= ]\n" + "-numa hmat-lb,initiator=3Dnode,target=3Dnode,hierarchy=3Dmemory|first= -level|second-level|third-level,data-type=3Daccess-latency|read-latency|wri= te-latency[,latency=3Dlat][,bandwidth=3Dbw]\n", QEMU_ARCH_ALL) STEXI @item -numa node[,mem=3D@var{size}][,cpus=3D@var{firstcpu}[-@var{lastcpu}]= ][,nodeid=3D@var{node}][,initiator=3D@var{initiator}] @itemx -numa node[,memdev=3D@var{id}][,cpus=3D@var{firstcpu}[-@var{lastcpu= }]][,nodeid=3D@var{node}][,initiator=3D@var{initiator}] @itemx -numa dist,src=3D@var{source},dst=3D@var{destination},val=3D@var{di= stance} @itemx -numa cpu,node-id=3D@var{node}[,socket-id=3D@var{x}][,core-id=3D@va= r{y}][,thread-id=3D@var{z}] +@itemx -numa hmat-lb,initiator=3D@var{node},target=3D@var{node},hierarchy= =3D@var{str},data-type=3D@var{str}[,latency=3D@var{lat}][,bandwidth=3D@var{= bw}] @findex -numa Define a NUMA node and assign RAM and VCPUs to it. Set the NUMA distance from a source node to a destination node. +Set the ACPI Heterogeneous Memory Attributes for the given nodes. =20 Legacy VCPU assignment uses @samp{cpus} option where @var{firstcpu} and @var{lastcpu} are CPU indexes. Each @@ -256,6 +259,50 @@ specified resources, it just assigns existing resource= s to NUMA nodes. This means that one still has to use the @option{-m}, @option{-smp} options to allocate RAM and VCPUs respectively. =20 +Use @samp{hmat-lb} to set System Locality Latency and Bandwidth Information +between initiator and target NUMA nodes in ACPI Heterogeneous Attribute Me= mory Table (HMAT). +Initiator NUMA node can create memory requests, usually including one or m= ore processors. +Target NUMA node contains addressable memory. + +In @samp{hmat-lb} option, @var{node} are NUMA node IDs. @var{str} of 'hier= archy' +is the memory hierarchy of the target NUMA node: if @var{str} is 'memory',= the structure +represents the memory performance; if @var{str} is 'first-level|second-lev= el|third-level', +this structure represents aggregated performance of memory side caches for= each domain. +@var{str} of 'data-type' is type of data represented by this structure ins= tance: +if 'hierarchy' is 'memory', 'data-type' is 'access|read|write' latency(nan= oseconds) +or 'access|read|write' bandwidth(MB/s) of the target memory; if 'hierarchy= ' is +'first-level|second-level|third-level', 'data-type' is 'access|read|write'= hit latency +or 'access|read|write' hit bandwidth of the target memory side cache. + +@var{lat} of 'latency' is latency value, the possible value and units are +NUM[ps|ns|us] (picosecond|nanosecond|microsecond), the recommended unit is= 'ns'. @var{bw} +is bandwidth value, the possible value and units are NUM[M|G|T], mean that +the bandwidth value are NUM MB/s, GB/s or TB/s. Note that max NUM is 65534, +if NUM is 0, means the corresponding latency or bandwidth information is n= ot provided. +And if input numbers without any unit, the latency unit will be 'ps' and t= he bandwidth +will be MB/s. + +For example, the following option assigns NUMA node 0 and 1. Node 0 has 2 = cpus and +a ram, node 1 has only a ram. The processors in node 0 access memory in no= de +0 with access-latency 5 nanoseconds, access-bandwidth is 200 MB/s; +The processors in NUMA node 0 access memory in NUMA node 1 with access-lat= ency 10 +nanoseconds, access-bandwidth is 100 MB/s. +@example +-machine hmat=3Don \ +-m 2G \ +-object memory-backend-ram,size=3D1G,id=3Dm0 \ +-object memory-backend-ram,size=3D1G,id=3Dm1 \ +-smp 2 \ +-numa node,nodeid=3D0,memdev=3Dm0 \ +-numa node,nodeid=3D1,memdev=3Dm1,initiator=3D0 \ +-numa cpu,node-id=3D0,socket-id=3D0 \ +-numa cpu,node-id=3D0,socket-id=3D1 \ +-numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmemory,data-type=3Dacce= ss-latency,latency=3D5ns \ +-numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D200M \ +-numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmemory,data-type=3Dacce= ss-latency,latency=3D10ns \ +-numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D100M +@end example + ETEXI =20 DEF("add-fd", HAS_ARG, QEMU_OPTION_add_fd, --=20 2.20.1