From nobody Sun May 5 19:40:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1567160085; cv=none; d=zoho.com; s=zohoarc; b=XLoyk93DYP+Xr4hfOJu2vyTBjeTs3LcijpSKm6WNiDY3KRkPSM66iBdel8b8KFwGE0e6BTWbEOmkAJfZlr8t6f6DMwNTMCewPn9Q+D8dvXatLeEXfckrAnAUVdIY+mr2VGatX7xqmrToqjiWH1fhfVrZQlZFf5O5FVmrysnXPRw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567160085; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=pj3C/q/k1F8DApESyi57w+CilFFlF1B9lCExETgH9Mw=; b=UqNHTF3mdKIT/tmdnPfYzpTfWGkhRzOqpF/zLq/rYQlxOWTfihN6pNtd9yCml36YdwyeALndqRhJNo9dx8hYC9K3rM4wwIlrZdMx0kT99nLlcTecB2kDs80YBHmszYiydvhmc5PuUqVcC95BzNvGgDqQPM27W0lIhgej4FNG87g= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567160085108921.9258388684927; Fri, 30 Aug 2019 03:14:45 -0700 (PDT) Received: from localhost ([::1]:57700 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i3dvV-0000WG-2Z for importer@patchew.org; Fri, 30 Aug 2019 06:14:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58070) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i3drB-0006fS-Qc for qemu-devel@nongnu.org; Fri, 30 Aug 2019 06:10:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i3drA-0005ea-D7 for qemu-devel@nongnu.org; Fri, 30 Aug 2019 06:10:13 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44872) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i3drA-0005bM-32; Fri, 30 Aug 2019 06:10:12 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 46D6F308FBB4; Fri, 30 Aug 2019 10:10:11 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-243.ams2.redhat.com [10.36.117.243]) by smtp.corp.redhat.com (Postfix) with ESMTP id 13901600F8; Fri, 30 Aug 2019 10:10:07 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Fri, 30 Aug 2019 12:09:58 +0200 Message-Id: <20190830100959.26615-2-david@redhat.com> In-Reply-To: <20190830100959.26615-1-david@redhat.com> References: <20190830100959.26615-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.43]); Fri, 30 Aug 2019 10:10:11 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 1/2] tcg: Make probe_write() return a pointer to the host page X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Riku Voipio , David Hildenbrand , Cornelia Huck , qemu-s390x@nongnu.org, Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" ... similar to tlb_vaddr_to_host(); however, allow access to the host page except when TLB_NOTDIRTY or TLB_MMIO is set. Signed-off-by: David Hildenbrand Reviewed-by: Richard Henderson --- accel/tcg/cputlb.c | 21 ++++++++++++++++----- accel/tcg/user-exec.c | 6 ++++-- include/exec/exec-all.h | 4 ++-- 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 707adf7631..cb969d8372 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1078,11 +1078,11 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env= , target_ulong addr) /* Probe for whether the specified guest write access is permitted. * If it is not permitted then an exception will be taken in the same * way as if this were a real write access (and we will not return). - * Otherwise the function will return, and there will be a valid - * entry in the TLB for this access. + * If the size is 0 or the page requires I/O access, returns NULL; otherwi= se, + * returns the address of the host page similar to tlb_vaddr_to_host(). */ -void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_i= dx, - uintptr_t retaddr) +void *probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_= idx, + uintptr_t retaddr) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); @@ -1101,12 +1101,23 @@ void probe_write(CPUArchState *env, target_ulong ad= dr, int size, int mmu_idx, tlb_addr =3D tlb_addr_write(entry); } =20 + if (!size) { + return NULL; + } + /* Handle watchpoints. */ - if ((tlb_addr & TLB_WATCHPOINT) && size > 0) { + if (tlb_addr & TLB_WATCHPOINT) { cpu_check_watchpoint(env_cpu(env), addr, size, env_tlb(env)->d[mmu_idx].iotlb[index].attrs, BP_MEM_WRITE, retaddr); } + + if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO)) { + /* I/O access */ + return NULL; + } + + return (void *)((uintptr_t)addr + entry->addend); } =20 void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 625c33f893..5720bf8056 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -188,8 +188,8 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, g_assert_not_reached(); } =20 -void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_i= dx, - uintptr_t retaddr) +void *probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_= idx, + uintptr_t retaddr) { g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); =20 @@ -202,6 +202,8 @@ void probe_write(CPUArchState *env, target_ulong addr, = int size, int mmu_idx, retaddr); g_assert_not_reached(); } + + return size ? g2h(addr) : NULL; } =20 #if defined(__i386__) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index cbcc85add3..a7893ed16b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -310,8 +310,8 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(= CPUState *cpu, { } #endif -void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_i= dx, - uintptr_t retaddr); +void *probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_= idx, + uintptr_t retaddr); =20 #define CODE_GEN_ALIGN 16 /* must be >=3D of the size of a icach= e line */ =20 --=20 2.21.0 From nobody Sun May 5 19:40:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1567159989; cv=none; d=zoho.com; s=zohoarc; b=msaFsSNXrlkH8aQVjVUr4bxbrlMt+T14TZM3yl1Ps9XsgF4fkH4II3fsJ66zt274akzrOmtbKKirg2Bk+CkiSHavV6C9+79p0cGfIZO5kiPZtPf7y/c3AubwfLFhh2TAN65fVDRrrVvKNkfmNOqov/frmVJjVe/ZKGL+fC+5DHc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567159989; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=9ehkWl42cmTVy7ICQ5xGuZsntXOuJRQbmWbjAU1rdiE=; b=CBbNUM5iLz4a7LUi+0XIL8LF8pyyDd5qSOPVOg+U2RTLP1T9l+5/HE3Vtz8CFuJR9VNIhso90DMluS+TCA+pkoDhPTrwkruiiQ42eEFSPBasTXa/kLfEoR/q88Vm/ggz1L4iRidop+dWwGybR3lBbC3ova6SF23h/0aqTCK5QfM= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567159989162479.16412984363353; Fri, 30 Aug 2019 03:13:09 -0700 (PDT) Received: from localhost ([::1]:57694 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i3dtv-0007wW-4O for importer@patchew.org; Fri, 30 Aug 2019 06:13:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58540) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i3drG-0006h9-Mj for qemu-devel@nongnu.org; Fri, 30 Aug 2019 06:10:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i3drC-0005o9-SQ for qemu-devel@nongnu.org; Fri, 30 Aug 2019 06:10:17 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39960) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i3drC-0005k7-Ga; Fri, 30 Aug 2019 06:10:14 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6D276693E7; Fri, 30 Aug 2019 10:10:13 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-243.ams2.redhat.com [10.36.117.243]) by smtp.corp.redhat.com (Postfix) with ESMTP id A2DF4600F8; Fri, 30 Aug 2019 10:10:11 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Fri, 30 Aug 2019 12:09:59 +0200 Message-Id: <20190830100959.26615-3-david@redhat.com> In-Reply-To: <20190830100959.26615-1-david@redhat.com> References: <20190830100959.26615-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Fri, 30 Aug 2019 10:10:13 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 2/2] tcg: Factor out probe_write() logic into probe_access() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Riku Voipio , David Hildenbrand , Cornelia Huck , qemu-s390x@nongnu.org, Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Let's also allow to probe other access types. Signed-off-by: David Hildenbrand Reviewed-by: Richard Henderson --- accel/tcg/cputlb.c | 43 ++++++++++++++++++++++++++++++----------- accel/tcg/user-exec.c | 26 +++++++++++++++++++------ include/exec/exec-all.h | 9 +++++++-- 3 files changed, 59 insertions(+), 19 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index cb969d8372..abae79650c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1075,30 +1075,51 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env= , target_ulong addr) return qemu_ram_addr_from_host_nofail(p); } =20 -/* Probe for whether the specified guest write access is permitted. - * If it is not permitted then an exception will be taken in the same - * way as if this were a real write access (and we will not return). +/* + * Probe for whether the specified guest access is permitted. If it is not + * permitted then an exception will be taken in the same way as if this + * were a real access (and we will not return). * If the size is 0 or the page requires I/O access, returns NULL; otherwi= se, * returns the address of the host page similar to tlb_vaddr_to_host(). */ -void *probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_= idx, - uintptr_t retaddr) +void *probe_access(CPUArchState *env, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retad= dr) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D tlb_addr_write(entry); + target_ulong tlb_addr; + size_t elt_ofs; + int wp_access; =20 g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); =20 + switch (access_type) { + case MMU_DATA_LOAD: + elt_ofs =3D offsetof(CPUTLBEntry, addr_read); + wp_access =3D BP_MEM_READ; + break; + case MMU_DATA_STORE: + elt_ofs =3D offsetof(CPUTLBEntry, addr_write); + wp_access =3D BP_MEM_WRITE; + break; + case MMU_INST_FETCH: + elt_ofs =3D offsetof(CPUTLBEntry, addr_code); + wp_access =3D BP_MEM_READ; + break; + default: + g_assert_not_reached(); + } + tlb_addr =3D tlb_read_ofs(entry, elt_ofs); + if (unlikely(!tlb_hit(tlb_addr, addr))) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, - mmu_idx, retaddr); + if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, + addr & TARGET_PAGE_MASK)) { + tlb_fill(env_cpu(env), addr, size, access_type, mmu_idx, retad= dr); /* TLB resize via tlb_fill may have moved the entry. */ index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); } - tlb_addr =3D tlb_addr_write(entry); + tlb_addr =3D tlb_read_ofs(entry, elt_ofs); } =20 if (!size) { @@ -1109,7 +1130,7 @@ void *probe_write(CPUArchState *env, target_ulong add= r, int size, int mmu_idx, if (tlb_addr & TLB_WATCHPOINT) { cpu_check_watchpoint(env_cpu(env), addr, size, env_tlb(env)->d[mmu_idx].iotlb[index].attrs, - BP_MEM_WRITE, retaddr); + wp_access, retaddr); } =20 if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO)) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5720bf8056..71c4bf6477 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -188,17 +188,31 @@ static inline int handle_cpu_signal(uintptr_t pc, sig= info_t *info, g_assert_not_reached(); } =20 -void *probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_= idx, - uintptr_t retaddr) +void *probe_access(CPUArchState *env, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retad= dr) { + int flags; + g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); =20 - if (!guest_addr_valid(addr) || - page_check_range(addr, size, PAGE_WRITE) < 0) { + switch (access_type) { + case MMU_DATA_STORE: + flags =3D PAGE_WRITE; + break; + case MMU_DATA_LOAD: + flags =3D PAGE_READ; + break; + case MMU_INST_FETCH: + flags =3D PAGE_EXEC; + break; + default: + g_assert_not_reached(); + } + + if (!guest_addr_valid(addr) || page_check_range(addr, size, flags) < 0= ) { CPUState *cpu =3D env_cpu(env); CPUClass *cc =3D CPU_GET_CLASS(cpu); - - cc->tlb_fill(cpu, addr, size, MMU_DATA_STORE, MMU_USER_IDX, false, + cc->tlb_fill(cpu, addr, size, access_type, MMU_USER_IDX, false, retaddr); g_assert_not_reached(); } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a7893ed16b..3eaf39cd0d 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -310,8 +310,13 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced= (CPUState *cpu, { } #endif -void *probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_= idx, - uintptr_t retaddr); +void *probe_access(CPUArchState *env, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retad= dr); +static inline void *probe_write(CPUArchState *env, target_ulong addr, int = size, + int mmu_idx, uintptr_t retaddr) +{ + return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); +} =20 #define CODE_GEN_ALIGN 16 /* must be >=3D of the size of a icach= e line */ =20 --=20 2.21.0