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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id s5sm485197pfm.97.2019.08.28.16.16.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 16:16:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tDJarBQckpHfmmZQqSzy2ha1vD1pFwdD3YsUtk0RotI=; b=D0VYwNye3al5GsUig7yHFzdRrwlPr/RYP7Wa3kgkSvxJq4NbC0cwOtBQOgRIvYJn7M oNzT7HCtyEoCIX2JATPuONq9G2SRy5Q3SoH2et2++HU336Heg139AreD9x5hhRzmP0O5 Tau+9xYiPhFhzws4P7PpvHMuFf35Lw4dixeSTTlR3Fp4jBFvpRuFENVpWcjvurbdNpOs pkffJsJpuv0tAFQ7ag3beAubHExhEX/kcczlB9PXI+pklvDZLKUQBwcG06A5yt/ewbAh zxBqZli8bZOUNWBSmjyxMghsuayTDbNMneiCTNcmkPUCFSVip67nB3UwLtqk5HfBKx/1 Thrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tDJarBQckpHfmmZQqSzy2ha1vD1pFwdD3YsUtk0RotI=; b=rP5deIwUkTgyI40gIEbZxy7doU4Nkz9hWAjNvMb5H7TTy+ZLzSYYqa89DHxSL40WO5 gGzwJl1ejWp1tKUwFw0MoxTx12PZPg1sFZSW+uLLCrN6qGUV9h/ixEVjIPVEkY4Kj0km Ittg8X2Il4L9Efqfu5smxnLFHqkOA43oJNFIGnIA1fLfSIgYWq0hGnJVvZkgr94VnwYG j+Toi3UnClLXdcSdhHd/iHwXMf6PN48hTfr0of7KQ6GdNxRLbylSZynXmWcNbKt8UF25 IEh8I9pjyFodfZuc6cQ/Ixq9J4uObeK5WiR6r7kosRip4b56z+bzP7xQDI9OslJsKe4a 7sQg== X-Gm-Message-State: APjAAAU6/zWf4fdstuG8BDuf3ykzn6OogufZ3iUuCsYDuRjk98Qq7tG+ Mt+5y1KF9fC43Y5KpmdpherXR5+A5Xc= X-Google-Smtp-Source: APXvYqyjPBW5QKcYAte+6fH6xVT0pSkbiENVKWqqMC/3taH4DQYDP5cwkVSsn/Nbohy2cT4qJcXonA== X-Received: by 2002:a65:5584:: with SMTP id j4mr5571598pgs.258.1567034214749; Wed, 28 Aug 2019 16:16:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 16:16:44 -0700 Message-Id: <20190828231651.17176-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828231651.17176-1-richard.henderson@linaro.org> References: <20190828231651.17176-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v2 1/8] exec: Move user-only watchpoint stubs inline X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Let the user-only watchpoint stubs resolve to empty inline functions. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 23 +++++++++++++++++++++++ exec.c | 26 ++------------------------ 2 files changed, 25 insertions(+), 24 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 77fca95a40..6de688059d 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1070,12 +1070,35 @@ static inline bool cpu_breakpoint_test(CPUState *cp= u, vaddr pc, int mask) return false; } =20 +#ifdef CONFIG_USER_ONLY +static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr l= en, + int flags, CPUWatchpoint **watchpo= int) +{ + return -ENOSYS; +} + +static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, + vaddr len, int flags) +{ + return -ENOSYS; +} + +static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, + CPUWatchpoint *wp) +{ +} + +static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) +{ +} +#else int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint); int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, int flags); void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint= ); void cpu_watchpoint_remove_all(CPUState *cpu, int mask); +#endif =20 /** * cpu_get_address_space: diff --git a/exec.c b/exec.c index 53a15b7ad7..31fb75901f 100644 --- a/exec.c +++ b/exec.c @@ -1062,28 +1062,7 @@ static void breakpoint_invalidate(CPUState *cpu, tar= get_ulong pc) } #endif =20 -#if defined(CONFIG_USER_ONLY) -void cpu_watchpoint_remove_all(CPUState *cpu, int mask) - -{ -} - -int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, - int flags) -{ - return -ENOSYS; -} - -void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) -{ -} - -int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, - int flags, CPUWatchpoint **watchpoint) -{ - return -ENOSYS; -} -#else +#ifndef CONFIG_USER_ONLY /* Add a watchpoint. */ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint) @@ -1173,8 +1152,7 @@ static inline bool cpu_watchpoint_address_matches(CPU= Watchpoint *wp, =20 return !(addr > wpend || wp->vaddr > addrend); } - -#endif +#endif /* !CONFIG_USER_ONLY */ =20 /* Add a breakpoint. */ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, --=20 2.17.1 From nobody Thu May 2 09:08:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567034548; cv=none; d=zoho.com; s=zohoarc; b=Wmtd7OSUYi1aPca93foYfV/DdIW12ojUfKTKTADydWx58JffUUnKvvgP4ZCRr5pcV7Vc30pQbzzS5meTPDdIJPAzTswFEj6wMPpWcJD62GalpXlq+G5Z17yr5lAvnlG8+ey7yDKwMa85EO6mT9sizzUrY7qwJRd+TXYp1uuphG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id s5sm485197pfm.97.2019.08.28.16.16.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 16:16:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4hy82QgJUYjjhSQJRivLUVd+yZYge9fg7c759/kiQtk=; b=dQ37Wgc8rakuIoinrc1m85v7oqC0osu9PpzDSxwCvCY5LVQtoorbpZj7A6PH5RiD5w 5GsQh13h2vUOJnqOilezQDN3OEsUcZ9RrV3vaJdp3sZgT+Ys4kwUMdVOwZNjUC4YnjAe 4xA2nj9QeSMn/vZa2BrY9RCzKj6RlQeIc9JGzcJRyhf+LBP18yIMjuSb8qyE+tLOwZPD HHLkZvGJwRz9mvz6+uyaaRzqC90mszevwPX833awajP2dreNNu2HkXFkN4b+kvJsjZYB AS4ZTDRFMYG8m6qiJNOFRSdJ22IzPFZDxhkxFmLETYFJtlCQa8wJXl3cT6n0enQZHoHI jAkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4hy82QgJUYjjhSQJRivLUVd+yZYge9fg7c759/kiQtk=; b=IzmU942fxQ742fbDtw0h7j0A9R0+nq/WQlt7ilpEIVK7ICZkNNAoB5xvWLysdKAnpo s1sKiuid56DMWNZlaH5DvwNg7kkZAT3YgX7dK1F45rxzX/Z1PBOk9DMTk5mElilAisf7 KJ5+DXIJ+KhWW02+q5Qb9TSllCZ1bxfMazHocynIn0csVIxW3Z906De16R1hlxdqYF7k RZIh9KtVxVYAfmmY77rP0V7DJIfMvZVR3pI6Som3JCqarhvR1YdGSrBVIQdVjPpce05O Lw3A68uhKohhfSPPtM9as8QTZ4y3QZvLbWNWO8xKafOdPFT6yWfbMYPOk83SICqLBxZ0 YwtQ== X-Gm-Message-State: APjAAAVPoF76itLyAShS76Y6Eq4n+3/JjsFK/vQmlIKIQGyQYfJ+Yf0L oL39aEnv6wD/ZZBHQr5OcV40Xfv/oZY= X-Google-Smtp-Source: APXvYqwsvd9qTfx5TujV9q45b5OyArLmTBlncdYLaPAWIA2gddqykEydic/5SMfLLjaJjkyt1Nl1Eg== X-Received: by 2002:a17:902:da8:: with SMTP id 37mr6679884plv.69.1567034216021; Wed, 28 Aug 2019 16:16:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 16:16:45 -0700 Message-Id: <20190828231651.17176-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828231651.17176-1-richard.henderson@linaro.org> References: <20190828231651.17176-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62b Subject: [Qemu-devel] [PATCH v2 2/8] exec: Factor out core logic of check_watchpoint() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: David Hildenbrand We want to perform the same checks in probe_write() to trigger a cpu exit before doing any modifications. We'll have to pass a PC. Signed-off-by: David Hildenbrand Reviewed-by: Richard Henderson Message-Id: <20190823100741.9621-9-david@redhat.com> [rth: Use vaddr for len, like other watchpoint functions; Move user-only stub to static inline.] Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 7 +++++++ exec.c | 26 ++++++++++++++++++-------- 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6de688059d..7bd8bed5b2 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1091,6 +1091,11 @@ static inline void cpu_watchpoint_remove_by_ref(CPUS= tate *cpu, static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) { } + +static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr l= en, + MemTxAttrs atr, int fl, uintptr_t = ra) +{ +} #else int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint); @@ -1098,6 +1103,8 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, int flags); void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint= ); void cpu_watchpoint_remove_all(CPUState *cpu, int mask); +void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, + MemTxAttrs attrs, int flags, uintptr_t ra); #endif =20 /** diff --git a/exec.c b/exec.c index 31fb75901f..cb6f5763dc 100644 --- a/exec.c +++ b/exec.c @@ -2789,11 +2789,10 @@ static const MemoryRegionOps notdirty_mem_ops =3D { }; =20 /* Generate a debug exception if a watchpoint has been hit. */ -static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int fl= ags) +void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, + MemTxAttrs attrs, int flags, uintptr_t ra) { - CPUState *cpu =3D current_cpu; CPUClass *cc =3D CPU_GET_CLASS(cpu); - target_ulong vaddr; CPUWatchpoint *wp; =20 assert(tcg_enabled()); @@ -2804,17 +2803,17 @@ static void check_watchpoint(int offset, int len, M= emTxAttrs attrs, int flags) cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); return; } - vaddr =3D (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; - vaddr =3D cc->adjust_watchpoint_address(cpu, vaddr, len); + + addr =3D cc->adjust_watchpoint_address(cpu, addr, len); QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - if (cpu_watchpoint_address_matches(wp, vaddr, len) + if (cpu_watchpoint_address_matches(wp, addr, len) && (wp->flags & flags)) { if (flags =3D=3D BP_MEM_READ) { wp->flags |=3D BP_WATCHPOINT_HIT_READ; } else { wp->flags |=3D BP_WATCHPOINT_HIT_WRITE; } - wp->hitaddr =3D vaddr; + wp->hitaddr =3D MAX(addr, wp->vaddr); wp->hitattrs =3D attrs; if (!cpu->watchpoint_hit) { if (wp->flags & BP_CPU && @@ -2829,11 +2828,14 @@ static void check_watchpoint(int offset, int len, M= emTxAttrs attrs, int flags) if (wp->flags & BP_STOP_BEFORE_ACCESS) { cpu->exception_index =3D EXCP_DEBUG; mmap_unlock(); - cpu_loop_exit(cpu); + cpu_loop_exit_restore(cpu, ra); } else { /* Force execution of one insn next time. */ cpu->cflags_next_tb =3D 1 | curr_cflags(); mmap_unlock(); + if (ra) { + cpu_restore_state(cpu, ra, true); + } cpu_loop_exit_noexc(cpu); } } @@ -2843,6 +2845,14 @@ static void check_watchpoint(int offset, int len, Me= mTxAttrs attrs, int flags) } } =20 +static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int fl= ags) +{ + CPUState *cpu =3D current_cpu; + vaddr addr =3D (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; + + cpu_check_watchpoint(cpu, addr, len, attrs, flags, 0); +} + /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, so these check for a hit then pass through to the normal out-of-line phys routines. */ --=20 2.17.1 From nobody Thu May 2 09:08:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567034372; cv=none; d=zoho.com; s=zohoarc; b=K3zQYXvX44fASDtBkRDxmUxOOxeHiM+4QCGeuWSMFUHdcz8HPm7FW72JZrVQsBiwDuvQ3wMxeO4OxfJXKJKNY9v5PSUaNw/VTeDqxDKZLdJv6X8nG8frKgVsRdZaMPm/2BZMWo2Yjb3HP1hfBRATrbwomGZkjYaDYw0SczN7ENU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567034372; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=w8riBbsouW08D/+bMCAznTOfjfqW9MSyfbe4Ou/2wHU=; b=YCGbu6Ce1rlEsupNQ9XlWNNAacfpG4HHPw5vCGXgs/HuYKRZ5OVz4sO+WZblpTq/xpOnr4GVHm3bXraExGjQnvvD1tWbkkgrgX8wkqPlFhJhJNLgfZLo7tudWfV5XuNWSMpWsR/jf2il9m6/DRXwE6WXHFcYsY0ATVMbufXu0cs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567034372555888.3473540246356; Wed, 28 Aug 2019 16:19:32 -0700 (PDT) Received: from localhost ([::1]:43614 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i37Dv-00068f-7D for importer@patchew.org; Wed, 28 Aug 2019 19:19:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52313) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i37BV-0004Dd-8X for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:17:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i37BS-0008G6-Mv for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:17:01 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:36658) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i37BS-0008Fr-FQ for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:16:58 -0400 Received: by mail-pg1-x544.google.com with SMTP id l21so522193pgm.3 for ; Wed, 28 Aug 2019 16:16:58 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id s5sm485197pfm.97.2019.08.28.16.16.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 16:16:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=w8riBbsouW08D/+bMCAznTOfjfqW9MSyfbe4Ou/2wHU=; b=lcNI02nXJ3YpMEpimCjFROSnAmILHNwYjYfUBwy9ERVOuW2psHmTPwgOIF4mQrDw0O juwNnwHAN4PqCBYHBKSoSYtoM0YmHgG+U9YAQ02y5eMAoJk9+Le2/sexdVRy6vDiJoli rqwKLbbGTv1U2FCkiTV+oDbCtillXANhnB16Jx7EiKkfBeIwQ6KPgYf52Tk3Z5NOIv8D WnmhxTNu580jNwoBMeMbZ5yjjtyjaYZTmckB6d2WacQJG800ux4pLiHOoHrf7ITLL3wC zblX9/BzjusjKdWYora+7XF/O5lv/FHm/mC8eUO6BE++bEhDkm5m7yp8LXjllXKxc3+P boqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=w8riBbsouW08D/+bMCAznTOfjfqW9MSyfbe4Ou/2wHU=; b=TmD1nrI/HlBabdDs2gYD2qZZD9eKWssIhdONiqvvjGqR1eFsCMGdlGThEfcqVLM1Jk 8hd30x5rfan/4O/T2HbqiK3jRgccjQuqCriIF8pIn/0kS+VwsqZpi5jvJZEjRq/WNibX 8O8M/IbpII17+afIQqtY9bhoynWSdmemzPNIlhY5aH95PhZ/FixLsaG6b9dOv9hmFxP+ KaRHLpam0UvfVo/tbuRenFJeGW01xVlQ4cY+8liuUPJF336z1x/I00ueM73KFT2BfqFS oub+oM2/RREvPbWw/VaI/ewjZ4nbuQBc6bmg9pngQZbfucgMyCIvu0VaDQPzdpRm96QG ANxg== X-Gm-Message-State: APjAAAVgB+0pPhpdcbqh0lMaH3do85zJUgDV85b860RHtOqbLyce3KFb pEBzCe9z3mT179LMcobFIaZL2Gqyo+8= X-Google-Smtp-Source: APXvYqw9cbwyCL0mCc0HTACpYn6DVQybYO3CeQPWZ+5gQft5pWzgT/D3yXVmDINKg1lEBczfe17ULg== X-Received: by 2002:a63:ee0c:: with SMTP id e12mr5764544pgi.184.1567034217080; Wed, 28 Aug 2019 16:16:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 16:16:46 -0700 Message-Id: <20190828231651.17176-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828231651.17176-1-richard.henderson@linaro.org> References: <20190828231651.17176-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v2 3/8] cputlb: Fold TLB_RECHECK into TLB_INVALID_MASK X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We had two different mechanisms to force a recheck of the tlb. Before TLB_RECHECK was introduced, we had a PAGE_WRITE_INV bit that would immediate set TLB_INVALID_MASK, which automatically means that a second check of the tlb entry fails. We can use the same mechanism to handle small pages. Conserve TLB_* bits by removing TLB_RECHECK. Cc: peter.maydell@linaro.org Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 5 +-- accel/tcg/cputlb.c | 86 +++++++++++------------------------------- 2 files changed, 24 insertions(+), 67 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 8323094648..8d07ae23a5 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -329,14 +329,11 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS - 2)) /* Set if TLB entry is an IO callback. */ #define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) -/* Set if TLB entry must have MMU lookup repeated for every access */ -#define TLB_RECHECK (1 << (TARGET_PAGE_BITS - 4)) =20 /* Use this mask to check interception with an alignment mask * in a TCG backend. */ -#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_RECHECK) +#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO) =20 /** * tlb_hit_page: return true if page aligned @addr is a hit against the diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d9787cc893..c9576bebcf 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -732,11 +732,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulo= ng vaddr, =20 address =3D vaddr_page; if (size < TARGET_PAGE_SIZE) { - /* - * Slow-path the TLB entries; we will repeat the MMU check and TLB - * fill on every access. - */ - address |=3D TLB_RECHECK; + /* Repeat the MMU check and TLB fill on every access. */ + address |=3D TLB_INVALID_MASK; } if (attrs.byte_swap) { /* Force the access through the I/O slow path. */ @@ -1026,10 +1023,15 @@ static bool victim_tlb_hit(CPUArchState *env, size_= t mmu_idx, size_t index, victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \ (ADDR) & TARGET_PAGE_MASK) =20 -/* NOTE: this function can trigger an exception */ -/* NOTE2: the returned address is not exactly the physical address: it - * is actually a ram_addr_t (in system mode; the user mode emulation - * version of this function returns a guest virtual address). +/* + * Return a ram_addr_t for the virtual address for execution. + * + * Return -1 if we can't translate and execute from an entire page + * of RAM. This will force us to execute by loading and translating + * one insn at a time, without caching. + * + * NOTE: This function will trigger an exception if the page is + * not executable. */ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) { @@ -1043,19 +1045,20 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env= , target_ulong addr) tlb_fill(env_cpu(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0); index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); + + if (unlikely(entry->addr_code & TLB_INVALID_MASK)) { + /* + * The MMU protection covers a smaller range than a target + * page, so we must redo the MMU check for every insn. + */ + return -1; + } } assert(tlb_hit(entry->addr_code, addr)); } =20 - if (unlikely(entry->addr_code & (TLB_RECHECK | TLB_MMIO))) { - /* - * Return -1 if we can't translate and execute from an entire - * page of RAM here, which will cause us to execute by loading - * and translating one insn at a time, without caching: - * - TLB_RECHECK: means the MMU protection covers a smaller range - * than a target page, so we must redo the MMU check every insn - * - TLB_MMIO: region is not backed by RAM - */ + if (unlikely(entry->addr_code & TLB_MMIO)) { + /* The region is not backed by RAM. */ return -1; } =20 @@ -1180,7 +1183,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, } =20 /* Notice an IO access or a needs-MMU-lookup access */ - if (unlikely(tlb_addr & (TLB_MMIO | TLB_RECHECK))) { + if (unlikely(tlb_addr & TLB_MMIO)) { /* There's really nothing that can be done to support this apart from stop-the-world. */ goto stop_the_world; @@ -1258,6 +1261,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, entry =3D tlb_entry(env, mmu_idx, addr); } tlb_addr =3D code_read ? entry->addr_code : entry->addr_read; + tlb_addr &=3D ~TLB_INVALID_MASK; } =20 /* Handle an IO access. */ @@ -1265,27 +1269,6 @@ load_helper(CPUArchState *env, target_ulong addr, TC= GMemOpIdx oi, if ((addr & (size - 1)) !=3D 0) { goto do_unaligned_access; } - - if (tlb_addr & TLB_RECHECK) { - /* - * This is a TLB_RECHECK access, where the MMU protection - * covers a smaller range than a target page, and we must - * repeat the MMU check here. This tlb_fill() call might - * longjump out if this access should cause a guest exception. - */ - tlb_fill(env_cpu(env), addr, size, - access_type, mmu_idx, retaddr); - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); - - tlb_addr =3D code_read ? entry->addr_code : entry->addr_read; - tlb_addr &=3D ~TLB_RECHECK; - if (!(tlb_addr & ~TARGET_PAGE_MASK)) { - /* RAM access */ - goto do_aligned_access; - } - } - return io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, addr, retaddr, access_type, op); } @@ -1314,7 +1297,6 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, return res & MAKE_64BIT_MASK(0, size * 8); } =20 - do_aligned_access: haddr =3D (void *)((uintptr_t)addr + entry->addend); switch (op) { case MO_UB: @@ -1509,27 +1491,6 @@ store_helper(CPUArchState *env, target_ulong addr, u= int64_t val, if ((addr & (size - 1)) !=3D 0) { goto do_unaligned_access; } - - if (tlb_addr & TLB_RECHECK) { - /* - * This is a TLB_RECHECK access, where the MMU protection - * covers a smaller range than a target page, and we must - * repeat the MMU check here. This tlb_fill() call might - * longjump out if this access should cause a guest exception. - */ - tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, - mmu_idx, retaddr); - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); - - tlb_addr =3D tlb_addr_write(entry); - tlb_addr &=3D ~TLB_RECHECK; - if (!(tlb_addr & ~TARGET_PAGE_MASK)) { - /* RAM access */ - goto do_aligned_access; - } - } - io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, val, addr, retaddr, op); return; @@ -1579,7 +1540,6 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, return; } =20 - do_aligned_access: haddr =3D (void *)((uintptr_t)addr + entry->addend); switch (op) { case MO_UB: --=20 2.17.1 From nobody Thu May 2 09:08:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567034372; cv=none; d=zoho.com; s=zohoarc; b=nSSZ+6//PxiGKCXQyzZ4pD+ipOMMjZ5vIFW0lOi/Id1soSsvA54Co2d/4TIJAayMR2CqCz/lUU8Vktat9+Pc/97F2lPTuR41qDHlJEOasjuwbERcVVCE4vD23FpJTG5ldZTJRfrXHGtirKquh8IotvSHbwkRkeKKP9gTFiYwZVE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567034372; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=goOolIueQxF4ldrHBZeQkgOys0U39zehwPxKYyDrcRk=; b=TeyJK/sxKvoo5Jv9yJU2cjYb2yuJa7igNNlKJYWRjv/F+8O8AHUnnbuQMbVNLNW7hm77z4whHMaOq6CGOCMSFAluLBi+FlXvLdjkGN4qdt3tOLPkpESyWfBL9XLq0fDUuvcx0IXcYqfDcqE0ismzegCFjcXaYB7jeCQj0G35X7A= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567034372576391.00658878362196; Wed, 28 Aug 2019 16:19:32 -0700 (PDT) Received: from localhost ([::1]:43610 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i37Dv-000657-8p for importer@patchew.org; Wed, 28 Aug 2019 19:19:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52323) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i37BV-0004EC-S2 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:17:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i37BU-0008GS-Lq for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:17:01 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:38781) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i37BT-0008GF-Fp for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:17:00 -0400 Received: by mail-pg1-x543.google.com with SMTP id e11so516493pga.5 for ; Wed, 28 Aug 2019 16:16:59 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id s5sm485197pfm.97.2019.08.28.16.16.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 16:16:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=goOolIueQxF4ldrHBZeQkgOys0U39zehwPxKYyDrcRk=; b=qbmyFNLdnc0xOSmK/Gwy9OeN+58Hg6olND6KrcBwNGUQwWV6EHeIjoNFU/qqtjy6Bs iUJyRVF3KG3q0KXncYTuQdi2RBj0My1AJhBCGim7TkKhQzCNqO3bWv52YYbIBSMVHhnc jPap4m/45dBld8BMVGiYfQ7shg+h+babPrkfj+nq3dl5DIPvuJa5fjpL1Fp6odBvoRd6 V6POlPaSiq0re+D8nH3dmOVsyJ0APYRGs3ZEGdnmU5QQzOKmTDbFOuNJq+RZNRKkf1c8 rcJzS1rjJhSUkrDrGKOO7vr0jMm2rN0GYys6ab2OAvfuS04FNoMtTM1W93QBHBAtKDYc uq1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=goOolIueQxF4ldrHBZeQkgOys0U39zehwPxKYyDrcRk=; b=q/TTm3uzSNGTn7a+aXeGXm7/aKxX67oMUw4dwDqv7xY76WFRRtDP7QFzKTuJ7dq+fU Ajs3Zp8aRA0Go9WqN7WZhzFF+Brpjlj8xZFR+HWd4vIDskJpt8xxkctcTMi8sg7DFQS2 2XyS+20VvuGkWI12wJNanfcu1J24qCIAn3GdDsDjmCLqrL40cbolyrO5XLbCrRFLQmFk y6daIRPNhijaw1Wl8xqey+rLQVhEC8T3BWCimXS60nKmLlbuBPv3PrerXpS2mVoFd/By 8ecUJEvWchJuV8O1gWZ6PP0Z5qEolgww/E1C1jlksInsZKBp6lYLSV+Yu5LK+ZQH9o2V ZuZQ== X-Gm-Message-State: APjAAAWYrSIv0/0xryUWqIo/bs1XaMMRFh49lztXnGIAFwGgv4VoNbpd MqRlqugG2SNdpGyo59xsSS1d1tlE+xs= X-Google-Smtp-Source: APXvYqwdPriDxDlO4ampxxN0vhix9rmgk0l5xV0ftRZVxpnyM55mAaHdVKM8k0OcSW0HMMTIHnx5bw== X-Received: by 2002:a17:90a:e012:: with SMTP id u18mr6675489pjy.66.1567034218253; Wed, 28 Aug 2019 16:16:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 16:16:47 -0700 Message-Id: <20190828231651.17176-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828231651.17176-1-richard.henderson@linaro.org> References: <20190828231651.17176-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v2 4/8] exec: Factor out cpu_watchpoint_address_matches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We want to move the check for watchpoints from memory_region_section_get_iotlb to tlb_set_page_with_attrs. Isolate the loop over watchpoints to an exported function. Rename the existing cpu_watchpoint_address_matches to watchpoint_address_matches, since it doesn't actually have a cpu argument. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 7 +++++++ exec.c | 45 ++++++++++++++++++++++++++++--------------- 2 files changed, 36 insertions(+), 16 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 7bd8bed5b2..c7cda65c66 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1096,6 +1096,12 @@ static inline void cpu_check_watchpoint(CPUState *cp= u, vaddr addr, vaddr len, MemTxAttrs atr, int fl, uintptr_t = ra) { } + +static inline int cpu_watchpoint_address_matches(CPUState *cpu, + vaddr addr, vaddr len) +{ + return 0; +} #else int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint); @@ -1105,6 +1111,7 @@ void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUW= atchpoint *watchpoint); void cpu_watchpoint_remove_all(CPUState *cpu, int mask); void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, MemTxAttrs attrs, int flags, uintptr_t ra); +int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); #endif =20 /** diff --git a/exec.c b/exec.c index cb6f5763dc..8575ce51ad 100644 --- a/exec.c +++ b/exec.c @@ -1138,9 +1138,8 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mas= k) * partially or completely with the address range covered by the * access). */ -static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp, - vaddr addr, - vaddr len) +static inline bool watchpoint_address_matches(CPUWatchpoint *wp, + vaddr addr, vaddr len) { /* We know the lengths are non-zero, but a little caution is * required to avoid errors in the case where the range ends @@ -1152,6 +1151,20 @@ static inline bool cpu_watchpoint_address_matches(CP= UWatchpoint *wp, =20 return !(addr > wpend || wp->vaddr > addrend); } + +/* Return flags for watchpoints that match addr + prot. */ +int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len) +{ + CPUWatchpoint *wp; + int ret =3D 0; + + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { + if (watchpoint_address_matches(wp, addr, TARGET_PAGE_SIZE)) { + ret |=3D wp->flags; + } + } + return ret; +} #endif /* !CONFIG_USER_ONLY */ =20 /* Add a breakpoint. */ @@ -1459,7 +1472,7 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu, target_ulong *address) { hwaddr iotlb; - CPUWatchpoint *wp; + int flags, match; =20 if (memory_region_is_ram(section->mr)) { /* Normal RAM. */ @@ -1477,17 +1490,17 @@ hwaddr memory_region_section_get_iotlb(CPUState *cp= u, iotlb +=3D xlat; } =20 - /* Make accesses to pages with watchpoints go via the - watchpoint trap routines. */ - QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) { - /* Avoid trapping reads of pages with a write breakpoint. */ - if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { - iotlb =3D PHYS_SECTION_WATCH + paddr; - *address |=3D TLB_MMIO; - break; - } - } + /* Avoid trapping reads of pages with a write breakpoint. */ + match =3D (prot & PAGE_READ ? BP_MEM_READ : 0) + | (prot & PAGE_WRITE ? BP_MEM_WRITE : 0); + flags =3D cpu_watchpoint_address_matches(cpu, vaddr, TARGET_PAGE_SIZE); + if (flags & match) { + /* + * Make accesses to pages with watchpoints go via the + * watchpoint trap routines. + */ + iotlb =3D PHYS_SECTION_WATCH + paddr; + *address |=3D TLB_MMIO; } =20 return iotlb; @@ -2806,7 +2819,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, = vaddr len, =20 addr =3D cc->adjust_watchpoint_address(cpu, addr, len); QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - if (cpu_watchpoint_address_matches(wp, addr, len) + if (watchpoint_address_matches(wp, addr, len) && (wp->flags & flags)) { if (flags =3D=3D BP_MEM_READ) { wp->flags |=3D BP_WATCHPOINT_HIT_READ; --=20 2.17.1 From nobody Thu May 2 09:08:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567034559; cv=none; d=zoho.com; s=zohoarc; b=NfYVJBLyT6zVeX1koljXXp2xsbpX0pyQp4Zp1QVnJ7/r+A6WV5h8IHzUGJxRiu151m3N4hXlbQVnCZchOjNX3ZmyTbTTGG/wZJR4Y+ZeXo+OwCb02MVAlLaXF8ae4A32Dh/nm1Coy1Yu0ZWI0daRxeIGRrmgwWaaBHbvXPWdlFI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567034559; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=g2Ys6FT3dAIWRm2+sxUDBYBh9aclrTTCcmC9pqtLRPs=; b=cbsiGaPr/N8fOvxB7I6hiEQg/K7YHRf6CAO4dfI9XIqvkeh0rQ+zj+A7ORCghehLo+gWkj42nhn1fMCdr5bUUUqBjm54uXtk9hW96ncOQaACmZUoX7lhbl5AgB5FuAPDRQNSYARBMlgXGgPJWAoilc96vgaebt/mMjkhlqc7aAM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567034558995873.4627611863842; Wed, 28 Aug 2019 16:22:38 -0700 (PDT) Received: from localhost ([::1]:43660 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i37Gu-0001Ua-Tq for importer@patchew.org; Wed, 28 Aug 2019 19:22:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52327) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i37BW-0004EM-6C for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:17:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i37BU-0008Ga-My for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:17:01 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:34188) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i37BU-0008GK-HL for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:17:00 -0400 Received: by mail-pg1-x542.google.com with SMTP id n9so527977pgc.1 for ; Wed, 28 Aug 2019 16:17:00 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id s5sm485197pfm.97.2019.08.28.16.16.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 16:16:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g2Ys6FT3dAIWRm2+sxUDBYBh9aclrTTCcmC9pqtLRPs=; b=STphK/P731J0GmYktFaMQOTVo3Pflb9IUOw8II6nZn6jbPbD6UKAZ3OWJrb4oo3Ve+ y/bZALj+aPVbczYOkNHDntHtdUhLS6HHb9Pdblrtdzb4wXtffLaFW/E2moJ/fm99xIZ6 LeGeT1xZm31FxGtaWJNZ5yaVT5wuux56zhdBmAR4XuWUcj2j5imCTvmgX4hVWrhZ1RsE d9ekp8cvrKOMhnHR5L9kvtIogAeU3Fe2+NSNKbXjXPF1nv1SOmS0mo7psfCa5XVDEjZ9 fnB57d2H0nLUrfsGU6TR2wuQiX52JJxQNlK1PlWbTl1bs9wus/4tHfB0jO+ctPHY3Eud rZww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g2Ys6FT3dAIWRm2+sxUDBYBh9aclrTTCcmC9pqtLRPs=; b=DXUjKYw+GskDLpbb4saDFCIwuEJ5xWezQSp06WHP2oCGIIu+sHMoCe3ac58ACnPTw3 efbh8sr+KPLjAHDkl1X4YTJS/SLS3fwwWBy/3L5fQQwE9otPTD7pSRmcKsCoLpUEMOCQ Lq7bZ9RWHbnn3xqHXxrC/XrogL7hEG8Pe6F8a4EROI6LZsfoEwjxEE7T6Q1OTJO0vZAO 5qkh41/16K48BT149FoN8WT/8bx6MBYWOeVdHqPhODhlZeVEZcO0Q44UgDJEUAYPI3QN efe/cIStMzGmjrlWsoEYxSkoou7M/0VVc38yYeJIJTrQP204K/ngbGCwMOh5Ie737YSc /99w== X-Gm-Message-State: APjAAAVdqwN27r4f+p1h9seTeLMOEGJIZy69RbGdLFwl3jRi7LHOC+sB aXTS7aLoZVnFMa29yvNHq+yB0IM0esY= X-Google-Smtp-Source: APXvYqyhZQiiEP5ypT+SjIzunCjNc5KtTSdQQGWBRcctQByz8zmDXd/UGqNRhqwufrf2akmJsoonQw== X-Received: by 2002:a17:90a:f011:: with SMTP id bt17mr6700083pjb.21.1567034219275; Wed, 28 Aug 2019 16:16:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 16:16:48 -0700 Message-Id: <20190828231651.17176-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828231651.17176-1-richard.henderson@linaro.org> References: <20190828231651.17176-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 5/8] cputlb: Fix size operand for tlb_fill on unaligned store X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We are currently passing the size of the full write to the tlb_fill for the second page. Instead pass the real size of the write to that page. This argument is unused within all tlb_fill, except to be logged via tracing, so in practice this makes no difference. But in a moment we'll need the value of size2 for watchpoints, and if we've computed the value we might as well use it. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/cputlb.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c9576bebcf..7fb67d2f05 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1504,6 +1504,8 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, uintptr_t index2; CPUTLBEntry *entry2; target_ulong page2, tlb_addr2; + size_t size2; + do_unaligned_access: /* * Ensure the second page is in the TLB. Note that the first page @@ -1511,13 +1513,14 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, * cannot evict the first. */ page2 =3D (addr + size) & TARGET_PAGE_MASK; + size2 =3D (addr + size) & ~TARGET_PAGE_MASK; index2 =3D tlb_index(env, mmu_idx, page2); entry2 =3D tlb_entry(env, mmu_idx, page2); tlb_addr2 =3D tlb_addr_write(entry2); if (!tlb_hit_page(tlb_addr2, page2) && !victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2 & TARGET_PAGE_MASK)) { - tlb_fill(env_cpu(env), page2, size, MMU_DATA_STORE, + tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE, mmu_idx, retaddr); } =20 --=20 2.17.1 From nobody Thu May 2 09:08:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567034545; cv=none; d=zoho.com; s=zohoarc; b=YdxmtQPp0cCdAhQ+EcWPod+s65A20X/o351VYGirw8HeYFT18mCTpqCr/x7sHJD78SXnW2ad+ivuuJPXnU+fgbpltOkd0oulhL+l4PNArsODXtNS/uslQV4wrBK17wNHY+fazbI/PtBmNesxWLqvwfm3B05ll57TBqHuUsUn2ds= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567034545; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Gm01TIX2dgmE2RJ8CmJz1CGP7nGYi+1YuaceKCL3Jzs=; b=N81dyh8X558CjQiEcMDrifcqYQtn318zH966p7yZezV8zcDi51KtmbbZnPk1aSduHGAX5WNVK+EaFr78A/TT+LAiNgF/2dzUwCj0YuOCmMS4EaO1nghMVIPU2O+HrqT1OVvZHjpb+C5YKy4Q/pNsvFC9BrM1zoM1LzC5L/NxPQM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567034545278318.63300626214016; Wed, 28 Aug 2019 16:22:25 -0700 (PDT) Received: from localhost ([::1]:43652 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i37Gh-0001Fz-M6 for importer@patchew.org; Wed, 28 Aug 2019 19:22:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52344) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i37BW-0004FK-S3 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:17:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i37BV-0008H5-Uo for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:17:02 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:38780) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i37BV-0008Gn-Oc for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:17:01 -0400 Received: by mail-pg1-x541.google.com with SMTP id e11so516530pga.5 for ; Wed, 28 Aug 2019 16:17:01 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id s5sm485197pfm.97.2019.08.28.16.16.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 16:16:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Gm01TIX2dgmE2RJ8CmJz1CGP7nGYi+1YuaceKCL3Jzs=; b=orlrpns2pUjBuMAHKF+faUFWHNQVF3WdegcMszTxlLr2nXp0hsLQ2IMUCoxy56T5GL gXfV+6fhHvTTfsDMLurG0ZWuoVflCrBHeaN6Dpq5ShbfLfrPYdzk07NoMaAxWPSCe8FE dk7qnKC/SDU1vi4/zJRoe+cAgit/sXFpk0851sxCTWSgo/fSzQm6JpVEB6G8OmRlO48O LLCiqZo3juMV1Tf/LvYXvlPf4v475mE4wvcA5LLsQisW/ybuapygUwA30P7ISW6MP9JX aXLntQ5Ffa+9/UOCHTifLlE9UxhViphb52IUvXDzFm7xbmDxixULjaPpQ963U4OE4bON fDTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Gm01TIX2dgmE2RJ8CmJz1CGP7nGYi+1YuaceKCL3Jzs=; b=a4BibgxAnsSsSPyb/Qsz3M7dgmEKoiVjdesxKl04DGS/MyetPtIfl7laIauaJf86Ur omIcUDmKoRnsgxukKMjKUHWL3Zb/H21ywOX2GKoiDVZobYRgk7foQHWmX+U3vNykgkfl NCTdZLiat/uOW/lcCg47qhZaVjod/vea+lpLToEq0DVpWqvfC8IqlDdh7VTEnjfGMEpY /RLnzfiDWPFfxgzxlkQeNbF4ZAQngBh/pU6W7458x96dG3bhcI0hEbin87V3RJlUUDwK 04HztF/4J0BLa9GfLNN7EVjeE3A1WPdH4d1hkF3NhJo1tFOpj6Xbjf6XgCr/8tp/eex2 JTkw== X-Gm-Message-State: APjAAAVYDVK4zg4DjoqJ7tNTstmrRFtRMlH3LFtMlYfytTljKf98aqqZ guxoxdmzV+OJ64TYT7hi3mHD7z7WWbY= X-Google-Smtp-Source: APXvYqx8C/yfNoMPnwNHRygwbs14sIiKP8AhiXoS/PAwo2fp0UKjB7PF7tuLeIfwZzOZuGDFPaQ4gg== X-Received: by 2002:a63:ed50:: with SMTP id m16mr5525536pgk.209.1567034220394; Wed, 28 Aug 2019 16:17:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 16:16:49 -0700 Message-Id: <20190828231651.17176-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828231651.17176-1-richard.henderson@linaro.org> References: <20190828231651.17176-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 6/8] cputlb: Remove double-alignment in store_helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We have already aligned page2 to the start of the next page. There is no reason to do that a second time. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/cputlb.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 7fb67d2f05..d0f8db33a2 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1518,8 +1518,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, entry2 =3D tlb_entry(env, mmu_idx, page2); tlb_addr2 =3D tlb_addr_write(entry2); if (!tlb_hit_page(tlb_addr2, page2) - && !victim_tlb_hit(env, mmu_idx, index2, tlb_off, - page2 & TARGET_PAGE_MASK)) { + && !victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2)) { tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE, mmu_idx, retaddr); } --=20 2.17.1 From nobody Thu May 2 09:08:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567034562; cv=none; d=zoho.com; s=zohoarc; b=Q825Ex/NbmAp+/pXDcbIC0gTE10ZEXouDSBdWDFWEWfxT7KPlLKQgH0G8SUPNYstSdKudD88fg/Dah7tDwcE85X78AhsFSC0Qnt+jLIz/OCiNPFEHL/LFMitAwmF80WE8CRKJ7mIuau39XIwv5exlpI4JbQD/6yRXypai8rKnbU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567034562; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=KCFma7SPazR+PLydn5oSHe1JBODXX4LgyHEufkm540A=; b=ha+E5hy7isDNc3pICpp1Sm2KJM00CiKD8JFaeONTg+iO61lqy9FV97LqQIBCUvfR1t9CtOB0C2te8b9Cw6UIm1LRJRVFzv4GB8cOkKpSbb/57doUEE0Sltj2poYRh2EeKhk67S9+loRyiuhnRtzgj2c33O1PZDJSYfIkiCrbO90= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567034562874233.81229897625678; Wed, 28 Aug 2019 16:22:42 -0700 (PDT) Received: from localhost ([::1]:43664 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i37Gz-0001XZ-AZ for importer@patchew.org; Wed, 28 Aug 2019 19:22:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52374) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i37BZ-0004I4-IW for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:17:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i37BX-0008Hb-Gd for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:17:05 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:33648) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i37BX-0008HN-8t for qemu-devel@nongnu.org; Wed, 28 Aug 2019 19:17:03 -0400 Received: by mail-pf1-x443.google.com with SMTP id g2so762425pfq.0 for ; Wed, 28 Aug 2019 16:17:03 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id s5sm485197pfm.97.2019.08.28.16.17.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 16:17:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KCFma7SPazR+PLydn5oSHe1JBODXX4LgyHEufkm540A=; b=QU+LQD2FKy2L75iqZLScRvDpFU/V6y2tadISgmUZ+APhklye+3Zo8lxmUApQBsMiVf 78JnksPAV3AWcGMT/BXtAgVv4hT/y/CxgDH+fakoM68x3isY0nbYUzgH2OsdCFPWqpbB ly3gw70cthnx0dAriUQ50WSNXjXFpXBJcwSe46D4Q2vVVa8TgquNMzTGnxu+LDy1kOGY 94D3xauDp0kLNfIddOMMRVpfyH2WLXwukWO25fIG+5B1itLyUcUdTc6Wo+Uu5IBN043u lobW+nyFp1RlZICsiKokqTPtN0myCU+q23bdLXKpH8qxeV/vYsqxU9YMvoNeRaGXVWVS baSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KCFma7SPazR+PLydn5oSHe1JBODXX4LgyHEufkm540A=; b=JGDet66r/yc9Gt/pZfHwsdBdOkIoxxJJogi1kLX6yLuzqSXew8D64/ppAsbL5dw5ia 0F64NVMTWwxExhGyRnRWzisrV91WdXqKetvw+AojNkktG9vMx1xtoOLhBxB2pqauK86a u2quIYF8Ii4AD7TEEB8mBg045DY8g4HZVWNh9qJ2MqatjrBu06TDuz71r39Gt0iS3sRH o+2RME+Pb/bAo96mYffUIeMOXbGJ9YWtzfx9uR2A2cl7BQADHh5UZNYtWhnCeGJijugv y5cmbe+Vw63lzWBYx65xPA9lyHsIn86+fMuKrollGQiLyaQBZ/kZ9yZd3k0rDAHwagAf gnig== X-Gm-Message-State: APjAAAVxosJ32f3xtlltiWQhcDGTS+WZgdyMH8QYQVbdctJhHduCfgZU Ff2zvo7Su0TrafZwBDI6K4ZsDCgaAp0= X-Google-Smtp-Source: APXvYqwf7YlxmxFGS5emx/A0Ip555ldmXAVbx75+ezCh5dcCzVdKyhbzqq3xqwYlovxf+UbHM6mLMA== X-Received: by 2002:a62:2c94:: with SMTP id s142mr7613495pfs.45.1567034221904; Wed, 28 Aug 2019 16:17:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 16:16:50 -0700 Message-Id: <20190828231651.17176-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828231651.17176-1-richard.henderson@linaro.org> References: <20190828231651.17176-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v2 7/8] cputlb: Handle watchpoints via TLB_WATCHPOINT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The raising of exceptions from check_watchpoint, buried inside of the I/O subsystem, is fundamentally broken. We do not have the helper return address with which we can unwind guest state. Replace PHYS_SECTION_WATCH and io_mem_watch with TLB_WATCHPOINT. Move the call to cpu_check_watchpoint into the cputlb helpers where we do have the helper return address. This also allows us to handle watchpoints on RAM to bypass the full i/o access path. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-all.h | 5 +- accel/tcg/cputlb.c | 89 ++++++++++++++++++++++++++++---- exec.c | 114 +++-------------------------------------- 3 files changed, 90 insertions(+), 118 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 8d07ae23a5..d2d443c4f9 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -329,11 +329,14 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS - 2)) /* Set if TLB entry is an IO callback. */ #define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) +/* Set if TLB entry contains a watchpoint. */ +#define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS - 4)) =20 /* Use this mask to check interception with an alignment mask * in a TCG backend. */ -#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO) +#define TLB_FLAGS_MASK \ + (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO | TLB_WATCHPOINT) =20 /** * tlb_hit_page: return true if page aligned @addr is a hit against the diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d0f8db33a2..9a9a626938 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -710,6 +710,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, hwaddr iotlb, xlat, sz, paddr_page; target_ulong vaddr_page; int asidx =3D cpu_asidx_from_attrs(cpu, attrs); + int wp_flags; =20 assert_cpu_is_self(cpu); =20 @@ -752,6 +753,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, code_address =3D address; iotlb =3D memory_region_section_get_iotlb(cpu, section, vaddr_page, paddr_page, xlat, prot, &addre= ss); + wp_flags =3D cpu_watchpoint_address_matches(cpu, vaddr_page, + TARGET_PAGE_SIZE); =20 index =3D tlb_index(env, mmu_idx, vaddr_page); te =3D tlb_entry(env, mmu_idx, vaddr_page); @@ -805,6 +808,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, tn.addend =3D addend - vaddr_page; if (prot & PAGE_READ) { tn.addr_read =3D address; + if (wp_flags & BP_MEM_READ) { + tn.addr_read |=3D TLB_WATCHPOINT; + } } else { tn.addr_read =3D -1; } @@ -831,6 +837,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, if (prot & PAGE_WRITE_INV) { tn.addr_write |=3D TLB_INVALID_MASK; } + if (wp_flags & BP_MEM_WRITE) { + tn.addr_write |=3D TLB_WATCHPOINT; + } } =20 copy_tlb_helper_locked(te, &tn); @@ -1264,13 +1273,33 @@ load_helper(CPUArchState *env, target_ulong addr, T= CGMemOpIdx oi, tlb_addr &=3D ~TLB_INVALID_MASK; } =20 - /* Handle an IO access. */ + /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + CPUIOTLBEntry *iotlbentry; + + /* For anything that is unaligned, recurse through full_load. */ if ((addr & (size - 1)) !=3D 0) { goto do_unaligned_access; } - return io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], - mmu_idx, addr, retaddr, access_type, op); + + iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + + /* Handle watchpoints. */ + if (unlikely(tlb_addr & TLB_WATCHPOINT)) { + /* On watchpoint hit, this will longjmp out. */ + cpu_check_watchpoint(env_cpu(env), addr, size, + iotlbentry->attrs, BP_MEM_READ, retaddr); + + /* The backing page may or may not require I/O. */ + tlb_addr &=3D ~TLB_WATCHPOINT; + if ((tlb_addr & ~TARGET_PAGE_MASK) =3D=3D 0) { + goto do_aligned_access; + } + } + + /* Handle I/O access. */ + return io_readx(env, iotlbentry, mmu_idx, addr, + retaddr, access_type, op); } =20 /* Handle slow unaligned access (it spans two pages or IO). */ @@ -1297,6 +1326,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, return res & MAKE_64BIT_MASK(0, size * 8); } =20 + do_aligned_access: haddr =3D (void *)((uintptr_t)addr + entry->addend); switch (op) { case MO_UB: @@ -1486,13 +1516,32 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, tlb_addr =3D tlb_addr_write(entry) & ~TLB_INVALID_MASK; } =20 - /* Handle an IO access. */ + /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + CPUIOTLBEntry *iotlbentry; + + /* For anything that is unaligned, recurse through byte stores. */ if ((addr & (size - 1)) !=3D 0) { goto do_unaligned_access; } - io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, - val, addr, retaddr, op); + + iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + + /* Handle watchpoints. */ + if (unlikely(tlb_addr & TLB_WATCHPOINT)) { + /* On watchpoint hit, this will longjmp out. */ + cpu_check_watchpoint(env_cpu(env), addr, size, + iotlbentry->attrs, BP_MEM_WRITE, retaddr); + + /* The backing page may or may not require I/O. */ + tlb_addr &=3D ~TLB_WATCHPOINT; + if ((tlb_addr & ~TARGET_PAGE_MASK) =3D=3D 0) { + goto do_aligned_access; + } + } + + /* Handle I/O access. */ + io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, op); return; } =20 @@ -1517,10 +1566,29 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, index2 =3D tlb_index(env, mmu_idx, page2); entry2 =3D tlb_entry(env, mmu_idx, page2); tlb_addr2 =3D tlb_addr_write(entry2); - if (!tlb_hit_page(tlb_addr2, page2) - && !victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2)) { - tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE, - mmu_idx, retaddr); + if (!tlb_hit_page(tlb_addr2, page2)) { + if (!victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2)) { + tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE, + mmu_idx, retaddr); + index2 =3D tlb_index(env, mmu_idx, page2); + entry2 =3D tlb_entry(env, mmu_idx, page2); + } + tlb_addr2 =3D tlb_addr_write(entry2); + } + + /* + * Handle watchpoints. Since this may trap, all checks + * must happen before any store. + */ + if (unlikely(tlb_addr & TLB_WATCHPOINT)) { + cpu_check_watchpoint(env_cpu(env), addr, size - size2, + env_tlb(env)->d[mmu_idx].iotlb[index].att= rs, + BP_MEM_WRITE, retaddr); + } + if (unlikely(tlb_addr2 & TLB_WATCHPOINT)) { + cpu_check_watchpoint(env_cpu(env), page2, size2, + env_tlb(env)->d[mmu_idx].iotlb[index2].at= trs, + BP_MEM_WRITE, retaddr); } =20 /* @@ -1542,6 +1610,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, return; } =20 + do_aligned_access: haddr =3D (void *)((uintptr_t)addr + entry->addend); switch (op) { case MO_UB: diff --git a/exec.c b/exec.c index 8575ce51ad..ad0f4a598f 100644 --- a/exec.c +++ b/exec.c @@ -193,15 +193,12 @@ typedef struct subpage_t { #define PHYS_SECTION_UNASSIGNED 0 #define PHYS_SECTION_NOTDIRTY 1 #define PHYS_SECTION_ROM 2 -#define PHYS_SECTION_WATCH 3 =20 static void io_mem_init(void); static void memory_map_init(void); static void tcg_log_global_after_sync(MemoryListener *listener); static void tcg_commit(MemoryListener *listener); =20 -static MemoryRegion io_mem_watch; - /** * CPUAddressSpace: all the information a CPU needs about an AddressSpace * @cpu: the CPU whose AddressSpace this is @@ -1472,7 +1469,6 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu, target_ulong *address) { hwaddr iotlb; - int flags, match; =20 if (memory_region_is_ram(section->mr)) { /* Normal RAM. */ @@ -1490,19 +1486,6 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu, iotlb +=3D xlat; } =20 - /* Avoid trapping reads of pages with a write breakpoint. */ - match =3D (prot & PAGE_READ ? BP_MEM_READ : 0) - | (prot & PAGE_WRITE ? BP_MEM_WRITE : 0); - flags =3D cpu_watchpoint_address_matches(cpu, vaddr, TARGET_PAGE_SIZE); - if (flags & match) { - /* - * Make accesses to pages with watchpoints go via the - * watchpoint trap routines. - */ - iotlb =3D PHYS_SECTION_WATCH + paddr; - *address |=3D TLB_MMIO; - } - return iotlb; } #endif /* defined(CONFIG_USER_ONLY) */ @@ -2810,10 +2793,14 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr= , vaddr len, =20 assert(tcg_enabled()); if (cpu->watchpoint_hit) { - /* We re-entered the check after replacing the TB. Now raise - * the debug interrupt so that is will trigger after the - * current instruction. */ + /* + * We re-entered the check after replacing the TB. + * Now raise the debug interrupt so that it will + * trigger after the current instruction. + */ + qemu_mutex_lock_iothread(); cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); + qemu_mutex_unlock_iothread(); return; } =20 @@ -2858,88 +2845,6 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr,= vaddr len, } } =20 -static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int fl= ags) -{ - CPUState *cpu =3D current_cpu; - vaddr addr =3D (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; - - cpu_check_watchpoint(cpu, addr, len, attrs, flags, 0); -} - -/* Watchpoint access routines. Watchpoints are inserted using TLB tricks, - so these check for a hit then pass through to the normal out-of-line - phys routines. */ -static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pda= ta, - unsigned size, MemTxAttrs attrs) -{ - MemTxResult res; - uint64_t data; - int asidx =3D cpu_asidx_from_attrs(current_cpu, attrs); - AddressSpace *as =3D current_cpu->cpu_ases[asidx].as; - - check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ); - switch (size) { - case 1: - data =3D address_space_ldub(as, addr, attrs, &res); - break; - case 2: - data =3D address_space_lduw(as, addr, attrs, &res); - break; - case 4: - data =3D address_space_ldl(as, addr, attrs, &res); - break; - case 8: - data =3D address_space_ldq(as, addr, attrs, &res); - break; - default: abort(); - } - *pdata =3D data; - return res; -} - -static MemTxResult watch_mem_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) -{ - MemTxResult res; - int asidx =3D cpu_asidx_from_attrs(current_cpu, attrs); - AddressSpace *as =3D current_cpu->cpu_ases[asidx].as; - - check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE); - switch (size) { - case 1: - address_space_stb(as, addr, val, attrs, &res); - break; - case 2: - address_space_stw(as, addr, val, attrs, &res); - break; - case 4: - address_space_stl(as, addr, val, attrs, &res); - break; - case 8: - address_space_stq(as, addr, val, attrs, &res); - break; - default: abort(); - } - return res; -} - -static const MemoryRegionOps watch_mem_ops =3D { - .read_with_attrs =3D watch_mem_read, - .write_with_attrs =3D watch_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid =3D { - .min_access_size =3D 1, - .max_access_size =3D 8, - .unaligned =3D false, - }, - .impl =3D { - .min_access_size =3D 1, - .max_access_size =3D 8, - .unaligned =3D false, - }, -}; - static MemTxResult flatview_read(FlatView *fv, hwaddr addr, MemTxAttrs attrs, uint8_t *buf, hwaddr le= n); static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs at= trs, @@ -3115,9 +3020,6 @@ static void io_mem_init(void) memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, NULL, UINT64_MAX); memory_region_clear_global_locking(&io_mem_notdirty); - - memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL, - NULL, UINT64_MAX); } =20 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) @@ -3131,8 +3033,6 @@ AddressSpaceDispatch *address_space_dispatch_new(Flat= View *fv) assert(n =3D=3D PHYS_SECTION_NOTDIRTY); n =3D dummy_section(&d->map, fv, &io_mem_rom); assert(n =3D=3D PHYS_SECTION_ROM); - n =3D dummy_section(&d->map, fv, &io_mem_watch); - assert(n =3D=3D PHYS_SECTION_WATCH); =20 d->phys_map =3D (PhysPageEntry) { .ptr =3D PHYS_MAP_NODE_NIL, .skip = =3D 1 }; =20 --=20 2.17.1 From nobody Thu May 2 09:08:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id s5sm485197pfm.97.2019.08.28.16.17.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 16:17:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JQUPutWQvF8Cc5oeNW7RTy29F84wJ8I1Hnzwo9VUtUk=; b=zpyDqQQTi4XvJgPrR7M/XbhQyAuuDVR95eHWkhVnKf0Gm4EaXYZTmXCWkLk8kAQjom TrPjQdli2V5LD+lnFioB/iO3N199HEMY+FZ9/Fy/qLonyqP9v9YAw/zgtAQk3uZhd0+w gOzRSGQqoDX141zTJl+x7p+6z7Gbz2S/TJrMGJlAvVBTMXnPw1ynwbzButLqYEvhQcus +gt7pTaYtcHw2tMXPeAOAcPSwCC2gpryuZI2h5AQz2MUQHuoA2tsJqPd6xUj9EWUUZvC QrEZwwRyzSpmpZ17yzN4o9Hk7pc6Uhc7/zrHIMvqiU2WuiWBLMcM1yj472oTeDigyHXC +B5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JQUPutWQvF8Cc5oeNW7RTy29F84wJ8I1Hnzwo9VUtUk=; b=cFMzAVTHJTmHPwBdvhIXCB1O3Gy/YH7M2n84LlkHdQ3tUHuW1WVajaLbM1JzByBNBF DC28u6xRFyA/5lzQJt4m6ytbsayecSn/qsoxtsy34N726+VvMIEe36f3YphFD5EJSaMs 8NMlQSBTlsZ+pO4auAu78QXkdYkJ+nUMWMJy/HxMBT76ocVVP75wiwonfdIMUUg+59Rm lnngag1eiDEpPO6yr1v0w8ivUFklnfCyEKrwy9zqiL8JkRgpRe47S0seiMgWFFWmhHDd 8i1AcbgAPSxCzCqOYKo6/aiC5VJCqQ4EGbRAQtuZ71SmoTsFXVVlxPo34sYSd2o9EVFH NQQQ== X-Gm-Message-State: APjAAAXIMVj1OnMO0NYfBhEZqFhsYjx0F0B6DzBTLkyrs+egmZeGaJv9 fvxyYnMP0G69vYVrRQjAr8s9W6pCUsk= X-Google-Smtp-Source: APXvYqwQovGK4nirC8PtWAmoviAcggTqyVJUTSuNgJBez8cgunog25BRQJORx6l8TU33lbiNpN5j7A== X-Received: by 2002:a63:1743:: with SMTP id 3mr5406212pgx.435.1567034223098; Wed, 28 Aug 2019 16:17:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 16:16:51 -0700 Message-Id: <20190828231651.17176-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828231651.17176-1-richard.henderson@linaro.org> References: <20190828231651.17176-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PATCH v2 8/8] tcg: Check for watchpoints in probe_write() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: David Hildenbrand Let size > 0 indicate a promise to write to those bytes. Check for write watchpoints in the probed range. Suggested-by: Richard Henderson Signed-off-by: David Hildenbrand Message-Id: <20190823100741.9621-10-david@redhat.com> [rth: Recompute index after tlb_fill; check TLB_WATCHPOINT.] Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 9a9a626938..010c4c6e3c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1086,13 +1086,24 @@ void probe_write(CPUArchState *env, target_ulong ad= dr, int size, int mmu_idx, { uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr =3D tlb_addr_write(entry); =20 - if (!tlb_hit(tlb_addr_write(entry), addr)) { - /* TLB entry is for a different page */ + if (unlikely(!tlb_hit(tlb_addr, addr))) { if (!VICTIM_TLB_HIT(addr_write, addr)) { tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); + /* TLB resize via tlb_fill may have moved the entry. */ + index =3D tlb_index(env, mmu_idx, addr); + entry =3D tlb_entry(env, mmu_idx, addr); } + tlb_addr =3D tlb_addr_write(entry); + } + + /* Handle watchpoints. */ + if ((tlb_addr & TLB_WATCHPOINT) && size > 0) { + cpu_check_watchpoint(env_cpu(env), addr, size, + env_tlb(env)->d[mmu_idx].iotlb[index].attrs, + BP_MEM_WRITE, retaddr); } } =20 --=20 2.17.1