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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:06:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kwRo4zZzHNj2f8dsvm1cnawVi86AhDJJQQALYH4bbvo=; b=RxbwHwdaNXVghcwQxxv2AhEAgUCdq06Zam78cjeGv2zovSoZTyCduTZGZyddgatOxY VZ6kGBKtsdCi44JXVAjf87ZODnUcyCX2wQ/pxR5aDWWWiApvgdDnfy+GZlqrbDzyWMrE dMl/VpkBOEkNNpma9HfeRWofcBWkJ9aaqTpcz1xkN0Ym/OP6e+1PykGBbfJ/H/17uFSn fAWBbadEzT3QI1rifD48scQMgVQQjiixIUsaKYw1dHWE4eKoGJXfuRQisKf3s+UfblYC lGUMThWP4Diwkrl1ZjIMdjQHz0IAJH5YluVfJ3wNrG8I7T7g/JHcl7dKWPYL4hB6iOXZ 1qGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kwRo4zZzHNj2f8dsvm1cnawVi86AhDJJQQALYH4bbvo=; b=eUq/krBSJbzEC3jXKEf5EkMQewV5CnPRpb26ujbViMSSWbvtMCbZmgInYZdT7sAm7y 0p4wi/hKyP5Lo9CVwNIUlHGs1njuF2RUcmkhPHuMROiJBE/zEYbJNy/J+yoBKSqJxPXj s0/snaBFAxawCehrTHJfK1HBGXyAEkqu7cQDvCe9L05ZTFk7OA2TKHbbRbochhe4UJLN NydyncR+Alfi8FglpCTJAf+PL+AD/ugZmmtIHHF4Dzjp8FUfo7XML/M4ZslA0dD+0Y/w wN97q1yjXHCKuSsuUOQkX3kUutG+y41wX0WMwy0TqibmjMUpP2PmtS3KldwGATfrEGlk ptRA== X-Gm-Message-State: APjAAAWwvn7NlHzPDsDHj136zw2GM5sAFVA/ZURUj33ruHfZ57kjcvd0 t+cxaEzCmRgTxMAQv3dklzkMTzaTzhE= X-Google-Smtp-Source: APXvYqzY+FObHV9HFL+LRR2ji2p/lI0wWZe42rTGy5Rfl4UJp+gkaWSlwIuDB1bS2ky6iREwWmNbPg== X-Received: by 2002:a17:902:e407:: with SMTP id ci7mr5967774plb.326.1567019161183; Wed, 28 Aug 2019 12:06:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:35 -0700 Message-Id: <20190828190456.30315-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 48/69] target/arm: Convert T16 load/store (immediate offset) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 94 +++--------------------------------------- target/arm/t16.decode | 33 +++++++++++++++ 2 files changed, 38 insertions(+), 89 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 73b4ac8efb..8e182f338c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10840,97 +10840,13 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) */ goto illegal_op; =20 - case 5: - /* load/store register offset, in decodetree */ + case 5: /* load/store register offset, in decodetree */ + case 6: /* load/store word immediate offset, in decodetree */ + case 7: /* load/store byte immediate offset, in decodetree */ + case 8: /* load/store halfword immediate offset, in decodetree */ + case 9: /* load/store from stack, in decodetree */ goto illegal_op; =20 - case 6: - /* load/store word immediate offset */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - addr =3D load_reg(s, rn); - val =3D (insn >> 4) & 0x7c; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 7: - /* load/store byte immediate offset */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - addr =3D load_reg(s, rn); - val =3D (insn >> 6) & 0x1f; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16B= it); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 8: - /* load/store halfword immediate offset */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - addr =3D load_reg(s, rn); - val =3D (insn >> 5) & 0x3e; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 9: - /* load/store from stack */ - rd =3D (insn >> 8) & 7; - addr =3D load_reg(s, 13); - val =3D (insn & 0xff) * 4; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - case 10: /* * 0b1010_xxxx_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 83fe4363c7..1cf79789ac 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ldst_rr !extern p w u rn rt rm shimm shtype +&ldst_ri !extern p w u rn rt imm =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -69,3 +70,35 @@ LDR_rr 0101 100 ... ... ... @ldst_rr LDRH_rr 0101 101 ... ... ... @ldst_rr LDRB_rr 0101 110 ... ... ... @ldst_rr LDRSH_rr 0101 111 ... ... ... @ldst_rr + +# Load/store word/byte (immediate offset) + +%imm5_6x4 6:5 !function=3Dtimes_4 + +@ldst_ri_1 ..... imm:5 rn:3 rt:3 \ + &ldst_ri p=3D1 w=3D0 u=3D1 +@ldst_ri_4 ..... ..... rn:3 rt:3 \ + &ldst_ri p=3D1 w=3D0 u=3D1 imm=3D%imm5_6x4 + +STR_ri 01100 ..... ... ... @ldst_ri_4 +LDR_ri 01101 ..... ... ... @ldst_ri_4 +STRB_ri 01110 ..... ... ... @ldst_ri_1 +LDRB_ri 01111 ..... ... ... @ldst_ri_1 + +# Load/store halfword (immediate offset) + +%imm5_6x2 6:5 !function=3Dtimes_2 +@ldst_ri_2 ..... ..... rn:3 rt:3 \ + &ldst_ri p=3D1 w=3D0 u=3D1 imm=3D%imm5_6x2 + +STRH_ri 10000 ..... ... ... @ldst_ri_2 +LDRH_ri 10001 ..... ... ... @ldst_ri_2 + +# Load/store (SP-relative) + +%imm8_0x4 0:8 !function=3Dtimes_4 +@ldst_spec_i ..... rt:3 ........ \ + &ldst_ri p=3D1 w=3D0 u=3D1 imm=3D%imm8_0x4 + +STR_ri 10010 ... ........ @ldst_spec_i rn=3D13 +LDR_ri 10011 ... ........ @ldst_spec_i rn=3D13 --=20 2.17.1