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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ENB9E1VePGgEvpljqAX8EyWULibUwHF2u0OAo21pbuU=; b=DO6gaC//GIpneYcXV+mDdDit5od2Vlkcx53NuOuHBPR4okk6WvHoj5+PfDKc7Ems7d Q7eCVQ6l4Bi/TDsbXOchcucDrNf7V5PTS5wO45ulcaM8INtUyclH3XnO+SkT24Sn3bwU nZv0ObJWh0G4l8czS5jdNmSxAcwl2Qf4gRdEeTzOFBQJrcsuGCY0IT+Yo4KRm8VS/3Iq cVZ0KoWOVYvnJpVWLUbpqzqCbRCLAq0Lc9LlKH0AkyeKJuJ5U0nm+3TBS3dIOASyB6d7 4xgYcN3OY5JGZclRkWwPphnc9Ma7QUcRkICGWGjDGKqmio5cHlBmpQqxqkc9JzmTB4lJ 02+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ENB9E1VePGgEvpljqAX8EyWULibUwHF2u0OAo21pbuU=; b=Vp68NeJ3F9J3O0v97HWuwqYJZHPDAufWuyLanHowLmjCscuy2GQM9aVVl5zihkmgi1 Q2/DPl2rIrHN0ZGQefL95Bky6HEq3btK+OQ97pGI17wz66bxZ69ZFrN/j9EVwoU4FThb tr5sNE/Wtr4PSK+Kjzw5QUSWvfMod5sGXUkOHIpMnap7R33pItblpzxjwcTqcG25ZO/L HEnA97p4V8QGGLoU2HGMJmLkt8/HBqdlEsmvBgRlqiTf4rwnNlQHsjF9WbsZF6y4sdSe QLRmJWZYXXTkeU3ZkJTVbOUYWJRT23D88Ch3BBi+rYRtdd95bVf8IRawZxgkm1klFvUX xqbg== X-Gm-Message-State: APjAAAUnlsfWn4jh7URSv3jDiBjgzcJfTDWGnFHL9F9eqw7p/VEkLnH7 caby6zc1egnHcpfx+OJuWOCQEO8Uf0Q= X-Google-Smtp-Source: APXvYqwrtBIVAgI+JViajIuxpLiNxc3HcEIRWKHeFLBKE3VA+tFuhbgq1i9MB0jNovELoHS9euI6QQ== X-Received: by 2002:a17:902:24c:: with SMTP id 70mr5709334plc.331.1567019152568; Wed, 28 Aug 2019 12:05:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:28 -0700 Message-Id: <20190828190456.30315-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 41/69] target/arm: Convert SG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 51 ++++++++++++++++++++++++------------------ target/arm/t32.decode | 5 ++++- 2 files changed, 33 insertions(+), 23 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 92b3a66e05..52da7f4fa8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8441,6 +8441,34 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a) return true; } =20 +static bool trans_SG(DisasContext *s, arg_SG *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + /* + * SG (v8M only) + * The bulk of the behaviour for this instruction is implemented + * in v7m_handle_execute_nsc(), which deals with the insn when + * it is executed by a CPU in non-secure state from memory + * which is Secure & NonSecure-Callable. + * Here we only need to handle the remaining cases: + * * in NS memory (including the "security extension not + * implemented" case) : NOP + * * in S memory but CPU already secure (clear IT bits) + * We know that the attribute for the memory this insn is + * in must match the current CPU state, because otherwise + * get_phys_addr_pmsav8 would have generated an exception. + */ + if (s->v8m_secure) { + /* Like the IT insn, we don't need to generate any code */ + s->condexec_cond =3D 0; + s->condexec_mask =3D 0; + } + return true; +} + /* * Load/store register index */ @@ -10530,28 +10558,7 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) * - load/store doubleword, load/store exclusive, ldacq/strel, * table branch, TT. */ - if (insn =3D=3D 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M)= && - arm_dc_feature(s, ARM_FEATURE_V8)) { - /* 0b1110_1001_0111_1111_1110_1001_0111_111 - * - SG (v8M only) - * The bulk of the behaviour for this instruction is imple= mented - * in v7m_handle_execute_nsc(), which deals with the insn = when - * it is executed by a CPU in non-secure state from memory - * which is Secure & NonSecure-Callable. - * Here we only need to handle the remaining cases: - * * in NS memory (including the "security extension not - * implemented" case) : NOP - * * in S memory but CPU already secure (clear IT bits) - * We know that the attribute for the memory this insn is - * in must match the current CPU state, because otherwise - * get_phys_addr_pmsav8 would have generated an exception. - */ - if (s->v8m_secure) { - /* Like the IT insn, we don't need to generate any cod= e */ - s->condexec_cond =3D 0; - s->condexec_mask =3D 0; - } - } else if (insn & 0x01200000) { + if (insn & 0x01200000) { /* load/store dual, in decodetree */ goto illegal_op; } else if ((insn & (1 << 23)) =3D=3D 0) { diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 24482e0eeb..2b30a767fe 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -487,7 +487,10 @@ STRD_ri_t32 1110 1001 .100 .... .... .... .......= . @ldstd_ri8 w=3D0 p=3D1 LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=3D= 0 p=3D1 =20 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 -LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 +{ + SG 1110 1001 0111 1111 1110 1001 01111111 + LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 +} =20 # Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch =20 --=20 2.17.1