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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.04.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=14GQARTvu8E3U5TivytnupYS9fMVqAtXGLnyFkmLB/c=; b=MycaWecfNnxPRxXOZYPfu/QLR6YZmEo7fdFiu1esJs7vWwo+lMvsukw2tZfYkWLKUd ypGagD49XDmTcOfARcHSXtaRYfyTLVGSpybjGpeNSMbjtynU5LzFehP6X4y9qS/EUNxh RdvPQj+V6WJCoOm3kRqNgNVYjhWfiswrPmaFHzK+bg+Mga40b3G08/9Tp/jMa/4000eQ xWq8xLfbh6XkNwG2aRzy9WjhecY8IC3T2QzEfUSJxqWarJqN3xFswFudeqNH0TUb3lXD cgji9TfzLxVIME4w+gGp25uG5sTkk7huxh4vZ5MUc28W8TMgd6ycadC3vXTNx/9Eyny4 FKtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=14GQARTvu8E3U5TivytnupYS9fMVqAtXGLnyFkmLB/c=; b=iJenbbbxpNkkhwnr8mZjdxUsUGFv6Me1xZfV4TJZtf0jGZUbLgNtTITNm3ggef2jNu keFMHXfFVb1c+bs6gvIp/8OtmeJbEgThVi7VIMAS+CkHPfwJivp5HUSo2T8B0vZWaGEw TkbUSIdzLiWRbpdTdqSasiFAsuTPIFssmUgX4PjXkFLAM3FLWrFMaIOQXfZkRhYhjGiV W7m93n2nUa5AIykDR8XLAVFnkW7CJidCYytpElDq0bhn9jDDIC9AKw4j9+0/V6hWtVJw CyXafrkiELgBht4Us4hiPpMyw2VeVWQlIlXKynJXHjDXYRmE5Ls3cFD5eCnog0K7VDdd DFZQ== X-Gm-Message-State: APjAAAVJRtvCeXyOL272mpLXqrAA+nSWPZ5Dr9yaM45Bbc0shwYOIpC0 UefmQ7KCaG5QlceoRJjCcrjiYBURV94= X-Google-Smtp-Source: APXvYqzUiKK5Jdqgv8octrMDvt1KxpgDOg343m1u1xNHQXkxIX/MWjE5IFF9mr5hF9s/RZVA/YgFbA== X-Received: by 2002:a17:902:e406:: with SMTP id ci6mr5716394plb.207.1567019100988; Wed, 28 Aug 2019 12:05:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:03:49 -0700 Message-Id: <20190828190456.30315-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 02/69] target/arm: Add stubs for aa32 decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Add the infrastructure that will become the new decoder. No instructions adjusted so far. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 31 ++++++++++++++++++++++++++++++- target/arm/Makefile.objs | 18 ++++++++++++++++++ target/arm/a32-uncond.decode | 23 +++++++++++++++++++++++ target/arm/a32.decode | 23 +++++++++++++++++++++++ target/arm/t32.decode | 20 ++++++++++++++++++++ 5 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 target/arm/a32-uncond.decode create mode 100644 target/arm/a32.decode create mode 100644 target/arm/t32.decode diff --git a/target/arm/translate.c b/target/arm/translate.c index 35e59a8a16..91651b9736 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7657,6 +7657,18 @@ static void arm_skip_unless(DisasContext *s, uint32_= t cond) arm_gen_test_cc(cond ^ 1, s->condlabel); } =20 +/* + * Include the generated decoders. + */ + +#include "decode-a32.inc.c" +#include "decode-a32-uncond.inc.c" +#include "decode-t32.inc.c" + +/* + * Legacy decoder. + */ + static void disas_arm_insn(DisasContext *s, unsigned int insn) { unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; @@ -7675,7 +7687,8 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) return; } cond =3D insn >> 28; - if (cond =3D=3D 0xf){ + + if (cond =3D=3D 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we * choose to UNDEF. In ARMv5 and above the space is used * for miscellaneous unconditional instructions. @@ -7683,6 +7696,11 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) ARCH(5); =20 /* Unconditional instructions. */ + if (disas_a32_uncond(s, insn)) { + return; + } + /* fall back to legacy decoder */ + if (((insn >> 25) & 7) =3D=3D 1) { /* NEON Data processing. */ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { @@ -7897,6 +7915,12 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) next instruction */ arm_skip_unless(s, cond); } + + if (disas_a32(s, insn)) { + return; + } + /* fall back to legacy decoder */ + if ((insn & 0x0f900000) =3D=3D 0x03000000) { if ((insn & (1 << 21)) =3D=3D 0) { ARCH(6T2); @@ -9379,6 +9403,11 @@ static void disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) ARCH(6T2); } =20 + if (disas_t32(s, insn)) { + return; + } + /* fall back to legacy decoder */ + rn =3D (insn >> 16) & 0xf; rs =3D (insn >> 12) & 0xf; rd =3D (insn >> 8) & 0xf; diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 5cafc1eb6c..7806b4dac0 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -28,9 +28,27 @@ target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/a= rm/vfp-uncond.decode $(D $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\ "GEN", $(TARGET_DIR)$@) =20 +target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETRE= E) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.deco= de $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETRE= E) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c +target/arm/translate.o: target/arm/decode-a32.inc.c +target/arm/translate.o: target/arm/decode-a32-uncond.inc.c +target/arm/translate.o: target/arm/decode-t32.inc.c =20 obj-y +=3D tlb_helper.o debug_helper.o obj-y +=3D translate.o op_helper.o diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode new file mode 100644 index 0000000000..8dee26d3b6 --- /dev/null +++ b/target/arm/a32-uncond.decode @@ -0,0 +1,23 @@ +# A32 unconditional instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# All insns that have 0xf in insn[31:28] are decoded here. +# All of those that have a COND field in insn[31:28] are in a32.decode +# diff --git a/target/arm/a32.decode b/target/arm/a32.decode new file mode 100644 index 0000000000..a3e6e8c1c2 --- /dev/null +++ b/target/arm/a32.decode @@ -0,0 +1,23 @@ +# A32 conditional instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# All of the insn that have a COND field in insn[31:28] are here. +# All insns that have 0xf in insn[31:28] are in a32-uncond.decode. +# diff --git a/target/arm/t32.decode b/target/arm/t32.decode new file mode 100644 index 0000000000..ac01fb6958 --- /dev/null +++ b/target/arm/t32.decode @@ -0,0 +1,20 @@ +# Thumb2 instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# --=20 2.17.1