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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.04.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:04:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jAqvd/2BIuSZJ/quAHqjRlBcC779AH2rhSu4pCUKbkY=; b=cwqrKVKkM5ZDHJULoLzd1MCeKIvJCsqMAGtjwM1WNM7n+rhC4YXa/ccKWJkv8YEMmv JjWU2O2Bq3SUEmz01uGx2lSLb7aa9rdCDAQ2kIW1/M4VeXP4EYwSpzagpH8tz8sqM4Sh d7p7jC+crnZ1u4+rIfNMhw7u181jPTsCIhLo5nhE00FXC7B+oTl8tqR9VQEeqIQ9XS2Y 1HeQggQK+WwyhcTUeswIOq8q7EONBd+EHc/3uIZuw53/DQMK5WOyMk+zErSrXcxA/s2S WBODvBSQZKLE397QAmOKFPtUFwzrmk1C4pjmsH3+PJji+XpTsrRGXqBlMwtQ2GsmuzwY AqQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jAqvd/2BIuSZJ/quAHqjRlBcC779AH2rhSu4pCUKbkY=; b=WUb4YnYwtxQpQakR1j0Lx2HTKkU7j8Oyk+08bMHK0Fn6tjpnNKI/2CjElDMHJSsbfi UfsBnHsJjHCOPrpCzmPMmGgK6noPXTKXcdr9a+vX2jPqI3M3iaFsxtoyuhlSzEGrXzFd fG2KrYIxV9Ityd56YrY4bbsVLnFZYjmJ+CJSSHv1JAJHrTSazXT3QIqFLj4kYJbWVzgc RspENH/fsaTrVvuX47a7lamEpZokU/GOvT86nqUuYfWYX6xNg3uMJfD7Ve5IXg87u+O6 /8Vo6vzReZqSbB9JS/n38hqkUd4GSMWE22wmVe9F5is9A6IgFkC7UB5c8uGQ8pyKPtjR 2/8w== X-Gm-Message-State: APjAAAUd4Zq2uV7cNjVxMzlxMK19wSxyHUlZKD7300iqoxhbvl8OB6g8 7fTKlqnD809EGBz5Hu81aO+JhtiBCb8= X-Google-Smtp-Source: APXvYqyXqw2otp/bOrb2PgK0HPRFqbBNvbB2HqaOa66IZlx7F+1wOcGEqFSOLuVRubqm5QXlCEZNew== X-Received: by 2002:a62:e516:: with SMTP id n22mr6559250pff.105.1567019099849; Wed, 28 Aug 2019 12:04:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:03:48 -0700 Message-Id: <20190828190456.30315-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 01/69] target/arm: Use store_reg_from_load in thumb2 code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This function already includes the test for an interworking write to PC from a load. Change the T32 LDM implementation to match the A32 LDM implementation. For LDM, the reordering of the tests does not change valid behaviour because the only case that differs is has rn =3D=3D 15, which is UNPREDICTABLE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index cbe19b7a62..35e59a8a16 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9707,13 +9707,11 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) /* Load. */ tmp =3D tcg_temp_new_i32(); gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i =3D=3D 15) { - gen_bx_excret(s, tmp); - } else if (i =3D=3D rn) { + if (i =3D=3D rn) { loaded_var =3D tmp; loaded_base =3D 1; } else { - store_reg(s, i, tmp); + store_reg_from_load(s, i, tmp); } } else { /* Store. */ @@ -10847,11 +10845,7 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tcg_temp_free_i32(addr); goto illegal_op; } - if (rs =3D=3D 15) { - gen_bx_excret(s, tmp); - } else { - store_reg(s, rs, tmp); - } + store_reg_from_load(s, rs, tmp); } else { /* Store. */ tmp =3D load_reg(s, rs); --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567019513; cv=none; d=zoho.com; s=zohoarc; b=oDSH+iVBy7TyYJlq/mjJY8NhMXkuUX1p0pZsxs0GKMjAc7bGOIU5DxaRrhwnnUHN4tMJaCL52b4cYV1/9h7kTBS6Upg3IiO8wr6xtwwoUgF4E/g6htwKF7mhsQO3JUH1ItMIhfegyraLXk8qsDYk4vkMaM4Y6XPhaHeZYgxo97Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567019513; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=14GQARTvu8E3U5TivytnupYS9fMVqAtXGLnyFkmLB/c=; b=Ziy0MGpsW3C7NTWL+8kG0CkJhZIxzKnTfrSqwaxg71jRpSrMM60Z652S3vdYjsWfytWLucB7CwTVgq86g4VpgNW1wbNAiHw+tYCooVOVQB4a3TDQtpjzbPDLmS/FtCsX4EBVV/3nrcHTBIchHSeyLVdP8Wm+HLqVPcEsqgzrmIY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567019513248249.74084803812627; Wed, 28 Aug 2019 12:11:53 -0700 (PDT) Received: from localhost ([::1]:40942 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33MF-0000rz-Mi for importer@patchew.org; Wed, 28 Aug 2019 15:11:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37366) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Fg-0002xQ-M8 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33Fe-00085Z-JI for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:04 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:39663) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33Fe-00084w-DT for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:02 -0400 Received: by mail-pl1-x641.google.com with SMTP id z3so394707pln.6 for ; Wed, 28 Aug 2019 12:05:02 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.04.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=14GQARTvu8E3U5TivytnupYS9fMVqAtXGLnyFkmLB/c=; b=MycaWecfNnxPRxXOZYPfu/QLR6YZmEo7fdFiu1esJs7vWwo+lMvsukw2tZfYkWLKUd ypGagD49XDmTcOfARcHSXtaRYfyTLVGSpybjGpeNSMbjtynU5LzFehP6X4y9qS/EUNxh RdvPQj+V6WJCoOm3kRqNgNVYjhWfiswrPmaFHzK+bg+Mga40b3G08/9Tp/jMa/4000eQ xWq8xLfbh6XkNwG2aRzy9WjhecY8IC3T2QzEfUSJxqWarJqN3xFswFudeqNH0TUb3lXD cgji9TfzLxVIME4w+gGp25uG5sTkk7huxh4vZ5MUc28W8TMgd6ycadC3vXTNx/9Eyny4 FKtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=14GQARTvu8E3U5TivytnupYS9fMVqAtXGLnyFkmLB/c=; b=iJenbbbxpNkkhwnr8mZjdxUsUGFv6Me1xZfV4TJZtf0jGZUbLgNtTITNm3ggef2jNu keFMHXfFVb1c+bs6gvIp/8OtmeJbEgThVi7VIMAS+CkHPfwJivp5HUSo2T8B0vZWaGEw TkbUSIdzLiWRbpdTdqSasiFAsuTPIFssmUgX4PjXkFLAM3FLWrFMaIOQXfZkRhYhjGiV W7m93n2nUa5AIykDR8XLAVFnkW7CJidCYytpElDq0bhn9jDDIC9AKw4j9+0/V6hWtVJw CyXafrkiELgBht4Us4hiPpMyw2VeVWQlIlXKynJXHjDXYRmE5Ls3cFD5eCnog0K7VDdd DFZQ== X-Gm-Message-State: APjAAAVJRtvCeXyOL272mpLXqrAA+nSWPZ5Dr9yaM45Bbc0shwYOIpC0 UefmQ7KCaG5QlceoRJjCcrjiYBURV94= X-Google-Smtp-Source: APXvYqzUiKK5Jdqgv8octrMDvt1KxpgDOg343m1u1xNHQXkxIX/MWjE5IFF9mr5hF9s/RZVA/YgFbA== X-Received: by 2002:a17:902:e406:: with SMTP id ci6mr5716394plb.207.1567019100988; Wed, 28 Aug 2019 12:05:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:03:49 -0700 Message-Id: <20190828190456.30315-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 02/69] target/arm: Add stubs for aa32 decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Add the infrastructure that will become the new decoder. No instructions adjusted so far. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 31 ++++++++++++++++++++++++++++++- target/arm/Makefile.objs | 18 ++++++++++++++++++ target/arm/a32-uncond.decode | 23 +++++++++++++++++++++++ target/arm/a32.decode | 23 +++++++++++++++++++++++ target/arm/t32.decode | 20 ++++++++++++++++++++ 5 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 target/arm/a32-uncond.decode create mode 100644 target/arm/a32.decode create mode 100644 target/arm/t32.decode diff --git a/target/arm/translate.c b/target/arm/translate.c index 35e59a8a16..91651b9736 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7657,6 +7657,18 @@ static void arm_skip_unless(DisasContext *s, uint32_= t cond) arm_gen_test_cc(cond ^ 1, s->condlabel); } =20 +/* + * Include the generated decoders. + */ + +#include "decode-a32.inc.c" +#include "decode-a32-uncond.inc.c" +#include "decode-t32.inc.c" + +/* + * Legacy decoder. + */ + static void disas_arm_insn(DisasContext *s, unsigned int insn) { unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; @@ -7675,7 +7687,8 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) return; } cond =3D insn >> 28; - if (cond =3D=3D 0xf){ + + if (cond =3D=3D 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we * choose to UNDEF. In ARMv5 and above the space is used * for miscellaneous unconditional instructions. @@ -7683,6 +7696,11 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) ARCH(5); =20 /* Unconditional instructions. */ + if (disas_a32_uncond(s, insn)) { + return; + } + /* fall back to legacy decoder */ + if (((insn >> 25) & 7) =3D=3D 1) { /* NEON Data processing. */ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { @@ -7897,6 +7915,12 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) next instruction */ arm_skip_unless(s, cond); } + + if (disas_a32(s, insn)) { + return; + } + /* fall back to legacy decoder */ + if ((insn & 0x0f900000) =3D=3D 0x03000000) { if ((insn & (1 << 21)) =3D=3D 0) { ARCH(6T2); @@ -9379,6 +9403,11 @@ static void disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) ARCH(6T2); } =20 + if (disas_t32(s, insn)) { + return; + } + /* fall back to legacy decoder */ + rn =3D (insn >> 16) & 0xf; rs =3D (insn >> 12) & 0xf; rd =3D (insn >> 8) & 0xf; diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 5cafc1eb6c..7806b4dac0 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -28,9 +28,27 @@ target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/a= rm/vfp-uncond.decode $(D $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\ "GEN", $(TARGET_DIR)$@) =20 +target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETRE= E) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.deco= de $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETRE= E) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c +target/arm/translate.o: target/arm/decode-a32.inc.c +target/arm/translate.o: target/arm/decode-a32-uncond.inc.c +target/arm/translate.o: target/arm/decode-t32.inc.c =20 obj-y +=3D tlb_helper.o debug_helper.o obj-y +=3D translate.o op_helper.o diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode new file mode 100644 index 0000000000..8dee26d3b6 --- /dev/null +++ b/target/arm/a32-uncond.decode @@ -0,0 +1,23 @@ +# A32 unconditional instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# All insns that have 0xf in insn[31:28] are decoded here. +# All of those that have a COND field in insn[31:28] are in a32.decode +# diff --git a/target/arm/a32.decode b/target/arm/a32.decode new file mode 100644 index 0000000000..a3e6e8c1c2 --- /dev/null +++ b/target/arm/a32.decode @@ -0,0 +1,23 @@ +# A32 conditional instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# All of the insn that have a COND field in insn[31:28] are here. +# All insns that have 0xf in insn[31:28] are in a32-uncond.decode. +# diff --git a/target/arm/t32.decode b/target/arm/t32.decode new file mode 100644 index 0000000000..ac01fb6958 --- /dev/null +++ b/target/arm/t32.decode @@ -0,0 +1,20 @@ +# Thumb2 instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567019358; cv=none; d=zoho.com; s=zohoarc; b=F/q9Uc5FTbzbs/7EYduuUcRh+1RpcWWqnUJK45Cnt2PHmrF4BB3bazsb1UPum3V4sVKFDc4L7oCSfGZkjlc2hdY8RxbsooAZgbJVPg9mPTAHTBnl1bnAoX9DGfUzaG7vscNkCX2v1X4NVWdK1ruOA78vj23nCTpET86G+p40mJ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567019358; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=33zm58TIwdxjcCCsm2mwmZDQsqXbSGvtAgfMtmmrvjg=; b=e9kmHLppI/bHwy7Hr+MGC/Ht6ZSKKQS4BBZaCmfUY14Cyy0WU7Z7ubptP7PY+0KDQoWpXHcmlx7rmbDukHZGxvKNvLS0j05tvO73T5BGJLMI7QpVLxfKFNOWSZ+vR5MmSW29IhO9ZAqb7wo43DyOSgLArVRIAj3WJ4syQSm/1kE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156701935820390.44316559249671; Wed, 28 Aug 2019 12:09:18 -0700 (PDT) Received: from localhost ([::1]:40894 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Jk-0006dE-Nv for importer@patchew.org; Wed, 28 Aug 2019 15:09:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37396) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Fi-0002ys-Jc for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33Fg-00086H-1I for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:06 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:40930) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33Ff-00085z-QC for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:03 -0400 Received: by mail-pg1-x542.google.com with SMTP id w10so216546pgj.7 for ; Wed, 28 Aug 2019 12:05:03 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=33zm58TIwdxjcCCsm2mwmZDQsqXbSGvtAgfMtmmrvjg=; b=KYP0s76QJ8P2BiQew3JWybT3963RaOvnyejUdMwpTyYy+TBnUe0Vfu02BnP9SbcCfi gLsQp4S1RaRDtDxAtgcMimZuhnEJebO/1nnMiNgonmNabMxj42iNATFl2U0AknAtPg47 lpS8RcuWa7I+wcPvUgsJeunTzgvJOqDeFsRpoP7sK+JO4NSAoqvqY9ViV+BriwT/G2Pr rzahkP6qvJ8viMGy6Un2AEZmhOwmU7xsrbvADSbG38rKj2madCoLBWz/UxkJ2KGPNI9D z8uMDqMGFtX3C8izxUs7wcqOaIpXzs7iwSkpp141SDfzM/KEl7kAcXnl0YYqTAqvriB0 um9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=33zm58TIwdxjcCCsm2mwmZDQsqXbSGvtAgfMtmmrvjg=; b=an0zZFKAudeAlOqE2i7bytEO32y9Lyzmq8SjhZVdOFZmmqVHuopyX1vsFJce/XqTwF 7tWoLEt0oIxltF54ggS8etM3BhBcJP2s5Gl6YZtGSzECsYKfT0S4f86TjLokCHAD8zef CBdAZyhO+VlQ1ZAqS/wsihizXtaAVy8EahZvcG06yywA5/I8Z/EbBf2TyPgS2tg49gm1 YOhq6S6PQsW5DEzVvn5hRL2oO/Wu9ZR/l7l+yGiKgGtwBYI5palGzeblabTpwkUfQjXK 41yd0un4om/46M0zEkcrTdtrILV9/gzqzfyqvJda/rhL7bhyHHxF3BK4x/EGeLLyLgeD ElUg== X-Gm-Message-State: APjAAAXQpQONp5AcO6gcrgNAr1h5i0EjGWOmeAPYfvDLjhLinNG0YUyG XF//qkXCKVsrj5qwcSA2wyPFXzWj4Rg= X-Google-Smtp-Source: APXvYqx0oEOwW5cSurvyCNbwffWW7buTcltA7fR36ePVH/2UnTOemiIf1NLrMCeQ6wOCCoCtEOmqCQ== X-Received: by 2002:a17:90a:9905:: with SMTP id b5mr2794124pjp.117.1567019102261; Wed, 28 Aug 2019 12:05:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:03:50 -0700 Message-Id: <20190828190456.30315-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 03/69] target/arm: Convert Data Processing (register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding for user/hyp check. --- target/arm/translate.c | 236 ++++++++++++++++++++++++++++++++++------- target/arm/a32.decode | 28 +++++ target/arm/t32.decode | 43 ++++++++ 3 files changed, 271 insertions(+), 36 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 91651b9736..a4606eacfb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7665,6 +7665,204 @@ static void arm_skip_unless(DisasContext *s, uint32= _t cond) #include "decode-a32-uncond.inc.c" #include "decode-t32.inc.c" =20 +/* Helpers to swap operands for reverse-subtract. */ +static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_sub_i32(dst, b, a); +} + +static void gen_rsb_CC(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) +{ + gen_sub_CC(dst, b, a); +} + +static void gen_rsc(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b) +{ + gen_sub_carry(dest, b, a); +} + +static void gen_rsc_CC(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b) +{ + gen_sbc_CC(dest, b, a); +} + +/* + * Helpers for the data processing routines. + * + * After the computation store the results back. + * This may be suppressed altogether (STREG_NONE), require a runtime + * check against the stack limits (STREG_SP_CHECK), or generate an + * exception return. Oh, or store into a register. + * + * Always return true, indicating success for a trans_* function. + */ +typedef enum { + STREG_NONE, + STREG_NORMAL, + STREG_SP_CHECK, + STREG_EXC_RET, +} StoreRegKind; + +static bool store_reg_kind(DisasContext *s, int rd, + TCGv_i32 val, StoreRegKind kind) +{ + switch (kind) { + case STREG_NONE: + tcg_temp_free_i32(val); + return true; + case STREG_NORMAL: + /* See ALUWritePC: Interworking only from a32 mode. */ + if (s->thumb) { + store_reg(s, rd, val); + } else { + store_reg_bx(s, rd, val); + } + return true; + case STREG_SP_CHECK: + store_sp_checked(s, val); + return true; + case STREG_EXC_RET: + gen_exception_return(s, val); + return true; + } + g_assert_not_reached(); +} + +/* + * Data Processing (register) + * + * Operate, with set flags, one register source, + * one immediate shifted register source, and a destination. + */ +static bool op_s_rrr_shi(DisasContext *s, arg_s_rrr_shi *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp2 =3D load_reg(s, a->rm); + gen_arm_shift_im(tmp2, a->shty, a->shim, logic_cc); + tmp1 =3D load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxr_shi(DisasContext *s, arg_s_rrr_shi *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp; + + tmp =3D load_reg(s, a->rm); + gen_arm_shift_im(tmp, a->shty, a->shim, logic_cc); + + gen(tmp, tmp); + if (logic_cc) { + gen_logic_CC(tmp); + } + return store_reg_kind(s, a->rd, tmp, kind); +} + +#define DO_ANY3(NAME, OP, L, K) \ + static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ + { StoreRegKind k =3D (K); return op_s_rrr_shi(s, a, OP, L, k); } + +#define DO_ANY2(NAME, OP, L, K) \ + static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ + { StoreRegKind k =3D (K); return op_s_rxr_shi(s, a, OP, L, k); } + +#define DO_CMP2(NAME, OP, L) \ + static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ + { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } + +DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) +DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) +DO_ANY3(ORR, tcg_gen_or_i32, a->s, STREG_NORMAL) +DO_ANY3(BIC, tcg_gen_andc_i32, a->s, STREG_NORMAL) + +DO_ANY3(RSB, a->s ? gen_rsb_CC : gen_rsb, false, STREG_NORMAL) +DO_ANY3(ADC, a->s ? gen_adc_CC : gen_add_carry, false, STREG_NORMAL) +DO_ANY3(SBC, a->s ? gen_sbc_CC : gen_sub_carry, false, STREG_NORMAL) +DO_ANY3(RSC, a->s ? gen_rsc_CC : gen_rsc, false, STREG_NORMAL) + +DO_CMP2(TST, tcg_gen_and_i32, true) +DO_CMP2(TEQ, tcg_gen_xor_i32, true) +DO_CMP2(CMN, gen_add_CC, false) +DO_CMP2(CMP, gen_sub_CC, false) + +DO_ANY3(ADD, a->s ? gen_add_CC : tcg_gen_add_i32, false, + a->rd =3D=3D 13 && a->rn =3D=3D 13 ? STREG_SP_CHECK : STREG_NORMAL) + +/* + * Note for the computation of StoreRegKind we return out of the + * middle of the functions that are expanded by DO_ANY3, and that + * we modify a->s via that parameter before it is used by OP. + */ +DO_ANY3(SUB, a->s ? gen_sub_CC : tcg_gen_sub_i32, false, + ({ + StoreRegKind ret =3D STREG_NORMAL; + if (a->rd =3D=3D 15 && a->s) { + /* + * See ALUExceptionReturn: + * In User mode, UNPREDICTABLE; we choose UNDEF. + * In Hyp mode, UNDEFINED. + */ + if (IS_USER(s) || s->current_el =3D=3D 2) { + unallocated_encoding(s); + return true; + } + /* There is no writeback of nzcv to PSTATE. */ + a->s =3D 0; + ret =3D STREG_EXC_RET; + } else if (a->rd =3D=3D 13 && a->rn =3D=3D 13) { + ret =3D STREG_SP_CHECK; + } + ret; + })) + +DO_ANY2(MOV, tcg_gen_mov_i32, a->s, + ({ + StoreRegKind ret =3D STREG_NORMAL; + if (a->rd =3D=3D 15 && a->s) { + /* + * See ALUExceptionReturn: + * In User mode, UNPREDICTABLE; we choose UNDEF. + * In Hyp mode, UNDEFINED. + */ + if (IS_USER(s) || s->current_el =3D=3D 2) { + unallocated_encoding(s); + return true; + } + /* There is no writeback of nzcv to PSTATE. */ + a->s =3D 0; + ret =3D STREG_EXC_RET; + } else if (a->rd =3D=3D 13) { + ret =3D STREG_SP_CHECK; + } + ret; + })) + +DO_ANY2(MVN, tcg_gen_not_i32, a->s, STREG_NORMAL) + +/* + * ORN is only available with T32, so there is no register-shifted-register + * form of the insn. Using the DO_ANY3 macro would create an unused funct= ion. + */ +static bool trans_ORN_rrri(DisasContext *s, arg_s_rrr_shi *a) +{ + return op_s_rrr_shi(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); +} + +#undef DO_ANY3 +#undef DO_ANY2 +#undef DO_CMP2 + /* * Legacy decoder. */ @@ -9270,13 +9468,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uin= t32_t pc, uint32_t insn) return true; } =20 -/* Return true if this is a Thumb-2 logical op. */ -static int -thumb2_logic_op(int op) -{ - return (op < 8); -} - /* Generate code for a Thumb-2 data processing operation. If CONDS is non= zero then set condition code flags based on the result of the operation. If SHIFTER_OUT is nonzero then set the carry flag for logical operations @@ -9364,8 +9555,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32= _t insn) TCGv_i32 addr; TCGv_i64 tmp64; int op; - int shiftop; - int conds; int logic_cc; =20 /* @@ -9795,33 +9984,8 @@ static void disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) store_reg(s, rd, tmp); } else { /* Data processing register constant shift. */ - if (rn =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp =3D load_reg(s, rn); - } - tmp2 =3D load_reg(s, rm); - - shiftop =3D (insn >> 4) & 3; - shift =3D ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); - conds =3D (insn & (1 << 20)) !=3D 0; - logic_cc =3D (conds && thumb2_logic_op(op)); - gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); - if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2)) - goto illegal_op; - tcg_temp_free_i32(tmp2); - if (rd =3D=3D 13 && - ((op =3D=3D 2 && rn =3D=3D 15) || - (op =3D=3D 8 && rn =3D=3D 13) || - (op =3D=3D 13 && rn =3D=3D 13))) { - /* MOV SP, ... or ADD SP, SP, ... or SUB SP, SP, ... */ - store_sp_checked(s, tmp); - } else if (rd !=3D 15) { - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } break; case 13: /* Misc data processing. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index a3e6e8c1c2..b23e83f17c 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -21,3 +21,31 @@ # All of the insn that have a COND field in insn[31:28] are here. # All insns that have 0xf in insn[31:28] are in a32-uncond.decode. # + +&s_rrr_shi s rd rn rm shim shty + +# Data-processing (register) + +@s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \ + &s_rrr_shi +@s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \ + &s_rrr_shi rn=3D0 +@S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \ + &s_rrr_shi s=3D1 rd=3D0 + +AND_rrri .... 000 0000 . .... .... ..... .. 0 .... @s_rrr_shi +EOR_rrri .... 000 0001 . .... .... ..... .. 0 .... @s_rrr_shi +SUB_rrri .... 000 0010 . .... .... ..... .. 0 .... @s_rrr_shi +RSB_rrri .... 000 0011 . .... .... ..... .. 0 .... @s_rrr_shi +ADD_rrri .... 000 0100 . .... .... ..... .. 0 .... @s_rrr_shi +ADC_rrri .... 000 0101 . .... .... ..... .. 0 .... @s_rrr_shi +SBC_rrri .... 000 0110 . .... .... ..... .. 0 .... @s_rrr_shi +RSC_rrri .... 000 0111 . .... .... ..... .. 0 .... @s_rrr_shi +TST_xrri .... 000 1000 1 .... 0000 ..... .. 0 .... @S_xrr_shi +TEQ_xrri .... 000 1001 1 .... 0000 ..... .. 0 .... @S_xrr_shi +CMP_xrri .... 000 1010 1 .... 0000 ..... .. 0 .... @S_xrr_shi +CMN_xrri .... 000 1011 1 .... 0000 ..... .. 0 .... @S_xrr_shi +ORR_rrri .... 000 1100 . .... .... ..... .. 0 .... @s_rrr_shi +MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi +BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi +MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ac01fb6958..7068596b99 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -18,3 +18,46 @@ # # This file is processed by scripts/decodetree.py # + +&s_rrr_shi !extern s rd rn rm shim shty + +# Data-processing (register) + +%imm5_12_6 12:3 6:2 + +@s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \ + &s_rrr_shi shim=3D%imm5_12_6 +@s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \ + &s_rrr_shi shim=3D%imm5_12_6 rn=3D0 +@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \ + &s_rrr_shi shim=3D%imm5_12_6 s=3D1 rd=3D0 + +{ + TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi + AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi +} +BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi +{ + MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi + ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi +} +{ + MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi + ORN_rrri 1110101 0011 . .... 0 ... .... .... .... @s_rrr_shi +} +{ + TEQ_xrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi + EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi +} +# PKHBT, PKHTB at opc1 =3D 0110 +{ + CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi + ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi +} +ADC_rrri 1110101 1010 . .... 0 ... .... .... .... @s_rrr_shi +SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi +{ + CMP_xrri 1110101 1101 1 .... 0 ... 1111 .... .... @S_xrr_shi + SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi +} +RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 04/69] target/arm: Convert Data Processing (reg-shifted-reg) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 74 ++++++++++++++++++++++++++++++------------ target/arm/a32.decode | 27 +++++++++++++++ target/arm/t32.decode | 6 ++++ 3 files changed, 87 insertions(+), 20 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index a4606eacfb..d8a341203b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7769,17 +7769,66 @@ static bool op_s_rxr_shi(DisasContext *s, arg_s_rrr= _shi *a, return store_reg_kind(s, a->rd, tmp, kind); } =20 +/* + * Data-processing (register-shifted register) + * + * Operate, with set flags, one register source, + * one register shifted register source, and a destination. + */ +static bool op_s_rrr_shr(DisasContext *s, arg_s_rrr_shr *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp1 =3D load_reg(s, a->rs); + tmp2 =3D load_reg(s, a->rm); + gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); + tmp1 =3D load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxr_shr(DisasContext *s, arg_s_rrr_shr *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp1 =3D load_reg(s, a->rs); + tmp2 =3D load_reg(s, a->rm); + gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); + + gen(tmp2, tmp2); + if (logic_cc) { + gen_logic_CC(tmp2); + } + return store_reg_kind(s, a->rd, tmp2, kind); +} + #define DO_ANY3(NAME, OP, L, K) \ static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ - { StoreRegKind k =3D (K); return op_s_rrr_shi(s, a, OP, L, k); } + { StoreRegKind k =3D (K); return op_s_rrr_shi(s, a, OP, L, k); } \ + static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \ + { StoreRegKind k =3D (K); return op_s_rrr_shr(s, a, OP, L, k); } =20 #define DO_ANY2(NAME, OP, L, K) \ static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ - { StoreRegKind k =3D (K); return op_s_rxr_shi(s, a, OP, L, k); } + { StoreRegKind k =3D (K); return op_s_rxr_shi(s, a, OP, L, k); } \ + static bool trans_##NAME##_rxrr(DisasContext *s, arg_s_rrr_shr *a) \ + { StoreRegKind k =3D (K); return op_s_rxr_shr(s, a, OP, L, k); } =20 #define DO_CMP2(NAME, OP, L) \ static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ - { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } + { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } \ + static bool trans_##NAME##_xrrr(DisasContext *s, arg_s_rrr_shr *a) \ + { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } =20 DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) @@ -9555,7 +9604,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32= _t insn) TCGv_i32 addr; TCGv_i64 tmp64; int op; - int logic_cc; =20 /* * ARMv6-M supports a limited subset of Thumb2 instructions. @@ -9993,22 +10041,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) if (op < 4 && (insn & 0xf000) !=3D 0xf000) goto illegal_op; switch (op) { - case 0: /* Register controlled shift. */ - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - if ((insn & 0x70) !=3D 0) - goto illegal_op; - /* - * 0b1111_1010_0xxx_xxxx_1111_xxxx_0000_xxxx: - * - MOV, MOVS (register-shifted register), flagsetting - */ - op =3D (insn >> 21) & 3; - logic_cc =3D (insn & (1 << 20)) !=3D 0; - gen_arm_shift_reg(tmp, op, tmp2, logic_cc); - if (logic_cc) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - break; + case 0: /* Register controlled shift, in decodetree */ + goto illegal_op; case 1: /* Sign/zero extend. */ op =3D (insn >> 20) & 7; switch (op) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index b23e83f17c..8e0fb06d05 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -23,6 +23,7 @@ # =20 &s_rrr_shi s rd rn rm shim shty +&s_rrr_shr s rn rd rm rs shty =20 # Data-processing (register) =20 @@ -49,3 +50,29 @@ ORR_rrri .... 000 1100 . .... .... ..... .. 0 ..= .. @s_rrr_shi MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi + +# Data-processing (register-shifted register) + +@s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \ + &s_rrr_shr +@s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \ + &s_rrr_shr rn=3D0 +@S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \ + &s_rrr_shr rd=3D0 s=3D1 + +AND_rrrr .... 000 0000 . .... .... .... 0 .. 1 .... @s_rrr_shr +EOR_rrrr .... 000 0001 . .... .... .... 0 .. 1 .... @s_rrr_shr +SUB_rrrr .... 000 0010 . .... .... .... 0 .. 1 .... @s_rrr_shr +RSB_rrrr .... 000 0011 . .... .... .... 0 .. 1 .... @s_rrr_shr +ADD_rrrr .... 000 0100 . .... .... .... 0 .. 1 .... @s_rrr_shr +ADC_rrrr .... 000 0101 . .... .... .... 0 .. 1 .... @s_rrr_shr +SBC_rrrr .... 000 0110 . .... .... .... 0 .. 1 .... @s_rrr_shr +RSC_rrrr .... 000 0111 . .... .... .... 0 .. 1 .... @s_rrr_shr +TST_xrrr .... 000 1000 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +TEQ_xrrr .... 000 1001 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +CMP_xrrr .... 000 1010 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +CMN_xrrr .... 000 1011 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .... @s_rrr_shr +MOV_rxrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr +BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr +MVN_rxrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 7068596b99..f0a73fa003 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -20,6 +20,7 @@ # =20 &s_rrr_shi !extern s rd rn rm shim shty +&s_rrr_shr !extern s rn rd rm rs shty =20 # Data-processing (register) =20 @@ -61,3 +62,8 @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... ....= @s_rrr_shi SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi } RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi + +# Data-processing (register-shifted register) + +MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ + &s_rrr_shr rn=3D0 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=B2A6/wpXJBux6uYypYFk2UWEy4WHVhRgcH9FGKQ+apQ=; b=j4xM/CNZTJpa80Nt7N0KtZ8+BGrCGhb5yUKc7dRqfcxyitTWYn86bha5ULcKsQdXdH APfD13V+l9wUM6H7VTxJkLjBTv3VVIpH378eMV0zB5+HTQ1+TdBJCXM/yg+ueKnSQqh4 9XwFHUtjIsXhnzBv/ulOH4Zbd+7pN4zcpTRYo7QBgg/P1Q/9W/WrRpwagOZi6QP1saGC w8NvwHQRKM9BDsZHAR5I3wWLP4tHZ3osQltnezVvFR/Z5Gs77Sz8JKVDGDcw48eUn0R/ PHur3Npu9pkbw0DqWlCuvJ05JeHpNjETi9WamKcKgbTEdgsCsXYpETVumnrD49PlKKpg oD2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=B2A6/wpXJBux6uYypYFk2UWEy4WHVhRgcH9FGKQ+apQ=; b=qy1P2H9VxH/7RayA562onagtydVqKpo6rsnskRACWAG574Dr+baCKna05skWvEnKo5 GMFTXVgGye9IQEUbIWaruJ1mNUPGULFFKXg/9In5DzWQ00FHcayMqENluse7pHmPPQF9 ksEQH9CBzGI6JeaZ6ql2wDPvZl40n3v3v+dd1U+tr+BJBuYK0qGTxILClT8ZT0Fx7Wvt OZ72wPaNeWRRKWNNnpZW2e+Ik/DzzGPaydZl97ysj45rJX4U7XKLIP5SqjWxR87xm5Ta C5X96wl77FF9XnmVoDh+sLSWxhnKFoiRrpf5Jjedm6SUuYQKutiS9a121Lx+vb2FOAfG hzYQ== X-Gm-Message-State: APjAAAXNSwUPkVNdMczZK3+JKfyUqBkRcaPLMQPfTbBMmGYa93Q1eY20 HCYC1zJnTFKxAsQJo8lWPBteAPbWKnY= X-Google-Smtp-Source: APXvYqw0x1BhDNq1nKk06YtBswxzFl/EnbdNLEAoJ0TsMscw/325hcry/GwqRl0Tsf4QHRf+X9jo6Q== X-Received: by 2002:a17:902:2f24:: with SMTP id s33mr5610012plb.314.1567019104969; Wed, 28 Aug 2019 12:05:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:03:52 -0700 Message-Id: <20190828190456.30315-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 05/69] target/arm: Convert Data Processing (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 449 +++++++++++------------------------------ target/arm/a32.decode | 29 +++ target/arm/t32.decode | 42 ++++ 3 files changed, 186 insertions(+), 334 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d8a341203b..d5689a16e2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -439,12 +439,6 @@ static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) tcg_temp_free_i32(t1); } =20 -/* Set CF to the top bit of var. */ -static void gen_set_CF_bit31(TCGv_i32 var) -{ - tcg_gen_shri_i32(cpu_CF, var, 31); -} - /* Set N and Z flags from var. */ static inline void gen_logic_CC(TCGv_i32 var) { @@ -857,25 +851,6 @@ void arm_gen_test_cc(int cc, TCGLabel *label) arm_free_cc(&cmp); } =20 -static const uint8_t table_logic_cc[16] =3D { - 1, /* and */ - 1, /* xor */ - 0, /* sub */ - 0, /* rsb */ - 0, /* add */ - 0, /* adc */ - 0, /* sbc */ - 0, /* rsc */ - 1, /* andl */ - 1, /* xorl */ - 0, /* cmp */ - 0, /* cmn */ - 1, /* orr */ - 1, /* mov */ - 1, /* bic */ - 1, /* mvn */ -}; - static inline void gen_set_condexec(DisasContext *s) { if (s->condexec_mask) { @@ -7657,6 +7632,48 @@ static void arm_skip_unless(DisasContext *s, uint32_= t cond) arm_gen_test_cc(cond ^ 1, s->condlabel); } =20 + +/* + * Constant expanders for the decoders. + */ + +static int times_2(DisasContext *s, int x) +{ + return x * 2; +} + +/* Return only the rotation part of T32ExpandImm. */ +static int t32_expandimm_rot(DisasContext *s, int x) +{ + return x & 0xc00 ? extract32(x, 7, 5) : 0; +} + +/* Return the unrotated immediate from T32ExpandImm. */ +static int t32_expandimm_imm(DisasContext *s, int x) +{ + int imm =3D extract32(x, 0, 8); + + switch (extract32(x, 8, 4)) { + case 0: /* XY */ + /* Nothing to do. */ + break; + case 1: /* 00XY00XY */ + imm *=3D 0x00010001; + break; + case 2: /* XY00XY00 */ + imm *=3D 0x01000100; + break; + case 3: /* XYXYXYXY */ + imm *=3D 0x01010101; + break; + default: + /* Rotated constant. */ + imm |=3D 0x80; + break; + } + return imm; +} + /* * Include the generated decoders. */ @@ -7812,23 +7829,82 @@ static bool op_s_rxr_shr(DisasContext *s, arg_s_rrr= _shr *a, return store_reg_kind(s, a->rd, tmp2, kind); } =20 +/* + * Data-processing (immediate) + * + * Operate, with set flags, one register source, + * one rotated immediate, and a destination. + * + * Note that logic_cc && a->rot setting CF based on the msb of the + * immediate is the reason why we must pass in the unrotated form + * of the immediate. + */ +static bool op_s_rri_rot(DisasContext *s, arg_s_rri_rot *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + uint32_t imm; + + imm =3D ror32(a->imm, a->rot); + if (logic_cc && a->rot) { + tcg_gen_movi_i32(cpu_CF, imm >> 31); + } + tmp2 =3D tcg_const_i32(imm); + tmp1 =3D load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxi_rot(DisasContext *s, arg_s_rri_rot *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp; + uint32_t imm; + + imm =3D ror32(a->imm, a->rot); + if (logic_cc && a->rot) { + tcg_gen_movi_i32(cpu_CF, imm >> 31); + } + tmp =3D tcg_const_i32(imm); + + gen(tmp, tmp); + if (logic_cc) { + gen_logic_CC(tmp); + } + return store_reg_kind(s, a->rd, tmp, kind); +} + #define DO_ANY3(NAME, OP, L, K) \ static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ { StoreRegKind k =3D (K); return op_s_rrr_shi(s, a, OP, L, k); } \ static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \ - { StoreRegKind k =3D (K); return op_s_rrr_shr(s, a, OP, L, k); } + { StoreRegKind k =3D (K); return op_s_rrr_shr(s, a, OP, L, k); } \ + static bool trans_##NAME##_rri(DisasContext *s, arg_s_rri_rot *a) \ + { StoreRegKind k =3D (K); return op_s_rri_rot(s, a, OP, L, k); } =20 #define DO_ANY2(NAME, OP, L, K) \ static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ { StoreRegKind k =3D (K); return op_s_rxr_shi(s, a, OP, L, k); } \ static bool trans_##NAME##_rxrr(DisasContext *s, arg_s_rrr_shr *a) \ - { StoreRegKind k =3D (K); return op_s_rxr_shr(s, a, OP, L, k); } + { StoreRegKind k =3D (K); return op_s_rxr_shr(s, a, OP, L, k); } \ + static bool trans_##NAME##_rxi(DisasContext *s, arg_s_rri_rot *a) \ + { StoreRegKind k =3D (K); return op_s_rxi_rot(s, a, OP, L, k); } =20 #define DO_CMP2(NAME, OP, L) \ static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } \ static bool trans_##NAME##_xrrr(DisasContext *s, arg_s_rrr_shr *a) \ - { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } + { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } \ + static bool trans_##NAME##_xri(DisasContext *s, arg_s_rri_rot *a) \ + { return op_s_rri_rot(s, a, OP, L, STREG_NONE); } =20 DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) @@ -7908,6 +7984,11 @@ static bool trans_ORN_rrri(DisasContext *s, arg_s_rr= r_shi *a) return op_s_rrr_shi(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); } =20 +static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a) +{ + return op_s_rri_rot(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); +} + #undef DO_ANY3 #undef DO_ANY2 #undef DO_CMP2 @@ -8445,182 +8526,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) } else if (((insn & 0x0e000000) =3D=3D 0 && (insn & 0x00000090) !=3D 0x90) || ((insn & 0x0e000000) =3D=3D (1 << 25))) { - int set_cc, logic_cc, shiftop; - - op1 =3D (insn >> 21) & 0xf; - set_cc =3D (insn >> 20) & 1; - logic_cc =3D table_logic_cc[op1] & set_cc; - - /* data processing instruction */ - if (insn & (1 << 25)) { - /* immediate operand */ - val =3D insn & 0xff; - shift =3D ((insn >> 8) & 0xf) * 2; - val =3D ror32(val, shift); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, val); - if (logic_cc && shift) { - gen_set_CF_bit31(tmp2); - } - } else { - /* register */ - rm =3D (insn) & 0xf; - tmp2 =3D load_reg(s, rm); - shiftop =3D (insn >> 5) & 3; - if (!(insn & (1 << 4))) { - shift =3D (insn >> 7) & 0x1f; - gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); - } else { - rs =3D (insn >> 8) & 0xf; - tmp =3D load_reg(s, rs); - gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc); - } - } - if (op1 !=3D 0x0f && op1 !=3D 0x0d) { - rn =3D (insn >> 16) & 0xf; - tmp =3D load_reg(s, rn); - } else { - tmp =3D NULL; - } - rd =3D (insn >> 12) & 0xf; - switch(op1) { - case 0x00: - tcg_gen_and_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x01: - tcg_gen_xor_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x02: - if (set_cc && rd =3D=3D 15) { - /* SUBS r15, ... is used for exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - gen_sub_CC(tmp, tmp, tmp2); - gen_exception_return(s, tmp); - } else { - if (set_cc) { - gen_sub_CC(tmp, tmp, tmp2); - } else { - tcg_gen_sub_i32(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - } - break; - case 0x03: - if (set_cc) { - gen_sub_CC(tmp, tmp2, tmp); - } else { - tcg_gen_sub_i32(tmp, tmp2, tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x04: - if (set_cc) { - gen_add_CC(tmp, tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x05: - if (set_cc) { - gen_adc_CC(tmp, tmp, tmp2); - } else { - gen_add_carry(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x06: - if (set_cc) { - gen_sbc_CC(tmp, tmp, tmp2); - } else { - gen_sub_carry(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x07: - if (set_cc) { - gen_sbc_CC(tmp, tmp2, tmp); - } else { - gen_sub_carry(tmp, tmp2, tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x08: - if (set_cc) { - tcg_gen_and_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - } - tcg_temp_free_i32(tmp); - break; - case 0x09: - if (set_cc) { - tcg_gen_xor_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - } - tcg_temp_free_i32(tmp); - break; - case 0x0a: - if (set_cc) { - gen_sub_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp); - break; - case 0x0b: - if (set_cc) { - gen_add_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp); - break; - case 0x0c: - tcg_gen_or_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x0d: - if (logic_cc && rd =3D=3D 15) { - /* MOVS r15, ... is used for exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - gen_exception_return(s, tmp2); - } else { - if (logic_cc) { - gen_logic_CC(tmp2); - } - store_reg_bx(s, rd, tmp2); - } - break; - case 0x0e: - tcg_gen_andc_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - default: - case 0x0f: - tcg_gen_not_i32(tmp2, tmp2); - if (logic_cc) { - gen_logic_CC(tmp2); - } - store_reg_bx(s, rd, tmp2); - break; - } - if (op1 !=3D 0x0f && op1 !=3D 0x0d) { - tcg_temp_free_i32(tmp2); - } + /* Data-processing (reg, reg-shift-reg, imm). */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { /* other instructions */ op1 =3D (insn >> 24) & 0xf; @@ -9517,82 +9425,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uin= t32_t pc, uint32_t insn) return true; } =20 -/* Generate code for a Thumb-2 data processing operation. If CONDS is non= zero - then set condition code flags based on the result of the operation. - If SHIFTER_OUT is nonzero then set the carry flag for logical operations - to the high bit of T1. - Returns zero if the opcode is valid. */ - -static int -gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_ou= t, - TCGv_i32 t0, TCGv_i32 t1) -{ - int logic_cc; - - logic_cc =3D 0; - switch (op) { - case 0: /* and */ - tcg_gen_and_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 1: /* bic */ - tcg_gen_andc_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 2: /* orr */ - tcg_gen_or_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 3: /* orn */ - tcg_gen_orc_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 4: /* eor */ - tcg_gen_xor_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 8: /* add */ - if (conds) - gen_add_CC(t0, t0, t1); - else - tcg_gen_add_i32(t0, t0, t1); - break; - case 10: /* adc */ - if (conds) - gen_adc_CC(t0, t0, t1); - else - gen_adc(t0, t1); - break; - case 11: /* sbc */ - if (conds) { - gen_sbc_CC(t0, t0, t1); - } else { - gen_sub_carry(t0, t0, t1); - } - break; - case 13: /* sub */ - if (conds) - gen_sub_CC(t0, t0, t1); - else - tcg_gen_sub_i32(t0, t0, t1); - break; - case 14: /* rsb */ - if (conds) - gen_sub_CC(t0, t1, t0); - else - tcg_gen_sub_i32(t0, t1, t0); - break; - default: /* 5, 6, 7, 9, 12, 15. */ - return 1; - } - if (logic_cc) { - gen_logic_CC(t0); - if (shifter_out) - gen_set_CF_bit31(t1); - } - return 0; -} - /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { @@ -10867,60 +10699,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } } } else { - /* - * 0b1111_0x0x_xxxx_0xxx_xxxx_xxxx - * - Data-processing (modified immediate) - */ - int shifter_out =3D 0; - /* modified 12-bit immediate. */ - shift =3D ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >= > 12); - imm =3D (insn & 0xff); - switch (shift) { - case 0: /* XY */ - /* Nothing to do. */ - break; - case 1: /* 00XY00XY */ - imm |=3D imm << 16; - break; - case 2: /* XY00XY00 */ - imm |=3D imm << 16; - imm <<=3D 8; - break; - case 3: /* XYXYXYXY */ - imm |=3D imm << 16; - imm |=3D imm << 8; - break; - default: /* Rotated constant. */ - shift =3D (shift << 1) | (imm >> 7); - imm |=3D 0x80; - imm =3D imm << (32 - shift); - shifter_out =3D 1; - break; - } - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, imm); - rn =3D (insn >> 16) & 0xf; - if (rn =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp =3D load_reg(s, rn); - } - op =3D (insn >> 21) & 0xf; - if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) !=3D 0, - shifter_out, tmp, tmp2)) - goto illegal_op; - tcg_temp_free_i32(tmp2); - rd =3D (insn >> 8) & 0xf; - if (rd =3D=3D 13 && rn =3D=3D 13 - && (op =3D=3D 8 || op =3D=3D 13)) { - /* ADD(S) SP, SP, imm or SUB(S) SP, SP, imm */ - store_sp_checked(s, tmp); - } else if (rd !=3D 15) { - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } + /* Data-processing (modified immediate) */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } } break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 8e0fb06d05..286adcbf89 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -24,6 +24,7 @@ =20 &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty +&s_rri_rot s rn rd imm rot =20 # Data-processing (register) =20 @@ -76,3 +77,31 @@ ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .= ... @s_rrr_shr MOV_rxrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr MVN_rxrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr + +# Data-processing (immediate) + +%a32extrot 8:4 !function=3Dtimes_2 + +@s_rri_rot ---- ... .... s:1 rn:4 rd:4 .... imm:8 \ + &s_rri_rot rot=3D%a32extrot +@s_rxi_rot ---- ... .... s:1 .... rd:4 .... imm:8 \ + &s_rri_rot rot=3D%a32extrot rn=3D0 +@S_xri_rot ---- ... .... . rn:4 .... .... imm:8 \ + &s_rri_rot rot=3D%a32extrot rd=3D0 s=3D1 + +AND_rri .... 001 0000 . .... .... ............ @s_rri_rot +EOR_rri .... 001 0001 . .... .... ............ @s_rri_rot +SUB_rri .... 001 0010 . .... .... ............ @s_rri_rot +RSB_rri .... 001 0011 . .... .... ............ @s_rri_rot +ADD_rri .... 001 0100 . .... .... ............ @s_rri_rot +ADC_rri .... 001 0101 . .... .... ............ @s_rri_rot +SBC_rri .... 001 0110 . .... .... ............ @s_rri_rot +RSC_rri .... 001 0111 . .... .... ............ @s_rri_rot +TST_xri .... 001 1000 1 .... 0000 ............ @S_xri_rot +TEQ_xri .... 001 1001 1 .... 0000 ............ @S_xri_rot +CMP_xri .... 001 1010 1 .... 0000 ............ @S_xri_rot +CMN_xri .... 001 1011 1 .... 0000 ............ @S_xri_rot +ORR_rri .... 001 1100 . .... .... ............ @s_rri_rot +MOV_rxi .... 001 1101 . 0000 .... ............ @s_rxi_rot +BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot +MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f0a73fa003..50cbe48cc8 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -21,6 +21,7 @@ =20 &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty +&s_rri_rot !extern s rn rd imm rot =20 # Data-processing (register) =20 @@ -67,3 +68,44 @@ RSB_rrri 1110101 1110 . .... 0 ... .... .... ...= . @s_rrr_shi =20 MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ &s_rrr_shr rn=3D0 + +# Data-processing (immediate) + +%t32extrot 26:1 12:3 0:8 !function=3Dt32_expandimm_rot +%t32extimm 26:1 12:3 0:8 !function=3Dt32_expandimm_imm + +@s_rri_rot ....... .... s:1 rn:4 . ... rd:4 ........ \ + &s_rri_rot imm=3D%t32extimm rot=3D%t32extrot +@s_rxi_rot ....... .... s:1 .... . ... rd:4 ........ \ + &s_rri_rot imm=3D%t32extimm rot=3D%t32extrot rn=3D0 +@S_xri_rot ....... .... . rn:4 . ... .... ........ \ + &s_rri_rot imm=3D%t32extimm rot=3D%t32extrot s=3D1 rd=3D0 + +{ + TST_xri 1111 0.0 0000 1 .... 0 ... 1111 ........ @S_xri_rot + AND_rri 1111 0.0 0000 . .... 0 ... .... ........ @s_rri_rot +} +BIC_rri 1111 0.0 0001 . .... 0 ... .... ........ @s_rri_rot +{ + MOV_rxi 1111 0.0 0010 . 1111 0 ... .... ........ @s_rxi_rot + ORR_rri 1111 0.0 0010 . .... 0 ... .... ........ @s_rri_rot +} +{ + MVN_rxi 1111 0.0 0011 . 1111 0 ... .... ........ @s_rxi_rot + ORN_rri 1111 0.0 0011 . .... 0 ... .... ........ @s_rri_rot +} +{ + TEQ_xri 1111 0.0 0100 1 .... 0 ... 1111 ........ @S_xri_rot + EOR_rri 1111 0.0 0100 . .... 0 ... .... ........ @s_rri_rot +} +{ + CMN_xri 1111 0.0 1000 1 .... 0 ... 1111 ........ @S_xri_rot + ADD_rri 1111 0.0 1000 . .... 0 ... .... ........ @s_rri_rot +} +ADC_rri 1111 0.0 1010 . .... 0 ... .... ........ @s_rri_rot +SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot +{ + CMP_xri 1111 0.0 1101 1 .... 0 ... 1111 ........ @S_xri_rot + SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot +} +RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::531 Subject: [Qemu-devel] [PATCH v3 06/69] target/arm: Convert multiply and multiply accumulate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 248 +++++++++++++++++++++++------------------ target/arm/a32.decode | 17 +++ target/arm/t32.decode | 19 ++++ 3 files changed, 177 insertions(+), 107 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d5689a16e2..b7845d825b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7993,6 +7993,125 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rr= i_rot *a) #undef DO_ANY2 #undef DO_CMP2 =20 +/* + * Multiply and multiply accumulate + */ + +static bool op_mla(DisasContext *s, arg_s_rrrr *a, bool add) +{ + TCGv_i32 t1, t2; + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + tcg_gen_mul_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + if (add) { + t2 =3D load_reg(s, a->ra); + tcg_gen_add_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + } + if (a->s) { + gen_logic_CC(t1); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_MUL(DisasContext *s, arg_MUL *a) +{ + return op_mla(s, a, false); +} + +static bool trans_MLA(DisasContext *s, arg_MLA *a) +{ + return op_mla(s, a, true); +} + +static bool trans_MLS(DisasContext *s, arg_MLS *a) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6T2) { + return false; + } + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + tcg_gen_mul_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + t2 =3D load_reg(s, a->ra); + tcg_gen_sub_i32(t1, t2, t1); + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool op_mlal(DisasContext *s, arg_s_rrrr *a, bool uns, bool add) +{ + TCGv_i32 t0, t1, t2, t3; + + t0 =3D load_reg(s, a->rm); + t1 =3D load_reg(s, a->rn); + if (uns) { + tcg_gen_mulu2_i32(t0, t1, t0, t1); + } else { + tcg_gen_muls2_i32(t0, t1, t0, t1); + } + if (add) { + t2 =3D load_reg(s, a->ra); + t3 =3D load_reg(s, a->rd); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + } + if (a->s) { + gen_logicq_cc(t0, t1); + } + store_reg(s, a->ra, t0); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_UMULL(DisasContext *s, arg_UMULL *a) +{ + return op_mlal(s, a, true, false); +} + +static bool trans_SMULL(DisasContext *s, arg_SMULL *a) +{ + return op_mlal(s, a, false, false); +} + +static bool trans_UMLAL(DisasContext *s, arg_UMLAL *a) +{ + return op_mlal(s, a, true, true); +} + +static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a) +{ + return op_mlal(s, a, false, true); +} + +static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 =3D load_reg(s, a->rm); + t1 =3D load_reg(s, a->rn); + t64 =3D gen_mulu_i64_i32(t0, t1); + gen_addq_lo(s, t64, a->ra); + gen_addq_lo(s, t64, a->rd); + gen_storeq_reg(s, a->ra, a->rd, t64); + tcg_temp_free_i64(t64); + return true; +} + /* * Legacy decoder. */ @@ -8539,71 +8658,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) sh =3D (insn >> 5) & 3; if (sh =3D=3D 0) { if (op1 =3D=3D 0x0) { - rd =3D (insn >> 16) & 0xf; - rn =3D (insn >> 12) & 0xf; - rs =3D (insn >> 8) & 0xf; - rm =3D (insn) & 0xf; - op1 =3D (insn >> 20) & 0xf; - switch (op1) { - case 0: case 1: case 2: case 3: case 6: - /* 32 bit mul */ - tmp =3D load_reg(s, rs); - tmp2 =3D load_reg(s, rm); - tcg_gen_mul_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (insn & (1 << 22)) { - /* Subtract (mls) */ - ARCH(6T2); - tmp2 =3D load_reg(s, rn); - tcg_gen_sub_i32(tmp, tmp2, tmp); - tcg_temp_free_i32(tmp2); - } else if (insn & (1 << 21)) { - /* Add */ - tmp2 =3D load_reg(s, rn); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - if (insn & (1 << 20)) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - break; - case 4: - /* 64 bit mul double accumulate (UMAAL) */ - ARCH(6); - tmp =3D load_reg(s, rs); - tmp2 =3D load_reg(s, rm); - tmp64 =3D gen_mulu_i64_i32(tmp, tmp2); - gen_addq_lo(s, tmp64, rn); - gen_addq_lo(s, tmp64, rd); - gen_storeq_reg(s, rn, rd, tmp64); - tcg_temp_free_i64(tmp64); - break; - case 8: case 9: case 10: case 11: - case 12: case 13: case 14: case 15: - /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */ - tmp =3D load_reg(s, rs); - tmp2 =3D load_reg(s, rm); - if (insn & (1 << 22)) { - tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2); - } else { - tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2); - } - if (insn & (1 << 21)) { /* mult accumulate */ - TCGv_i32 al =3D load_reg(s, rn); - TCGv_i32 ah =3D load_reg(s, rd); - tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, al, ah); - tcg_temp_free_i32(al); - tcg_temp_free_i32(ah); - } - if (insn & (1 << 20)) { - gen_logicq_cc(tmp, tmp2); - } - store_reg(s, rn, tmp); - store_reg(s, rd, tmp2); - break; - default: - goto illegal_op; - } + /* Multiply and multiply accumulate. */ + /* All done in decodetree. Reach here for illegal ops= . */ + goto illegal_op; } else { rn =3D (insn >> 16) & 0xf; rd =3D (insn >> 12) & 0xf; @@ -10040,7 +10097,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. = */ switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ + case 0: /* 32 x 32 -> 32, in decodetree */ + goto illegal_op; case 7: /* Unsigned sum of absolute differences. */ break; case 1: /* 16 x 16 -> 32 */ @@ -10057,18 +10115,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tmp =3D load_reg(s, rn); tmp2 =3D load_reg(s, rm); switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ - tcg_gen_mul_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rs !=3D 15) { - tmp2 =3D load_reg(s, rs); - if (op) - tcg_gen_sub_i32(tmp, tmp2, tmp); - else - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 1: /* 16 x 16 -> 32 */ gen_mulxy(tmp, tmp2, op & 2, op & 1); tcg_temp_free_i32(tmp2); @@ -10191,36 +10237,24 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) gen_storeq_reg(s, rs, rd, tmp64); tcg_temp_free_i64(tmp64); } else { - if (op & 0x20) { - /* Unsigned 64-bit multiply */ - tmp64 =3D gen_mulu_i64_i32(tmp, tmp2); - } else { - if (op & 8) { - /* smlalxy */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - gen_mulxy(tmp, tmp2, op & 2, op & 1); - tcg_temp_free_i32(tmp2); - tmp64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - } else { - /* Signed 64-bit multiply */ - tmp64 =3D gen_muls_i64_i32(tmp, tmp2); - } + if ((op & 0x20) || !(op & 8)) { + /* Signed/unsigned 64-bit multiply, in decodetree */ + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + goto illegal_op; } - if (op & 4) { - /* umaal */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i64(tmp64); - goto illegal_op; - } - gen_addq_lo(s, tmp64, rs); - gen_addq_lo(s, tmp64, rd); - } else if (op & 0x40) { + /* smlalxy */ + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + goto illegal_op; + } + gen_mulxy(tmp, tmp2, op & 2, op & 1); + tcg_temp_free_i32(tmp2); + tmp64 =3D tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(tmp64, tmp); + tcg_temp_free_i32(tmp); + if (op & 0x40) { /* 64-bit accumulate. */ gen_addq(s, tmp64, rs, rd); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 286adcbf89..87bbb2eec2 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -25,6 +25,8 @@ &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty &s_rri_rot s rn rd imm rot +&s_rrrr s rd rn rm ra +&rrrr rd rn rm ra =20 # Data-processing (register) =20 @@ -105,3 +107,18 @@ ORR_rri .... 001 1100 . .... .... ...........= . @s_rri_rot MOV_rxi .... 001 1101 . 0000 .... ............ @s_rxi_rot BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot + +# Multiply and multiply accumulate + +@s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr +@s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra= =3D0 +@rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr + +MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn +MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn +UMAAL .... 0000 010 0 .... .... .... 1001 .... @rdamn +MLS .... 0000 011 0 .... .... .... 1001 .... @rdamn +UMULL .... 0000 100 . .... .... .... 1001 .... @s_rdamn +UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn +SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn +SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 50cbe48cc8..40cc69aee3 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -22,6 +22,8 @@ &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot +&s_rrrr !extern s rd rn rm ra +&rrrr !extern rd rn rm ra =20 # Data-processing (register) =20 @@ -109,3 +111,20 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... .....= ... @s_rri_rot SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot } RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot + +# Multiply and multiply accumulate + +@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 +@s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra= =3D0 s=3D0 +@rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr + +{ + MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm + MLA 1111 1011 0000 .... .... .... 0000 .... @s0_rnadm +} +MLS 1111 1011 0000 .... .... .... 0001 .... @rnadm +SMULL 1111 1011 1000 .... .... .... 0000 .... @s0_rnadm +UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm +SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm +UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm +UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y5yPfgEriWWma7y9hU2/xgK2vFUjf1uQUjpsxHdDPIY=; b=yMq3/iJIs+X2hHMLBXGUONjwOV07estLLoofNW7mzhCS/ghswkzmTIi3WUGIcYUTY1 y1eUDawNAjO1pMYfz3OVEneK59MGv/0jvXXD23idfG478JSMENqsjmhKk/+0hO9jmpMs TzuhF7InGuX9Q71WkNMmRUTH238lmfyJEQpZpbqoXNDcxjjrDaMoa3gZ74bw/HnRPDy5 eToc6DPH3Th2Zq6+YdrbImTra3GGD7tD/YZFOrZBzbw9xWyGni9xg6VKwM64CSf6UfaO ksBohpHL+SvbOGp2OGv2tV7lvw4PdhqHKNRe3h200BpT6HC6RS7L5wAl+L/y0ok0Fhow 7XBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y5yPfgEriWWma7y9hU2/xgK2vFUjf1uQUjpsxHdDPIY=; b=FagH1sApOul13wQXfVGlaQ0snqnJ/EFGLyxxpv15Kz9zjp7JryVv/Mf89KnVAyQ6mC 6uTihRwZuJ8v9sfjD2cUHTew59YdD6v3D8tXgG1MgMYYBCW4E5O8nSjD/clGNNYKwwxa ZA7Ub0jK6t9Bu14gxVzy1rbIng9+Y8uTYqdbUfxK9lKBbPFp/jD2jujh2Nm/k6OEH/oB Y9pd2tQPtf1LBPTuthkJuFqSinYOF2e9E0fVuwFZ70vuTrPOgQ3ETugZ3MIl+7gs73X/ GWD4Xa+8TG5ejKLPjXXqic8aYmsz/I7Hnq9+Z8/4HVp5QDXWW2HHqCmPWAk9gvgEYy2t caqA== X-Gm-Message-State: APjAAAXXDqS2luBLq3hYNMdgrd/JYw0zTjLSanPG3+IiFmjC4XAF4/0N I3Qd1qWlVJgU+8j4GTQ705TnJVpxC0A= X-Google-Smtp-Source: APXvYqyg+3vJy+xt1536W63PlCsaw1VSsi1KCckuDkxhvyn1dmTKHyV6dYJ7VtkBUTQEhdAVnoRihg== X-Received: by 2002:a63:de4c:: with SMTP id y12mr4869451pgi.264.1567019107645; Wed, 28 Aug 2019 12:05:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:03:54 -0700 Message-Id: <20190828190456.30315-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 07/69] target/arm: Simplify UMAAL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_mulu2_i32 and tcg_gen_add2_i32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 34 ++++++++++++---------------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b7845d825b..17659627b1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7320,21 +7320,6 @@ static void gen_storeq_reg(DisasContext *s, int rlow= , int rhigh, TCGv_i64 val) store_reg(s, rhigh, tmp); } =20 -/* load a 32-bit value from a register and perform a 64-bit accumulate. */ -static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow) -{ - TCGv_i64 tmp; - TCGv_i32 tmp2; - - /* Load value and extend to 64 bits. */ - tmp =3D tcg_temp_new_i64(); - tmp2 =3D load_reg(s, rlow); - tcg_gen_extu_i32_i64(tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_gen_add_i64(val, val, tmp); - tcg_temp_free_i64(tmp); -} - /* load and add a 64-bit value from a register pair. */ static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) { @@ -8093,8 +8078,7 @@ static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a) =20 static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) { - TCGv_i32 t0, t1; - TCGv_i64 t64; + TCGv_i32 t0, t1, t2, zero; =20 if (s->thumb ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) @@ -8104,11 +8088,17 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL = *a) =20 t0 =3D load_reg(s, a->rm); t1 =3D load_reg(s, a->rn); - t64 =3D gen_mulu_i64_i32(t0, t1); - gen_addq_lo(s, t64, a->ra); - gen_addq_lo(s, t64, a->rd); - gen_storeq_reg(s, a->ra, a->rd, t64); - tcg_temp_free_i64(t64); + tcg_gen_mulu2_i32(t0, t1, t0, t1); + zero =3D tcg_const_i32(0); + t2 =3D load_reg(s, a->ra); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); + tcg_temp_free_i32(t2); + t2 =3D load_reg(s, a->rd); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(zero); + store_reg(s, a->ra, t0); + store_reg(s, a->rd, t1); return true; } =20 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567019866; cv=none; d=zoho.com; s=zohoarc; b=Y8xf7F/wB9sSeOKnWcQj0WUgY/ms/t338DzVF4bA2CAtzpmKi7N2LSyl2VazGTkR3/k7GlzVmwc8sWQJuTbcV9ht5vrA/dmKb93yaVbwMUoNQ9U9PEwjRteolaVT0steYP6k2gW03exjojuEdB3diMKXPMTSPZnuSsS9ioZ1S8g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567019866; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=apUZtrcjAYHXG/DQT2c+ZwTy4vc4Zs/04QzrnC09KMU=; b=iJVLkiKjN4M6xNON1t3fOTB8HmcZtG31VmupvkgyCoGlNod7tGV97sDMN7kWu/pOGLOq/2eVm1ZBbSMkUoqpY8/E+jjkpqIYayOtW6Rwy6hks0rj2fh/j9AV164Q+HGsFReUxNx5mr7hAPa71FbjnaAcTzBBxQUcrUz/1Uh0lN0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567019866084180.25301963092716; Wed, 28 Aug 2019 12:17:46 -0700 (PDT) Received: from localhost ([::1]:41066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Rw-0005xW-HM for importer@patchew.org; Wed, 28 Aug 2019 15:17:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37500) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Fp-00035j-1K for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33Fm-0008Er-Nc for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:12 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:44922) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33Fm-0008C8-Ag for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:10 -0400 Received: by mail-pl1-x629.google.com with SMTP id t14so383255plr.11 for ; Wed, 28 Aug 2019 12:05:10 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::629 Subject: [Qemu-devel] [PATCH v3 08/69] target/arm: Convert Saturating addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 75 +++++++++++++++++++++++++++--------------- target/arm/a32.decode | 10 ++++++ target/arm/t32.decode | 9 +++++ 3 files changed, 67 insertions(+), 27 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 17659627b1..70bbad48fc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8102,6 +8102,48 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *= a) return true; } =20 +/* + * Saturating addition and subtraction + */ + +static bool op_qaddsub(DisasContext *s, arg_rrr *a, bool add, bool doub) +{ + TCGv_i32 t0, t1; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_5TE) { + return false; + } + + t0 =3D load_reg(s, a->rm); + t1 =3D load_reg(s, a->rn); + if (doub) { + gen_helper_add_saturate(t1, cpu_env, t1, t1); + } + if (add) { + gen_helper_add_saturate(t0, cpu_env, t0, t1); + } else { + gen_helper_sub_saturate(t0, cpu_env, t0, t1); + } + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +#define DO_QADDSUB(NAME, ADD, DOUB) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_qaddsub(s, a, ADD, DOUB); \ +} + +DO_QADDSUB(QADD, true, false) +DO_QADDSUB(QSUB, false, false) +DO_QADDSUB(QDADD, true, true) +DO_QADDSUB(QDSUB, false, true) + +#undef DO_QADDSUB + /* * Legacy decoder. */ @@ -8511,21 +8553,10 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) store_reg(s, rd, tmp); break; } - case 0x5: /* saturating add/subtract */ - ARCH(5TE); - rd =3D (insn >> 12) & 0xf; - rn =3D (insn >> 16) & 0xf; - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rn); - if (op1 & 2) - gen_helper_add_saturate(tmp2, cpu_env, tmp2, tmp2); - if (op1 & 1) - gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2); - else - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + case 0x5: + /* Saturating addition and subtraction. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0x6: /* ERET */ if (op1 !=3D 3) { goto illegal_op; @@ -9989,18 +10020,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) op =3D ((insn >> 17) & 0x38) | ((insn >> 4) & 7); if (op < 4) { /* Saturating add/subtract. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - if (op & 1) - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp); - if (op & 2) - gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp); - else - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { switch (op) { case 0x0a: /* rbit */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 87bbb2eec2..7791be5590 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -27,6 +27,7 @@ &s_rri_rot s rn rd imm rot &s_rrrr s rd rn rm ra &rrrr rd rn rm ra +&rrr rd rn rm =20 # Data-processing (register) =20 @@ -122,3 +123,12 @@ UMULL .... 0000 100 . .... .... .... 1001 .= ... @s_rdamn UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn + +# Saturating addition and subtraction + +@rndm ---- .... .... rn:4 rd:4 .... .... rm:4 &rrr + +QADD .... 0001 0000 .... .... 0000 0101 .... @rndm +QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm +QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm +QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 40cc69aee3..7c6226e0af 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra +&rrr !extern rd rn rm =20 # Data-processing (register) =20 @@ -117,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ......= .. @s_rri_rot @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 @s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra= =3D0 s=3D0 @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr +@rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr =20 { MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm @@ -128,3 +130,10 @@ UMULL 1111 1011 1010 .... .... .... 0000 ..= .. @s0_rnadm SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm + +# Data-processing (two source registers) + +QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm +QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm +QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm +QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567020176; cv=none; d=zoho.com; s=zohoarc; b=L/kLORpO/u4yz1eLfbbRIV/ndjIjLemM3imx43l2paI9hUIf5Mn1u6vRCG/clntjuF2+Z/9adjM7Un4hR5ZDer6MKzyjNshK2RuCdbOLdva1pYdo9IuLEdkEcAXY7bC2Io5E1KlBwQuTGB7uxlXWIIEE7U3qa0KTfeaM1Htrt+M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567020176; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ry+lSTRq65PFYdHQdRgdWT07MSGGQsMfz5o03ct2Dk0=; b=X7SYZ3dnHjGRc5ktkRmVuGaitmtm9rCjTe3HqVpKkHNaUckZ2gjV/1WI98PFi0YnyJS/br9tm2ZxWW4QD3lY2mPoUUuv/QmPdMSNa8KLV+ECdRCzK3/DOlv5N4KT04kK8XymKZcl+pPlvUb/Ua0SsCfEk3AbQKaca8kkeh3LSh8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567020176296924.726641943832; Wed, 28 Aug 2019 12:22:56 -0700 (PDT) Received: from localhost ([::1]:41162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Ww-0002hk-KM for importer@patchew.org; Wed, 28 Aug 2019 15:22:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37563) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Fs-00038Z-1O for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33Fo-0008I6-Ol for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:15 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:35413) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33Fn-0008FN-Qz for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:12 -0400 Received: by mail-pg1-x541.google.com with SMTP id n4so231310pgv.2 for ; Wed, 28 Aug 2019 12:05:11 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 09/69] target/arm: Convert Halfword multiply and multiply accumulate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 218 +++++++++++++++++++++++------------------ target/arm/a32.decode | 20 ++++ target/arm/t32.decode | 29 ++++++ 3 files changed, 170 insertions(+), 97 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 70bbad48fc..58983ccf88 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8144,6 +8144,117 @@ DO_QADDSUB(QDSUB, false, true) =20 #undef DO_QADDSUB =20 +/* + * Halfword multiply and multiply accumulate + */ + +static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, + int add_long, bool nt, bool mt) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_5TE) { + return false; + } + + t0 =3D load_reg(s, a->rn); + t1 =3D load_reg(s, a->rm); + gen_mulxy(t0, t1, nt, mt); + tcg_temp_free_i32(t1); + + switch (add_long) { + case 0: + store_reg(s, a->rd, t0); + break; + case 1: + t1 =3D load_reg(s, a->ra); + gen_helper_add_setq(t0, cpu_env, t0, t1); + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + break; + case 2: + t64 =3D tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(t64, t0); + tcg_temp_free_i32(t0); + gen_addq(s, t64, a->ra, a->rd); + gen_storeq_reg(s, a->ra, a->rd, t64); + tcg_temp_free_i64(t64); + break; + default: + g_assert_not_reached(); + } + return true; +} + +#define DO_SMLAX(NAME, add, nt, mt) \ +static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \ +{ \ + return op_smlaxxx(s, a, add, nt, mt); \ +} + +DO_SMLAX(SMULBB, 0, 0, 0) +DO_SMLAX(SMULBT, 0, 0, 1) +DO_SMLAX(SMULTB, 0, 1, 0) +DO_SMLAX(SMULTT, 0, 1, 1) + +DO_SMLAX(SMLABB, 1, 0, 0) +DO_SMLAX(SMLABT, 1, 0, 1) +DO_SMLAX(SMLATB, 1, 1, 0) +DO_SMLAX(SMLATT, 1, 1, 1) + +DO_SMLAX(SMLALBB, 2, 0, 0) +DO_SMLAX(SMLALBT, 2, 0, 1) +DO_SMLAX(SMLALTB, 2, 1, 0) +DO_SMLAX(SMLALTT, 2, 1, 1) + +#undef DO_SMLAX + +static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (!ENABLE_ARCH_5TE) { + return false; + } + + t0 =3D load_reg(s, a->rn); + t1 =3D load_reg(s, a->rm); + if (mt) { + tcg_gen_sari_i32(t1, t1, 16); + } else { + gen_sxth(t1); + } + t64 =3D gen_muls_i64_i32(t0, t1); + tcg_gen_shri_i64(t64, t64, 16); + t1 =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t1, t64); + tcg_temp_free_i64(t64); + if (add) { + t0 =3D load_reg(s, a->ra); + gen_helper_add_setq(t1, cpu_env, t1, t0); + tcg_temp_free_i32(t0); + } + store_reg(s, a->rd, t1); + return true; +} + +#define DO_SMLAWX(NAME, add, mt) \ +static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \ +{ \ + return op_smlawx(s, a, add, mt); \ +} + +DO_SMLAWX(SMULWB, 0, 0) +DO_SMLAWX(SMULWT, 0, 1) +DO_SMLAWX(SMLAWB, 1, 0) +DO_SMLAWX(SMLAWT, 1, 1) + +#undef DO_SMLAWX + /* * Legacy decoder. */ @@ -8610,56 +8721,13 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) } break; } - case 0x8: /* signed multiply */ + case 0x8: case 0xa: case 0xc: case 0xe: - ARCH(5TE); - rs =3D (insn >> 8) & 0xf; - rn =3D (insn >> 12) & 0xf; - rd =3D (insn >> 16) & 0xf; - if (op1 =3D=3D 1) { - /* (32 * 16) >> 16 */ - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - if (sh & 4) - tcg_gen_sari_i32(tmp2, tmp2, 16); - else - gen_sxth(tmp2); - tmp64 =3D gen_muls_i64_i32(tmp, tmp2); - tcg_gen_shri_i64(tmp64, tmp64, 16); - tmp =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); - if ((sh & 2) =3D=3D 0) { - tmp2 =3D load_reg(s, rn); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - } else { - /* 16 * 16 */ - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - gen_mulxy(tmp, tmp2, sh & 2, sh & 4); - tcg_temp_free_i32(tmp2); - if (op1 =3D=3D 2) { - tmp64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - gen_addq(s, tmp64, rn, rd); - gen_storeq_reg(s, rn, rd, tmp64); - tcg_temp_free_i64(tmp64); - } else { - if (op1 =3D=3D 0) { - tmp2 =3D load_reg(s, rn); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - } - } - break; + /* Halfword multiply and multiply accumulate. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; default: goto illegal_op; } @@ -10108,13 +10176,14 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. = */ switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32, in decodetree */ + case 0: /* 32 x 32 -> 32 */ + case 1: /* 16 x 16 -> 32 */ + case 3: /* 32 * 16 -> 32msb */ + /* in decodetree */ goto illegal_op; case 7: /* Unsigned sum of absolute differences. */ break; - case 1: /* 16 x 16 -> 32 */ case 2: /* Dual multiply add. */ - case 3: /* 32 * 16 -> 32msb */ case 4: /* Dual multiply subtract. */ case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { @@ -10126,15 +10195,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tmp =3D load_reg(s, rn); tmp2 =3D load_reg(s, rm); switch ((insn >> 20) & 7) { - case 1: /* 16 x 16 -> 32 */ - gen_mulxy(tmp, tmp2, op & 2, op & 1); - tcg_temp_free_i32(tmp2); - if (rs !=3D 15) { - tmp2 =3D load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 2: /* Dual multiply add. */ case 4: /* Dual multiply subtract. */ if (op) @@ -10158,23 +10218,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tcg_temp_free_i32(tmp2); } break; - case 3: /* 32 * 16 -> 32msb */ - if (op) - tcg_gen_sari_i32(tmp2, tmp2, 16); - else - gen_sxth(tmp2); - tmp64 =3D gen_muls_i64_i32(tmp, tmp2); - tcg_gen_shri_i64(tmp64, tmp64, 16); - tmp =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); - if (rs !=3D 15) - { - tmp2 =3D load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); if (rs !=3D 15) { @@ -10248,29 +10291,10 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) gen_storeq_reg(s, rs, rd, tmp64); tcg_temp_free_i64(tmp64); } else { - if ((op & 0x20) || !(op & 8)) { - /* Signed/unsigned 64-bit multiply, in decodetree */ - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - /* smlalxy */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - gen_mulxy(tmp, tmp2, op & 2, op & 1); + /* Signed/unsigned 64-bit multiply, in decodetree */ tcg_temp_free_i32(tmp2); - tmp64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); tcg_temp_free_i32(tmp); - if (op & 0x40) { - /* 64-bit accumulate. */ - gen_addq(s, tmp64, rs, rd); - } - gen_storeq_reg(s, rs, rd, tmp64); - tcg_temp_free_i64(tmp64); + goto illegal_op; } break; } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 7791be5590..19d12e726b 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -114,6 +114,7 @@ MVN_rxi .... 001 1111 . 0000 .... ............= @s_rxi_rot @s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr @s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra= =3D0 @rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr +@rd0mn ---- .... ... . rd:4 .... rm:4 .... rn:4 &rrrr ra=3D0 =20 MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn @@ -132,3 +133,22 @@ QADD .... 0001 0000 .... .... 0000 0101 ..= .. @rndm QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm + +# Halfword multiply and multiply accumulate + +SMLABB .... 0001 0000 .... .... .... 1000 .... @rdamn +SMLABT .... 0001 0000 .... .... .... 1100 .... @rdamn +SMLATB .... 0001 0000 .... .... .... 1010 .... @rdamn +SMLATT .... 0001 0000 .... .... .... 1110 .... @rdamn +SMLAWB .... 0001 0010 .... .... .... 1000 .... @rdamn +SMULWB .... 0001 0010 .... 0000 .... 1010 .... @rd0mn +SMLAWT .... 0001 0010 .... .... .... 1100 .... @rdamn +SMULWT .... 0001 0010 .... 0000 .... 1110 .... @rd0mn +SMLALBB .... 0001 0100 .... .... .... 1000 .... @rdamn +SMLALBT .... 0001 0100 .... .... .... 1100 .... @rdamn +SMLALTB .... 0001 0100 .... .... .... 1010 .... @rdamn +SMLALTT .... 0001 0100 .... .... .... 1110 .... @rdamn +SMULBB .... 0001 0110 .... 0000 .... 1000 .... @rd0mn +SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn +SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn +SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 7c6226e0af..122a0537ed 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -118,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ......= .. @s_rri_rot @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 @s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra= =3D0 s=3D0 @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr +@rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=3D0 @rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr =20 { @@ -130,6 +131,34 @@ UMULL 1111 1011 1010 .... .... .... 0000 ..= .. @s0_rnadm SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm +{ + SMULWB 1111 1011 0011 .... 1111 .... 0000 .... @rn0dm + SMLAWB 1111 1011 0011 .... .... .... 0000 .... @rnadm +} +{ + SMULWT 1111 1011 0011 .... 1111 .... 0001 .... @rn0dm + SMLAWT 1111 1011 0011 .... .... .... 0001 .... @rnadm +} +{ + SMULBB 1111 1011 0001 .... 1111 .... 0000 .... @rn0dm + SMLABB 1111 1011 0001 .... .... .... 0000 .... @rnadm +} +{ + SMULBT 1111 1011 0001 .... 1111 .... 0001 .... @rn0dm + SMLABT 1111 1011 0001 .... .... .... 0001 .... @rnadm +} +{ + SMULTB 1111 1011 0001 .... 1111 .... 0010 .... @rn0dm + SMLATB 1111 1011 0001 .... .... .... 0010 .... @rnadm +} +{ + SMULTT 1111 1011 0001 .... 1111 .... 0011 .... @rn0dm + SMLATT 1111 1011 0001 .... .... .... 0011 .... @rnadm +} +SMLALBB 1111 1011 1100 .... .... .... 1000 .... @rnadm +SMLALBT 1111 1011 1100 .... .... .... 1001 .... @rnadm +SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm +SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm =20 # Data-processing (two source registers) =20 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VO3W9DH8N43psEbK5DhPL38cP8IqwAsRisCTRHkRmo0=; b=KjA6QUR6nHRZf6I+bVkPcfociKyMauAjE0flKOHl0ZsKmjwS76Ihi0WhkoTM4CYjYk 3ahHSdxrIHvLVvuV+l/u17TJNj51OW6px917/Bt4bVz3WL6Ka5A9OQPBe4psgOahx6xW 6yI3uhnq04Db+XW7ja/dqvpUias5pPPCn5hHK8p8e7qI1pwsLpBI/4h/HN+ECiYkMU7E RM7EzIrR4z6C0WHvB+vOy6kocsNgWCzMSNCgW/tYtMGIg7ltlx7/dS4vwef7YogVUdmJ SIxnka9OdTGl792W6/KEvKmHv5Z2hXPIDWK4gjLwE2j2tBj3bhsCPkPJg6WMg+rd2jd5 pVbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VO3W9DH8N43psEbK5DhPL38cP8IqwAsRisCTRHkRmo0=; b=EyLP/iNEQrmbP8c67DTx9Qvu2flA/iThiDoILGppNf7G/CMHcAr51HGogwCL9oM6Z3 0BPd5pgbNmkXrdXHJ4hD7Cifz7QUCpAffe1+Khlwkua6qe7rWCKcJfl13AZnOrCBJGQu 4ddOoZZKcDB5mHX58yV1fB+ybvxUd3/h1eKnM24Fo0tYTMDPqmnfITwYAMZ2QO1pwNHj B+sEYhI8a3IWKjYjE5d0vtCpE21ajS/SC0zi5rmQGHGftbMl28db29Zgz9erw2qgXmqO H1vzub/LZW46+2ISk82hHL+o5vXpQslQbiu9nyLDQjndtzSwKWowH9KuaxmMiIWQ+SBT uenw== X-Gm-Message-State: APjAAAVkXKdXZHVu8isyFcOg6SBp8iDZVb47fdog4Erhc2OZIzWxQui2 YCfqQ4wg7U29B9V2DaDOT3SaF54ZfkQ= X-Google-Smtp-Source: APXvYqxsBuwQqfDhlS389wsiUNKIIE8GeeGluu8x+1zrQ1GircnEVa3qT1CIeVlQOi+HK6ik9UD6og== X-Received: by 2002:a65:5b09:: with SMTP id y9mr4889095pgq.345.1567019111704; Wed, 28 Aug 2019 12:05:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:03:57 -0700 Message-Id: <20190828190456.30315-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 10/69] target/arm: Simplify op_smlaxxx for SMLAL* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_add2_i32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 58983ccf88..8813d40a2c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8151,8 +8151,7 @@ DO_QADDSUB(QDSUB, false, true) static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, int add_long, bool nt, bool mt) { - TCGv_i32 t0, t1; - TCGv_i64 t64; + TCGv_i32 t0, t1, tl, th; =20 if (s->thumb ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) @@ -8176,12 +8175,14 @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, store_reg(s, a->rd, t0); break; case 2: - t64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(t64, t0); + tl =3D load_reg(s, a->ra); + th =3D load_reg(s, a->rd); + t1 =3D tcg_const_i32(0); + tcg_gen_add2_i32(tl, th, tl, th, t0, t1); tcg_temp_free_i32(t0); - gen_addq(s, t64, a->ra, a->rd); - gen_storeq_reg(s, a->ra, a->rd, t64); - tcg_temp_free_i64(t64); + tcg_temp_free_i32(t1); + store_reg(s, a->ra, tl); + store_reg(s, a->rd, th); break; default: g_assert_not_reached(); --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567019966; cv=none; d=zoho.com; s=zohoarc; b=X7yZMJx91s4L2Nwya4qcGu8/bZu2ip0PFWaSzDD1oLvspMLZYBn82KNXVgdQd0wIVU5UJV3xXbyfUhbvoZSfsIrG6N8eh5vju89VG6mGhZF2KgmEwPm1yyJXGDrs7x8+DgrpczV84YI9aey21se9kpYkHlv+TFMYjqNDX7b+uAA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567019966; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=XK0pfbS5nVG6fwyWU5L/Wqmb0aEonSQXz/8cuqg+DQA=; b=Li/ehgNFw4xAeAIercqU4dKSbdXpyuFCJNUKBGqBvKqtOYvwuT2a90hPI8Gy3Jn4YbjqlQ7CvhUTdcrP7hbCPgGhp2Fev0SsVAej+wxR/G1OU7z/xcGoEOEqR/MjZbWs464YkhOimw8jlLQ28JkUp0PS4cF98eNPhH6t06LPyO0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15670199668761015.5437289960985; Wed, 28 Aug 2019 12:19:26 -0700 (PDT) Received: from localhost ([::1]:41080 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33TW-0007Tr-QW for importer@patchew.org; Wed, 28 Aug 2019 15:19:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37592) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Ft-00039r-6R for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33Fr-0008KI-CO for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:16 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:39426) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33Fr-0008JT-1G for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:15 -0400 Received: by mail-pf1-x444.google.com with SMTP id y200so389279pfb.6 for ; Wed, 28 Aug 2019 12:05:14 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 11/69] target/arm: Simplify op_smlawx for SMLAW* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" By shifting the 16-bit input left by 16, we can align the desired portion of the 48-bit product and use tcg_gen_muls2_i32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 8813d40a2c..fad07499d2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8216,7 +8216,6 @@ DO_SMLAX(SMLALTT, 2, 1, 1) static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) { TCGv_i32 t0, t1; - TCGv_i64 t64; =20 if (!ENABLE_ARCH_5TE) { return false; @@ -8224,16 +8223,17 @@ static bool op_smlawx(DisasContext *s, arg_rrrr *a,= bool add, bool mt) =20 t0 =3D load_reg(s, a->rn); t1 =3D load_reg(s, a->rm); + /* + * Since the nominal result is product<47:16>, shift the 16-bit + * input up by 16 bits, so that the result is at product<63:32>. + */ if (mt) { - tcg_gen_sari_i32(t1, t1, 16); + tcg_gen_andi_i32(t1, t1, 0xffff0000); } else { - gen_sxth(t1); + tcg_gen_shli_i32(t1, t1, 16); } - t64 =3D gen_muls_i64_i32(t0, t1); - tcg_gen_shri_i64(t64, t64, 16); - t1 =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, t64); - tcg_temp_free_i64(t64); + tcg_gen_muls2_i32(t0, t1, t0, t1); + tcg_temp_free_i32(t0); if (add) { t0 =3D load_reg(s, a->ra); gen_helper_add_setq(t1, cpu_env, t1, t0); --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567019828; cv=none; d=zoho.com; s=zohoarc; b=PiUR+P34O9XtVAaHMS7tHFr0m9JjrK/QWDqJVFawkfgaD35i1mtjCiTo5YYasBCW5pAzImSqCyXV0M1Z3NUfCuhCTkWYwnBZGaRndm4U3ybeeVXsPM5yIq/JX+4bebhqcUq/kliD68oCPibd2saPMXqEcqksDjmEFBo/xtkspUQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567019828; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=b8pLyu80ByK5bjQKITtTY/uW/k9pGohqmOEr3RJeigk=; b=NnWhHrY09ySumGbD+/x6VvUq8EeoX9r3qdcIn//7uwWmoiobvbzj/BYaRlH1s3+xvxZv/fjJ0B/GXIxtm2w8JrHQaS3ZU4jlOhSzv4vHbxgQc2Kd+NaQwzmfK9RS1B/5UUxyyuNd3hCAXrpUGw9z6RXFMFjHBMnewbnuBDY4tFA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567019828789530.8203705523889; Wed, 28 Aug 2019 12:17:08 -0700 (PDT) Received: from localhost ([::1]:41042 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33RK-0005Nn-JI for importer@patchew.org; Wed, 28 Aug 2019 15:17:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37700) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Fy-0003HZ-ON for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33Fs-0008LO-PG for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:22 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:35769) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33Fs-0008Kq-Bn for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:16 -0400 Received: by mail-pf1-x442.google.com with SMTP id d85so404543pfd.2 for ; Wed, 28 Aug 2019 12:05:16 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b8pLyu80ByK5bjQKITtTY/uW/k9pGohqmOEr3RJeigk=; b=FK+sZt64dEgio/3pfoLpi9DL1F7YWE2P0LT0q7GfMrJcc65LpUG8DrZY6oaTE/fGzn aEmhpu5MdgiiioBXKwHWmqDPAIJCQK1gtGZkpLEb7kqWx7Spx/1GOpFOZIgDj3vLHrEB eXVJB3QihgfgB81V7RIHdHIHXDg4SNHkRCzzEpOM2JlguN0dlFspFc2T0XhUf3glOHKl iA6m43zFnFbIgPTgN0BUcNYHBqYbTrKR/CY7lJer0Mz7YE835Hy3UGCIqHhQZAr0qfHk oA43UyOHhXPCtDV1StI4126QAkquj8b4N/94L0DHrWhfhC5OuAI/OfXlqhSwYxdRkuEd wChw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b8pLyu80ByK5bjQKITtTY/uW/k9pGohqmOEr3RJeigk=; b=qsg6EHgQeNrjJxkdjKZkGHwPH69k8euYRv4XvPSpmomY/pXQ2SJcce7urI1FOvI6Qa uDZzmzK+RqUtWUQVGaYNQ2edFfeOmQkKCTuJolv0tpXchXKXJ26XusgphB/psD/SIgDy oyi3lhSpyHNE5U8DxHRw7+baxJi1Vp+bN7bcjm8WN3AEm6ElMhDaxSmaaoBI+oGaUNAf gKnEfYgSe0PcXqqrR/RE1UcAEr7Vn9u+/c0lo44lT5GzpfQvANcfI+wzEsJsDfRjo/26 HdtXP4kMyno0tZWNizZiK41aYaOv95xEXD4ZrqM9yeiFIvmd3cafTEZ9r3+s7TR0kObA RlaA== X-Gm-Message-State: APjAAAW6LRifG9WV0oAgvOFyUZzbNBiYbPISjSjshQ17zxj6/AiA7aT0 EM4QyTmEf4Yfqa/7hfLuN+NAsxGt5ec= X-Google-Smtp-Source: APXvYqw2Qv/42HXUYwnFzAfTgfddkgU3sth6fdYmPUB3OlKNlR1BP0pA/R07jlVamSkaXJNxOOVrRw== X-Received: by 2002:a63:5945:: with SMTP id j5mr4740469pgm.452.1567019114863; Wed, 28 Aug 2019 12:05:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:03:59 -0700 Message-Id: <20190828190456.30315-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 12/69] target/arm: Convert MSR (immediate) and hints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 60 +++++++++++++++++++++++++++++------------- target/arm/a32.decode | 25 ++++++++++++++++++ target/arm/t32.decode | 17 ++++++++++++ 3 files changed, 84 insertions(+), 18 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index fad07499d2..d1599db2df 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8256,6 +8256,44 @@ DO_SMLAWX(SMLAWT, 1, 1) =20 #undef DO_SMLAWX =20 +/* + * MSR (immediate) and hints + */ + +static bool trans_YIELD(DisasContext *s, arg_YIELD *a) +{ + gen_nop_hint(s, 1); + return true; +} + +static bool trans_WFE(DisasContext *s, arg_WFE *a) +{ + gen_nop_hint(s, 2); + return true; +} + +static bool trans_WFI(DisasContext *s, arg_WFI *a) +{ + gen_nop_hint(s, 3); + return true; +} + +static bool trans_NOP(DisasContext *s, arg_NOP *a) +{ + return true; +} + +static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) +{ + uint32_t val =3D ror32(a->imm, a->rot * 2); + uint32_t mask =3D msr_mask(s, a->mask, a->r); + + if (gen_set_psr_im(s, mask, a->r, val)) { + unallocated_encoding(s); + } + return true; +} + /* * Legacy decoder. */ @@ -8529,21 +8567,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) } store_reg(s, rd, tmp); } else { - if (((insn >> 12) & 0xf) !=3D 0xf) - goto illegal_op; - if (((insn >> 16) & 0xf) =3D=3D 0) { - gen_nop_hint(s, insn & 0xff); - } else { - /* CPSR =3D immediate */ - val =3D insn & 0xff; - shift =3D ((insn >> 8) & 0xf) * 2; - val =3D ror32(val, shift); - i =3D ((insn & (1 << 22)) !=3D 0); - if (gen_set_psr_im(s, msr_mask(s, (insn >> 16) & 0xf, i), - i, val)) { - goto illegal_op; - } - } + /* MSR (immediate) and hints */ + /* All done in decodetree. Illegal ops already signalled. */ + g_assert_not_reached(); } } else if ((insn & 0x0f900000) =3D=3D 0x01000000 && (insn & 0x00000090) !=3D 0x00000090) { @@ -10480,9 +10506,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) goto illegal_op; break; case 2: /* cps, nop-hint. */ - if (((insn >> 8) & 7) =3D=3D 0) { - gen_nop_hint(s, insn & 0xff); - } + /* nop hints in decodetree */ /* Implemented as NOP in user mode. */ if (IS_USER(s)) break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 19d12e726b..3d5c5408f9 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -22,6 +22,7 @@ # All insns that have 0xf in insn[31:28] are in a32-uncond.decode. # =20 +&empty &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty &s_rri_rot s rn rd imm rot @@ -152,3 +153,27 @@ SMULBB .... 0001 0110 .... 0000 .... 1000 ..= .. @rd0mn SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn + +# MSR (immediate) and hints + +&msr_i r mask rot imm +@msr_i ---- .... .... mask:4 .... rot:4 imm:8 &msr_i + +{ + { + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + + # The canonical nop ends in 00000000, but the whole of the + # rest of the space executes as nop if otherwise unsupported. + NOP ---- 0011 0010 0000 1111 ---- ---- ---- + } + # Note mask =3D 0 is covered by NOP + MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=3D0 +} +MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=3D1 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 122a0537ed..ccb7cdd4ef 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -19,6 +19,7 @@ # This file is processed by scripts/decodetree.py # =20 +&empty !extern &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot @@ -166,3 +167,19 @@ QADD 1111 1010 1000 .... 1111 .... 1000 ..= .. @rndm QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm + +# Branches and miscellaneous control + +{ + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- +} --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567020296; cv=none; d=zoho.com; s=zohoarc; b=TMA75AqK3IBjNBsixwnY5jED+UXKI9ud/AO0bEMWXfctqJBV3fPKZC7SDqwBPw3mEwb5aQ7oEDd2HAc/AU5l5L5Ac5dxPlLFUJow0fYqNhcDSwn2aOt+IWUAr5KqCDJqynYEyynT34j4YG1mGKjf9MJcXL5p76j+MTK8xSoQjnU= ARC-Message-Signature: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hSDSzPPDS+CE4fLVLBTTY//0zE1tWf4F3OCm6ELFB/Q=; b=QdBkp5xqkAEMAEVMpK6z8+Ps9l3/sy8tGE2qpRq3Epc1xjbMumZx+vgO/6CPHY/iJY hkRb/irAEDPR0P3oMPrMYB3ebFrVaq7j0rpx0VbmrnD4ODoMaQoHvcFTYb8vkoVTi/5T X8XIkAlcZ6B6Vu4kzOwvpp9r/fd51ZLnkFePCKaYPSfT3oQIeEoIai0BkIyv/BAkwhfh I5ooSdknXMPplKdeDBWLTbhVdomj9z0KgKrOWEklzcbrNcOtz4/qVeG3N6xh99o3HAD/ NesQz1vgYp01rk89ecv3kAyj4CkKBYNtX9SekUMWLKT2wHyXFNZxEJz9RhC6iAb3wtKn MBDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hSDSzPPDS+CE4fLVLBTTY//0zE1tWf4F3OCm6ELFB/Q=; b=Vxp/2pMf7yqRzNSG3x2czUk4rXHiyUcQ405YFz2M11FhNpYMUqWJMKNHcWr9g8msiv 9ERUTuvcZIrBhlcXSFB0ziye3UUy4F9JCZ3SRdfCOt0+jiXjFAE7ahdwPOq31pl6V8mr R6WBqxb0n42k+/BYsOjsxRzGqf0xLq/m3uhqSDtu0QJCKrda7ZZIN3pNkePB7O7lJ78P R1SPMWDh6krPlt5D0qrwpDCeqZ0ZfgrQrM/TDlpnBLSqgrbHsvbZJagmtFTDEOfkvfqw +85zq+yzujS32hnpWX6hSrFyafwUvCEbx9/Nyp9TbCFoxeh9Y0plLgVh6fvSW09mPRgr hm5Q== X-Gm-Message-State: APjAAAWb/CdzF3JVZPjxNlZt6+55T37EQhR7lzs3LbFe+BPJ2Y/MFTEG GfVUNowtwVbuY+ecDDMdI77wNmbUHlU= X-Google-Smtp-Source: APXvYqxavGWLER2WN3xe2FIPypzXBejjZ1HcdU4DPW6HrhejwnDqLiFC+lZ1AKpCTwluS+aZZpaLQA== X-Received: by 2002:a17:902:9889:: with SMTP id s9mr5974869plp.100.1567019116435; Wed, 28 Aug 2019 12:05:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:00 -0700 Message-Id: <20190828190456.30315-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 13/69] target/arm: Convert MRS/MSR (banked, register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The m-profile and a-profile decodings overlap. Only return false for the case of wrong profile; handle UNDEFINED for permission failure directly. This ensures that we don't accidentally pass an insn that applies to the wrong profile. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 226 ++++++++++++++++++----------------------- target/arm/a32.decode | 14 +++ target/arm/t32.decode | 40 ++++++-- 3 files changed, 142 insertions(+), 138 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d1599db2df..491c8bdc8b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8294,6 +8294,93 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_i= mm *a) return true; } =20 +/* + * Miscellaneous instructions + */ + +static bool trans_MRS_bank(DisasContext *s, arg_MRS_bank *a) +{ + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_mrs_banked(s, a->r, a->sysm, a->rd); + return true; +} + +static bool trans_MSR_bank(DisasContext *s, arg_MSR_bank *a) +{ + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_msr_banked(s, a->r, a->sysm, a->rn); + return true; +} + +static bool trans_MRS_reg(DisasContext *s, arg_MRS_reg *a) +{ + TCGv_i32 tmp; + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (a->r) { + if (IS_USER(s)) { + unallocated_encoding(s); + return true; + } + tmp =3D load_cpu_field(spsr); + } else { + tmp =3D tcg_temp_new_i32(); + gen_helper_cpsr_read(tmp, cpu_env); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MSR_reg(DisasContext *s, arg_MSR_reg *a) +{ + TCGv_i32 tmp; + uint32_t mask =3D msr_mask(s, a->mask, a->r); + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tmp =3D load_reg(s, a->rn); + if (gen_set_psr(s, mask, a->r, tmp)) { + unallocated_encoding(s); + } + return true; +} + +static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a) +{ + TCGv_i32 tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tmp =3D tcg_const_i32(a->sysm); + gen_helper_v7m_mrs(tmp, cpu_env, tmp); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) +{ + TCGv_i32 addr, reg; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + addr =3D tcg_const_i32((a->mask << 10) | a->sysm); + reg =3D load_reg(s, a->rn); + gen_helper_v7m_msr(cpu_env, addr, reg); + tcg_temp_free_i32(addr); + tcg_temp_free_i32(reg); + gen_lookup_tb(s); + return true; +} + /* * Legacy decoder. */ @@ -8578,46 +8665,10 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) sh =3D (insn >> 4) & 0xf; rm =3D insn & 0xf; switch (sh) { - case 0x0: /* MSR, MRS */ - if (insn & (1 << 9)) { - /* MSR (banked) and MRS (banked) */ - int sysm =3D extract32(insn, 16, 4) | - (extract32(insn, 8, 1) << 4); - int r =3D extract32(insn, 22, 1); - - if (op1 & 1) { - /* MSR (banked) */ - gen_msr_banked(s, r, sysm, rm); - } else { - /* MRS (banked) */ - int rd =3D extract32(insn, 12, 4); - - gen_mrs_banked(s, r, sysm, rd); - } - break; - } - - /* MSR, MRS (for PSRs) */ - if (op1 & 1) { - /* PSR =3D reg */ - tmp =3D load_reg(s, rm); - i =3D ((op1 & 2) !=3D 0); - if (gen_set_psr(s, msr_mask(s, (insn >> 16) & 0xf, i), i, = tmp)) - goto illegal_op; - } else { - /* reg =3D PSR */ - rd =3D (insn >> 12) & 0xf; - if (op1 & 2) { - if (IS_USER(s)) - goto illegal_op; - tmp =3D load_cpu_field(spsr); - } else { - tmp =3D tcg_temp_new_i32(); - gen_helper_cpsr_read(tmp, cpu_env); - } - store_reg(s, rd, tmp); - } - break; + case 0x0: + /* MSR/MRS (banked/register) */ + /* All done in decodetree. Illegal ops already signalled. */ + g_assert_not_reached(); case 0x1: if (op1 =3D=3D 1) { /* branch/exchange thumb (bx). */ @@ -10471,40 +10522,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } else { op =3D (insn >> 20) & 7; switch (op) { - case 0: /* msr cpsr. */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - tmp =3D load_reg(s, rn); - /* the constant is the mask and SYSm fields */ - addr =3D tcg_const_i32(insn & 0xfff); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - tcg_temp_free_i32(tmp); - gen_lookup_tb(s); - break; - } - /* fall through */ - case 1: /* msr spsr. */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - - if (extract32(insn, 5, 1)) { - /* MSR (banked) */ - int sysm =3D extract32(insn, 8, 4) | - (extract32(insn, 4, 1) << 4); - int r =3D op & 1; - - gen_msr_banked(s, r, sysm, rm); - break; - } - - /* MSR (for PSRs) */ - tmp =3D load_reg(s, rn); - if (gen_set_psr(s, - msr_mask(s, (insn >> 8) & 0xf, op =3D=3D 1), - op =3D=3D 1, tmp)) - goto illegal_op; - break; + case 0: /* msr cpsr, in decodetree */ + case 1: /* msr spsr, in decodetree */ + goto illegal_op; case 2: /* cps, nop-hint. */ /* nop hints in decodetree */ /* Implemented as NOP in user mode. */ @@ -10596,61 +10616,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } gen_exception_return(s, tmp); break; - case 6: /* MRS */ - if (extract32(insn, 5, 1) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - /* MRS (banked) */ - int sysm =3D extract32(insn, 16, 4) | - (extract32(insn, 4, 1) << 4); - - gen_mrs_banked(s, 0, sysm, rd); - break; - } - - if (extract32(insn, 16, 4) !=3D 0xf) { - goto illegal_op; - } - if (!arm_dc_feature(s, ARM_FEATURE_M) && - extract32(insn, 0, 8) !=3D 0) { - goto illegal_op; - } - - /* mrs cpsr */ - tmp =3D tcg_temp_new_i32(); - if (arm_dc_feature(s, ARM_FEATURE_M)) { - addr =3D tcg_const_i32(insn & 0xff); - gen_helper_v7m_mrs(tmp, cpu_env, addr); - tcg_temp_free_i32(addr); - } else { - gen_helper_cpsr_read(tmp, cpu_env); - } - store_reg(s, rd, tmp); - break; - case 7: /* MRS */ - if (extract32(insn, 5, 1) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - /* MRS (banked) */ - int sysm =3D extract32(insn, 16, 4) | - (extract32(insn, 4, 1) << 4); - - gen_mrs_banked(s, 1, sysm, rd); - break; - } - - /* mrs spsr. */ - /* Not accessible in user mode. */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)= ) { - goto illegal_op; - } - - if (extract32(insn, 16, 4) !=3D 0xf || - extract32(insn, 0, 8) !=3D 0) { - goto illegal_op; - } - - tmp =3D load_cpu_field(spsr); - store_reg(s, rd, tmp); - break; + case 6: /* MRS, in decodetree */ + case 7: /* MSR, in decodetree */ + goto illegal_op; } } } else { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 3d5c5408f9..6ee12c1140 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,10 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&msr_reg rn r mask +&mrs_reg rd r +&msr_bank rn r sysm +&mrs_bank rd r sysm =20 # Data-processing (register) =20 @@ -177,3 +181,13 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 ..= .. @rd0mn MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=3D0 } MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=3D1 + +# Miscellaneous instructions + +%sysm 8:1 16:4 + +MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %s= ysm +MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %s= ysm + +MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg +MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ccb7cdd4ef..98b682e7ec 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,10 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&msr_reg !extern rn r mask +&mrs_reg !extern rd r +&msr_bank !extern rn r sysm +&mrs_bank !extern rd r sysm =20 # Data-processing (register) =20 @@ -170,16 +174,34 @@ QDSUB 1111 1010 1000 .... 1111 .... 1011 .= ... @rndm =20 # Branches and miscellaneous control =20 +%msr_sysm 4:1 8:4 +%mrs_sysm 4:1 16:4 + { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + { + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 - # The canonical nop ends in 0000 0000, but the whole rest - # of the space is "reserved hint, behaves as nop". - NOP 1111 0011 1010 1111 1000 0000 ---- ---- + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- + } + # Note that the v7m insn overlaps both the normal and banked insn. + { + MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ + &mrs_bank sysm=3D%mrs_sysm + MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg + MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 + } + { + MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ + &msr_bank sysm=3D%msr_sysm + MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg + MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 + } } --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 14/69] target/arm: Convert Cyclic Redundancy Check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 121 +++++++++++++++++++---------------------- target/arm/a32.decode | 9 +++ target/arm/t32.decode | 7 +++ 3 files changed, 72 insertions(+), 65 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 491c8bdc8b..c2420ff45e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8294,6 +8294,57 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_i= mm *a) return true; } =20 +/* + * Cyclic Redundancy Check + */ + +static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, TCGMemOp sz) +{ + TCGv_i32 t1, t2, t3; + + if (!dc_isar_feature(aa32_crc32, s)) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + switch (sz) { + case MO_8: + gen_uxtb(t2); + break; + case MO_16: + gen_uxth(t2); + break; + case MO_32: + break; + default: + g_assert_not_reached(); + } + t3 =3D tcg_const_i32(1 << sz); + if (c) { + gen_helper_crc32c(t1, t1, t2, t3); + } else { + gen_helper_crc32(t1, t1, t2, t3); + } + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + store_reg(s, a->rd, t1); + return true; +} + +#define DO_CRC32(NAME, c, sz) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ + { return op_crc32(s, a, c, sz); } + +DO_CRC32(CRC32B, false, MO_8) +DO_CRC32(CRC32H, false, MO_16) +DO_CRC32(CRC32W, false, MO_32) +DO_CRC32(CRC32CB, true, MO_8) +DO_CRC32(CRC32CH, true, MO_16) +DO_CRC32(CRC32CW, true, MO_32) + +#undef DO_CRC32 + /* * Miscellaneous instructions */ @@ -8709,39 +8760,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) gen_bx(s, tmp); break; case 0x4: - { - /* crc32/crc32c */ - uint32_t c =3D extract32(insn, 8, 4); - - /* Check this CPU supports ARMv8 CRC instructions. - * op1 =3D=3D 3 is UNPREDICTABLE but handle as UNDEFINED. - * Bits 8, 10 and 11 should be zero. - */ - if (!dc_isar_feature(aa32_crc32, s) || op1 =3D=3D 0x3 || (c & = 0xd) !=3D 0) { - goto illegal_op; - } - - rn =3D extract32(insn, 16, 4); - rd =3D extract32(insn, 12, 4); - - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - if (op1 =3D=3D 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (op1 =3D=3D 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 =3D tcg_const_i32(1 << op1); - if (c & 0x2) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - store_reg(s, rd, tmp); - break; - } + /* crc32 */ + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; case 0x5: /* Saturating addition and subtraction. */ /* All done in decodetree. Reach here for illegal ops. */ @@ -10181,16 +10202,13 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) goto illegal_op; } break; - case 0x20: /* crc32/crc32c */ + case 0x20: /* crc32/crc32c, in decodetree */ case 0x21: case 0x22: case 0x28: case 0x29: case 0x2a: - if (!dc_isar_feature(aa32_crc32, s)) { - goto illegal_op; - } - break; + goto illegal_op; default: goto illegal_op; } @@ -10219,33 +10237,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) case 0x18: /* clz */ tcg_gen_clzi_i32(tmp, tmp, 32); break; - case 0x20: - case 0x21: - case 0x22: - case 0x28: - case 0x29: - case 0x2a: - { - /* crc32/crc32c */ - uint32_t sz =3D op & 0x3; - uint32_t c =3D op & 0x8; - - tmp2 =3D load_reg(s, rm); - if (sz =3D=3D 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (sz =3D=3D 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 =3D tcg_const_i32(1 << sz); - if (c) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - break; - } default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 6ee12c1140..a8ef435b15 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -182,6 +182,15 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 ..= .. @rd0mn } MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=3D1 =20 +# Cyclic Redundancy Check + +CRC32B .... 0001 0000 .... .... 0000 0100 .... @rndm +CRC32H .... 0001 0010 .... .... 0000 0100 .... @rndm +CRC32W .... 0001 0100 .... .... 0000 0100 .... @rndm +CRC32CB .... 0001 0000 .... .... 0010 0100 .... @rndm +CRC32CH .... 0001 0010 .... .... 0010 0100 .... @rndm +CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm + # Miscellaneous instructions =20 %sysm 8:1 16:4 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 98b682e7ec..261db100ff 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -172,6 +172,13 @@ QSUB 1111 1010 1000 .... 1111 .... 1010 ..= .. @rndm QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm =20 +CRC32B 1111 1010 1100 .... 1111 .... 1000 .... @rndm +CRC32H 1111 1010 1100 .... 1111 .... 1001 .... @rndm +CRC32W 1111 1010 1100 .... 1111 .... 1010 .... @rndm +CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm +CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm +CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm + # Branches and miscellaneous control =20 %msr_sysm 4:1 8:4 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4BlHSKKgCoxdyyhEVII1opm34EFeT9rrl5mK0jjuq2M=; b=dIZQrwjTiTx3SgRVTJH6mdPA656tRn1XAECyK8OETWjgX/qUooFw5ZDQuExf4DWy+Q O7uAlZBLKivbgGj12tFuvEEIqt0QVWTAwtsrs0Jgb5ZyE6zXf6MeznN6BXUIcJshBRcU 6WbL5Z5hTMXfBodpynZUp6xN8zoWPoy1Y7OP97YkL1EmM5nYmibpZ2X3XAwprHZPj5Eq GXOWs2wH81oviaF6/DFlrkWv50t9XGQPA50Lq60X3sd5NuPK02uxwDi9Bu8bCPF9hNrw jaZOaW9npr3/lR2lDwLRVN7Vs9Hkmwu0fq70/qATGN8Zp/riTWFQRJYZRN1ficm5IpoZ pozw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4BlHSKKgCoxdyyhEVII1opm34EFeT9rrl5mK0jjuq2M=; b=Cvl6QCXTX3qJjQ20gsyTM96qGsqtMvxzVyEHpdO6UQXcG2kVz/t+BB6/ab2un2t62w ArJcEO2WJZVx+fx9oSb/flHNs4czliohW/BWojIWy3D/56Rfk1pHHzfINHMcFj/8r4cT eHiLTJ9//w7TlZIGk8MZ4euWo/14iKcJKX3pgHVFFa1DR7UWEvKz6vSrq182jijxTvH1 WBf1BDVSYVtniNT8NJk5Y9NIZIeT1bbbXQf9uSol9R7ykbD9f9odsu/ds3qvE9Vo8tDA iMCzBODAiuBG12r8Qrmvp7G8Y8oTN9rJYBTettMiTLhgfLfedfgl3VfTgxivLYKtKFoH eLpQ== X-Gm-Message-State: APjAAAVGS2KbLRC53sjbH90pf05OeAOw26QmcRx8I9FvTwWNl3kQxkoP FbZeMQr3DFvnLF10R2AAI/VaaA2uspM= X-Google-Smtp-Source: APXvYqxKHDSXXYpv3YJuY7m7kVqRAxmPZ39mVcI5otPpjd4OurkWhPc62CkvHWi+lrSHibO1nq4gkw== X-Received: by 2002:aa7:908b:: with SMTP id i11mr4165351pfa.199.1567019119118; Wed, 28 Aug 2019 12:05:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:02 -0700 Message-Id: <20190828190456.30315-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 15/69] target/arm: Convert BX, BXJ, BLX (register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 78 ++++++++++++++++++++---------------------- target/arm/a32.decode | 7 ++++ target/arm/t32.decode | 2 ++ 3 files changed, 47 insertions(+), 40 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index c2420ff45e..d60e859624 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8432,6 +8432,38 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v= 7m *a) return true; } =20 +static bool trans_BX(DisasContext *s, arg_BX *a) +{ + if (!ENABLE_ARCH_4T) { + return false; + } + gen_bx(s, load_reg(s, a->rm)); + return true; +} + +static bool trans_BXJ(DisasContext *s, arg_BXJ *a) +{ + if (!ENABLE_ARCH_5J || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + /* Trivial implementation equivalent to bx. */ + gen_bx(s, load_reg(s, a->rm)); + return true; +} + +static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_5) { + return false; + } + tmp =3D load_reg(s, a->rm); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_bx(s, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8721,12 +8753,7 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) /* All done in decodetree. Illegal ops already signalled. */ g_assert_not_reached(); case 0x1: - if (op1 =3D=3D 1) { - /* branch/exchange thumb (bx). */ - ARCH(4T); - tmp =3D load_reg(s, rm); - gen_bx(s, tmp); - } else if (op1 =3D=3D 3) { + if (op1 =3D=3D 3) { /* clz */ ARCH(5); rd =3D (insn >> 12) & 0xf; @@ -8737,30 +8764,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) goto illegal_op; } break; - case 0x2: - if (op1 =3D=3D 1) { - ARCH(5J); /* bxj */ - /* Trivial implementation equivalent to bx. */ - tmp =3D load_reg(s, rm); - gen_bx(s, tmp); - } else { - goto illegal_op; - } - break; - case 0x3: - if (op1 !=3D 1) - goto illegal_op; - - ARCH(5); - /* branch link/exchange thumb (blx) */ - tmp =3D load_reg(s, rm); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - break; - case 0x4: - /* crc32 */ + case 0x2: /* bxj */ + case 0x3: /* blx */ + case 0x4: /* crc32 */ /* All done in decodetree. Illegal ops reach here. */ goto illegal_op; case 0x5: @@ -10578,16 +10584,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) goto illegal_op; } break; - case 4: /* bxj */ - /* Trivial implementation equivalent to bx. - * This instruction doesn't exist at all for M-pro= file. - */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - tmp =3D load_reg(s, rn); - gen_bx(s, tmp); - break; + case 4: /* bxj, in decodetree */ + goto illegal_op; case 5: /* Exception return. */ if (IS_USER(s)) { goto illegal_op; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index a8ef435b15..6cb9c16e2f 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,7 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&r rm &msr_reg rn r mask &mrs_reg rd r &msr_bank rn r sysm @@ -195,8 +196,14 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 ..= .. @rndm =20 %sysm 8:1 16:4 =20 +@rm ---- .... .... .... .... .... .... rm:4 &r + MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %s= ysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %s= ysm =20 MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg + +BX .... 0001 0010 1111 1111 1111 0001 .... @rm +BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm +BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 261db100ff..337706ebbe 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,7 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&r !extern rm &msr_reg !extern rn r mask &mrs_reg !extern rd r &msr_bank !extern rn r sysm @@ -211,4 +212,5 @@ CRC32CW 1111 1010 1101 .... 1111 .... 1010 ...= . @rndm MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 } + BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r } --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567019867; cv=none; d=zoho.com; s=zohoarc; b=LGWa0GRTSvu1xtDMPmo5Vuh8VuH9QvJgD+lc+S26/CLRmTfae5xPnyQH5/0Gvo1RXSuJ4wPKoJoQ/Q1br8pz2oEYq0bufQPVBiR/Z2kdvknJNfSIEvJsg7CDKYMamHvuuZldug7ma3zGJlWwPxRC/XeLnNnGs1R8kg786OtJq4c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567019867; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=0LZRj16kFkT1uXjnCeSfnp3o1Mv4gGpmSHzsaMSrhpQ=; b=NesLkjr2AHTqMfI+2OAdv/Z/k3j/xz2HFvWyLTC+Z11bFH+jq2IJru8P76cuvfka2vjxhKKi3/TjLFjyPsdgAnDuXH9LOK4L/8PK3jf27L2NCDmPOmJJscUMvvPrdcWahbPb5iENK0UX+8F9S9IVjEpOe47z7M2p/9YiFLa2YKw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567019867292142.82284169682487; Wed, 28 Aug 2019 12:17:47 -0700 (PDT) Received: from localhost ([::1]:41070 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Rx-00065b-C3 for importer@patchew.org; Wed, 28 Aug 2019 15:17:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37745) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33G1-0003LE-5T for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33Fx-0008SL-Ux for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:24 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:36090) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33Fx-0008Rc-P1 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:21 -0400 Received: by mail-pf1-x443.google.com with SMTP id w2so398846pfi.3 for ; Wed, 28 Aug 2019 12:05:21 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0LZRj16kFkT1uXjnCeSfnp3o1Mv4gGpmSHzsaMSrhpQ=; b=EPPwyjSP+91CgRvX5JJz2SRb8NFqNtTEWGTSFT+IrNhz2U+O/MppR+NIcwICAZ86Cr Wonhno6pWQEIxPwhjLoaZcLz/kiMKiXs2DMJJbzXanONUXE9/Z1/bRgZA/zphCgfLY0b 3o8B8I5b+uETVCu9bKzwzqPgxNjygKV6ERiEBakZoSGw0vmYfrx3fi+6e/dX9F3vUEa/ lYIvIn5Ep4VMWRgAiESeKhdGjD93URT5f8ITD+ZuhV0FGtkJAr+hE7bn5dyoyXCiwCxC iR+y4KnEBoWZWjISO/QP9Yy3Lk2kvRt64kxYKePVRY0WLHxdhpnz20MkGRfPtf3jLTB4 wBnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0LZRj16kFkT1uXjnCeSfnp3o1Mv4gGpmSHzsaMSrhpQ=; b=cIosXs0XALTI1h+7LWLJUx3T21qT3GAKvg6uI2heKz+NGv8zYW0FLB7bFI8TjijJEI 0QYpsl1kBr49BBio8FR39Qrb+m/jhuvnDxvaWfb6mD7ZKTn+EMHJ3B2Fi3aV3gR/l9Ts /Bvz8f+/1aO1ur4pZgCf3tmBRgW2uyHJ1RtLsF4hA0QFnW5wHnkOtRRE8gmDzAAk5P35 tTNW4erotWlDP9tFXoJMMqAI7xxodTCM+N507JlpE8Cai26yp+ehthSRxzbpuldth5Af Dg4lBcxmXDfYtS39UMO9uTgUqYhXa+UGznJkJ6Wp74jmljvq2loWta0QXCdbIcOr1hHT Bgqw== X-Gm-Message-State: APjAAAXtFwI3TzbgpwrtnDvk+wTDfX2U2UkUdxsh5ms7a6UO/eBYnzcB GQ5Kc9nm3/YOBBdrTyzIxJQRTlXzdcY= X-Google-Smtp-Source: APXvYqymNrRr5PHe6rJIUKEvuQoid6M6GB2i6PY+13mUePbjf+hCMKAdzRaqssmZm7i+SUJX2r3w2w== X-Received: by 2002:a65:68d9:: with SMTP id k25mr4786735pgt.337.1567019120381; Wed, 28 Aug 2019 12:05:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:03 -0700 Message-Id: <20190828190456.30315-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 16/69] target/arm: Convert CLZ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Document our choice about the T32 CONSTRAINED UNPREDICTABLE behaviour. This matches the undocumented choice made by the legacy decoder. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 31 +++++++++++++++---------------- target/arm/a32.decode | 4 ++++ target/arm/t32.decode | 5 +++++ 3 files changed, 24 insertions(+), 16 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d60e859624..c285d4f882 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8464,6 +8464,19 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *= a) return true; } =20 +static bool trans_CLZ(DisasContext *s, arg_CLZ *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_5) { + return false; + } + tmp =3D load_reg(s, a->rm); + tcg_gen_clzi_i32(tmp, tmp, 32); + store_reg(s, a->rd, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8752,18 +8765,7 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) /* MSR/MRS (banked/register) */ /* All done in decodetree. Illegal ops already signalled. */ g_assert_not_reached(); - case 0x1: - if (op1 =3D=3D 3) { - /* clz */ - ARCH(5); - rd =3D (insn >> 12) & 0xf; - tmp =3D load_reg(s, rm); - tcg_gen_clzi_i32(tmp, tmp, 32); - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - break; + case 0x1: /* bx, clz */ case 0x2: /* bxj */ case 0x3: /* blx */ case 0x4: /* crc32 */ @@ -10201,13 +10203,13 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) case 0x08: /* rev */ case 0x09: /* rev16 */ case 0x0b: /* revsh */ - case 0x18: /* clz */ break; case 0x10: /* sel */ if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { goto illegal_op; } break; + case 0x18: /* clz, in decodetree */ case 0x20: /* crc32/crc32c, in decodetree */ case 0x21: case 0x22: @@ -10240,9 +10242,6 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) tcg_temp_free_i32(tmp3); tcg_temp_free_i32(tmp2); break; - case 0x18: /* clz */ - tcg_gen_clzi_i32(tmp, tmp, 32); - break; default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 6cb9c16e2f..182f2b6725 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,7 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&rr rd rm &r rm &msr_reg rn r mask &mrs_reg rd r @@ -197,6 +198,7 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 ...= . @rndm %sysm 8:1 16:4 =20 @rm ---- .... .... .... .... .... .... rm:4 &r +@rdm ---- .... .... .... rd:4 .... .... rm:4 &rr =20 MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %s= ysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %s= ysm @@ -207,3 +209,5 @@ MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 00= 00 rn:4 &msr_reg BX .... 0001 0010 1111 1111 1111 0001 .... @rm BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm + +CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 337706ebbe..67724efe4b 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,7 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&rr !extern rd rm &r !extern rm &msr_reg !extern rn r mask &mrs_reg !extern rd r @@ -126,6 +127,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ......= .. @s_rri_rot @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr @rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=3D0 @rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr +@rdm .... .... .... .... .... rd:4 .... rm:4 &rr =20 { MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm @@ -180,6 +182,9 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 ...= . @rndm CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm =20 +# Note rn !=3D rm is CONSTRAINED UNPREDICTABLE; we choose to ignore rn. +CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm + # Branches and miscellaneous control =20 %msr_sysm 4:1 8:4 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567020296; cv=none; d=zoho.com; s=zohoarc; b=L8FlBQOrdE/Z2kgJoAVgJ6/QMFRevYsGG/XcVmUF0+WfzTJZZSWV2ZZhacVlGZ480Na4vyZ633uRSvoX6o5Osr8GIpclAef3hjpU2ZiI+dcsw8nZu8mYubTcCHhq9bDO+MmOwGA+vUDM5NFf377VvJgkCt9cAzfY+0Shv9+YUag= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QCVrNyP4aQ0jX7CvYJg0KqtkiSJELZNM0Q5/bhu0tlI=; b=L9ub4gFlnNTqqoViMGHLAPW95jwbeBVCJHQKC9zmbl44JbKBUXlk+U//kLRnbD7ueb MKFRR9CgFUJkuzs9ndYooe9WfLqDKc51fPjs0R3ilQ8W4cdGCRpsrv/7XB8SlAouY11T htYvPnUyfPdrj5g/IuBSu9s9Y4MtpvfDH9ghirN5LqjEbpSFyTj5X6AL71QeYO6VDBUY 1uTrGJWgsY+2TidYV6c19vgxUBdclHrQY2glQZaTYdS6gmggWl2a10i5tbNmHQc+Q7y+ YNOc9WIZPjtHUbTbt9OelhWuIOsa6E1JcGs78sZu6RAFwXeDCZoLbb8Glijh750CMWfD yRiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QCVrNyP4aQ0jX7CvYJg0KqtkiSJELZNM0Q5/bhu0tlI=; b=t0vY/HC7u6kOZutaW1Y+qE4KTC36wLNP4Cj27FERKG+jXZ6LASpMPbzYQM+FOxor2q xjdCHfCle6HFZrcgBAC7w7/vanyvPicIJD+rsCDOQamNVFXsExsf5gOMz5RaBiQYVSIJ /txM4OSZTeI7nq9xu5ycODTI9OPU//LukppxCrtAtmS6EocIc4blRn9PsueNIrVP0fKS QxbQyriPkNvI9gfApUU5Pl7Ey5CamFJwBrYF6AL0B3GMpCCbhm9F3J2VakVOu8zasFjI GRJO24fcdpFFh/p41JIxS99z5k/j3njn0SUliXoQTwXV43isZOLj1544jG2PVOfTvfns +HhA== X-Gm-Message-State: APjAAAX+I1uTvmLJtE2VnDLYDoE67eYnCZg3m3jaiZE1lUXojysScKNr +1X9s8tdp+sMEcUtvJ139CwxhGPPfgA= X-Google-Smtp-Source: APXvYqwiZ+NvHZReUAqRyp3P3GxdXs6Xq2kT29kecjwWXeJIOUuozlMU8CvVjm6OY4XLPyjALmFgnA== X-Received: by 2002:a17:90a:342d:: with SMTP id o42mr5916292pjb.27.1567019121835; Wed, 28 Aug 2019 12:05:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:04 -0700 Message-Id: <20190828190456.30315-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 17/69] target/arm: Convert ERET X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Pass the T5 encoding of SUBS PC, LR, #IMM through the normal SUBS path to make it clear exactly what's happening -- we hit ALUExceptionReturn along that path. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding for IS_USER check. --- target/arm/translate.c | 62 ++++++++++++++++-------------------------- target/arm/a32.decode | 2 ++ target/arm/t32.decode | 8 ++++++ 3 files changed, 33 insertions(+), 39 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index c285d4f882..203b6160da 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8477,6 +8477,27 @@ static bool trans_CLZ(DisasContext *s, arg_CLZ *a) return true; } =20 +static bool trans_ERET(DisasContext *s, arg_ERET *a) +{ + TCGv_i32 tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) { + return false; + } + if (IS_USER(s)) { + unallocated_encoding(s); + return true; + } + if (s->current_el =3D=3D 2) { + /* ERET from Hyp uses ELR_Hyp, not LR */ + tmp =3D load_cpu_field(elr_el[2]); + } else { + tmp =3D load_reg(s, 14); + } + gen_exception_return(s, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8771,29 +8792,10 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) case 0x4: /* crc32 */ /* All done in decodetree. Illegal ops reach here. */ goto illegal_op; - case 0x5: - /* Saturating addition and subtraction. */ + case 0x5: /* Saturating addition and subtraction. */ + case 0x6: /* ERET */ /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; - case 0x6: /* ERET */ - if (op1 !=3D 3) { - goto illegal_op; - } - if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) { - goto illegal_op; - } - if ((insn & 0x000fff0f) !=3D 0x0000000e) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - - if (s->current_el =3D=3D 2) { - tmp =3D load_cpu_field(elr_el[2]); - } else { - tmp =3D load_reg(s, 14); - } - gen_exception_return(s, tmp); - break; case 7: { int imm16 =3D extract32(insn, 0, 4) | (extract32(insn, 8, 12) = << 4); @@ -10586,24 +10588,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) case 4: /* bxj, in decodetree */ goto illegal_op; case 5: /* Exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - if (rn !=3D 14 || rd !=3D 15) { - goto illegal_op; - } - if (s->current_el =3D=3D 2) { - /* ERET from Hyp uses ELR_Hyp, not LR */ - if (insn & 0xff) { - goto illegal_op; - } - tmp =3D load_cpu_field(elr_el[2]); - } else { - tmp =3D load_reg(s, rn); - tcg_gen_subi_i32(tmp, tmp, insn & 0xff); - } - gen_exception_return(s, tmp); - break; case 6: /* MRS, in decodetree */ case 7: /* MSR, in decodetree */ goto illegal_op; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 182f2b6725..52a66dd1d5 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -211,3 +211,5 @@ BXJ .... 0001 0010 1111 1111 1111 0010 ...= . @rm BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm =20 CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm + +ERET ---- 0001 0110 0000 0000 0000 0110 1110 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 67724efe4b..6236d28b99 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -218,4 +218,12 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ..= .. @rdm MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 } BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r + { + # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as = for + # every other encoding of SUBS. With v7VE, IMM=3D0 is redefined as ER= ET. + # The distinction between the two only matters for Hyp mode. + ERET 1111 0011 1101 1110 1000 1111 0000 0000 + SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ + &s_rri_rot rot=3D0 s=3D1 rd=3D15 rn=3D14 + } } --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567020551; cv=none; d=zoho.com; s=zohoarc; b=XRV6Is93O3WIoVm76YTWFvP9oMrde2jM08Y1eG/CUk/CO4iU0TCiKXeMAMbuo4rLrk/maHbblfD4y6/YZyQgFyj3fIF5ogmyIHOeFpiLJR5vFmPhICEO8ShXYhnMbq203j6tVRh/MykjtQd1UgWfMcsmZz3JAushq9VQJFVMCi4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567020551; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=M4p7h/i/Z1XZ25OuZSRZK70uUr5w+EGNQy0NQKl5v38=; b=kqno1KYaKUom5gmMjP3Al82ywpu/9XxKg1K0eZVKzF0xf2xoOYYX3yk/4miTB7w7R6UV/nbxqswGw5y+nDnBN5VFB8SsthhXj+uOdpE/uf+dpJFPcqz4kMz/BmJQpZKVgb4pYZnk/2n+JyRpfRCqE4WvBAkxqh64riBBJ+oY6oU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567020551550731.303092987807; Wed, 28 Aug 2019 12:29:11 -0700 (PDT) Received: from localhost ([::1]:41280 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33cz-0001hr-Uq for importer@patchew.org; Wed, 28 Aug 2019 15:29:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37813) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33G4-0003Qd-G8 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33G1-0008Vc-6B for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:28 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:42123) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33G0-0008U0-O1 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:24 -0400 Received: by mail-pg1-x541.google.com with SMTP id p3so210587pgb.9 for ; Wed, 28 Aug 2019 12:05:24 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=M4p7h/i/Z1XZ25OuZSRZK70uUr5w+EGNQy0NQKl5v38=; b=DBgsO1/xWzgPpKNvrbG+YB3HQ4JL62aYAPH+viDgSpAf8VLn0Hmybnp7Q4hGMd2R1d Vy1kibEJdR9rtiKYrkr3iD9xBEuT0RAv1Z8VGUUEidmeSdEgy8HhYlvX6EvMKt4xCWTI md5hSQIOwO9c3wAc4bA4gEWKBqEt31AQM3miIANLGY24Kt7Vc97ecx/xVtBUYpTsYfCl +jwHKBt5opkh2vvacJ/xg1ic+++cPUKUFWG4/MQ1EHQxaZL8UifQV2GxHtL8uO60JZhr C8Hwh9v42qHzLEat7EoFdrfs2f3zsJhZrccGTjdkv667+xWJHY3KG3D8Odf58lRP68xk TVjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=M4p7h/i/Z1XZ25OuZSRZK70uUr5w+EGNQy0NQKl5v38=; b=A0+Cj6jgSBqk1wD3gDqU7OUF2p5/zfD688ky/cQV2VkqZFVXfBIFvN6NqT3q+W7j4L Q459fN1tMIONu8l+3HZRgOdjQTH9C+Hxn4D7237plHOb+/EIMu1qWyyS4Zmf0VCA7Yaj LjzLnvXj4vQN8dKAVh+tV3is2KmnzUpA5RWyXvmnviwDC1fJrqrciZ1O3rroEX7i4snG FPaUzErzapW1ETNgvUlxOlodZtZXavg3p9pDooYDCo1oH3A3NFNoZ06O0QC+xiSX75en arUz91ubDWcr7Qtoh32Rpn+lWMv+tH+yCYY3ablhpwwFY6eYZZ5LochHK8Lrhbp4rYwK xX9Q== X-Gm-Message-State: APjAAAUWEVbtFNHEeOFYitWHe3Zja5DWaEB5OOsR86hgBd8Kk9YfnqMm bBrOXxY4EsL8RVhgX5vXG3nVd7vkSW4= X-Google-Smtp-Source: APXvYqzN+e/5c+9N5Wjrn6GgzH99rmyRWRjKrMDuWtoDykAaACpqHMnbOo0okSJg0HOx8EmVB1thfQ== X-Received: by 2002:a63:2043:: with SMTP id r3mr4797328pgm.311.1567019123045; Wed, 28 Aug 2019 12:05:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:05 -0700 Message-Id: <20190828190456.30315-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 18/69] target/arm: Convert the rest of A32 Miscelaneous instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Call unallocated_encoding for IS_USER. --- target/arm/translate.c | 127 +++++++++++++++-------------------------- target/arm/a32.decode | 8 +++ target/arm/t32.decode | 5 ++ 3 files changed, 58 insertions(+), 82 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 203b6160da..ad4b3c55c6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8498,6 +8498,47 @@ static bool trans_ERET(DisasContext *s, arg_ERET *a) return true; } =20 +static bool trans_HLT(DisasContext *s, arg_HLT *a) +{ + gen_hlt(s, a->imm); + return true; +} + +static bool trans_BKPT(DisasContext *s, arg_BKPT *a) +{ + if (!ENABLE_ARCH_5) { + return false; + } + gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); + return true; +} + +static bool trans_HVC(DisasContext *s, arg_HVC *a) +{ + if (!ENABLE_ARCH_7 || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + unallocated_encoding(s); + } else { + gen_hvc(s, a->imm); + } + return true; +} + +static bool trans_SMC(DisasContext *s, arg_SMC *a) +{ + if (!ENABLE_ARCH_6K || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + unallocated_encoding(s); + } else { + gen_smc(s); + } + return true; +} + /* * Legacy decoder. */ @@ -8778,68 +8819,8 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) } else if ((insn & 0x0f900000) =3D=3D 0x01000000 && (insn & 0x00000090) !=3D 0x00000090) { /* miscellaneous instructions */ - op1 =3D (insn >> 21) & 3; - sh =3D (insn >> 4) & 0xf; - rm =3D insn & 0xf; - switch (sh) { - case 0x0: - /* MSR/MRS (banked/register) */ - /* All done in decodetree. Illegal ops already signalled. */ - g_assert_not_reached(); - case 0x1: /* bx, clz */ - case 0x2: /* bxj */ - case 0x3: /* blx */ - case 0x4: /* crc32 */ - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - case 0x5: /* Saturating addition and subtraction. */ - case 0x6: /* ERET */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - case 7: - { - int imm16 =3D extract32(insn, 0, 4) | (extract32(insn, 8, 12) = << 4); - switch (op1) { - case 0: - /* HLT */ - gen_hlt(s, imm16); - break; - case 1: - /* bkpt */ - ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false)); - break; - case 2: - /* Hypervisor call (v7) */ - ARCH(7); - if (IS_USER(s)) { - goto illegal_op; - } - gen_hvc(s, imm16); - break; - case 3: - /* Secure monitor call (v6+) */ - ARCH(6K); - if (IS_USER(s)) { - goto illegal_op; - } - gen_smc(s); - break; - default: - g_assert_not_reached(); - } - break; - } - case 0x8: - case 0xa: - case 0xc: - case 0xe: - /* Halfword multiply and multiply accumulate. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - default: - goto illegal_op; - } + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; } else if (((insn & 0x0e000000) =3D=3D 0 && (insn & 0x00000090) !=3D 0x90) || ((insn & 0x0e000000) =3D=3D (1 << 25))) { @@ -10497,26 +10478,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) goto illegal_op; =20 if (insn & (1 << 26)) { - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - if (!(insn & (1 << 20))) { - /* Hypervisor call (v7) */ - int imm16 =3D extract32(insn, 16, 4) << 12 - | extract32(insn, 0, 12); - ARCH(7); - if (IS_USER(s)) { - goto illegal_op; - } - gen_hvc(s, imm16); - } else { - /* Secure monitor call (v6+) */ - ARCH(6K); - if (IS_USER(s)) { - goto illegal_op; - } - gen_smc(s); - } + /* hvc, smc, in decodetree */ + goto illegal_op; } else { op =3D (insn >> 20) & 7; switch (op) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 52a66dd1d5..c7f156be6d 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -31,6 +31,7 @@ &rrr rd rn rm &rr rd rm &r rm +&i imm &msr_reg rn r mask &mrs_reg rd r &msr_bank rn r sysm @@ -196,9 +197,11 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 ..= .. @rndm # Miscellaneous instructions =20 %sysm 8:1 16:4 +%imm16_8_0 8:12 0:4 =20 @rm ---- .... .... .... .... .... .... rm:4 &r @rdm ---- .... .... .... rd:4 .... .... rm:4 &rr +@i16 ---- .... .... .... .... .... .... .... &i imm=3D%im= m16_8_0 =20 MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %s= ysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %s= ysm @@ -213,3 +216,8 @@ BLX_r .... 0001 0010 1111 1111 1111 0011 ...= . @rm CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm =20 ERET ---- 0001 0110 0000 0000 0000 0110 1110 + +HLT .... 0001 0000 .... .... .... 0111 .... @i16 +BKPT .... 0001 0010 .... .... .... 0111 .... @i16 +HVC .... 0001 0100 .... .... .... 0111 .... @i16 +SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 6236d28b99..5116c6165a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -28,6 +28,7 @@ &rrr !extern rd rn rm &rr !extern rd rm &r !extern rm +&i !extern imm &msr_reg !extern rn r mask &mrs_reg !extern rd r &msr_bank !extern rn r sysm @@ -189,6 +190,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ...= . @rdm =20 %msr_sysm 4:1 8:4 %mrs_sysm 4:1 16:4 +%imm16_16_0 16:4 0:12 =20 { { @@ -226,4 +228,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ...= . @rdm SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ &s_rri_rot rot=3D0 s=3D1 rd=3D15 rn=3D14 } + SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i + HVC 1111 0111 1110 .... 1000 .... .... .... \ + &i imm=3D%imm16_16_0 } --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mEt0ovniA8TTjKeMb0D1ZbNJS4Vt4wC0E+O60CpepFo=; b=LRRMr0DBNj4ZvFE58LSrUeLNN0WHIqoy8J5VQw0s0wh/LoDixtLa6m8KxR7CKpBmWQ ijXJPH6zjqVcn720ikSxS9EAkYAE6CyHIYxDN0NaVSoEN7zFWYeK3osjR1RalNw3oE63 mq7XUvNvk4ud9y37C7N4QrFH1cZsSEllaE14G+vwsgS9KZyAowTBIsS9e1vYWM/U4sXh envNwGqCVVgPnVqDV0ly+MUb4lMB6Y/vhVEDiamq5wxr4KEyGQj9zQ1nFa909LeGlNLs KoLdEtMXUcKv+wUP8xQ1LLjrozzhYrARxuCoVJgoM9qQ1mciiK04XYCGrr7sCwSpQNgQ 6ciA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mEt0ovniA8TTjKeMb0D1ZbNJS4Vt4wC0E+O60CpepFo=; b=oKYjdX98MurZ9Eq2tUiLHSQi/7Hafb/QJVyQ/dw+KGD62R1t96P0Exy7HniucS3beJ 3dPEDofVg9HrBL26m84aeiQknhYUq65e9aJtFFMq6BG2JMP7YbFQQcNxgF54dH0HwX92 0hKG8cR6I1CA7KnUtHwQiudPW9EpO0OKYIOoCMog4TNZCz0dhv1g/q5qpzurXXB+ZLDH MabwW+KeOT5BEeP52oNkNru2ka2MuH7VBqiTiKJk7vnWyiH+FAv8A9kTAG2Ssbc3uhQS XY7ythQk3tLhFeaVCw2rcVE7W3cXb7PPTvlghgySKh7QDfHTOdhN4msbrvjLrfIFreeu EBAg== X-Gm-Message-State: APjAAAVmKFUnvXO6NVwygExriPYbjcBRRC0OWuuQ9yqOctDiAPSfYv0Z gQzT7xoQyYRWsvdLfePzInX4zzADzTs= X-Google-Smtp-Source: APXvYqxz+EnhGQV36A97X98pRqK0LchjqSEfu0zaOjAXytB1VDs8I+fE6LMcVGMDFxU1qWj6oaditw== X-Received: by 2002:a63:a302:: with SMTP id s2mr4797000pge.125.1567019124364; Wed, 28 Aug 2019 12:05:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:06 -0700 Message-Id: <20190828190456.30315-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 19/69] target/arm: Convert T32 ADDW/SUBW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 24 +++++++++++++----------- target/arm/a32.decode | 1 + target/arm/t32.decode | 19 +++++++++++++++++++ 3 files changed, 33 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ad4b3c55c6..257ee6b5ea 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7622,6 +7622,11 @@ static void arm_skip_unless(DisasContext *s, uint32_= t cond) * Constant expanders for the decoders. */ =20 +static int negate(DisasContext *s, int x) +{ + return -x; +} + static int times_2(DisasContext *s, int x) { return x * 2; @@ -7978,6 +7983,12 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rri= _rot *a) #undef DO_ANY2 #undef DO_CMP2 =20 +static bool trans_ADR(DisasContext *s, arg_ri *a) +{ + store_reg_bx(s, a->rd, add_reg_for_lit(s, 15, a->imm)); + return true; +} + /* * Multiply and multiply accumulate */ @@ -10682,17 +10693,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } store_reg(s, rd, tmp); } else { - /* Add/sub 12-bit immediate. */ - if (insn & (1 << 23)) { - imm =3D -imm; - } - tmp =3D add_reg_for_lit(s, rn, imm); - if (rn =3D=3D 13 && rd =3D=3D 13) { - /* ADD SP, SP, imm or SUB SP, SP, imm */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } + /* Add/sub 12-bit immediate, in decodetree */ + goto illegal_op; } } } else { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index c7f156be6d..aac991664d 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -30,6 +30,7 @@ &rrrr rd rn rm ra &rrr rd rn rm &rr rd rm +&ri rd imm &r rm &i imm &msr_reg rn r mask diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 5116c6165a..be4e5f087c 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -27,6 +27,7 @@ &rrrr !extern rd rn rm ra &rrr !extern rd rn rm &rr !extern rd rm +&ri !extern rd imm &r !extern rm &i !extern imm &msr_reg !extern rn r mask @@ -121,6 +122,24 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... .....= ... @s_rri_rot } RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot =20 +# Data processing (plain binary immediate) + +%imm12_26_12_0 26:1 12:3 0:8 +%neg12_26_12_0 26:1 12:3 0:8 !function=3Dnegate +@s0_rri_12 .... ... .... . rn:4 . ... rd:4 ........ \ + &s_rri_rot imm=3D%imm12_26_12_0 rot=3D0 s=3D0 + +{ + ADR 1111 0.1 0000 0 1111 0 ... rd:4 ........ \ + &ri imm=3D%imm12_26_12_0 + ADD_rri 1111 0.1 0000 0 .... 0 ... .... ........ @s0_rri_12 +} +{ + ADR 1111 0.1 0101 0 1111 0 ... rd:4 ........ \ + &ri imm=3D%neg12_26_12_0 + SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 +} + # Multiply and multiply accumulate =20 @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dSu/WI2p7Zu7RkNmlaDDRF7EyRvRP4Vvqe5rGiQe2vs=; b=p/BhHqjZHOPJyMdMdckx+94f40E7jPf36UVf4OpPatgQolpznftse2rtl0Ln2Cg07J EWHN4W0iC1Gr7H1WPqawUYwQGqNqOznYIVCkxX4i/osWGjx72ByR4p3tgutJmgueTgof cyVx4mxTRKYr4WNC2GkXgIJiOC/4Dkw3PznBMFffMoZryHJZNXoDFF1A/UmERT1LlM5O wlDdYGFNP67ONkps5bOcY0FUZ0oNpJAe1ZdiTmmdwyvTObSQU2LeRiA6SxcvIbgSuDjB 1ccrSodTBkwywdf0WShmJ7FLJbjhvhm+FRYBnujAtR9fdkx4TTD8Lr6dch4HFMRbLMlr q1ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dSu/WI2p7Zu7RkNmlaDDRF7EyRvRP4Vvqe5rGiQe2vs=; b=spxm23j2jUq+gQ74uv9hKllHV5A6fIzPCcD0+TNIEVi/u/UsA6CAY8YZa8KSHiqSag qvEMpPs3DzRzpUstGACSfcXJH2E8G1F6jjwynzHhzeYLy0Y0XXSYf8NWFGM8nxz0Y7ID 88emWCC90faJANAuVZ1907lxuZkhz20F6BY7qgIuPSYxINorMMBxiOrlhgwbiH0M7fKS /ker20MsVo5KYR5TXyazOBJ2HEpZkzBGUY9zAiYoc7rwtHSh/0kGl3Z6kjJQjRuygDzL 5OwI3Oli3b40K95NVFcCabWdHw9wti06LTWTnXeuG+5vIKXAvgYNS6ZlMUf4JITNzYnE 0+EQ== X-Gm-Message-State: APjAAAVD9f1ywmTFbNFiy6pPZGlN8WESHLo8w7VVxtUhebkgec6RQpKi baa+7y0PH2V5xARa8I9vz0bCSlHLEtY= X-Google-Smtp-Source: APXvYqyyV+tSBce6753p+5ZPOiqz8jxnDGUjf4I03UFn2MAGRuUpp63MsWRiqfueks3l05ASs8wGnA== X-Received: by 2002:a17:902:b18b:: with SMTP id s11mr6000876plr.1.1567019125732; Wed, 28 Aug 2019 12:05:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:07 -0700 Message-Id: <20190828190456.30315-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62a Subject: [Qemu-devel] [PATCH v3 20/69] target/arm: Convert load/store (register, immediate, literal) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding for RT odd --- target/arm/translate.c | 805 ++++++++++++++++++----------------------- target/arm/a32.decode | 120 ++++++ target/arm/t32.decode | 141 ++++++++ 3 files changed, 623 insertions(+), 443 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 257ee6b5ea..a92b90a4e3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1246,62 +1246,6 @@ static inline void gen_hlt(DisasContext *s, int imm) unallocated_encoding(s); } =20 -static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, - TCGv_i32 var) -{ - int val, rm, shift, shiftop; - TCGv_i32 offset; - - if (!(insn & (1 << 25))) { - /* immediate */ - val =3D insn & 0xfff; - if (!(insn & (1 << 23))) - val =3D -val; - if (val !=3D 0) - tcg_gen_addi_i32(var, var, val); - } else { - /* shift/register */ - rm =3D (insn) & 0xf; - shift =3D (insn >> 7) & 0x1f; - shiftop =3D (insn >> 5) & 3; - offset =3D load_reg(s, rm); - gen_arm_shift_im(offset, shiftop, shift, 0); - if (!(insn & (1 << 23))) - tcg_gen_sub_i32(var, var, offset); - else - tcg_gen_add_i32(var, var, offset); - tcg_temp_free_i32(offset); - } -} - -static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn, - int extra, TCGv_i32 var) -{ - int val, rm; - TCGv_i32 offset; - - if (insn & (1 << 22)) { - /* immediate */ - val =3D (insn & 0xf) | ((insn >> 4) & 0xf0); - if (!(insn & (1 << 23))) - val =3D -val; - val +=3D extra; - if (val !=3D 0) - tcg_gen_addi_i32(var, var, val); - } else { - /* register */ - if (extra) - tcg_gen_addi_i32(var, var, extra); - rm =3D (insn) & 0xf; - offset =3D load_reg(s, rm); - if (!(insn & (1 << 23))) - tcg_gen_sub_i32(var, var, offset); - else - tcg_gen_add_i32(var, var, offset); - tcg_temp_free_i32(offset); - } -} - static TCGv_ptr get_fpstatus_ptr(int neon) { TCGv_ptr statusptr =3D tcg_temp_new_ptr(); @@ -7632,6 +7576,11 @@ static int times_2(DisasContext *s, int x) return x * 2; } =20 +static int times_4(DisasContext *s, int x) +{ + return x * 4; +} + /* Return only the rotation part of T32ExpandImm. */ static int t32_expandimm_rot(DisasContext *s, int x) { @@ -8550,6 +8499,353 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a) return true; } =20 +/* + * Load/store register index + */ + +static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w) +{ + ISSInfo ret; + + /* ISS not valid if writeback */ + if (p && !w) { + ret =3D rd; + } else { + ret =3D ISSInvalid; + } + return ret; +} + +static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a) +{ + TCGv_i32 addr =3D load_reg(s, a->rn); + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + if (a->p) { + TCGv_i32 ofs =3D load_reg(s, a->rm); + gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); + if (a->u) { + tcg_gen_add_i32(addr, addr, ofs); + } else { + tcg_gen_sub_i32(addr, addr, ofs); + } + tcg_temp_free_i32(ofs); + } + return addr; +} + +static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a, + TCGv_i32 addr, int address_offset) +{ + if (!a->p) { + TCGv_i32 ofs =3D load_reg(s, a->rm); + gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); + if (a->u) { + tcg_gen_add_i32(addr, addr, ofs); + } else { + tcg_gen_sub_i32(addr, addr, ofs); + } + tcg_temp_free_i32(ofs); + } else if (!a->w) { + tcg_temp_free_i32(addr); + return; + } + tcg_gen_addi_i32(addr, addr, address_offset); + store_reg(s, a->rn, addr); +} + +static bool op_load_rr(DisasContext *s, arg_ldst_rr *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo =3D make_issinfo(s, a->rt, a->p, a->w); + TCGv_i32 addr, tmp; + + addr =3D op_addr_rr_pre(s, a); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + + /* + * Perform base writeback before the loaded value to + * ensure correct behavior with overlapping index registers. + */ + op_addr_rr_post(s, a, addr, 0); + store_reg_from_load(s, a->rt, tmp); + return true; +} + +static bool op_store_rr(DisasContext *s, arg_ldst_rr *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo =3D make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; + TCGv_i32 addr, tmp; + + addr =3D op_addr_rr_pre(s, a); + + tmp =3D load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + tcg_temp_free_i32(tmp); + + op_addr_rr_post(s, a, addr, 0); + return true; +} + +static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) +{ + int mem_idx =3D get_mem_index(s); + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_5TE) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + addr =3D op_addr_rr_pre(s, a); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt, tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt + 1, tmp); + + /* LDRD w/ base writeback is undefined if the registers overlap. */ + op_addr_rr_post(s, a, addr, -4); + return true; +} + +static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) +{ + int mem_idx =3D get_mem_index(s); + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_5TE) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + addr =3D op_addr_rr_pre(s, a); + + tmp =3D load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp =3D load_reg(s, a->rt + 1); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + op_addr_rr_post(s, a, addr, -4); + return true; +} + +/* + * Load/store immediate index + */ + +static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a) +{ + int ofs =3D a->imm; + + if (!a->u) { + ofs =3D -ofs; + } + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + /* + * Stackcheck. Here we know 'addr' is the current SP; + * U is set if we're moving SP up, else down. It is + * UNKNOWN whether the limit check triggers when SP starts + * below the limit and ends up above it; we chose to do so. + */ + if (!a->u) { + TCGv_i32 newsp =3D tcg_temp_new_i32(); + tcg_gen_addi_i32(newsp, cpu_R[13], ofs); + gen_helper_v8m_stackcheck(cpu_env, newsp); + tcg_temp_free_i32(newsp); + } else { + gen_helper_v8m_stackcheck(cpu_env, cpu_R[13]); + } + } + + return add_reg_for_lit(s, a->rn, a->p ? ofs : 0); +} + +static void op_addr_ri_post(DisasContext *s, arg_ldst_ri *a, + TCGv_i32 addr, int address_offset) +{ + if (!a->p) { + if (a->u) { + address_offset +=3D a->imm; + } else { + address_offset -=3D a->imm; + } + } else if (!a->w) { + tcg_temp_free_i32(addr); + return; + } + tcg_gen_addi_i32(addr, addr, address_offset); + store_reg(s, a->rn, addr); +} + +static bool op_load_ri(DisasContext *s, arg_ldst_ri *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo =3D make_issinfo(s, a->rt, a->p, a->w); + TCGv_i32 addr, tmp; + + addr =3D op_addr_ri_pre(s, a); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + + /* + * Perform base writeback before the loaded value to + * ensure correct behavior with overlapping index registers. + */ + op_addr_ri_post(s, a, addr, 0); + store_reg_from_load(s, a->rt, tmp); + return true; +} + +static bool op_store_ri(DisasContext *s, arg_ldst_ri *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo =3D make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; + TCGv_i32 addr, tmp; + + addr =3D op_addr_ri_pre(s, a); + + tmp =3D load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + tcg_temp_free_i32(tmp); + + op_addr_ri_post(s, a, addr, 0); + return true; +} + +static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) +{ + int mem_idx =3D get_mem_index(s); + TCGv_i32 addr, tmp; + + addr =3D op_addr_ri_pre(s, a); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt, tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, rt2, tmp); + + /* LDRD w/ base writeback is undefined if the registers overlap. */ + op_addr_ri_post(s, a, addr, -4); + return true; +} + +static bool trans_LDRD_ri_a32(DisasContext *s, arg_ldst_ri *a) +{ + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + return op_ldrd_ri(s, a, a->rt + 1); +} + +static bool trans_LDRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) +{ + arg_ldst_ri b =3D { + .u =3D a->u, .w =3D a->w, .p =3D a->p, + .rn =3D a->rn, .rt =3D a->rt, .imm =3D a->imm + }; + return op_ldrd_ri(s, &b, a->rt2); +} + +static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) +{ + int mem_idx =3D get_mem_index(s); + TCGv_i32 addr, tmp; + + addr =3D op_addr_ri_pre(s, a); + + tmp =3D load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp =3D load_reg(s, rt2); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + op_addr_ri_post(s, a, addr, -4); + return true; +} + +static bool trans_STRD_ri_a32(DisasContext *s, arg_ldst_ri *a) +{ + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + return op_strd_ri(s, a, a->rt + 1); +} + +static bool trans_STRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) +{ + arg_ldst_ri b =3D { + .u =3D a->u, .w =3D a->w, .p =3D a->p, + .rn =3D a->rn, .rt =3D a->rt, .imm =3D a->imm + }; + return op_strd_ri(s, &b, a->rt2); +} + +#define DO_LDST(NAME, WHICH, MEMOP) \ +static bool trans_##NAME##_ri(DisasContext *s, arg_ldst_ri *a) \ +{ \ + return op_##WHICH##_ri(s, a, MEMOP, get_mem_index(s)); \ +} \ +static bool trans_##NAME##T_ri(DisasContext *s, arg_ldst_ri *a) \ +{ \ + return op_##WHICH##_ri(s, a, MEMOP, get_a32_user_mem_index(s)); \ +} \ +static bool trans_##NAME##_rr(DisasContext *s, arg_ldst_rr *a) \ +{ \ + return op_##WHICH##_rr(s, a, MEMOP, get_mem_index(s)); \ +} \ +static bool trans_##NAME##T_rr(DisasContext *s, arg_ldst_rr *a) \ +{ \ + return op_##WHICH##_rr(s, a, MEMOP, get_a32_user_mem_index(s)); \ +} + +DO_LDST(LDR, load, MO_UL) +DO_LDST(LDRB, load, MO_UB) +DO_LDST(LDRH, load, MO_UW) +DO_LDST(LDRSB, load, MO_SB) +DO_LDST(LDRSH, load, MO_SW) + +DO_LDST(STR, store, MO_UL) +DO_LDST(STRB, store, MO_UB) +DO_LDST(STRH, store, MO_UW) + +#undef DO_LDST + /* * Legacy decoder. */ @@ -9007,100 +9303,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) } } } else { - int address_offset; - bool load =3D insn & (1 << 20); - bool wbit =3D insn & (1 << 21); - bool pbit =3D insn & (1 << 24); - bool doubleword =3D false; - ISSInfo issinfo; - - /* Misc load/store */ - rn =3D (insn >> 16) & 0xf; - rd =3D (insn >> 12) & 0xf; - - /* ISS not valid if writeback */ - issinfo =3D (pbit & !wbit) ? rd : ISSInvalid; - - if (!load && (sh & 2)) { - /* doubleword */ - ARCH(5TE); - if (rd & 1) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - load =3D (sh & 1) =3D=3D 0; - doubleword =3D true; - } - - addr =3D load_reg(s, rn); - if (pbit) { - gen_add_datah_offset(s, insn, 0, addr); - } - address_offset =3D 0; - - if (doubleword) { - if (!load) { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp =3D load_reg(s, rd + 1); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } else { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - rd++; - } - address_offset =3D -4; - } else if (load) { - /* load */ - tmp =3D tcg_temp_new_i32(); - switch (sh) { - case 1: - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - case 2: - gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - default: - case 3: - gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - } - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issi= nfo); - tcg_temp_free_i32(tmp); - } - /* Perform base writeback before the loaded value to - ensure correct behavior with overlapping index register= s. - ldrd with base writeback is undefined if the - destination and index registers overlap. */ - if (!pbit) { - gen_add_datah_offset(s, insn, address_offset, addr); - store_reg(s, rn, addr); - } else if (wbit) { - if (address_offset) - tcg_gen_addi_i32(addr, addr, address_offset); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - if (load) { - /* Complete the load. */ - store_reg(s, rd, tmp); - } + /* Extra load/store (register) instructions */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } break; case 0x4: @@ -9408,58 +9613,8 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) break; } do_ldst: - /* Check for undefined extension instructions - * per the ARM Bible IE: - * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx - */ - sh =3D (0xf << 20) | (0xf << 4); - if (op1 =3D=3D 0x7 && ((insn & sh) =3D=3D sh)) - { - goto illegal_op; - } - /* load/store byte/word */ - rn =3D (insn >> 16) & 0xf; - rd =3D (insn >> 12) & 0xf; - tmp2 =3D load_reg(s, rn); - if ((insn & 0x01200000) =3D=3D 0x00200000) { - /* ldrt/strt */ - i =3D get_a32_user_mem_index(s); - } else { - i =3D get_mem_index(s); - } - if (insn & (1 << 24)) - gen_add_data_offset(s, insn, tmp2); - if (insn & (1 << 20)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - if (insn & (1 << 22)) { - gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd); - } else { - gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd); - } - } else { - /* store */ - tmp =3D load_reg(s, rd); - if (insn & (1 << 22)) { - gen_aa32_st8_iss(s, tmp, tmp2, i, rd); - } else { - gen_aa32_st32_iss(s, tmp, tmp2, i, rd); - } - tcg_temp_free_i32(tmp); - } - if (!(insn & (1 << 24))) { - gen_add_data_offset(s, insn, tmp2); - store_reg(s, rn, tmp2); - } else if (insn & (1 << 21)) { - store_reg(s, rn, tmp2); - } else { - tcg_temp_free_i32(tmp2); - } - if (insn & (1 << 20)) { - /* Complete the load. */ - store_reg_from_load(s, rd, tmp); - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0x08: case 0x09: { @@ -9760,75 +9915,8 @@ static void disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) s->condexec_mask =3D 0; } } else if (insn & 0x01200000) { - /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (post-indexed) - * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (literal and immediate) - * 0b1111_1001_x11x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (pre-indexed) - */ - bool wback =3D extract32(insn, 21, 1); - - if (rn =3D=3D 15 && (insn & (1 << 21))) { - /* UNPREDICTABLE */ - goto illegal_op; - } - - addr =3D add_reg_for_lit(s, rn, 0); - offset =3D (insn & 0xff) * 4; - if ((insn & (1 << 23)) =3D=3D 0) { - offset =3D -offset; - } - - if (s->v8m_stackcheck && rn =3D=3D 13 && wback) { - /* - * Here 'addr' is the current SP; if offset is +ve we'= re - * moving SP up, else down. It is UNKNOWN whether the = limit - * check triggers when SP starts below the limit and e= nds - * up above it; check whichever of the current and fin= al - * SP is lower, so QEMU will trigger in that situation. - */ - if ((int32_t)offset < 0) { - TCGv_i32 newsp =3D tcg_temp_new_i32(); - - tcg_gen_addi_i32(newsp, addr, offset); - gen_helper_v8m_stackcheck(cpu_env, newsp); - tcg_temp_free_i32(newsp); - } else { - gen_helper_v8m_stackcheck(cpu_env, addr); - } - } - - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, offset); - offset =3D 0; - } - if (insn & (1 << 20)) { - /* ldrd */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rs, tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - } else { - /* strd */ - tmp =3D load_reg(s, rs); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp =3D load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - if (wback) { - /* Base writeback. */ - tcg_gen_addi_i32(addr, addr, offset - 4); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } + /* load/store dual, in decodetree */ + goto illegal_op; } else if ((insn & (1 << 23)) =3D=3D 0) { /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx * - load/store exclusive word @@ -10704,184 +10792,15 @@ static void disas_thumb2_insn(DisasContext *s, u= int32_t insn) } } break; - case 12: /* Load/store single data item. */ - { - int postinc =3D 0; - int writeback =3D 0; - int memidx; - ISSInfo issinfo; - + case 12: if ((insn & 0x01100000) =3D=3D 0x01000000) { if (disas_neon_ls_insn(s, insn)) { goto illegal_op; } break; } - op =3D ((insn >> 21) & 3) | ((insn >> 22) & 4); - if (rs =3D=3D 15) { - if (!(insn & (1 << 20))) { - goto illegal_op; - } - if (op !=3D 2) { - /* Byte or halfword load space with dest =3D=3D r15 : memo= ry hints. - * Catch them early so we don't emit pointless addressing = code. - * This space is a mix of: - * PLD/PLDW/PLI, which we implement as NOPs (note that u= nlike - * the ARM encodings, PLDW space doesn't UNDEF for non= -v7MP - * cores) - * unallocated hints, which must be treated as NOPs - * UNPREDICTABLE space, which we NOP or UNDEF depending on - * which is easiest for the decoding logic - * Some space which must UNDEF - */ - int op1 =3D (insn >> 23) & 3; - int op2 =3D (insn >> 6) & 0x3f; - if (op & 2) { - goto illegal_op; - } - if (rn =3D=3D 15) { - /* UNPREDICTABLE, unallocated hint or - * PLD/PLDW/PLI (literal) - */ - return; - } - if (op1 & 1) { - return; /* PLD/PLDW/PLI or unallocated hint */ - } - if ((op2 =3D=3D 0) || ((op2 & 0x3c) =3D=3D 0x30)) { - return; /* PLD/PLDW/PLI or unallocated hint */ - } - /* UNDEF space, or an UNPREDICTABLE */ - goto illegal_op; - } - } - memidx =3D get_mem_index(s); - imm =3D insn & 0xfff; - if (insn & (1 << 23)) { - /* PC relative or Positive offset. */ - addr =3D add_reg_for_lit(s, rn, imm); - } else if (rn =3D=3D 15) { - /* PC relative with negative offset. */ - addr =3D add_reg_for_lit(s, rn, -imm); - } else { - addr =3D load_reg(s, rn); - imm =3D insn & 0xff; - switch ((insn >> 8) & 0xf) { - case 0x0: /* Shifted Register. */ - shift =3D (insn >> 4) & 0xf; - if (shift > 3) { - tcg_temp_free_i32(addr); - goto illegal_op; - } - tmp =3D load_reg(s, rm); - tcg_gen_shli_i32(tmp, tmp, shift); - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - break; - case 0xc: /* Negative offset. */ - tcg_gen_addi_i32(addr, addr, -imm); - break; - case 0xe: /* User privilege. */ - tcg_gen_addi_i32(addr, addr, imm); - memidx =3D get_a32_user_mem_index(s); - break; - case 0x9: /* Post-decrement. */ - imm =3D -imm; - /* Fall through. */ - case 0xb: /* Post-increment. */ - postinc =3D 1; - writeback =3D 1; - break; - case 0xd: /* Pre-decrement. */ - imm =3D -imm; - /* Fall through. */ - case 0xf: /* Pre-increment. */ - writeback =3D 1; - break; - default: - tcg_temp_free_i32(addr); - goto illegal_op; - } - } - - issinfo =3D writeback ? ISSInvalid : rs; - - if (s->v8m_stackcheck && rn =3D=3D 13 && writeback) { - /* - * Stackcheck. Here we know 'addr' is the current SP; - * if imm is +ve we're moving SP up, else down. It is - * UNKNOWN whether the limit check triggers when SP starts - * below the limit and ends up above it; we chose to do so. - */ - if ((int32_t)imm < 0) { - TCGv_i32 newsp =3D tcg_temp_new_i32(); - - tcg_gen_addi_i32(newsp, addr, imm); - gen_helper_v8m_stackcheck(cpu_env, newsp); - tcg_temp_free_i32(newsp); - } else { - gen_helper_v8m_stackcheck(cpu_env, addr); - } - } - - if (writeback && !postinc) { - tcg_gen_addi_i32(addr, addr, imm); - } - - if (insn & (1 << 20)) { - /* Load. */ - tmp =3D tcg_temp_new_i32(); - switch (op) { - case 0: - gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo); - break; - case 4: - gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo); - break; - case 1: - gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo); - break; - case 5: - gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo); - break; - case 2: - gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo); - break; - default: - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - goto illegal_op; - } - store_reg_from_load(s, rs, tmp); - } else { - /* Store. */ - tmp =3D load_reg(s, rs); - switch (op) { - case 0: - gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo); - break; - case 1: - gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo); - break; - case 2: - gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo); - break; - default: - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - goto illegal_op; - } - tcg_temp_free_i32(tmp); - } - if (postinc) - tcg_gen_addi_i32(addr, addr, imm); - if (writeback) { - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - } - break; + /* Load/store single data item, in decodetree */ + goto illegal_op; default: goto illegal_op; } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index aac991664d..f7742deaee 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -37,6 +37,8 @@ &mrs_reg rd r &msr_bank rn r sysm &mrs_bank rd r sysm +&ldst_rr p w u rn rt rm shimm shtype +&ldst_ri p w u rn rt imm =20 # Data-processing (register) =20 @@ -222,3 +224,121 @@ HLT .... 0001 0000 .... .... .... 0111 .= ... @i16 BKPT .... 0001 0010 .... .... .... 0111 .... @i16 HVC .... 0001 0100 .... .... .... 0111 .... @i16 SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i + +# Load/Store Dual, Half, Signed Byte (register) + +@ldst_rr_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=3D1 shimm=3D0 shtype=3D0 +@ldst_rr_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=3D0 w=3D0 shimm=3D0 shtype=3D0 + +STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_pw0 +STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p1w + +LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_pw0 +LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_p1w + +STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_pw0 +STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_p1w + +LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_pw0 +LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p1w + +LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_pw0 +LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p1w + +LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_pw0 +LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p1w + +# Note the unpriv load/stores use the previously invalid P=3D0, W=3D1 enco= ding, +# and act as normal post-indexed (P=3D0, W=3D0). +@ldst_rr_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=3D0 w=3D0 shimm=3D0 shtype=3D0 + +STRHT_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p0w1 +LDRHT_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p0w1 +LDRSBT_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p0w1 +LDRSHT_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p0w1 + +# Load/Store word and unsigned byte (register) + +@ldst_rs_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=3D1 +@ldst_rs_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=3D0 w=3D0 + +STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_pw0 +STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p1w +STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_pw0 +STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p1w + +LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_pw0 +LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p1w +LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_pw0 +LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p1w + +@ldst_rs_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=3D0 w=3D0 + +STRT_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p0w1 +STRBT_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p0w1 +LDRT_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p0w1 +LDRBT_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p0w1 + +# Load/Store Dual, Half, Signed Byte (immediate) + +%imm8s_8_0 8:4 0:4 +@ldst_ri8_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=3D%imm8s_8_0 p=3D1 +@ldst_ri8_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=3D%imm8s_8_0 p=3D0 w=3D0 + +STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_pw0 +STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p1w + +LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_pw0 +LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_p1w + +STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_pw0 +STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_p1w + +LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_pw0 +LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p1w + +LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_pw0 +LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p1w + +LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_pw0 +LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p1w + +# Note the unpriv load/stores use the previously invalid P=3D0, W=3D1 enco= ding, +# and act as normal post-indexed (P=3D0, W=3D0). +@ldst_ri8_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=3D%imm8s_8_0 p=3D0 w=3D0 + +STRHT_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p0= w1 +LDRHT_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p0= w1 +LDRSBT_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p0= w1 +LDRSHT_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p0= w1 + +# Load/Store word and unsigned byte (immediate) + +@ldst_ri12_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 imm:12 &ldst_ri p= =3D1 +@ldst_ri12_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 imm:12 &ldst_ri p= =3D0 w=3D0 + +STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p= 1w +STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p= w0 +STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p= 1w +STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p= w0 + +LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p= 1w +LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p= w0 +LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p= 1w +LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p= w0 + +@ldst_ri12_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 imm:12 &ldst_ri p= =3D0 w=3D0 + +STRT_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p= 0w1 +STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p= 0w1 +LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p= 0w1 +LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p= 0w1 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index be4e5f087c..a86597562b 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -34,6 +34,8 @@ &mrs_reg !extern rd r &msr_bank !extern rn r sysm &mrs_bank !extern rd r sysm +&ldst_rr !extern p w u rn rt rm shimm shtype +&ldst_ri !extern p w u rn rt imm =20 # Data-processing (register) =20 @@ -251,3 +253,142 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .= ... @rdm HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=3D%imm16_16_0 } + +# Load/store (register, immediate, literal) + +@ldst_rr .... .... .... rn:4 rt:4 ...... shimm:2 rm:4 \ + &ldst_rr p=3D1 w=3D0 u=3D1 shtype=3D0 +@ldst_ri_idx .... .... .... rn:4 rt:4 . p:1 u:1 . imm:8 \ + &ldst_ri w=3D1 +@ldst_ri_neg .... .... .... rn:4 rt:4 .... imm:8 \ + &ldst_ri p=3D1 w=3D0 u=3D0 +@ldst_ri_unp .... .... .... rn:4 rt:4 .... imm:8 \ + &ldst_ri p=3D1 w=3D0 u=3D1 +@ldst_ri_pos .... .... .... rn:4 rt:4 imm:12 \ + &ldst_ri p=3D1 w=3D0 u=3D1 +@ldst_ri_lit .... .... u:1 ... .... rt:4 imm:12 \ + &ldst_ri p=3D1 w=3D0 rn=3D15 + +STRB_rr 1111 1000 0000 .... .... 000000 .. .... @ldst_rr +STRB_ri 1111 1000 0000 .... .... 1..1 ........ @ldst_ri_idx +STRB_ri 1111 1000 0000 .... .... 1100 ........ @ldst_ri_neg +STRBT_ri 1111 1000 0000 .... .... 1110 ........ @ldst_ri_unp +STRB_ri 1111 1000 1000 .... .... ............ @ldst_ri_pos + +STRH_rr 1111 1000 0010 .... .... 000000 .. .... @ldst_rr +STRH_ri 1111 1000 0010 .... .... 1..1 ........ @ldst_ri_idx +STRH_ri 1111 1000 0010 .... .... 1100 ........ @ldst_ri_neg +STRHT_ri 1111 1000 0010 .... .... 1110 ........ @ldst_ri_unp +STRH_ri 1111 1000 1010 .... .... ............ @ldst_ri_pos + +STR_rr 1111 1000 0100 .... .... 000000 .. .... @ldst_rr +STR_ri 1111 1000 0100 .... .... 1..1 ........ @ldst_ri_idx +STR_ri 1111 1000 0100 .... .... 1100 ........ @ldst_ri_neg +STRT_ri 1111 1000 0100 .... .... 1110 ........ @ldst_ri_unp +STR_ri 1111 1000 1100 .... .... ............ @ldst_ri_pos + +# Note that Load, unsigned (literal) overlaps all other load encodings. +{ + { + NOP 1111 1000 -001 1111 1111 ------------ # PLD + LDRB_ri 1111 1000 .001 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1000 1001 ---- 1111 ------------ # PLD + LDRB_ri 1111 1000 1001 .... .... ............ @ldst_ri_pos + } + LDRB_ri 1111 1000 0001 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1000 0001 ---- 1111 1100 -------- # PLD + LDRB_ri 1111 1000 0001 .... .... 1100 ........ @ldst_ri_neg + } + LDRBT_ri 1111 1000 0001 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1000 0001 ---- 1111 000000 -- ---- # PLD + LDRB_rr 1111 1000 0001 .... .... 000000 .. .... @ldst_rr + } +} +{ + { + NOP 1111 1000 -011 1111 1111 ------------ # PLD + LDRH_ri 1111 1000 .011 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1000 1011 ---- 1111 ------------ # PLDW + LDRH_ri 1111 1000 1011 .... .... ............ @ldst_ri_pos + } + LDRH_ri 1111 1000 0011 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1000 0011 ---- 1111 1100 -------- # PLDW + LDRH_ri 1111 1000 0011 .... .... 1100 ........ @ldst_ri_neg + } + LDRHT_ri 1111 1000 0011 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1000 0011 ---- 1111 000000 -- ---- # PLDW + LDRH_rr 1111 1000 0011 .... .... 000000 .. .... @ldst_rr + } +} +{ + LDR_ri 1111 1000 .101 1111 .... ............ @ldst_ri_lit + LDR_ri 1111 1000 1101 .... .... ............ @ldst_ri_pos + LDR_ri 1111 1000 0101 .... .... 1..1 ........ @ldst_ri_idx + LDR_ri 1111 1000 0101 .... .... 1100 ........ @ldst_ri_neg + LDRT_ri 1111 1000 0101 .... .... 1110 ........ @ldst_ri_unp + LDR_rr 1111 1000 0101 .... .... 000000 .. .... @ldst_rr +} +# NOPs here are PLI. +{ + { + NOP 1111 1001 -001 1111 1111 ------------ + LDRSB_ri 1111 1001 .001 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1001 1001 ---- 1111 ------------ + LDRSB_ri 1111 1001 1001 .... .... ............ @ldst_ri_pos + } + LDRSB_ri 1111 1001 0001 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1001 0001 ---- 1111 1100 -------- + LDRSB_ri 1111 1001 0001 .... .... 1100 ........ @ldst_ri_neg + } + LDRSBT_ri 1111 1001 0001 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1001 0001 ---- 1111 000000 -- ---- + LDRSB_rr 1111 1001 0001 .... .... 000000 .. .... @ldst_rr + } +} +# NOPs here are unallocated memory hints, treated as NOP. +{ + { + NOP 1111 1001 -011 1111 1111 ------------ + LDRSH_ri 1111 1001 .011 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1001 1011 ---- 1111 ------------ + LDRSH_ri 1111 1001 1011 .... .... ............ @ldst_ri_pos + } + LDRSH_ri 1111 1001 0011 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1001 0011 ---- 1111 1100 -------- + LDRSH_ri 1111 1001 0011 .... .... 1100 ........ @ldst_ri_neg + } + LDRSHT_ri 1111 1001 0011 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1001 0011 ---- 1111 000000 -- ---- + LDRSH_rr 1111 1001 0011 .... .... 000000 .. .... @ldst_rr + } +} + +%imm8x4 0:8 !function=3Dtimes_4 +&ldst_ri2 p w u rn rt rt2 imm +@ldstd_ri8 .... .... u:1 ... rn:4 rt:4 rt2:4 ........ \ + &ldst_ri2 imm=3D%imm8x4 + +STRD_ri_t32 1110 1000 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D0 +LDRD_ri_t32 1110 1000 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D0 + +STRD_ri_t32 1110 1001 .100 .... .... .... ........ @ldstd_ri8 w=3D= 0 p=3D1 +LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=3D= 0 p=3D1 + +STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 +LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 --=20 2.17.1 From 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kNBzQqD3B3o9SigDT6/pOwcq0pjl71BBo/Z7OB5fHLw=; b=L+HEd8Za5HBL2aQXB04r4C6y2WqX15WdSkUFLkn0Ree+Ds2syj1ydeZFd9Ti/2Ik84 XpUonOw6d9uEc3mccH8XnrVmVeDVV36t+IrdRZGKonwSY4ySbxQur0ywoEdtEgnjuP3p L75KybpQNHD5Vb1GPqQ3wT+6ixLURDgmJS1KuLv18C1jduF9mQfF7uOqbAv1P2GNfFJC PYxxPjWCvNpTkXYIFBensVg7ziVSNbBK62N1NIClbsQuiB1sBJFBYNAMIptAOgQZhAMm C1DEE45iWo0Iw6ds+9B3gZ/YjNXIQ4J+w7uZ6c0LTgxg3HO9WETaQ6dVWePnBNvUODPM HeFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kNBzQqD3B3o9SigDT6/pOwcq0pjl71BBo/Z7OB5fHLw=; b=lJ3V8NIl7I89RE/LZ0JwfO7UPRYMuuE7COQ09kOcByjr3QLTsT31vZ3prqzGSUWowX 4Pacxd4nPzWnTG8F5Bp5XCj9jALJ+1m9vJ/9MyqYIx214EHKardUzn20rAXoSqe7a2Tw hS1iHquZVW6l1lu4Ab+l0kUbA3cmqGdReN/aR51dpLD3AZTWvAfW9oDaCdKpxVm/UlBr 90EoC72gNWuzFMRgmXdeh+1nmnals0jDHvTkXgwNUJA5EGs7OVAtIucI5OIVWYXwgPeV kgX4aNk2IvKNm6ShpsXqe4GTj7hTqlCb5OD/bZOfXNr0ksmHM/8POamXA7lIPJ1Iyebt L8ug== X-Gm-Message-State: APjAAAXkCBMCObGiRxtgHKz+uZHQ9G94YH87P4iYGSFvPiVG7NPgSdJv Uws5UbqHaSfL6gkLdbZlpayLQHHSo1E= X-Google-Smtp-Source: APXvYqxLpA7lQZm1ctG6dvENSscIc/86NWUUcm7YpERnvCBNclOdm1uE86OxdN25H8vF6yGufl0qpw== X-Received: by 2002:aa7:9591:: with SMTP id z17mr6528146pfj.215.1567019126781; Wed, 28 Aug 2019 12:05:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:08 -0700 Message-Id: <20190828190456.30315-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 21/69] target/arm: Convert Synchronization primitives X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Fix arch test for {ld,st}rex[bh] Use unallocated_encoding for odd reg checks --- target/arm/translate.c | 576 +++++++++++++++++++++++------------------ target/arm/a32.decode | 48 ++++ target/arm/t32.decode | 46 ++++ 3 files changed, 412 insertions(+), 258 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index a92b90a4e3..10ec976bd9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8846,6 +8846,318 @@ DO_LDST(STRH, store, MO_UW) =20 #undef DO_LDST =20 +/* + * Synchronization primitives + */ + +static bool op_swp(DisasContext *s, arg_SWP *a, TCGMemOp opc) +{ + TCGv_i32 addr, tmp; + TCGv taddr; + + opc |=3D s->be_data; + addr =3D load_reg(s, a->rn); + taddr =3D gen_aa32_addr(s, addr, opc); + tcg_temp_free_i32(addr); + + tmp =3D load_reg(s, a->rt2); + tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, get_mem_index(s), opc); + tcg_temp_free(taddr); + + store_reg(s, a->rt, tmp); + return true; +} + +static bool trans_SWP(DisasContext *s, arg_SWP *a) +{ + return op_swp(s, a, MO_UL | MO_ALIGN); +} + +static bool trans_SWPB(DisasContext *s, arg_SWP *a) +{ + return op_swp(s, a, MO_UB); +} + +/* + * Load/Store Exclusive and Load-Acquire/Store-Release + */ + +static bool op_strex(DisasContext *s, arg_STREX *a, TCGMemOp mop, bool rel) +{ + TCGv_i32 addr; + + if (rel) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + + addr =3D tcg_temp_local_new_i32(); + load_reg_var(s, addr, a->rn); + tcg_gen_addi_i32(addr, addr, a->imm); + + gen_store_exclusive(s, a->rd, a->rt, a->rt2, addr, mop); + tcg_temp_free_i32(addr); + return true; +} + +static bool trans_STREX(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_strex(s, a, MO_32, false); +} + +static bool trans_STREXD_a32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + a->rt2 =3D a->rt + 1; + return op_strex(s, a, MO_64, false); +} + +static bool trans_STREXD_t32(DisasContext *s, arg_STREX *a) +{ + return op_strex(s, a, MO_64, false); +} + +static bool trans_STREXB(DisasContext *s, arg_STREX *a) +{ + if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { + return false; + } + return op_strex(s, a, MO_8, false); +} + +static bool trans_STREXH(DisasContext *s, arg_STREX *a) +{ + if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { + return false; + } + return op_strex(s, a, MO_16, false); +} + +static bool trans_STLEX(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_32, true); +} + +static bool trans_STLEXD_a32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + a->rt2 =3D a->rt + 1; + return op_strex(s, a, MO_64, true); +} + +static bool trans_STLEXD_t32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_64, true); +} + +static bool trans_STLEXB(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_8, true); +} + +static bool trans_STLEXH(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_16, true); +} + +static bool op_stl(DisasContext *s, arg_STL *a, TCGMemOp mop) +{ + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_8) { + return false; + } + addr =3D load_reg(s, a->rn); + + tmp =3D load_reg(s, a->rt); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(addr); + return true; +} + +static bool trans_STL(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UL); +} + +static bool trans_STLB(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UB); +} + +static bool trans_STLH(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UW); +} + +static bool op_ldrex(DisasContext *s, arg_LDREX *a, TCGMemOp mop, bool acq) +{ + TCGv_i32 addr; + + addr =3D tcg_temp_local_new_i32(); + load_reg_var(s, addr, a->rn); + tcg_gen_addi_i32(addr, addr, a->imm); + + gen_load_exclusive(s, a->rt, a->rt2, addr, mop); + tcg_temp_free_i32(addr); + + if (acq) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + return true; +} + +static bool trans_LDREX(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_ldrex(s, a, MO_32, false); +} + +static bool trans_LDREXD_a32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + a->rt2 =3D a->rt + 1; + return op_ldrex(s, a, MO_64, false); +} + +static bool trans_LDREXD_t32(DisasContext *s, arg_LDREX *a) +{ + return op_ldrex(s, a, MO_64, false); +} + +static bool trans_LDREXB(DisasContext *s, arg_LDREX *a) +{ + if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { + return false; + } + return op_ldrex(s, a, MO_8, false); +} + +static bool trans_LDREXH(DisasContext *s, arg_LDREX *a) +{ + if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { + return false; + } + return op_ldrex(s, a, MO_16, false); +} + +static bool trans_LDAEX(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_32, true); +} + +static bool trans_LDAEXD_a32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + a->rt2 =3D a->rt + 1; + return op_ldrex(s, a, MO_64, true); +} + +static bool trans_LDAEXD_t32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_64, true); +} + +static bool trans_LDAEXB(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_8, true); +} + +static bool trans_LDAEXH(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_16, true); +} + +static bool op_lda(DisasContext *s, arg_LDA *a, TCGMemOp mop) +{ + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_8) { + return false; + } + addr =3D load_reg(s, a->rn); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); + tcg_temp_free_i32(addr); + + store_reg(s, a->rt, tmp); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + return true; +} + +static bool trans_LDA(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UL); +} + +static bool trans_LDAB(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UB); +} + +static bool trans_LDAH(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UW); +} + /* * Legacy decoder. */ @@ -9141,172 +9453,8 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) case 0x0: case 0x1: /* multiplies, extra load/stores */ - sh =3D (insn >> 5) & 3; - if (sh =3D=3D 0) { - if (op1 =3D=3D 0x0) { - /* Multiply and multiply accumulate. */ - /* All done in decodetree. Reach here for illegal ops= . */ - goto illegal_op; - } else { - rn =3D (insn >> 16) & 0xf; - rd =3D (insn >> 12) & 0xf; - if (insn & (1 << 23)) { - /* load/store exclusive */ - bool is_ld =3D extract32(insn, 20, 1); - bool is_lasr =3D !extract32(insn, 8, 1); - int op2 =3D (insn >> 8) & 3; - op1 =3D (insn >> 21) & 0x3; - - switch (op2) { - case 0: /* lda/stl */ - if (op1 =3D=3D 1) { - goto illegal_op; - } - ARCH(8); - break; - case 1: /* reserved */ - goto illegal_op; - case 2: /* ldaex/stlex */ - ARCH(8); - break; - case 3: /* ldrex/strex */ - if (op1) { - ARCH(6K); - } else { - ARCH(6); - } - break; - } - - addr =3D tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - - if (is_lasr && !is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - - if (op2 =3D=3D 0) { - if (is_ld) { - tmp =3D tcg_temp_new_i32(); - switch (op1) { - case 0: /* lda */ - gen_aa32_ld32u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - case 2: /* ldab */ - gen_aa32_ld8u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - case 3: /* ldah */ - gen_aa32_ld16u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - default: - abort(); - } - store_reg(s, rd, tmp); - } else { - rm =3D insn & 0xf; - tmp =3D load_reg(s, rm); - switch (op1) { - case 0: /* stl */ - gen_aa32_st32_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - case 2: /* stlb */ - gen_aa32_st8_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - case 3: /* stlh */ - gen_aa32_st16_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - default: - abort(); - } - tcg_temp_free_i32(tmp); - } - } else if (is_ld) { - switch (op1) { - case 0: /* ldrex */ - gen_load_exclusive(s, rd, 15, addr, 2); - break; - case 1: /* ldrexd */ - gen_load_exclusive(s, rd, rd + 1, addr, 3); - break; - case 2: /* ldrexb */ - gen_load_exclusive(s, rd, 15, addr, 0); - break; - case 3: /* ldrexh */ - gen_load_exclusive(s, rd, 15, addr, 1); - break; - default: - abort(); - } - } else { - rm =3D insn & 0xf; - switch (op1) { - case 0: /* strex */ - gen_store_exclusive(s, rd, rm, 15, addr, 2= ); - break; - case 1: /* strexd */ - gen_store_exclusive(s, rd, rm, rm + 1, add= r, 3); - break; - case 2: /* strexb */ - gen_store_exclusive(s, rd, rm, 15, addr, 0= ); - break; - case 3: /* strexh */ - gen_store_exclusive(s, rd, rm, 15, addr, 1= ); - break; - default: - abort(); - } - } - tcg_temp_free_i32(addr); - - if (is_lasr && is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } - } else if ((insn & 0x00300f00) =3D=3D 0) { - /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx - * - SWP, SWPB - */ - - TCGv taddr; - TCGMemOp opc =3D s->be_data; - - rm =3D (insn) & 0xf; - - if (insn & (1 << 22)) { - opc |=3D MO_UB; - } else { - opc |=3D MO_UL | MO_ALIGN; - } - - addr =3D load_reg(s, rn); - taddr =3D gen_aa32_addr(s, addr, opc); - tcg_temp_free_i32(addr); - - tmp =3D load_reg(s, rm); - tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, - get_mem_index(s), opc); - tcg_temp_free(taddr); - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - } - } else { - /* Extra load/store (register) instructions */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; break; case 0x4: case 0x5: @@ -9952,15 +10100,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) } goto illegal_op; } - addr =3D tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2); - if (insn & (1 << 20)) { - gen_load_exclusive(s, rs, 15, addr, 2); - } else { - gen_store_exclusive(s, rd, rs, 15, addr, 2); - } - tcg_temp_free_i32(addr); + /* Load/store exclusive, in decodetree */ + goto illegal_op; } else if ((insn & (7 << 5)) =3D=3D 0) { /* Table Branch. */ addr =3D load_reg(s, rn); @@ -9982,89 +10123,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) tcg_gen_addi_i32(tmp, tmp, read_pc(s)); store_reg(s, 15, tmp); } else { - bool is_lasr =3D false; - bool is_ld =3D extract32(insn, 20, 1); - int op2 =3D (insn >> 6) & 0x3; - op =3D (insn >> 4) & 0x3; - switch (op2) { - case 0: - goto illegal_op; - case 1: - /* Load/store exclusive byte/halfword/doubleword */ - if (op =3D=3D 2) { - goto illegal_op; - } - ARCH(7); - break; - case 2: - /* Load-acquire/store-release */ - if (op =3D=3D 3) { - goto illegal_op; - } - /* Fall through */ - case 3: - /* Load-acquire/store-release exclusive */ - ARCH(8); - is_lasr =3D true; - break; - } - - if (is_lasr && !is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - - addr =3D tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - if (!(op2 & 1)) { - if (is_ld) { - tmp =3D tcg_temp_new_i32(); - switch (op) { - case 0: /* ldab */ - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(= s), - rs | ISSIsAcqRel); - break; - case 1: /* ldah */ - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index= (s), - rs | ISSIsAcqRel); - break; - case 2: /* lda */ - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index= (s), - rs | ISSIsAcqRel); - break; - default: - abort(); - } - store_reg(s, rs, tmp); - } else { - tmp =3D load_reg(s, rs); - switch (op) { - case 0: /* stlb */ - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s= ), - rs | ISSIsAcqRel); - break; - case 1: /* stlh */ - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(= s), - rs | ISSIsAcqRel); - break; - case 2: /* stl */ - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(= s), - rs | ISSIsAcqRel); - break; - default: - abort(); - } - tcg_temp_free_i32(tmp); - } - } else if (is_ld) { - gen_load_exclusive(s, rs, rd, addr, op); - } else { - gen_store_exclusive(s, rm, rs, rd, addr, op); - } - tcg_temp_free_i32(addr); - - if (is_lasr && is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } + /* Load/store exclusive, load-acq/store-rel, in decodetree= */ + goto illegal_op; } } else { /* Load/store multiple, RFE, SRS. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index f7742deaee..c76cbad569 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -39,6 +39,8 @@ &mrs_bank rd r sysm &ldst_rr p w u rn rt rm shimm shtype &ldst_ri p w u rn rt imm +&strex rn rd rt rt2 imm +&ldrex rn rt rt2 imm =20 # Data-processing (register) =20 @@ -342,3 +344,49 @@ STRT_ri .... 010. .0.0 .... .... ............= @ldst_ri12_p0w1 STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p= 0w1 LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p= 0w1 LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p= 0w1 + +# Synchronization primitives + +@swp ---- .... .... rn:4 rt:4 .... .... rt2:4 + +SWP .... 0001 0000 .... .... 0000 1001 .... @swp +SWPB .... 0001 0100 .... .... 0000 1001 .... @swp + +# Load/Store Exclusive and Load-Acquire/Store-Release +# +# Note rt2 for STREXD/LDREXD is set by the helper after checking rt is eve= n. + +@strex ---- .... .... rn:4 rd:4 .... .... rt:4 \ + &strex imm=3D0 rt2=3D15 +@ldrex ---- .... .... rn:4 rt:4 .... .... .... \ + &ldrex imm=3D0 rt2=3D15 +@stl ---- .... .... rn:4 .... .... .... rt:4 \ + &ldrex imm=3D0 rt2=3D15 + +STREX .... 0001 1000 .... .... 1111 1001 .... @strex +STREXD_a32 .... 0001 1010 .... .... 1111 1001 .... @strex +STREXB .... 0001 1100 .... .... 1111 1001 .... @strex +STREXH .... 0001 1110 .... .... 1111 1001 .... @strex + +STLEX .... 0001 1000 .... .... 1110 1001 .... @strex +STLEXD_a32 .... 0001 1010 .... .... 1110 1001 .... @strex +STLEXB .... 0001 1100 .... .... 1110 1001 .... @strex +STLEXH .... 0001 1110 .... .... 1110 1001 .... @strex + +STL .... 0001 1000 .... 1111 1100 1001 .... @stl +STLB .... 0001 1100 .... 1111 1100 1001 .... @stl +STLH .... 0001 1110 .... 1111 1100 1001 .... @stl + +LDREX .... 0001 1001 .... .... 1111 1001 1111 @ldrex +LDREXD_a32 .... 0001 1011 .... .... 1111 1001 1111 @ldrex +LDREXB .... 0001 1101 .... .... 1111 1001 1111 @ldrex +LDREXH .... 0001 1111 .... .... 1111 1001 1111 @ldrex + +LDAEX .... 0001 1001 .... .... 1110 1001 1111 @ldrex +LDAEXD_a32 .... 0001 1011 .... .... 1110 1001 1111 @ldrex +LDAEXB .... 0001 1101 .... .... 1110 1001 1111 @ldrex +LDAEXH .... 0001 1111 .... .... 1110 1001 1111 @ldrex + +LDA .... 0001 1001 .... .... 1100 1001 1111 @ldrex +LDAB .... 0001 1101 .... .... 1100 1001 1111 @ldrex +LDAH .... 0001 1111 .... .... 1100 1001 1111 @ldrex diff --git a/target/arm/t32.decode b/target/arm/t32.decode index a86597562b..70cf8039d7 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -36,6 +36,8 @@ &mrs_bank !extern rd r sysm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&strex !extern rn rd rt rt2 imm +&ldrex !extern rn rt rt2 imm =20 # Data-processing (register) =20 @@ -392,3 +394,47 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... .......= . @ldstd_ri8 w=3D0 p=3D1 =20 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 + +# Load/Store Exclusive and Load-Acquire/Store-Release + +@strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \ + &strex rt2=3D15 imm=3D%imm8x4 +@strex_0 .... .... .... rn:4 rt:4 .... .... rd:4 \ + &strex rt2=3D15 imm=3D0 +@strex_d .... .... .... rn:4 rt:4 rt2:4 .... rd:4 \ + &strex imm=3D0 + +@ldrex_i .... .... .... rn:4 rt:4 .... .... .... \ + &ldrex rt2=3D15 imm=3D%imm8x4 +@ldrex_0 .... .... .... rn:4 rt:4 .... .... .... \ + &ldrex rt2=3D15 imm=3D0 +@ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \ + &ldrex imm=3D0 + +STREX 1110 1000 0100 .... .... .... .... .... @strex_i +STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0 +STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0 +STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d + +STLEX 1110 1000 1100 .... .... 1111 1110 .... @strex_0 +STLEXB 1110 1000 1100 .... .... 1111 1100 .... @strex_0 +STLEXH 1110 1000 1100 .... .... 1111 1101 .... @strex_0 +STLEXD_t32 1110 1000 1100 .... .... .... 1111 .... @strex_d + +STL 1110 1000 1100 .... .... 1111 1010 1111 @ldrex_0 +STLB 1110 1000 1100 .... .... 1111 1000 1111 @ldrex_0 +STLH 1110 1000 1100 .... .... 1111 1001 1111 @ldrex_0 + +LDREX 1110 1000 0101 .... .... 1111 .... .... @ldrex_i +LDREXB 1110 1000 1101 .... .... 1111 0100 1111 @ldrex_0 +LDREXH 1110 1000 1101 .... .... 1111 0101 1111 @ldrex_0 +LDREXD_t32 1110 1000 1101 .... .... .... 0111 1111 @ldrex_d + +LDAEX 1110 1000 1101 .... .... 1111 1110 1111 @ldrex_0 +LDAEXB 1110 1000 1101 .... .... 1111 1100 1111 @ldrex_0 +LDAEXH 1110 1000 1101 .... .... 1111 1101 1111 @ldrex_0 +LDAEXD_t32 1110 1000 1101 .... .... .... 1111 1111 @ldrex_d + +LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 +LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 +LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567020890; cv=none; d=zoho.com; s=zohoarc; b=XLb64JVry6/WgycuUOOxGVogL7YizH3C3J/o7bMZfYx6ETlll1FFdz7RCBC3f0PTP6hTdAjLRYjtklxXYrmH2VUZrSzVvSziV601BUe5PB2wXiH/0R9IBXWcOBhunM6PNR0Exq3bMMhlQPmYIUDi7haDrPASDxNbdg5zGp4CfnE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567020890; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ZPbSh9zJCU6tFB8sqkv7S5LslxkLSpT7ZOLVU6IYp00=; b=SzXrqCSdi9P6qynmBc0Tvk4mn7dBVClvexipBQ9cEmB3rqocjDfwJYYgZH3darwzU8Heu70FJqkrje/y6aYqRiZiePnT03w1U2R0SGpJ9FrRjsJormz7s6kgXeRXZT8EjDetejPd95+nomiTj9kLFimdJQmjmpiZGghjVdDuxnQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567020890591584.6724861988907; Wed, 28 Aug 2019 12:34:50 -0700 (PDT) Received: from localhost ([::1]:41354 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33iS-000675-CV for importer@patchew.org; Wed, 28 Aug 2019 15:34:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37864) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33G8-0003Wr-6L for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33G6-0000AR-5c for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:32 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:41376) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33G5-00009y-Na for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:30 -0400 Received: by mail-pl1-x641.google.com with SMTP id m9so390610pls.8 for ; Wed, 28 Aug 2019 12:05:29 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 22/69] target/arm: Diagnose UNPREDICTABLE ldrex/strex cases X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 10ec976bd9..3f61916ff9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8886,6 +8886,18 @@ static bool op_strex(DisasContext *s, arg_STREX *a, = TCGMemOp mop, bool rel) { TCGv_i32 addr; =20 + /* We UNDEF for these UNPREDICTABLE cases. */ + if (a->rd =3D=3D 15 || a->rn =3D=3D 15 || a->rt =3D=3D 15 + || a->rd =3D=3D a->rn || a->rd =3D=3D a->rt + || (s->thumb && (a->rd =3D=3D 13 || a->rt =3D=3D 13)) + || (mop =3D=3D MO_64 + && (a->rt2 =3D=3D 15 + || a->rd =3D=3D a->rt2 || a->rt =3D=3D a->rt2 + || (s->thumb && a->rt2 =3D=3D 13)))) { + unallocated_encoding(s); + return true; + } + if (rel) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } @@ -8912,6 +8924,7 @@ static bool trans_STREXD_a32(DisasContext *s, arg_STR= EX *a) if (!ENABLE_ARCH_6K) { return false; } + /* We UNDEF for these UNPREDICTABLE cases. */ if (a->rt & 1) { unallocated_encoding(s); return true; @@ -8954,6 +8967,7 @@ static bool trans_STLEXD_a32(DisasContext *s, arg_STR= EX *a) if (!ENABLE_ARCH_8) { return false; } + /* We UNDEF for these UNPREDICTABLE cases. */ if (a->rt & 1) { unallocated_encoding(s); return true; @@ -8993,8 +9007,13 @@ static bool op_stl(DisasContext *s, arg_STL *a, TCGM= emOp mop) if (!ENABLE_ARCH_8) { return false; } - addr =3D load_reg(s, a->rn); + /* We UNDEF for these UNPREDICTABLE cases. */ + if (a->rn =3D=3D 15 || a->rt =3D=3D 15) { + unallocated_encoding(s); + return true; + } =20 + addr =3D load_reg(s, a->rn); tmp =3D load_reg(s, a->rt); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); @@ -9024,6 +9043,16 @@ static bool op_ldrex(DisasContext *s, arg_LDREX *a, = TCGMemOp mop, bool acq) { TCGv_i32 addr; =20 + /* We UNDEF for these UNPREDICTABLE cases. */ + if (a->rn =3D=3D 15 || a->rt =3D=3D 15 + || (s->thumb && a->rt =3D=3D 13) + || (mop =3D=3D MO_64 + && (a->rt2 =3D=3D 15 || a->rt =3D=3D a->rt2 + || (s->thumb && a->rt2 =3D=3D 13)))) { + unallocated_encoding(s); + return true; + } + addr =3D tcg_temp_local_new_i32(); load_reg_var(s, addr, a->rn); tcg_gen_addi_i32(addr, addr, a->imm); @@ -9050,6 +9079,7 @@ static bool trans_LDREXD_a32(DisasContext *s, arg_LDR= EX *a) if (!ENABLE_ARCH_6K) { return false; } + /* We UNDEF for these UNPREDICTABLE cases. */ if (a->rt & 1) { unallocated_encoding(s); return true; @@ -9092,6 +9122,7 @@ static bool trans_LDAEXD_a32(DisasContext *s, arg_LDR= EX *a) if (!ENABLE_ARCH_8) { return false; } + /* We UNDEF for these UNPREDICTABLE cases. */ if (a->rt & 1) { unallocated_encoding(s); return true; @@ -9131,8 +9162,13 @@ static bool op_lda(DisasContext *s, arg_LDA *a, TCGM= emOp mop) if (!ENABLE_ARCH_8) { return false; } - addr =3D load_reg(s, a->rn); + /* We UNDEF for these UNPREDICTABLE cases. */ + if (a->rn =3D=3D 15 || a->rt =3D=3D 15) { + unallocated_encoding(s); + return true; + } =20 + addr =3D load_reg(s, a->rn); tmp =3D tcg_temp_new_i32(); gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ddiE45pWeV7oZBDXDk+1vWfTRlgNhM08BhLXCnQaj24=; b=aoHcAeH2KjS0sDltOOCoyx9guO04jkhV+qxU+F1GCcf1j5EajJ4NbxkJotrXEIkr0G Th7btlxtx0NaZSPIeXmDUVXV+k1FI37MPkw6u0eWAApveVg9g6AR4HAyKaH6044riUhq bDAmPxLrfom1mUP90e0UjpjOoavEro3KSQVzDM/crRlPXXVxvLFplQECv1fc5SGthlOb Kuw7wCpPy1IekmMnuyr866uLLLHnBC1V/odgfDLl7j1vQTFDArhsux6JkVZpuD9aTyi5 PZPCrO5gbos4JVF3bBt4pTkTqQ77j4Q8Fv81yuSgCDuyMIrxtJcfB2Jw3e8o1XyDzl8o aVVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ddiE45pWeV7oZBDXDk+1vWfTRlgNhM08BhLXCnQaj24=; b=N5eeoHzF43aTlZwFLk8GUFp+toi+1MoiUjR0h+brp+uvzR2E+y6Fl/tYJQoJiFpzDa t9mCOr6Z0elQx+W5Heu9PYRrfUV6eSgk+QVIx1HxDxn4tWAQVTwQyJG/f6jForsXcl+j VJR9khtnIGLrDKonRjqB1YgqT6nq5dttGJm/n7unv03cxm2RIyiRT+0mrR3CfXZ7/kYB LcGjtVnn5vy1PZfldrXeDoKSNn4NJSOU3egdF37JeuhMDzQ9h8La7Idacl9YG7G65UNn E1fiN2aCnDRHcX2TYmEz+WjNnE6Ha7vWSpnOd5Qt6HL4seyKnFtOYlxnZcvDCVs4l5m2 /h0g== X-Gm-Message-State: APjAAAWPtBJDbDUptr5v9hDaCsE1ZoehjxGakACR2RFJZSZOW8/LpCQa fnVRWOHIdLAgSRgRcOv2jW8y9/p1bFc= X-Google-Smtp-Source: APXvYqzyDqeMk0IWGNMB1TKlX9/aLaqjeMv+kmOrGt8b1BQDoyTQ6KSFQSNmIGMs/PvrA+8tko3lkg== X-Received: by 2002:aa7:96b3:: with SMTP id g19mr6318408pfk.26.1567019129407; Wed, 28 Aug 2019 12:05:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:10 -0700 Message-Id: <20190828190456.30315-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PATCH v3 23/69] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In op_bfx, note that tcg_gen_{,s}extract_i32 already checks for width =3D=3D 32, so we don't need to special case that here. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding for out-of-range bitops. --- target/arm/translate.c | 201 +++++++++++++++++++++-------------------- target/arm/a32.decode | 20 ++++ target/arm/t32.decode | 19 ++++ 3 files changed, 144 insertions(+), 96 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 3f61916ff9..adc0a0f022 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9194,6 +9194,104 @@ static bool trans_LDAH(DisasContext *s, arg_LDA *a) return op_lda(s, a, MO_UW); } =20 +/* + * Media instructions + */ + +static bool trans_USADA8(DisasContext *s, arg_USADA8 *a) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + gen_helper_usad8(t1, t1, t2); + tcg_temp_free_i32(t2); + if (a->ra !=3D 15) { + t2 =3D load_reg(s, a->ra); + tcg_gen_add_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool op_bfx(DisasContext *s, arg_UBFX *a, bool u) +{ + TCGv_i32 tmp; + int width =3D a->widthm1 + 1; + int shift =3D a->lsb; + + if (!ENABLE_ARCH_6T2) { + return false; + } + if (shift + width > 32) { + /* UNPREDICTABLE; we choose to UNDEF */ + unallocated_encoding(s); + return true; + } + + tmp =3D load_reg(s, a->rn); + if (u) { + tcg_gen_extract_i32(tmp, tmp, shift, width); + } else { + tcg_gen_sextract_i32(tmp, tmp, shift, width); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SBFX(DisasContext *s, arg_SBFX *a) +{ + return op_bfx(s, a, false); +} + +static bool trans_UBFX(DisasContext *s, arg_UBFX *a) +{ + return op_bfx(s, a, true); +} + +static bool trans_BFCI(DisasContext *s, arg_BFCI *a) +{ + TCGv_i32 tmp; + int msb =3D a->msb, lsb =3D a->lsb; + int width; + + if (!ENABLE_ARCH_6T2) { + return false; + } + if (msb < lsb) { + /* UNPREDICTABLE; we choose to UNDEF */ + unallocated_encoding(s); + return true; + } + + width =3D msb + 1 - lsb; + if (a->rn =3D=3D 15) { + /* BFC */ + tmp =3D tcg_const_i32(0); + } else { + /* BFI */ + tmp =3D load_reg(s, a->rn); + } + if (width !=3D 32) { + TCGv_i32 tmp2 =3D load_reg(s, a->rd); + tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width); + tcg_temp_free_i32(tmp2); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_UDF(DisasContext *s, arg_UDF *a) +{ + unallocated_encoding(s); + return true; +} + /* * Legacy decoder. */ @@ -9734,65 +9832,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) } break; case 3: - op1 =3D ((insn >> 17) & 0x38) | ((insn >> 5) & 7); - switch (op1) { - case 0: /* Unsigned sum of absolute differences. */ - ARCH(6); - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - gen_helper_usad8(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rd !=3D 15) { - tmp2 =3D load_reg(s, rd); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rn, tmp); - break; - case 0x20: case 0x24: case 0x28: case 0x2c: - /* Bitfield insert/clear. */ - ARCH(6T2); - shift =3D (insn >> 7) & 0x1f; - i =3D (insn >> 16) & 0x1f; - if (i < shift) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - i =3D i + 1 - shift; - if (rm =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp =3D load_reg(s, rm); - } - if (i !=3D 32) { - tmp2 =3D load_reg(s, rd); - tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, i); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - break; - case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */ - case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */ - ARCH(6T2); - tmp =3D load_reg(s, rm); - shift =3D (insn >> 7) & 0x1f; - i =3D ((insn >> 16) & 0x1f) + 1; - if (shift + i > 32) - goto illegal_op; - if (i < 32) { - if (op1 & 0x20) { - tcg_gen_extract_i32(tmp, tmp, shift, i); - } else { - tcg_gen_sextract_i32(tmp, tmp, shift, i); - } - } - store_reg(s, rd, tmp); - break; - default: - goto illegal_op; - } - break; + /* USAD, BFI, BFC, SBFX, UBFX */ + /* Done by decodetree */ + goto illegal_op; } break; } @@ -10431,10 +10473,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) case 0: /* 32 x 32 -> 32 */ case 1: /* 16 x 16 -> 32 */ case 3: /* 32 * 16 -> 32msb */ + case 7: /* Unsigned sum of absolute differences. */ /* in decodetree */ goto illegal_op; - case 7: /* Unsigned sum of absolute differences. */ - break; case 2: /* Dual multiply add. */ case 4: /* Dual multiply subtract. */ case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ @@ -10492,15 +10533,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } tcg_temp_free_i32(tmp2); break; - case 7: /* Unsigned sum of absolute differences. */ - gen_helper_usad8(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rs !=3D 15) { - tmp2 =3D load_reg(s, rs); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; } store_reg(s, rd, tmp); break; @@ -10795,32 +10827,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tmp =3D load_reg(s, rn); } switch (op) { - case 2: /* Signed bitfield extract. */ - imm++; - if (shift + imm > 32) - goto illegal_op; - if (imm < 32) { - tcg_gen_sextract_i32(tmp, tmp, shift, imm); - } - break; - case 6: /* Unsigned bitfield extract. */ - imm++; - if (shift + imm > 32) - goto illegal_op; - if (imm < 32) { - tcg_gen_extract_i32(tmp, tmp, shift, imm); - } - break; - case 3: /* Bitfield insert/clear. */ - if (imm < shift) - goto illegal_op; - imm =3D imm + 1 - shift; - if (imm !=3D 32) { - tmp2 =3D load_reg(s, rd); - tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, imm= ); - tcg_temp_free_i32(tmp2); - } - break; + case 2: /* Signed bitfield extract, in decodetree */ + case 6: /* Unsigned bitfield extract, in decodetree */ + case 3: /* Bitfield insert/clear, in decodetree */ case 7: goto illegal_op; default: /* Saturate. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index c76cbad569..285c08ca22 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -41,6 +41,8 @@ &ldst_ri p w u rn rt imm &strex rn rd rt rt2 imm &ldrex rn rt rt2 imm +&bfx rd rn lsb widthm1 +&bfi rd rn lsb msb =20 # Data-processing (register) =20 @@ -390,3 +392,21 @@ LDAEXH .... 0001 1111 .... .... 1110 1001 11= 11 @ldrex LDA .... 0001 1001 .... .... 1100 1001 1111 @ldrex LDAB .... 0001 1101 .... .... 1100 1001 1111 @ldrex LDAH .... 0001 1111 .... .... 1100 1001 1111 @ldrex + +# Media instructions + +# usad8 is usada8 w/ ra=3D15 +USADA8 ---- 0111 1000 rd:4 ra:4 rm:4 0001 rn:4 + +# ubfx and sbfx +@bfx ---- .... ... widthm1:5 rd:4 lsb:5 ... rn:4 &bfx + +SBFX .... 0111 101 ..... .... ..... 101 .... @bfx +UBFX .... 0111 111 ..... .... ..... 101 .... @bfx + +# bfc is bfi w/ rn=3D15 +BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn:4 &bfi + +# While we could get UDEF by not including this, add the pattern for +# documentation and to conflict with any other typos in this file. +UDF 1110 0111 1111 ---- ---- ---- 1111 ---- diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 70cf8039d7..682fc5c2c4 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -38,6 +38,8 @@ &ldst_ri !extern p w u rn rt imm &strex !extern rn rd rt rt2 imm &ldrex !extern rn rt rt2 imm +&bfx !extern rd rn lsb widthm1 +&bfi !extern rd rn lsb msb =20 # Data-processing (register) =20 @@ -144,6 +146,19 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... .....= ... @s_rri_rot SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 } =20 +# Saturate, bitfield + +@bfx .... .... ... . rn:4 . ... rd:4 .. . widthm1:5 \ + &bfx lsb=3D%imm5_12_6 +@bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \ + &bfi lsb=3D%imm5_12_6 + +SBFX 1111 0011 010 0 .... 0 ... .... ..0..... @bfx +UBFX 1111 0011 110 0 .... 0 ... .... ..0..... @bfx + +# bfc is bfi w/ rn=3D15 +BFCI 1111 0011 011 0 .... 0 ... .... ..0..... @bfi + # Multiply and multiply accumulate =20 @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 @@ -192,6 +207,9 @@ SMLALBT 1111 1011 1100 .... .... .... 1001 ...= . @rnadm SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm =20 +# usad8 is usada8 w/ ra=3D15 +USADA8 1111 1011 0111 .... .... .... 0000 .... @rnadm + # Data-processing (two source registers) =20 QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm @@ -254,6 +272,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ...= . @rdm SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=3D%imm16_16_0 + UDF 1111 0111 1111 ---- 1010 ---- ---- ---- } =20 # Load/store (register, immediate, literal) --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mep0vFi11PfcusdAY5maYxXY8aLjJHFKL1U21aZXTOg=; b=RZth7B6juJFncpqwfSyTvZXJKkUcJDLliad6DODdhGqx0HPEWv8DdXFA2wiP404hol QhzRN5ioUy09Tcoteb7j/aQ6FlVBaVntjgNgP9/x6uS/xE8gtmjGLSb7miac2BO+JoaV Xsiagld4OCfQk8qPP8TYNdz0jVDDCpoviz0BDmi+iELEQPdweVsMPspRO/jHF98V2dGW KSq5z0caT/p2qPw3MYnCVlaiBFS1iKzkDbMYnHYmKdKafGOQvHyTZQFApOpbVR62bmd6 Iks25DqkTnCKwU39n0obUqlsxwX8ioIVL9SoZ2vKKmG1ViLG4z2RjEazORJOOoQRtZrk ZRcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mep0vFi11PfcusdAY5maYxXY8aLjJHFKL1U21aZXTOg=; b=DmH3elWA4gKXefinAHjYPSgIcEL3zIHHuiRw6Ai0bDA/KvsPYclxcED1+g8azJV6FK WtNTMjLnYkLqN06hfs8TqUrHhKUg6AbQkwt/XFb4DyYT0pToT+3piE/4vSPNFiQmT4Dg rmOl8lDk3Rkn5AwEcB81evqDnjiwZIEKrss7c1JHe1PHNK5dPefmrSYmrU4hpP/A5nv9 4MP0N9/rdCInzkqrMONv+LC3hrFtTfUBH7ma0HS4YCL6JRrbkMka0n8qDuxAsSesmnMK 0oS+N/Gteb6X0RuHIph3T9+8PV3vVU5KBbjpVtFCGx1n4FiB1qV/oOKQcoRPgTkEevM3 5PTg== X-Gm-Message-State: APjAAAWgs6TMOUjR+J74WS6Hxa07+R1+CY7wZXuoUuAmGCJkOqplT4rO /+Yz0qFh1qiwE4ko2g+v4FlxA75cIXo= X-Google-Smtp-Source: APXvYqynWzROJR/UvsziSNsB1CjdAjkNGFNBuJ9Act1K8ROr/dNR6mqcfteo8hyZAc6S1CgGSK+o3g== X-Received: by 2002:a17:902:20e3:: with SMTP id v32mr5593817plg.142.1567019130643; Wed, 28 Aug 2019 12:05:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:11 -0700 Message-Id: <20190828190456.30315-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 24/69] target/arm: Convert Parallel addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 229 ++++++++++++++++++++--------------------- target/arm/a32.decode | 44 ++++++++ target/arm/t32.decode | 44 ++++++++ 3 files changed, 200 insertions(+), 117 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index adc0a0f022..eb9d1d71ce 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -648,99 +648,6 @@ static inline void gen_arm_shift_reg(TCGv_i32 var, int= shiftop, tcg_temp_free_i32(shift); } =20 -#define PAS_OP(pfx) \ - switch (op2) { \ - case 0: gen_pas_helper(glue(pfx,add16)); break; \ - case 1: gen_pas_helper(glue(pfx,addsubx)); break; \ - case 2: gen_pas_helper(glue(pfx,subaddx)); break; \ - case 3: gen_pas_helper(glue(pfx,sub16)); break; \ - case 4: gen_pas_helper(glue(pfx,add8)); break; \ - case 7: gen_pas_helper(glue(pfx,sub8)); break; \ - } -static void gen_arm_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32= b) -{ - TCGv_ptr tmp; - - switch (op1) { -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) - case 1: - tmp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(s) - tcg_temp_free_ptr(tmp); - break; - case 5: - tmp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(u) - tcg_temp_free_ptr(tmp); - break; -#undef gen_pas_helper -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) - case 2: - PAS_OP(q); - break; - case 3: - PAS_OP(sh); - break; - case 6: - PAS_OP(uq); - break; - case 7: - PAS_OP(uh); - break; -#undef gen_pas_helper - } -} -#undef PAS_OP - -/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings= . */ -#define PAS_OP(pfx) \ - switch (op1) { \ - case 0: gen_pas_helper(glue(pfx,add8)); break; \ - case 1: gen_pas_helper(glue(pfx,add16)); break; \ - case 2: gen_pas_helper(glue(pfx,addsubx)); break; \ - case 4: gen_pas_helper(glue(pfx,sub8)); break; \ - case 5: gen_pas_helper(glue(pfx,sub16)); break; \ - case 6: gen_pas_helper(glue(pfx,subaddx)); break; \ - } -static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_= i32 b) -{ - TCGv_ptr tmp; - - switch (op2) { -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) - case 0: - tmp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(s) - tcg_temp_free_ptr(tmp); - break; - case 4: - tmp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(u) - tcg_temp_free_ptr(tmp); - break; -#undef gen_pas_helper -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) - case 1: - PAS_OP(q); - break; - case 2: - PAS_OP(sh); - break; - case 5: - PAS_OP(uq); - break; - case 6: - PAS_OP(uh); - break; -#undef gen_pas_helper - } -} -#undef PAS_OP - /* * Generate a conditional based on ARM condition code cc. * This is common between ARM and Aarch64 targets. @@ -9292,6 +9199,114 @@ static bool trans_UDF(DisasContext *s, arg_UDF *a) return true; } =20 +/* + * Parallel addition and subtraction + */ + +static bool op_par_addsub(DisasContext *s, arg_rrr *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 t0, t1; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 =3D load_reg(s, a->rn); + t1 =3D load_reg(s, a->rm); + + gen(t0, t0, t1); + + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +static bool op_par_addsub_ge(DisasContext *s, arg_rrr *a, + void (*gen)(TCGv_i32, TCGv_i32, + TCGv_i32, TCGv_ptr)) +{ + TCGv_i32 t0, t1; + TCGv_ptr ge; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 =3D load_reg(s, a->rn); + t1 =3D load_reg(s, a->rm); + + ge =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ge, cpu_env, offsetof(CPUARMState, GE)); + gen(t0, t0, t1, ge); + + tcg_temp_free_ptr(ge); + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +#define DO_PAR_ADDSUB(NAME, helper) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_par_addsub(s, a, helper); \ +} + +#define DO_PAR_ADDSUB_GE(NAME, helper) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_par_addsub_ge(s, a, helper); \ +} + +DO_PAR_ADDSUB_GE(SADD16, gen_helper_sadd16) +DO_PAR_ADDSUB_GE(SASX, gen_helper_saddsubx) +DO_PAR_ADDSUB_GE(SSAX, gen_helper_ssubaddx) +DO_PAR_ADDSUB_GE(SSUB16, gen_helper_ssub16) +DO_PAR_ADDSUB_GE(SADD8, gen_helper_sadd8) +DO_PAR_ADDSUB_GE(SSUB8, gen_helper_ssub8) + +DO_PAR_ADDSUB_GE(UADD16, gen_helper_uadd16) +DO_PAR_ADDSUB_GE(UASX, gen_helper_uaddsubx) +DO_PAR_ADDSUB_GE(USAX, gen_helper_usubaddx) +DO_PAR_ADDSUB_GE(USUB16, gen_helper_usub16) +DO_PAR_ADDSUB_GE(UADD8, gen_helper_uadd8) +DO_PAR_ADDSUB_GE(USUB8, gen_helper_usub8) + +DO_PAR_ADDSUB(QADD16, gen_helper_qadd16) +DO_PAR_ADDSUB(QASX, gen_helper_qaddsubx) +DO_PAR_ADDSUB(QSAX, gen_helper_qsubaddx) +DO_PAR_ADDSUB(QSUB16, gen_helper_qsub16) +DO_PAR_ADDSUB(QADD8, gen_helper_qadd8) +DO_PAR_ADDSUB(QSUB8, gen_helper_qsub8) + +DO_PAR_ADDSUB(UQADD16, gen_helper_uqadd16) +DO_PAR_ADDSUB(UQASX, gen_helper_uqaddsubx) +DO_PAR_ADDSUB(UQSAX, gen_helper_uqsubaddx) +DO_PAR_ADDSUB(UQSUB16, gen_helper_uqsub16) +DO_PAR_ADDSUB(UQADD8, gen_helper_uqadd8) +DO_PAR_ADDSUB(UQSUB8, gen_helper_uqsub8) + +DO_PAR_ADDSUB(SHADD16, gen_helper_shadd16) +DO_PAR_ADDSUB(SHASX, gen_helper_shaddsubx) +DO_PAR_ADDSUB(SHSAX, gen_helper_shsubaddx) +DO_PAR_ADDSUB(SHSUB16, gen_helper_shsub16) +DO_PAR_ADDSUB(SHADD8, gen_helper_shadd8) +DO_PAR_ADDSUB(SHSUB8, gen_helper_shsub8) + +DO_PAR_ADDSUB(UHADD16, gen_helper_uhadd16) +DO_PAR_ADDSUB(UHASX, gen_helper_uhaddsubx) +DO_PAR_ADDSUB(UHSAX, gen_helper_uhsubaddx) +DO_PAR_ADDSUB(UHSUB16, gen_helper_uhsub16) +DO_PAR_ADDSUB(UHADD8, gen_helper_uhadd8) +DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8) + +#undef DO_PAR_ADDSUB +#undef DO_PAR_ADDSUB_GE + /* * Legacy decoder. */ @@ -9604,16 +9619,8 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) rs =3D (insn >> 8) & 0xf; switch ((insn >> 23) & 3) { case 0: /* Parallel add/subtract. */ - op1 =3D (insn >> 20) & 7; - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - sh =3D (insn >> 5) & 7; - if ((op1 & 3) =3D=3D 0 || sh =3D=3D 5 || sh =3D=3D 6) - goto illegal_op; - gen_arm_parallel_addsub(op1, sh, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + /* Done by decodetree */ + goto illegal_op; case 1: if ((insn & 0x00700020) =3D=3D 0) { /* Halfword pack. */ @@ -10397,20 +10404,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } store_reg(s, rd, tmp); break; - case 2: /* SIMD add/subtract. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - op =3D (insn >> 20) & 7; - shift =3D (insn >> 4) & 7; - if ((op & 3) =3D=3D 3 || (shift & 3) =3D=3D 3) - goto illegal_op; - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - gen_thumb2_parallel_addsub(op, shift, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + case 2: /* SIMD add/subtract, in decodetree */ + goto illegal_op; case 3: /* Other data processing. */ op =3D ((insn >> 17) & 0x38) | ((insn >> 4) & 7); if (op < 4) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 285c08ca22..4dfd8133f7 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -410,3 +410,47 @@ BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn= :4 &bfi # While we could get UDEF by not including this, add the pattern for # documentation and to conflict with any other typos in this file. UDF 1110 0111 1111 ---- ---- ---- 1111 ---- + +# Parallel addition and subtraction + +SADD16 .... 0110 0001 .... .... 1111 0001 .... @rndm +SASX .... 0110 0001 .... .... 1111 0011 .... @rndm +SSAX .... 0110 0001 .... .... 1111 0101 .... @rndm +SSUB16 .... 0110 0001 .... .... 1111 0111 .... @rndm +SADD8 .... 0110 0001 .... .... 1111 1001 .... @rndm +SSUB8 .... 0110 0001 .... .... 1111 1111 .... @rndm + +QADD16 .... 0110 0010 .... .... 1111 0001 .... @rndm +QASX .... 0110 0010 .... .... 1111 0011 .... @rndm +QSAX .... 0110 0010 .... .... 1111 0101 .... @rndm +QSUB16 .... 0110 0010 .... .... 1111 0111 .... @rndm +QADD8 .... 0110 0010 .... .... 1111 1001 .... @rndm +QSUB8 .... 0110 0010 .... .... 1111 1111 .... @rndm + +SHADD16 .... 0110 0011 .... .... 1111 0001 .... @rndm +SHASX .... 0110 0011 .... .... 1111 0011 .... @rndm +SHSAX .... 0110 0011 .... .... 1111 0101 .... @rndm +SHSUB16 .... 0110 0011 .... .... 1111 0111 .... @rndm +SHADD8 .... 0110 0011 .... .... 1111 1001 .... @rndm +SHSUB8 .... 0110 0011 .... .... 1111 1111 .... @rndm + +UADD16 .... 0110 0101 .... .... 1111 0001 .... @rndm +UASX .... 0110 0101 .... .... 1111 0011 .... @rndm +USAX .... 0110 0101 .... .... 1111 0101 .... @rndm +USUB16 .... 0110 0101 .... .... 1111 0111 .... @rndm +UADD8 .... 0110 0101 .... .... 1111 1001 .... @rndm +USUB8 .... 0110 0101 .... .... 1111 1111 .... @rndm + +UQADD16 .... 0110 0110 .... .... 1111 0001 .... @rndm +UQASX .... 0110 0110 .... .... 1111 0011 .... @rndm +UQSAX .... 0110 0110 .... .... 1111 0101 .... @rndm +UQSUB16 .... 0110 0110 .... .... 1111 0111 .... @rndm +UQADD8 .... 0110 0110 .... .... 1111 1001 .... @rndm +UQSUB8 .... 0110 0110 .... .... 1111 1111 .... @rndm + +UHADD16 .... 0110 0111 .... .... 1111 0001 .... @rndm +UHASX .... 0110 0111 .... .... 1111 0011 .... @rndm +UHSAX .... 0110 0111 .... .... 1111 0101 .... @rndm +UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm +UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm +UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 682fc5c2c4..c899c56766 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -457,3 +457,47 @@ LDAEXD_t32 1110 1000 1101 .... .... .... 1111 11= 11 @ldrex_d LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 + +# Parallel addition and subtraction + +SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm +QADD8 1111 1010 1000 .... 1111 .... 0001 .... @rndm +SHADD8 1111 1010 1000 .... 1111 .... 0010 .... @rndm +UADD8 1111 1010 1000 .... 1111 .... 0100 .... @rndm +UQADD8 1111 1010 1000 .... 1111 .... 0101 .... @rndm +UHADD8 1111 1010 1000 .... 1111 .... 0110 .... @rndm + +SADD16 1111 1010 1001 .... 1111 .... 0000 .... @rndm +QADD16 1111 1010 1001 .... 1111 .... 0001 .... @rndm +SHADD16 1111 1010 1001 .... 1111 .... 0010 .... @rndm +UADD16 1111 1010 1001 .... 1111 .... 0100 .... @rndm +UQADD16 1111 1010 1001 .... 1111 .... 0101 .... @rndm +UHADD16 1111 1010 1001 .... 1111 .... 0110 .... @rndm + +SASX 1111 1010 1010 .... 1111 .... 0000 .... @rndm +QASX 1111 1010 1010 .... 1111 .... 0001 .... @rndm +SHASX 1111 1010 1010 .... 1111 .... 0010 .... @rndm +UASX 1111 1010 1010 .... 1111 .... 0100 .... @rndm +UQASX 1111 1010 1010 .... 1111 .... 0101 .... @rndm +UHASX 1111 1010 1010 .... 1111 .... 0110 .... @rndm + +SSUB8 1111 1010 1100 .... 1111 .... 0000 .... @rndm +QSUB8 1111 1010 1100 .... 1111 .... 0001 .... @rndm +SHSUB8 1111 1010 1100 .... 1111 .... 0010 .... @rndm +USUB8 1111 1010 1100 .... 1111 .... 0100 .... @rndm +UQSUB8 1111 1010 1100 .... 1111 .... 0101 .... @rndm +UHSUB8 1111 1010 1100 .... 1111 .... 0110 .... @rndm + +SSUB16 1111 1010 1101 .... 1111 .... 0000 .... @rndm +QSUB16 1111 1010 1101 .... 1111 .... 0001 .... @rndm +SHSUB16 1111 1010 1101 .... 1111 .... 0010 .... @rndm +USUB16 1111 1010 1101 .... 1111 .... 0100 .... @rndm +UQSUB16 1111 1010 1101 .... 1111 .... 0101 .... @rndm +UHSUB16 1111 1010 1101 .... 1111 .... 0110 .... @rndm + +SSAX 1111 1010 1110 .... 1111 .... 0000 .... @rndm +QSAX 1111 1010 1110 .... 1111 .... 0001 .... @rndm +SHSAX 1111 1010 1110 .... 1111 .... 0010 .... @rndm +USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm +UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm +UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 25/69] target/arm: Convert packing, unpacking, saturation, and reversal X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 541 ++++++++++++++++++----------------------- target/arm/a32.decode | 32 +++ target/arm/t32.decode | 37 ++- 3 files changed, 300 insertions(+), 310 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index eb9d1d71ce..86d7330458 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -355,7 +355,7 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) } =20 /* Byteswap each halfword. */ -static void gen_rev16(TCGv_i32 var) +static void gen_rev16(TCGv_i32 dest, TCGv_i32 var) { TCGv_i32 tmp =3D tcg_temp_new_i32(); TCGv_i32 mask =3D tcg_const_i32(0x00ff00ff); @@ -363,17 +363,17 @@ static void gen_rev16(TCGv_i32 var) tcg_gen_and_i32(tmp, tmp, mask); tcg_gen_and_i32(var, var, mask); tcg_gen_shli_i32(var, var, 8); - tcg_gen_or_i32(var, var, tmp); + tcg_gen_or_i32(dest, var, tmp); tcg_temp_free_i32(mask); tcg_temp_free_i32(tmp); } =20 /* Byteswap low halfword and sign extend. */ -static void gen_revsh(TCGv_i32 var) +static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) { tcg_gen_ext16u_i32(var, var); tcg_gen_bswap16_i32(var, var); - tcg_gen_ext16s_i32(var, var); + tcg_gen_ext16s_i32(dest, var); } =20 /* 32x32->64 multiply. Marks inputs as dead. */ @@ -426,7 +426,7 @@ static void gen_swap_half(TCGv_i32 var) t0 =3D (t0 + t1) ^ tmp; */ =20 -static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) +static void gen_add16(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) { TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_xor_i32(tmp, t0, t1); @@ -434,9 +434,8 @@ static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) tcg_gen_andi_i32(t0, t0, ~0x8000); tcg_gen_andi_i32(t1, t1, ~0x8000); tcg_gen_add_i32(t0, t0, t1); - tcg_gen_xor_i32(t0, t0, tmp); + tcg_gen_xor_i32(dest, t0, tmp); tcg_temp_free_i32(tmp); - tcg_temp_free_i32(t1); } =20 /* Set N and Z flags from var. */ @@ -6337,7 +6336,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } break; case NEON_2RM_VREV16: - gen_rev16(tmp); + gen_rev16(tmp, tmp); break; case NEON_2RM_VCLS: switch (size) { @@ -9307,13 +9306,225 @@ DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8) #undef DO_PAR_ADDSUB #undef DO_PAR_ADDSUB_GE =20 +/* + * Packing, unpacking, saturation, and reversal + */ + +static bool trans_PKH(DisasContext *s, arg_PKH *a) +{ + TCGv_i32 tn, tm; + int shift =3D a->imm; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + tn =3D load_reg(s, a->rn); + tm =3D load_reg(s, a->rm); + if (a->tb) { + /* PKHTB */ + if (shift =3D=3D 0) { + shift =3D 31; + } + tcg_gen_sari_i32(tm, tm, shift); + tcg_gen_deposit_i32(tn, tn, tm, 0, 16); + } else { + /* PKHBT */ + tcg_gen_shli_i32(tm, tm, shift); + tcg_gen_deposit_i32(tn, tm, tn, 0, 16); + } + tcg_temp_free_i32(tm); + store_reg(s, a->rd, tn); + return true; +} + +static bool op_sat(DisasContext *s, arg_sat *a, + void (*gen)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp, satimm; + int shift =3D a->imm; + + if (!ENABLE_ARCH_6) { + return false; + } + + tmp =3D load_reg(s, a->rn); + if (a->sh) { + tcg_gen_sari_i32(tmp, tmp, shift ? shift : 31); + } else { + tcg_gen_shli_i32(tmp, tmp, shift); + } + + satimm =3D tcg_const_i32(a->satimm); + gen(tmp, cpu_env, tmp, satimm); + tcg_temp_free_i32(satimm); + + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SSAT(DisasContext *s, arg_sat *a) +{ + return op_sat(s, a, gen_helper_ssat); +} + +static bool trans_USAT(DisasContext *s, arg_sat *a) +{ + return op_sat(s, a, gen_helper_usat); +} + +static bool trans_SSAT16(DisasContext *s, arg_sat *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_sat(s, a, gen_helper_ssat16); +} + +static bool trans_USAT16(DisasContext *s, arg_sat *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_sat(s, a, gen_helper_usat16); +} + +static bool op_xta(DisasContext *s, arg_rrr_rot *a, + void (*gen_extract)(TCGv_i32, TCGv_i32), + void (*gen_add)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6) { + return false; + } + + tmp =3D load_reg(s, a->rm); + /* + * TODO: In many cases we could do a shift instead of a rotate. + * Combined with a simple extend, that becomes an extract. + */ + tcg_gen_rotri_i32(tmp, tmp, a->rot * 8); + gen_extract(tmp, tmp); + + if (a->rn !=3D 15) { + TCGv_i32 tmp2 =3D load_reg(s, a->rn); + gen_add(tmp, tmp, tmp2); + tcg_temp_free_i32(tmp2); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SXTAB(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext8s_i32, tcg_gen_add_i32); +} + +static bool trans_SXTAH(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext16s_i32, tcg_gen_add_i32); +} + +static bool trans_SXTAB16(DisasContext *s, arg_rrr_rot *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_xta(s, a, gen_helper_sxtb16, gen_add16); +} + +static bool trans_UXTAB(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext8u_i32, tcg_gen_add_i32); +} + +static bool trans_UXTAH(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext16u_i32, tcg_gen_add_i32); +} + +static bool trans_UXTAB16(DisasContext *s, arg_rrr_rot *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_xta(s, a, gen_helper_uxtb16, gen_add16); +} + +static bool trans_SEL(DisasContext *s, arg_rrr *a) +{ + TCGv_i32 t1, t2, t3; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + t3 =3D tcg_temp_new_i32(); + tcg_gen_ld_i32(t3, cpu_env, offsetof(CPUARMState, GE)); + gen_helper_sel_flags(t1, t3, t1, t2); + tcg_temp_free_i32(t3); + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool op_rr(DisasContext *s, arg_rr *a, + void (*gen)(TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp; + + tmp =3D load_reg(s, a->rm); + gen(tmp, tmp); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_REV(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, tcg_gen_bswap32_i32); +} + +static bool trans_REV16(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, gen_rev16); +} + +static bool trans_REVSH(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, gen_revsh); +} + +static bool trans_RBIT(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6T2) { + return false; + } + return op_rr(s, a, gen_helper_rbit); +} + /* * Legacy decoder. */ =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; + unsigned int cond, val, op1, i, rm, rs, rn, rd; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 tmp3; @@ -9622,112 +9833,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) /* Done by decodetree */ goto illegal_op; case 1: - if ((insn & 0x00700020) =3D=3D 0) { - /* Halfword pack. */ - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - shift =3D (insn >> 7) & 0x1f; - if (insn & (1 << 6)) { - /* pkhtb */ - if (shift =3D=3D 0) { - shift =3D 31; - } - tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16); - } else { - /* pkhbt */ - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00200020) =3D=3D 0x00200000) { - /* [us]sat */ - tmp =3D load_reg(s, rm); - shift =3D (insn >> 7) & 0x1f; - if (insn & (1 << 6)) { - if (shift =3D=3D 0) - shift =3D 31; - tcg_gen_sari_i32(tmp, tmp, shift); - } else { - tcg_gen_shli_i32(tmp, tmp, shift); - } - sh =3D (insn >> 16) & 0x1f; - tmp2 =3D tcg_const_i32(sh); - if (insn & (1 << 22)) - gen_helper_usat(tmp, cpu_env, tmp, tmp2); - else - gen_helper_ssat(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00300fe0) =3D=3D 0x00200f20) { - /* [us]sat16 */ - tmp =3D load_reg(s, rm); - sh =3D (insn >> 16) & 0x1f; - tmp2 =3D tcg_const_i32(sh); - if (insn & (1 << 22)) - gen_helper_usat16(tmp, cpu_env, tmp, tmp2); - else - gen_helper_ssat16(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00700fe0) =3D=3D 0x00000fa0) { - /* Select bytes. */ - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - tmp3 =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState= , GE)); - gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); - tcg_temp_free_i32(tmp3); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x000003e0) =3D=3D 0x00000060) { - tmp =3D load_reg(s, rm); - shift =3D (insn >> 10) & 3; - /* ??? In many cases it's not necessary to do a - rotate, a shift is sufficient. */ - tcg_gen_rotri_i32(tmp, tmp, shift * 8); - op1 =3D (insn >> 20) & 7; - switch (op1) { - case 0: gen_sxtb16(tmp); break; - case 2: gen_sxtb(tmp); break; - case 3: gen_sxth(tmp); break; - case 4: gen_uxtb16(tmp); break; - case 6: gen_uxtb(tmp); break; - case 7: gen_uxth(tmp); break; - default: goto illegal_op; - } - if (rn !=3D 15) { - tmp2 =3D load_reg(s, rn); - if ((op1 & 3) =3D=3D 0) { - gen_add16(tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - } - store_reg(s, rd, tmp); - } else if ((insn & 0x003f0f60) =3D=3D 0x003f0f20) { - /* rev */ - tmp =3D load_reg(s, rm); - if (insn & (1 << 22)) { - if (insn & (1 << 7)) { - gen_revsh(tmp); - } else { - ARCH(6T2); - gen_helper_rbit(tmp, tmp); - } - } else { - if (insn & (1 << 7)) - gen_rev16(tmp); - else - tcg_gen_bswap32_i32(tmp, tmp); - } - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - break; + /* Halfword pack, [US]SAT, [US]SAT16, SEL, REV et al */ + /* Done by decodetree */ + goto illegal_op; case 2: /* Multiplies (Type 3). */ switch ((insn >> 20) & 0x7) { case 5: @@ -10063,7 +10171,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, ui= nt32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t imm, shift, offset; + uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10318,151 +10426,18 @@ static void disas_thumb2_insn(DisasContext *s, u= int32_t insn) } break; case 5: - - op =3D (insn >> 21) & 0xf; - if (op =3D=3D 6) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - /* Halfword pack. */ - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - shift =3D ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3); - if (insn & (1 << 5)) { - /* pkhtb */ - if (shift =3D=3D 0) { - shift =3D 31; - } - tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16); - } else { - /* pkhbt */ - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else { - /* Data processing register constant shift. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } - break; + /* All in decodetree */ + goto illegal_op; case 13: /* Misc data processing. */ op =3D ((insn >> 22) & 6) | ((insn >> 7) & 1); if (op < 4 && (insn & 0xf000) !=3D 0xf000) goto illegal_op; switch (op) { case 0: /* Register controlled shift, in decodetree */ - goto illegal_op; - case 1: /* Sign/zero extend. */ - op =3D (insn >> 20) & 7; - switch (op) { - case 0: /* SXTAH, SXTH */ - case 1: /* UXTAH, UXTH */ - case 4: /* SXTAB, SXTB */ - case 5: /* UXTAB, UXTB */ - break; - case 2: /* SXTAB16, SXTB16 */ - case 3: /* UXTAB16, UXTB16 */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - default: - goto illegal_op; - } - if (rn !=3D 15) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - } - tmp =3D load_reg(s, rm); - shift =3D (insn >> 4) & 3; - /* ??? In many cases it's not necessary to do a - rotate, a shift is sufficient. */ - tcg_gen_rotri_i32(tmp, tmp, shift * 8); - op =3D (insn >> 20) & 7; - switch (op) { - case 0: gen_sxth(tmp); break; - case 1: gen_uxth(tmp); break; - case 2: gen_sxtb16(tmp); break; - case 3: gen_uxtb16(tmp); break; - case 4: gen_sxtb(tmp); break; - case 5: gen_uxtb(tmp); break; - default: - g_assert_not_reached(); - } - if (rn !=3D 15) { - tmp2 =3D load_reg(s, rn); - if ((op >> 1) =3D=3D 1) { - gen_add16(tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - } - store_reg(s, rd, tmp); - break; + case 1: /* Sign/zero extend, in decodetree */ case 2: /* SIMD add/subtract, in decodetree */ + case 3: /* Other data processing, in decodetree */ goto illegal_op; - case 3: /* Other data processing. */ - op =3D ((insn >> 17) & 0x38) | ((insn >> 4) & 7); - if (op < 4) { - /* Saturating add/subtract. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - switch (op) { - case 0x0a: /* rbit */ - case 0x08: /* rev */ - case 0x09: /* rev16 */ - case 0x0b: /* revsh */ - break; - case 0x10: /* sel */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - case 0x18: /* clz, in decodetree */ - case 0x20: /* crc32/crc32c, in decodetree */ - case 0x21: - case 0x22: - case 0x28: - case 0x29: - case 0x2a: - goto illegal_op; - default: - goto illegal_op; - } - tmp =3D load_reg(s, rn); - switch (op) { - case 0x0a: /* rbit */ - gen_helper_rbit(tmp, tmp); - break; - case 0x08: /* rev */ - tcg_gen_bswap32_i32(tmp, tmp); - break; - case 0x09: /* rev16 */ - gen_rev16(tmp); - break; - case 0x0b: /* revsh */ - gen_revsh(tmp); - break; - case 0x10: /* sel */ - tmp2 =3D load_reg(s, rm); - tmp3 =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE= )); - gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); - tcg_temp_free_i32(tmp3); - tcg_temp_free_i32(tmp2); - break; - default: - g_assert_not_reached(); - } - } - store_reg(s, rd, tmp); - break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. = */ switch ((insn >> 20) & 7) { case 0: /* 32 x 32 -> 32 */ @@ -10809,60 +10784,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) * - Data-processing (plain binary immediate) */ if (insn & (1 << 24)) { - if (insn & (1 << 20)) - goto illegal_op; - /* Bitfield/Saturate. */ - op =3D (insn >> 21) & 7; - imm =3D insn & 0x1f; - shift =3D ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); - if (rn =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp =3D load_reg(s, rn); - } - switch (op) { - case 2: /* Signed bitfield extract, in decodetree */ - case 6: /* Unsigned bitfield extract, in decodetree */ - case 3: /* Bitfield insert/clear, in decodetree */ - case 7: - goto illegal_op; - default: /* Saturate. */ - if (op & 1) { - tcg_gen_sari_i32(tmp, tmp, shift); - } else { - tcg_gen_shli_i32(tmp, tmp, shift); - } - tmp2 =3D tcg_const_i32(imm); - if (op & 4) { - /* Unsigned. */ - if ((op & 1) && shift =3D=3D 0) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_D= SP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - gen_helper_usat16(tmp, cpu_env, tmp, tmp2); - } else { - gen_helper_usat(tmp, cpu_env, tmp, tmp2); - } - } else { - /* Signed. */ - if ((op & 1) && shift =3D=3D 0) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_D= SP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - gen_helper_ssat16(tmp, cpu_env, tmp, tmp2); - } else { - gen_helper_ssat(tmp, cpu_env, tmp, tmp2); - } - } - tcg_temp_free_i32(tmp2); - break; - } - store_reg(s, rd, tmp); + /* Bitfield/Saturate, in decodetree */ + goto illegal_op; } else { imm =3D ((insn & 0x04000000) >> 15) | ((insn & 0x7000) >> 4) | (insn & 0xff); @@ -11554,8 +11477,8 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) tmp =3D load_reg(s, rn); switch (op1) { case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_rev16(tmp); break; - case 3: gen_revsh(tmp); break; + case 1: gen_rev16(tmp, tmp); break; + case 3: gen_revsh(tmp, tmp); break; default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 4dfd8133f7..4990eb3839 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -28,6 +28,7 @@ &s_rri_rot s rn rd imm rot &s_rrrr s rd rn rm ra &rrrr rd rn rm ra +&rrr_rot rd rn rm rot &rrr rd rn rm &rr rd rm &ri rd imm @@ -43,6 +44,8 @@ &ldrex rn rt rt2 imm &bfx rd rn lsb widthm1 &bfi rd rn lsb msb +&sat rd rn satimm imm sh +&pkh rd rn rm imm tb =20 # Data-processing (register) =20 @@ -454,3 +457,32 @@ UHSAX .... 0110 0111 .... .... 1111 0101 ..= .. @rndm UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm + +# Packing, unpacking, saturation, and reversal + +PKH ---- 0110 1000 rn:4 rd:4 imm:5 tb:1 01 rm:4 &pkh + +@sat ---- .... ... satimm:5 rd:4 imm:5 sh:1 .. rn:4 &sat +@sat16 ---- .... .... satimm:4 rd:4 .... .... rn:4 \ + &sat imm=3D0 sh=3D0 + +SSAT .... 0110 101. .... .... .... ..01 .... @sat +USAT .... 0110 111. .... .... .... ..01 .... @sat + +SSAT16 .... 0110 1010 .... .... 1111 0011 .... @sat16 +USAT16 .... 0110 1110 .... .... 1111 0011 .... @sat16 + +@rrr_rot ---- .... .... rn:4 rd:4 rot:2 ...... rm:4 &rrr_rot + +SXTAB16 .... 0110 1000 .... .... ..00 0111 .... @rrr_rot +SXTAB .... 0110 1010 .... .... ..00 0111 .... @rrr_rot +SXTAH .... 0110 1011 .... .... ..00 0111 .... @rrr_rot +UXTAB16 .... 0110 1100 .... .... ..00 0111 .... @rrr_rot +UXTAB .... 0110 1110 .... .... ..00 0111 .... @rrr_rot +UXTAH .... 0110 1111 .... .... ..00 0111 .... @rrr_rot + +SEL .... 0110 1000 .... .... 1111 1011 .... @rndm +REV .... 0110 1011 1111 .... 1111 0011 .... @rdm +REV16 .... 0110 1011 1111 .... 1111 1011 .... @rdm +REVSH .... 0110 1111 1111 .... 1111 1011 .... @rdm +RBIT .... 0110 1111 1111 .... 1111 0011 .... @rdm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c899c56766..71f6d728f2 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -25,6 +25,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra +&rrr_rot !extern rd rn rm rot &rrr !extern rd rn rm &rr !extern rd rm &ri !extern rd imm @@ -40,6 +41,8 @@ &ldrex !extern rn rt rt2 imm &bfx !extern rd rn lsb widthm1 &bfi !extern rd rn lsb msb +&sat !extern rd rn satimm imm sh +&pkh !extern rd rn rm imm tb =20 # Data-processing (register) =20 @@ -69,7 +72,8 @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... ....= @s_rrr_shi TEQ_xrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi } -# PKHBT, PKHTB at opc1 =3D 0110 +PKH 1110101 0110 0 rn:4 0 ... rd:4 .. tb:1 0 rm:4 \ + &pkh imm=3D%imm5_12_6 { CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi @@ -148,6 +152,20 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... .....= ... @s_rri_rot =20 # Saturate, bitfield =20 +@sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \ + &sat imm=3D%imm5_12_6 +@sat16 .... .... .. . . rn:4 . ... rd:4 .. . satimm:5 \ + &sat sh=3D0 imm=3D0 + +{ + SSAT16 1111 0011 001 0 .... 0 000 .... 00 0 ..... @sat16 + SSAT 1111 0011 00. 0 .... 0 ... .... .. 0 ..... @sat +} +{ + USAT16 1111 0011 101 0 .... 0 000 .... 00 0 ..... @sat16 + USAT 1111 0011 10. 0 .... 0 ... .... .. 0 ..... @sat +} + @bfx .... .... ... . rn:4 . ... rd:4 .. . widthm1:5 \ &bfx lsb=3D%imm5_12_6 @bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \ @@ -224,7 +242,13 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 ..= .. @rndm CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm =20 +SEL 1111 1010 1010 .... 1111 .... 1000 .... @rndm + # Note rn !=3D rm is CONSTRAINED UNPREDICTABLE; we choose to ignore rn. +REV 1111 1010 1001 ---- 1111 .... 1000 .... @rdm +REV16 1111 1010 1001 ---- 1111 .... 1001 .... @rdm +RBIT 1111 1010 1001 ---- 1111 .... 1010 .... @rdm +REVSH 1111 1010 1001 ---- 1111 .... 1011 .... @rdm CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm =20 # Branches and miscellaneous control @@ -501,3 +525,14 @@ SHSAX 1111 1010 1110 .... 1111 .... 0010 ..= .. @rndm USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm + +# Register extends + +@rrr_rot .... .... .... rn:4 .... rd:4 .. rot:2 rm:4 &rrr_rot + +SXTAH 1111 1010 0000 .... 1111 .... 10.. .... @rrr_rot +UXTAH 1111 1010 0001 .... 1111 .... 10.. .... @rrr_rot +SXTAB16 1111 1010 0010 .... 1111 .... 10.. .... @rrr_rot +UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot +SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot +UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::630 Subject: [Qemu-devel] [PATCH v3 26/69] target/arm: Convert Signed multiply, signed and unsigned divide X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 467 +++++++++++++++++++---------------------- target/arm/a32.decode | 22 ++ target/arm/t32.decode | 18 ++ 3 files changed, 251 insertions(+), 256 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 86d7330458..9e47c2e0c4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9518,18 +9518,221 @@ static bool trans_RBIT(DisasContext *s, arg_rr *a) return op_rr(s, a, gen_helper_rbit); } =20 +/* + * Signed multiply, signed and unsigned divide + */ + +static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + if (m_swap) { + gen_swap_half(t2); + } + gen_smul_dual(t1, t2); + + if (sub) { + /* This subtraction cannot overflow. */ + tcg_gen_sub_i32(t1, t1, t2); + } else { + /* + * This addition cannot overflow 32 bits; however it may + * overflow considered as a signed operation, in which case + * we must set the Q flag. + */ + gen_helper_add_setq(t1, cpu_env, t1, t2); + } + tcg_temp_free_i32(t2); + + if (a->ra !=3D 15) { + t2 =3D load_reg(s, a->ra); + gen_helper_add_setq(t1, cpu_env, t1, t2); + tcg_temp_free_i32(t2); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SMLAD(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, false, false); +} + +static bool trans_SMLADX(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, true, false); +} + +static bool trans_SMLSD(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, false, true); +} + +static bool trans_SMLSDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, true, true); +} + +static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) +{ + TCGv_i32 t1, t2; + TCGv_i64 l1, l2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + if (m_swap) { + gen_swap_half(t2); + } + gen_smul_dual(t1, t2); + + l1 =3D tcg_temp_new_i64(); + l2 =3D tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(l1, t1); + tcg_gen_ext_i32_i64(l2, t2); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); + + if (sub) { + tcg_gen_sub_i64(l1, l1, l2); + } else { + tcg_gen_add_i64(l1, l1, l2); + } + tcg_temp_free_i64(l2); + + gen_addq(s, l1, a->ra, a->rd); + gen_storeq_reg(s, a->ra, a->rd, l1); + tcg_temp_free_i64(l1); + return true; +} + +static bool trans_SMLALD(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, false, false); +} + +static bool trans_SMLALDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, true, false); +} + +static bool trans_SMLSLD(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, false, true); +} + +static bool trans_SMLSLDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, true, true); +} + +static bool op_smmla(DisasContext *s, arg_rrrr *a, bool round, bool sub) +{ + TCGv_i32 t1, t2; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + tcg_gen_muls2_i32(t2, t1, t1, t2); + + if (a->ra !=3D 15) { + TCGv_i32 t3 =3D load_reg(s, a->ra); + if (sub) { + tcg_gen_sub_i32(t1, t1, t3); + } else { + tcg_gen_add_i32(t1, t1, t3); + } + tcg_temp_free_i32(t3); + } + if (round) { + /* + * Adding 0x80000000 to the 64-bit quantity means that we have + * carry in to the high word when the low word has the msb set. + */ + tcg_gen_shri_i32(t2, t2, 31); + tcg_gen_add_i32(t1, t1, t2); + } + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SMMLA(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, false, false); +} + +static bool trans_SMMLAR(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, true, false); +} + +static bool trans_SMMLS(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, false, true); +} + +static bool trans_SMMLSR(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, true, true); +} + +static bool op_div(DisasContext *s, arg_rrr *a, bool u) +{ + TCGv_i32 t1, t2; + + if (s->thumb + ? !dc_isar_feature(thumb_div, s) + : !dc_isar_feature(arm_div, s)) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + if (u) { + gen_helper_udiv(t1, t1, t2); + } else { + gen_helper_sdiv(t1, t1, t2); + } + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SDIV(DisasContext *s, arg_rrr *a) +{ + return op_div(s, a, false); +} + +static bool trans_UDIV(DisasContext *s, arg_rrr *a) +{ + return op_div(s, a, true); +} + /* * Legacy decoder. */ =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rm, rs, rn, rd; + unsigned int cond, val, op1, i, rn, rd; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 tmp3; TCGv_i32 addr; - TCGv_i64 tmp64; =20 /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -9812,148 +10015,10 @@ static void disas_arm_insn(DisasContext *s, unsig= ned int insn) switch(op1) { case 0x0: case 0x1: - /* multiplies, extra load/stores */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - break; case 0x4: case 0x5: - goto do_ldst; case 0x6: case 0x7: - if (insn & (1 << 4)) { - ARCH(6); - /* Armv6 Media instructions. */ - rm =3D insn & 0xf; - rn =3D (insn >> 16) & 0xf; - rd =3D (insn >> 12) & 0xf; - rs =3D (insn >> 8) & 0xf; - switch ((insn >> 23) & 3) { - case 0: /* Parallel add/subtract. */ - /* Done by decodetree */ - goto illegal_op; - case 1: - /* Halfword pack, [US]SAT, [US]SAT16, SEL, REV et al */ - /* Done by decodetree */ - goto illegal_op; - case 2: /* Multiplies (Type 3). */ - switch ((insn >> 20) & 0x7) { - case 5: - if (((insn >> 6) ^ (insn >> 7)) & 1) { - /* op2 not 00x or 11x : UNDEF */ - goto illegal_op; - } - /* Signed multiply most significant [accumulate]. - (SMMUL, SMMLA, SMMLS) */ - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); - - if (rd !=3D 15) { - tmp3 =3D load_reg(s, rd); - if (insn & (1 << 6)) { - tcg_gen_sub_i32(tmp, tmp, tmp3); - } else { - tcg_gen_add_i32(tmp, tmp, tmp3); - } - tcg_temp_free_i32(tmp3); - } - if (insn & (1 << 5)) { - /* - * Adding 0x80000000 to the 64-bit quantity - * means that we have carry in to the high - * word when the low word has the high bit set. - */ - tcg_gen_shri_i32(tmp2, tmp2, 31); - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rn, tmp); - break; - case 0: - case 4: - /* SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD */ - if (insn & (1 << 7)) { - goto illegal_op; - } - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - if (insn & (1 << 5)) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (insn & (1 << 22)) { - /* smlald, smlsld */ - TCGv_i64 tmp64_2; - - tmp64 =3D tcg_temp_new_i64(); - tmp64_2 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_gen_ext_i32_i64(tmp64_2, tmp2); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - if (insn & (1 << 6)) { - tcg_gen_sub_i64(tmp64, tmp64, tmp64_2); - } else { - tcg_gen_add_i64(tmp64, tmp64, tmp64_2); - } - tcg_temp_free_i64(tmp64_2); - gen_addq(s, tmp64, rd, rn); - gen_storeq_reg(s, rd, rn, tmp64); - tcg_temp_free_i64(tmp64); - } else { - /* smuad, smusd, smlad, smlsd */ - if (insn & (1 << 6)) { - /* This subtraction cannot overflow. */ - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - /* This addition cannot overflow 32 bits; - * however it may overflow considered as a - * signed operation, in which case we must= set - * the Q flag. - */ - gen_helper_add_setq(tmp, cpu_env, tmp, tmp= 2); - } - tcg_temp_free_i32(tmp2); - if (rd !=3D 15) - { - tmp2 =3D load_reg(s, rd); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp= 2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rn, tmp); - } - break; - case 1: - case 3: - /* SDIV, UDIV */ - if (!dc_isar_feature(arm_div, s)) { - goto illegal_op; - } - if (((insn >> 5) & 7) || (rd !=3D 15)) { - goto illegal_op; - } - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - if (insn & (1 << 21)) { - gen_helper_udiv(tmp, tmp, tmp2); - } else { - gen_helper_sdiv(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rn, tmp); - break; - default: - goto illegal_op; - } - break; - case 3: - /* USAD, BFI, BFC, SBFX, UBFX */ - /* Done by decodetree */ - goto illegal_op; - } - break; - } - do_ldst: /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; case 0x08: @@ -10175,9 +10240,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 tmp3; TCGv_i32 addr; - TCGv_i64 tmp64; int op; =20 /* @@ -10438,119 +10501,11 @@ static void disas_thumb2_insn(DisasContext *s, u= int32_t insn) case 2: /* SIMD add/subtract, in decodetree */ case 3: /* Other data processing, in decodetree */ goto illegal_op; - case 4: case 5: /* 32-bit multiply. Sum of absolute differences. = */ - switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ - case 1: /* 16 x 16 -> 32 */ - case 3: /* 32 * 16 -> 32msb */ - case 7: /* Unsigned sum of absolute differences. */ - /* in decodetree */ - goto illegal_op; - case 2: /* Dual multiply add. */ - case 4: /* Dual multiply subtract. */ - case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - } - op =3D (insn >> 4) & 0xf; - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - switch ((insn >> 20) & 7) { - case 2: /* Dual multiply add. */ - case 4: /* Dual multiply subtract. */ - if (op) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (insn & (1 << 22)) { - /* This subtraction cannot overflow. */ - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - /* This addition cannot overflow 32 bits; - * however it may overflow considered as a signed - * operation, in which case we must set the Q flag. - */ - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - if (rs !=3D 15) - { - tmp2 =3D load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; - case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ - tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); - if (rs !=3D 15) { - tmp3 =3D load_reg(s, rs); - if (insn & (1 << 20)) { - tcg_gen_add_i32(tmp, tmp, tmp3); - } else { - tcg_gen_sub_i32(tmp, tmp, tmp3); - } - tcg_temp_free_i32(tmp3); - } - if (insn & (1 << 4)) { - /* - * Adding 0x80000000 to the 64-bit quantity - * means that we have carry in to the high - * word when the low word has the high bit set. - */ - tcg_gen_shri_i32(tmp2, tmp2, 31); - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - break; - } - store_reg(s, rd, tmp); - break; - case 6: case 7: /* 64-bit multiply, Divide. */ - op =3D ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70); - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - if ((op & 0x50) =3D=3D 0x10) { - /* sdiv, udiv */ - if (!dc_isar_feature(thumb_div, s)) { - goto illegal_op; - } - if (op & 0x20) - gen_helper_udiv(tmp, tmp, tmp2); - else - gen_helper_sdiv(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((op & 0xe) =3D=3D 0xc) { - /* Dual multiply accumulate long. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - if (op & 1) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (op & 0x10) { - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - /* BUGFIX */ - tmp64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - gen_addq(s, tmp64, rs, rd); - gen_storeq_reg(s, rs, rd, tmp64); - tcg_temp_free_i64(tmp64); - } else { - /* Signed/unsigned 64-bit multiply, in decodetree */ - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - break; + case 4: case 5: + /* 32-bit multiply. Sum of absolute differences, in decodetre= e */ + goto illegal_op; + case 6: case 7: /* 64-bit multiply, Divide, in decodetree */ + goto illegal_op; } break; case 6: case 7: case 14: case 15: diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 4990eb3839..d7a333b90b 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -486,3 +486,25 @@ REV .... 0110 1011 1111 .... 1111 0011 ..= .. @rdm REV16 .... 0110 1011 1111 .... 1111 1011 .... @rdm REVSH .... 0110 1111 1111 .... 1111 1011 .... @rdm RBIT .... 0110 1111 1111 .... 1111 0011 .... @rdm + +# Signed multiply, signed and unsigned divide + +@rdmn ---- .... .... rd:4 .... rm:4 .... rn:4 &rrr + +SMLAD .... 0111 0000 .... .... .... 0001 .... @rdamn +SMLADX .... 0111 0000 .... .... .... 0011 .... @rdamn +SMLSD .... 0111 0000 .... .... .... 0101 .... @rdamn +SMLSDX .... 0111 0000 .... .... .... 0111 .... @rdamn + +SDIV .... 0111 0001 .... 1111 .... 0001 .... @rdmn +UDIV .... 0111 0011 .... 1111 .... 0001 .... @rdmn + +SMLALD .... 0111 0100 .... .... .... 0001 .... @rdamn +SMLALDX .... 0111 0100 .... .... .... 0011 .... @rdamn +SMLSLD .... 0111 0100 .... .... .... 0101 .... @rdamn +SMLSLDX .... 0111 0100 .... .... .... 0111 .... @rdamn + +SMMLA .... 0111 0101 .... .... .... 0001 .... @rdamn +SMMLAR .... 0111 0101 .... .... .... 0011 .... @rdamn +SMMLS .... 0111 0101 .... .... .... 1101 .... @rdamn +SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 71f6d728f2..677acb698d 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -228,6 +228,24 @@ SMLALTT 1111 1011 1100 .... .... .... 1011 ..= .. @rnadm # usad8 is usada8 w/ ra=3D15 USADA8 1111 1011 0111 .... .... .... 0000 .... @rnadm =20 +SMLAD 1111 1011 0010 .... .... .... 0000 .... @rnadm +SMLADX 1111 1011 0010 .... .... .... 0001 .... @rnadm +SMLSD 1111 1011 0100 .... .... .... 0000 .... @rnadm +SMLSDX 1111 1011 0100 .... .... .... 0001 .... @rnadm + +SMLALD 1111 1011 1100 .... .... .... 1100 .... @rnadm +SMLALDX 1111 1011 1100 .... .... .... 1101 .... @rnadm +SMLSLD 1111 1011 1101 .... .... .... 1100 .... @rnadm +SMLSLDX 1111 1011 1101 .... .... .... 1101 .... @rnadm + +SMMLA 1111 1011 0101 .... .... .... 0000 .... @rnadm +SMMLAR 1111 1011 0101 .... .... .... 0001 .... @rnadm +SMMLS 1111 1011 0110 .... .... .... 0000 .... @rnadm +SMMLSR 1111 1011 0110 .... .... .... 0001 .... @rnadm + +SDIV 1111 1011 1001 .... 1111 .... 1111 .... @rndm +UDIV 1111 1011 1011 .... 1111 .... 1111 .... @rndm + # Data-processing (two source registers) =20 QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LP98tMkuEY1Am6pgEun6YWYPwcU15PtWb8SPF+FrpSw=; b=YVuwxS6X4hRvLJ7uZxos4XDF5x3AYjKrLl+zni7Bcc5SaiwVv0Wh0C2l+YOHf3F3o1 dI+kPad05p7rPWoEnCQoyywZblETJZnGjSCwu6K9NmaG/LXy5CXvsbz/kQ2jt6AoLLk0 dlbLYW6+/Im6hnA0xPa1UFqDaOyHyV8Vvj2w8tEB1Ljs00gjU3vyb62IC+rlTdHhM66G MKcDYSh+c9tlAflv/wcyvdoR1vo7TgSiUQlo5GpJfFx9alJTDtzpcbXRK0KFZqWsqrHN zlZfT7tUT1tjJ/p5K0Y7tLCmwnLNUmhPdlmPN/zP81zwXUl4Z7qmNIgkp9u3zFOuyHMg 8xEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LP98tMkuEY1Am6pgEun6YWYPwcU15PtWb8SPF+FrpSw=; b=iK8Xy7IX0A94y1kOI7Y5z58x1lGvBkscjQXqOIOTl8yEmXOV1IN/iU3okUpaTGpIbb JiT0PtYwnQxz0eIosKWm7avYzOV0QP7VBWqKvC8vswl9bpVErC4eowac3bSuBYtEtMCj kIX3rOaO5cAZQqnmrPB12M14razjrER/RWVPdL4vCqtGX25rWkc1ey1aY9HsZ9Pg0Yyl U2hKbzH8PYmhWH3h98UQS0ZQNBQNWv7iMmYeBETPVQsd8aZLxSdizuBWZuNxjkN9ltpz xQuYwAKued/h377bSNDyOr1zFYKZXOC85UMb+OhCOEI3Ep7JdP+tKQ7fiRiX/WkxXgbD +HDQ== X-Gm-Message-State: APjAAAV6UN7IsUgwtqOee6lzMg2WrLxUCQe71hEk6Cw1s9/PJafYSFwV ywmJgpGEKHfi//h1nHG79B6Sy1fqlv0= X-Google-Smtp-Source: APXvYqxGORjZMHIKz4PfdxZip1QpVvU9FdBfNMPHIXyKsgjbhEDBPXnOYukL4xZwzlNbkg+Qpfai8A== X-Received: by 2002:a17:90a:7783:: with SMTP id v3mr5583940pjk.109.1567019134967; Wed, 28 Aug 2019 12:05:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:14 -0700 Message-Id: <20190828190456.30315-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 27/69] target/arm: Convert MOVW, MOVT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 89 ++++++++++++++++-------------------------- target/arm/a32.decode | 6 +++ target/arm/t32.decode | 9 +++++ 3 files changed, 48 insertions(+), 56 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9e47c2e0c4..6cbf34b424 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7844,6 +7844,34 @@ static bool trans_ADR(DisasContext *s, arg_ri *a) return true; } =20 +static bool trans_MOVW(DisasContext *s, arg_MOVW *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp =3D tcg_const_i32(a->imm); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MOVT(DisasContext *s, arg_MOVW *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp =3D load_reg(s, a->rd); + tcg_gen_ext16u_i32(tmp, tmp); + tcg_gen_ori_i32(tmp, tmp, a->imm << 16); + store_reg(s, a->rd, tmp); + return true; +} + /* * Multiply and multiply accumulate */ @@ -9729,7 +9757,7 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a) =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rn, rd; + unsigned int cond, val, op1, i, rn; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -9978,26 +10006,8 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) /* fall back to legacy decoder */ =20 if ((insn & 0x0f900000) =3D=3D 0x03000000) { - if ((insn & (1 << 21)) =3D=3D 0) { - ARCH(6T2); - rd =3D (insn >> 12) & 0xf; - val =3D ((insn >> 4) & 0xf000) | (insn & 0xfff); - if ((insn & (1 << 22)) =3D=3D 0) { - /* MOVW */ - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, val); - } else { - /* MOVT */ - tmp =3D load_reg(s, rd); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_ori_i32(tmp, tmp, val << 16); - } - store_reg(s, rd, tmp); - } else { - /* MSR (immediate) and hints */ - /* All done in decodetree. Illegal ops already signalled. */ - g_assert_not_reached(); - } + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; } else if ((insn & 0x0f900000) =3D=3D 0x01000000 && (insn & 0x00000090) !=3D 0x00000090) { /* miscellaneous instructions */ @@ -10732,42 +10742,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) /* * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx * - Data-processing (modified immediate, plain binary immedi= ate) + * All in decodetree. */ - if (insn & (1 << 25)) { - /* - * 0b1111_0x1x_xxxx_0xxx_xxxx_xxxx - * - Data-processing (plain binary immediate) - */ - if (insn & (1 << 24)) { - /* Bitfield/Saturate, in decodetree */ - goto illegal_op; - } else { - imm =3D ((insn & 0x04000000) >> 15) - | ((insn & 0x7000) >> 4) | (insn & 0xff); - if (insn & (1 << 22)) { - /* 16-bit immediate. */ - imm |=3D (insn >> 4) & 0xf000; - if (insn & (1 << 23)) { - /* movt */ - tmp =3D load_reg(s, rd); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_ori_i32(tmp, tmp, imm << 16); - } else { - /* movw */ - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, imm); - } - store_reg(s, rd, tmp); - } else { - /* Add/sub 12-bit immediate, in decodetree */ - goto illegal_op; - } - } - } else { - /* Data-processing (modified immediate) */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } + goto illegal_op; } break; case 12: diff --git a/target/arm/a32.decode b/target/arm/a32.decode index d7a333b90b..341882e637 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -73,6 +73,12 @@ MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 ..= .. @s_rxr_shi BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi =20 +%imm16 16:4 0:12 +@mov16 ---- .... .... .... rd:4 ............ &ri imm=3D%i= mm16 + +MOVW .... 0011 0000 .... .... ............ @mov16 +MOVT .... 0011 0100 .... .... ............ @mov16 + # Data-processing (register-shifted register) =20 @s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \ diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 677acb698d..f315fde0f4 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -150,6 +150,15 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... .....= ... @s_rri_rot SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 } =20 +# Move Wide + +%imm16_26_16_12_0 16:4 26:1 12:3 0:8 +@mov16 .... .... .... .... .... rd:4 .... .... \ + &ri imm=3D%imm16_26_16_12_0 + +MOVW 1111 0.10 0100 .... 0 ... .... ........ @mov16 +MOVT 1111 0.10 1100 .... 0 ... .... ........ @mov16 + # Saturate, bitfield =20 @sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \ --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567021526; cv=none; d=zoho.com; s=zohoarc; b=bk3njAJZDvd9DUCNw6MkftP4C87Il83zrsVYyF0dY3rf5i0DstX7JPbWLJeveh5mvCBNU7TKCnm6/E87I12vVnctcBJAwqkEmiEMSJ6086NQiHUsBSvclcP5gdHQbH2UQ3x4MTuf3Z9vLJ1y4fdTismsfIeal6vEbzXvLidG3xc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567021526; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=uqCus6BFItQ2BBy29Ji4ZyEwDIyTa1Al0KhmoHLz5r0=; b=KNRB8uubnwfjqt6bn+Rui5BATGZZXRze3Pfn7t4j/52FLc9F5DSF0TKgyM0YpatLwFElUrnfF3v/bED3DUIIt3iM+EV/lRSbwGRvsh0kg2/QghIBAlGm5omSCTz1MBZbe5UAA6BeFMpWsBCi9GmD1I02hoGsu3qSfqbSZhq1Xas= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156702152596438.330796980891364; Wed, 28 Aug 2019 12:45:25 -0700 (PDT) Received: from localhost ([::1]:41564 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33sf-0007z7-Lu for importer@patchew.org; Wed, 28 Aug 2019 15:45:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38142) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33GO-0003kZ-Gm for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33GE-0000FM-8V for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:46 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:45641) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33GD-0000Es-TI for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:38 -0400 Received: by mail-pf1-x42c.google.com with SMTP id w26so369409pfq.12 for ; Wed, 28 Aug 2019 12:05:37 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uqCus6BFItQ2BBy29Ji4ZyEwDIyTa1Al0KhmoHLz5r0=; b=I2ewTPpYAW7lHXiV9w/zRZkiO85/boVATPRYUiMH6bidKXjZflND9Dvg0XZvlByqI+ BwqEcVpU3KrEV/iTkz6pFd0An3b3GoCKzOVuhIne7Z+4Gnd++NI1cEg0GkGedW5cPhch 5Z1NdreaUWujpW4DtRj7NyN43Qdmhsq6jJ0rukPtd5TdU2qmQQkIqGUmhGYLscYLfSK1 eQbf0yJjStAYaSibB+F1rdm1KCNcLzD/Rjt6Ede6WUTgJ9i/oT875epUsPFDXnAluDKu 2SgeE2qvTrigpJLtf7mc0FVu6sVZPirTZpJPO+dzbLgolA6E9srOKqzdxs2ZW3bbVh5T Ph8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uqCus6BFItQ2BBy29Ji4ZyEwDIyTa1Al0KhmoHLz5r0=; b=pO9q1JcB8NYujsI2Ii/RMTmVjexmo3rl4b25GEKBZ/8MTjthPvIEQkOIBg53JMz/ur nHFSHfvtgBVfdhdgcmJ2VMCGwEw/D4UFOlAPvialH4BIC17HQBPox0WAdU4mHWofyE5x +UoYHzXy2Mixf22/HBWXEBgvB6PYJouw+WH6fWiA3WpFEgqcV3WtsceNzDPN4VENN7ln riqLysj5oYBV06J1Df/Hvg9Dz/GCqIlUy7xqNtOX1te2lUkhSMYcbOCpn0CUxwdBHkhw EAvoAs3kOeK3zQrnQvCPsMXic6Y9hPYU9YAa1Qe5KlkoBGxkZLoObpL/EMyxfttYNg8Y PNiw== X-Gm-Message-State: APjAAAXyYxAVq1CzombAYbP2AS8gMqnj2pWSlbEClu/q1e+NXl/Ilp+N Wh1QTu2meTi9zRKbefxedvmcEugQwBI= X-Google-Smtp-Source: APXvYqzurJH+uYLOHA67gwhpf22I9NfofZxvin3d9/AYjrwHhai9p20Av6jaOwrXJfvpT5016EPXaA== X-Received: by 2002:a65:6256:: with SMTP id q22mr4796695pgv.408.1567019136208; Wed, 28 Aug 2019 12:05:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:15 -0700 Message-Id: <20190828190456.30315-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42c Subject: [Qemu-devel] [PATCH v3 28/69] target/arm: Convert LDM, STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This includes a minor bug fix to LDM (user), which requires bit 21 to be 0, which means no writeback. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 428 ++++++++++++++++++++++------------------- target/arm/a32.decode | 6 + target/arm/t32.decode | 10 + 3 files changed, 246 insertions(+), 198 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 6cbf34b424..3a96866531 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9751,6 +9751,232 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a) return op_div(s, a, true); } =20 +/* + * Block data transfer + */ + +static TCGv_i32 op_addr_block_pre(DisasContext *s, arg_ldst_block *a, int = n) +{ + TCGv_i32 addr =3D load_reg(s, a->rn); + + if (a->b) { + if (a->i) { + /* pre increment */ + tcg_gen_addi_i32(addr, addr, 4); + } else { + /* pre decrement */ + tcg_gen_addi_i32(addr, addr, -(n * 4)); + } + } else if (!a->i && n !=3D 1) { + /* post decrement */ + tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); + } + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + /* + * If the writeback is incrementing SP rather than + * decrementing it, and the initial SP is below the + * stack limit but the final written-back SP would + * be above, then then we must not perform any memory + * accesses, but it is IMPDEF whether we generate + * an exception. We choose to do so in this case. + * At this point 'addr' is the lowest address, so + * either the original SP (if incrementing) or our + * final SP (if decrementing), so that's what we check. + */ + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + return addr; +} + +static void op_addr_block_post(DisasContext *s, arg_ldst_block *a, + TCGv_i32 addr, int n) +{ + if (a->w) { + /* write back */ + if (!a->b) { + if (a->i) { + /* post increment */ + tcg_gen_addi_i32(addr, addr, 4); + } else { + /* post decrement */ + tcg_gen_addi_i32(addr, addr, -(n * 4)); + } + } else if (!a->i && n !=3D 1) { + /* pre decrement */ + tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } +} + +static bool op_stm(DisasContext *s, arg_ldst_block *a) +{ + int i, j, n, list, mem_idx; + bool user =3D a->u; + TCGv_i32 addr, tmp, tmp2; + + if (user) { + /* STM (user) */ + if (IS_USER(s)) { + /* Only usable in supervisor mode. */ + unallocated_encoding(s); + return true; + } + } + + list =3D a->list; + n =3D ctpop16(list); + /* TODO: test invalid n =3D=3D 0 case */ + + addr =3D op_addr_block_pre(s, a, n); + mem_idx =3D get_mem_index(s); + + for (i =3D j =3D 0; i < 16; i++) { + if (!(list & (1 << i))) { + continue; + } + + if (user && i !=3D 15) { + tmp =3D tcg_temp_new_i32(); + tmp2 =3D tcg_const_i32(i); + gen_helper_get_user_reg(tmp, cpu_env, tmp2); + tcg_temp_free_i32(tmp2); + } else { + tmp =3D load_reg(s, i); + } + gen_aa32_st32(s, tmp, addr, mem_idx); + tcg_temp_free_i32(tmp); + + /* No need to add after the last transfer. */ + if (++j !=3D n) { + tcg_gen_addi_i32(addr, addr, 4); + } + } + + op_addr_block_post(s, a, addr, n); + return true; +} + +static bool trans_STM(DisasContext *s, arg_ldst_block *a) +{ + return op_stm(s, a); +} + +static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback register in register list is UNPREDICTABLE for T32. */ + if (a->w && (a->list & (1 << a->rn))) { + unallocated_encoding(s); + return true; + } + return op_stm(s, a); +} + +static bool do_ldm(DisasContext *s, arg_ldst_block *a) +{ + int i, j, n, list, mem_idx; + bool loaded_base; + bool user =3D a->u; + bool exc_return =3D false; + TCGv_i32 addr, tmp, tmp2, loaded_var; + + if (user) { + /* LDM (user), LDM (exception return) */ + if (IS_USER(s)) { + /* Only usable in supervisor mode. */ + unallocated_encoding(s); + return true; + } + if (extract32(a->list, 15, 1)) { + exc_return =3D true; + user =3D false; + } else { + /* LDM (user) does not allow writeback. */ + if (a->w) { + unallocated_encoding(s); + return true; + } + } + } + + list =3D a->list; + n =3D ctpop16(list); + /* TODO: test invalid n =3D=3D 0 case */ + + addr =3D op_addr_block_pre(s, a, n); + mem_idx =3D get_mem_index(s); + loaded_base =3D false; + loaded_var =3D NULL; + + for (i =3D j =3D 0; i < 16; i++) { + if (!(list & (1 << i))) { + continue; + } + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld32u(s, tmp, addr, mem_idx); + if (user) { + tmp2 =3D tcg_const_i32(i); + gen_helper_set_user_reg(cpu_env, tmp2, tmp); + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + } else if (i =3D=3D a->rn) { + loaded_var =3D tmp; + loaded_base =3D true; + } else if (i =3D=3D 15 && exc_return) { + store_pc_exc_ret(s, tmp); + } else { + store_reg_from_load(s, i, tmp); + } + + /* No need to add after the last transfer. */ + if (++j !=3D n) { + tcg_gen_addi_i32(addr, addr, 4); + } + } + + op_addr_block_post(s, a, addr, n); + + if (loaded_base) { + store_reg(s, a->rn, loaded_var); + } + + if (exc_return) { + /* Restore CPSR from SPSR. */ + tmp =3D load_cpu_field(spsr); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_cpsr_write_eret(cpu_env, tmp); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } + tcg_temp_free_i32(tmp); + /* Must exit loop to check un-masked IRQs */ + s->base.is_jmp =3D DISAS_EXIT; + } + return true; +} + +static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) +{ + return do_ldm(s, a); +} + +static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback register in register list is UNPREDICTABLE for T32. */ + if (a->w && (a->list & (1 << a->rn))) { + unallocated_encoding(s); + return true; + } + return do_ldm(s, a); +} + /* * Legacy decoder. */ @@ -10029,139 +10255,10 @@ static void disas_arm_insn(DisasContext *s, unsi= gned int insn) case 0x5: case 0x6: case 0x7: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; case 0x08: case 0x09: - { - int j, n, loaded_base; - bool exc_return =3D false; - bool is_load =3D extract32(insn, 20, 1); - bool user =3D false; - TCGv_i32 loaded_var; - /* load/store multiple words */ - /* XXX: store correct base if write back */ - if (insn & (1 << 22)) { - /* LDM (user), LDM (exception return) and STM (user) */ - if (IS_USER(s)) - goto illegal_op; /* only usable in supervisor mode= */ - - if (is_load && extract32(insn, 15, 1)) { - exc_return =3D true; - } else { - user =3D true; - } - } - rn =3D (insn >> 16) & 0xf; - addr =3D load_reg(s, rn); - - /* compute total size */ - loaded_base =3D 0; - loaded_var =3D NULL; - n =3D 0; - for (i =3D 0; i < 16; i++) { - if (insn & (1 << i)) - n++; - } - /* XXX: test invalid n =3D=3D 0 case ? */ - if (insn & (1 << 23)) { - if (insn & (1 << 24)) { - /* pre increment */ - tcg_gen_addi_i32(addr, addr, 4); - } else { - /* post increment */ - } - } else { - if (insn & (1 << 24)) { - /* pre decrement */ - tcg_gen_addi_i32(addr, addr, -(n * 4)); - } else { - /* post decrement */ - if (n !=3D 1) - tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); - } - } - j =3D 0; - for (i =3D 0; i < 16; i++) { - if (insn & (1 << i)) { - if (is_load) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (user) { - tmp2 =3D tcg_const_i32(i); - gen_helper_set_user_reg(cpu_env, tmp2, tmp= ); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - } else if (i =3D=3D rn) { - loaded_var =3D tmp; - loaded_base =3D 1; - } else if (i =3D=3D 15 && exc_return) { - store_pc_exc_ret(s, tmp); - } else { - store_reg_from_load(s, i, tmp); - } - } else { - /* store */ - if (i =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, read_pc(s)); - } else if (user) { - tmp =3D tcg_temp_new_i32(); - tmp2 =3D tcg_const_i32(i); - gen_helper_get_user_reg(tmp, cpu_env, tmp2= ); - tcg_temp_free_i32(tmp2); - } else { - tmp =3D load_reg(s, i); - } - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - j++; - /* no need to add after the last transfer */ - if (j !=3D n) - tcg_gen_addi_i32(addr, addr, 4); - } - } - if (insn & (1 << 21)) { - /* write back */ - if (insn & (1 << 23)) { - if (insn & (1 << 24)) { - /* pre increment */ - } else { - /* post increment */ - tcg_gen_addi_i32(addr, addr, 4); - } - } else { - if (insn & (1 << 24)) { - /* pre decrement */ - if (n !=3D 1) - tcg_gen_addi_i32(addr, addr, -((n - 1) * 4= )); - } else { - /* post decrement */ - tcg_gen_addi_i32(addr, addr, -(n * 4)); - } - } - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - if (loaded_base) { - store_reg(s, rn, loaded_var); - } - if (exc_return) { - /* Restore CPSR from SPSR. */ - tmp =3D load_cpu_field(spsr); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_cpsr_write_eret(cpu_env, tmp); - tcg_temp_free_i32(tmp); - /* Must exit loop to check un-masked IRQs */ - s->base.is_jmp =3D DISAS_EXIT; - } - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0xa: case 0xb: { @@ -10428,73 +10525,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) insn & (1 << 21)); } } else { - int i, loaded_base =3D 0; - TCGv_i32 loaded_var; - bool wback =3D extract32(insn, 21, 1); - /* Load/store multiple. */ - addr =3D load_reg(s, rn); - offset =3D 0; - for (i =3D 0; i < 16; i++) { - if (insn & (1 << i)) - offset +=3D 4; - } - - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, -offset); - } - - if (s->v8m_stackcheck && rn =3D=3D 13 && wback) { - /* - * If the writeback is incrementing SP rather than - * decrementing it, and the initial SP is below the - * stack limit but the final written-back SP would - * be above, then then we must not perform any memory - * accesses, but it is IMPDEF whether we generate - * an exception. We choose to do so in this case. - * At this point 'addr' is the lowest address, so - * either the original SP (if incrementing) or our - * final SP (if decrementing), so that's what we check. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - loaded_var =3D NULL; - for (i =3D 0; i < 16; i++) { - if ((insn & (1 << i)) =3D=3D 0) - continue; - if (insn & (1 << 20)) { - /* Load. */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i =3D=3D rn) { - loaded_var =3D tmp; - loaded_base =3D 1; - } else { - store_reg_from_load(s, i, tmp); - } - } else { - /* Store. */ - tmp =3D load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_gen_addi_i32(addr, addr, 4); - } - if (loaded_base) { - store_reg(s, rn, loaded_var); - } - if (wback) { - /* Base register writeback. */ - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, -offset); - } - /* Fault if writeback register is in register list. */ - if (insn & (1 << rn)) - goto illegal_op; - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } + /* Load/store multiple, in decodetree */ + goto illegal_op; } } break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 341882e637..1267a689e2 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -40,6 +40,7 @@ &mrs_bank rd r sysm &ldst_rr p w u rn rt rm shimm shtype &ldst_ri p w u rn rt imm +&ldst_block rn i b u w list &strex rn rd rt rt2 imm &ldrex rn rt rt2 imm &bfx rd rn lsb widthm1 @@ -514,3 +515,8 @@ SMMLA .... 0111 0101 .... .... .... 0001 ...= . @rdamn SMMLAR .... 0111 0101 .... .... .... 0011 .... @rdamn SMMLS .... 0111 0101 .... .... .... 1101 .... @rdamn SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn + +# Block data transfer + +STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block +LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f315fde0f4..f1e2b934f8 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -37,6 +37,7 @@ &mrs_bank !extern rd r sysm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&ldst_block !extern rn i b u w list &strex !extern rn rd rt rt2 imm &ldrex !extern rn rt rt2 imm &bfx !extern rd rn lsb widthm1 @@ -563,3 +564,12 @@ SXTAB16 1111 1010 0010 .... 1111 .... 10.. ..= .. @rrr_rot UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot + +# Load/store multiple + +@ldstm .... .... .. w:1 . rn:4 list:16 &ldst_block = u=3D0 + +STM_t32 1110 1000 10.0 .... ................ @ldstm i=3D1= b=3D0 +STM_t32 1110 1001 00.0 .... ................ @ldstm i=3D0= b=3D1 +LDM_t32 1110 1000 10.1 .... ................ @ldstm i=3D1= b=3D0 +LDM_t32 1110 1001 00.1 .... ................ @ldstm i=3D0= b=3D1 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IYp58wrZObrPG3dx71Rbw+Ikj8Xd6H3z4vbXYSZpilA=; b=E3kWkSXHIQ/XjfMSnhIfEhiX4W8kQE5YpFMq/uOWP5nU8c6ytbUscbra9APHSn2nMM 5oLCsWXFYFCW4l+wsq1vzNOqA7VdoSvev7pCz7sjlDM0vqAszelyKafxbxmvRp9/4x30 N0xr7O87SsQLYH1NQNfahHKSjtpSWzk2uoTEo8eBorChnLSKB6j35IajaqDa2xe9apqi bjzBihao9dWc8DmqFZVTMMXciUoXkloy71ydfg/06kldWxXt3d2WW+S5WsrFZhUWkVil cpPVZ3RVKSsxzRfJJKT7nUdvAQVjwHpEih+ruIZm+cKcBM+NKCYY1d0XetpG0xN+bpYf qeQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IYp58wrZObrPG3dx71Rbw+Ikj8Xd6H3z4vbXYSZpilA=; b=i9ahbz6zwV4Bc0VEWSa5ks5r/1copIW6UCdQ51iTi15eEEPwKTDKS6IaUTyu0DCbKb Y45CSiImon4YH/9lTJlWV5BSbO0wkXokMrgSbhTFjFZKhJLWhy8vHptujaZRoeQA9tNE wbDGFSK6X6vW+R98vLSbAEXYmgF1kG3OloOQnJjpVm1Jc+rLtMdr5qfKdeQecOS89WVh GaUZEoq6f/850tf+EkJhDXK+g3XO6DXjXBp/UQvjuZlfzM/mVlFBeG8fUuPtmG4Uf6c8 E/FFsFxSsDVJ2W6IM4LbB1bOO9MbWgAsQD5skBkMUU/DzMGVzc8ilHsQPukWBckUrN8D aRsw== X-Gm-Message-State: APjAAAXo+FL9iTIe1AaRglGwG7NoTzMQwyum4ZU1afaWS4XAK9oIhhOn Z60SMffYkqnDVqaoY4Yqua76M5QX1tU= X-Google-Smtp-Source: APXvYqySJulRVKOmkfU43WXCFcpTIYOIodzpogeXN4TgPYf4jxcwq0FlxH64LXGDZGrl10rlVJmefQ== X-Received: by 2002:a17:90a:9dca:: with SMTP id x10mr5887840pjv.100.1567019137672; Wed, 28 Aug 2019 12:05:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:16 -0700 Message-Id: <20190828190456.30315-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 29/69] target/arm: Diagnose writeback register in list for LDM for v7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Prior to v7, for the A32 encoding, this operation wrote an UNKNOWN value back to the base register. Starting in v7 this is UNPREDICTABLE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 3a96866531..529660eb35 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9964,6 +9964,15 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *= a) =20 static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) { + /* + * Writeback register in register list is UNPREDICTABLE + * for ArchVersion() >=3D 7. Prior to v7, A32 would write + * an UNKNOWN value to the base register. + */ + if (ENABLE_ARCH_7 && a->w && (a->list & (1 << a->rn))) { + unallocated_encoding(s); + return true; + } return do_ldm(s, a); } =20 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567021309; cv=none; d=zoho.com; s=zohoarc; b=LIC4LItmtHoRg/RcQATlXAmsghBYflHwEHYcs0r6CDinAnEjX8SHwRPlp6sthqD+nJZi6A1ukwh1F1CRScwjuMaLMJM57EbENMLHqjHD7tA4gj2M2Ubz28SucFg9tiAjuIN3so3QGEUc0MJ02SABwHnwZ1eMly7zQCkV6jPi6Eg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567021309; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=dyqbVPM8CjlhxJ0X4xzBIRTbITeZE2k+cAo7OEV0NYI=; b=KMg3NT+y73kyHWnXgrUnvkVv0jD1QTpvuPMLi/eD6vR6/zSWBAYFuqjT/RshbfLwB8ypJkVhg9Mmn5JUPo29IUi1qxooa3AmmOCAA8HITydMT6T9RAF/Mu38NlYZj9oJydrOR7KLVj9rlXDgF/9BtBS3N3pJWd8DAYk0sleXy1I= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567021309178892.9235410316097; Wed, 28 Aug 2019 12:41:49 -0700 (PDT) Received: from localhost ([::1]:41490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33pC-0004GN-R9 for importer@patchew.org; Wed, 28 Aug 2019 15:41:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38145) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33GP-0003kd-Ll for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33GG-0000HK-PR for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:47 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:40935) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33GG-0000Gb-HV for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:40 -0400 Received: by mail-pg1-x544.google.com with SMTP id w10so217321pgj.7 for ; Wed, 28 Aug 2019 12:05:40 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dyqbVPM8CjlhxJ0X4xzBIRTbITeZE2k+cAo7OEV0NYI=; b=nM108mhTAFLMCQZzRhGWwJFZu4vA3lBzqsS11J9rBTKL6CWPJwNYfNDVLZpUgVUaNf g46PIvwCYzyuRwgZXxWYaXIw8i8jyTt4jGt4+jA3dl/Yd03I8LNImepT9MS3iWgy1cG1 znXbl+1iZBcwUzA4OyzGASFb5OooQ8Po+YOCpGGW6Mw3aeaPJQuhwVnKpWcwibRudX60 tXcvMism++6U9zFIW8gV98lCejnrq0JAdkV5hl1n00VMnVQ6d2uISsrbqJYBY/MQZWfF wquqidmWhX2gcaMEDd0YF9pn2r1WrZ2yV/9dZ6ZFtTso3NaeU49MNsEFlWVe/D8y86++ oosA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dyqbVPM8CjlhxJ0X4xzBIRTbITeZE2k+cAo7OEV0NYI=; b=qYT3KXvUHnLxUewTZaDDPwxgG/THnIOKDYfwWRHrXHvpsOTAi8lt+YpTtEYadvFOdl fYPxBPKqP+H8YAf8zuHEMMpG9qPQfnxMhYKXGpnYpctlreBFnR0nv2n5Zzw5VykbUHmK tG4BwX+1PhP2G23KggNB1dUvDuDI/m3r9TEEBAy9QHnFdOCYagcai+W+6otefH8kiE1E QdK64A1Waloy0QYMB6mJZHRK1BJ0MzdzAhwLlVEzPcD58OUZ1rPBlhl2mZp8l8NzzkL/ 9z4YkBsc7rpB45d0RiMNqfgozs+pJr5xzgnVnGM8lvx2fNfDlaSF8XxZEDRI4Kwqg414 zWsw== X-Gm-Message-State: APjAAAVFYoyTNSsfKI/KMnL1gtF5V3dzZe0zUXbXa8DurVGVBFnmY5SX yXE3yJuF4/P2KtQXxEuA6P1v4qDoWSc= X-Google-Smtp-Source: APXvYqz1S4pKePYAozfdPqeya8sXsIsTrZX5dcfG9QC00QI/yf4P/AgsIhtyBl+mM3+hCdBBrT+4Og== X-Received: by 2002:a63:d30f:: with SMTP id b15mr4699713pgg.341.1567019139008; Wed, 28 Aug 2019 12:05:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:17 -0700 Message-Id: <20190828190456.30315-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 30/69] target/arm: Diagnose too few registers in list for LDM/STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This has been a TODO item for quite a while. The minimum bit count for A32 and T16 is 1, and for T32 is 2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 529660eb35..bfc4508321 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9813,7 +9813,7 @@ static void op_addr_block_post(DisasContext *s, arg_l= dst_block *a, } } =20 -static bool op_stm(DisasContext *s, arg_ldst_block *a) +static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) { int i, j, n, list, mem_idx; bool user =3D a->u; @@ -9830,7 +9830,10 @@ static bool op_stm(DisasContext *s, arg_ldst_block *= a) =20 list =3D a->list; n =3D ctpop16(list); - /* TODO: test invalid n =3D=3D 0 case */ + if (n < min_n) { + unallocated_encoding(s); + return true; + } =20 addr =3D op_addr_block_pre(s, a, n); mem_idx =3D get_mem_index(s); @@ -9863,7 +9866,8 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a) =20 static bool trans_STM(DisasContext *s, arg_ldst_block *a) { - return op_stm(s, a); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return op_stm(s, a, 1); } =20 static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) @@ -9873,10 +9877,11 @@ static bool trans_STM_t32(DisasContext *s, arg_ldst= _block *a) unallocated_encoding(s); return true; } - return op_stm(s, a); + /* BitCount(list) < 2 is UNPREDICTABLE */ + return op_stm(s, a, 2); } =20 -static bool do_ldm(DisasContext *s, arg_ldst_block *a) +static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) { int i, j, n, list, mem_idx; bool loaded_base; @@ -9905,7 +9910,10 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *= a) =20 list =3D a->list; n =3D ctpop16(list); - /* TODO: test invalid n =3D=3D 0 case */ + if (n < min_n) { + unallocated_encoding(s); + return true; + } =20 addr =3D op_addr_block_pre(s, a, n); mem_idx =3D get_mem_index(s); @@ -9973,7 +9981,8 @@ static bool trans_LDM_a32(DisasContext *s, arg_ldst_b= lock *a) unallocated_encoding(s); return true; } - return do_ldm(s, a); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return do_ldm(s, a, 1); } =20 static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) @@ -9983,7 +9992,8 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_b= lock *a) unallocated_encoding(s); return true; } - return do_ldm(s, a); + /* BitCount(list) < 2 is UNPREDICTABLE */ + return do_ldm(s, a, 2); } =20 /* --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567021180; cv=none; d=zoho.com; s=zohoarc; b=esuog17AZA8+XOiPk1tSVoSs5ZxscR9Z7/ohYc3bu3D313T0iVm2W6SGBRb5WBmoUwgBe687e9OsqsDamaR7fQMGOWldIY36x18PfBUvtFLE2lNzwZ+Ilv7iZT6KtaZ527rrbOuF/XWFIAvQ7RfRLa/U3Cvu45zFPvzYJksktWg= ARC-Message-Signature: i=1; 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 31/69] target/arm: Diagnose base == pc for LDM/STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We have been using store_reg and not store_reg_for_load when writing back a loaded value into the base register. At first glance this is incorrect when base =3D=3D pc, however that case is UNPREDICTABLE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index bfc4508321..812ce5037f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9830,7 +9830,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a= , int min_n) =20 list =3D a->list; n =3D ctpop16(list); - if (n < min_n) { + if (n < min_n || a->rn =3D=3D 15) { unallocated_encoding(s); return true; } @@ -9910,7 +9910,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) =20 list =3D a->list; n =3D ctpop16(list); - if (n < min_n) { + if (n < min_n || a->rn =3D=3D 15) { unallocated_encoding(s); return true; } @@ -9950,6 +9950,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) op_addr_block_post(s, a, addr, n); =20 if (loaded_base) { + /* Note that we reject base =3D=3D pc above. */ store_reg(s, a->rn, loaded_var); } =20 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567020526; cv=none; d=zoho.com; s=zohoarc; b=DZIEG/gEHT2LzIWPG15nwJ4azOberKIV/FgAU5rReUf/kDSRVXiS+TYJgxkyvXeXMXDaGez81jZPouSbIMjiJ4NIxq/9hU+Eanss8gVV3KHC0ucfacQ1w5elyXnZJbQtr7nY6oQS1UVVtJAvDhcEKA9c1iNsbpkMVYnMRQ57u7g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567020526; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=2z7Ln/9N4XB/zpfp9+WV/L8Yn7I2nO4gdCcvWAyiB/s=; b=GtqPy8uie9D64lb0yn5i0FXFWyE0MgfLXt56R8zF5nbLMX0tz0M5zNxR1c57OoJSTxUQKFDsmAoo8weEutVdBj4UelCVymOH8S7AcyuTNsduONIDU2LubQWkSBc3gTgaruNpeLBWUfPYKAemyCaROWSJL7EPk5w7CD8WuGkAApY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156702052659668.64861583477602; Wed, 28 Aug 2019 12:28:46 -0700 (PDT) Received: from localhost ([::1]:41276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33ca-0001BB-R7 for importer@patchew.org; Wed, 28 Aug 2019 15:28:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38166) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33GQ-0003kg-El for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33GK-0000JJ-KO for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:48 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:45248) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33GK-0000IQ-8g for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:44 -0400 Received: by mail-pl1-x630.google.com with SMTP id y8so379312plr.12 for ; Wed, 28 Aug 2019 12:05:43 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2z7Ln/9N4XB/zpfp9+WV/L8Yn7I2nO4gdCcvWAyiB/s=; b=Zmt8tJW6frf8+peKagExJljxGKBy66T4l+AJH6ShMG5qztZr/oLtAwEiWJ53LuqFN+ x+klBSvLmEPL1SSe/G2bjs27s3W8PlorfOLoolAeqTaaZnTbdDSxlWeq4Nf4IVUo62ag Ozyh2/5+i2NtkHznMbshJXxNOE6teMxUgHCalAZfngVy0P1+BjR6FRVhBkJ7Tmqrl8tI XL+gEGrX1gf5Vr9wo9CQkfq00G5N3YJLD8orAjAh+rbbEJuylGTDoFkIr2iu47x93t6D GFcpI6AMzR1cSb607R48wp9ncbkpqZFFcRX1a66710t3Gc6PqyNoqSIGqmUT1oq5TPno W+yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2z7Ln/9N4XB/zpfp9+WV/L8Yn7I2nO4gdCcvWAyiB/s=; b=OUA+WVpxF8Y8GHcLa8JB+FO6laDpL08qacgrp3Y7L2eJddXaHr8sZARt4/LBomnSnn h/NhyNiz+ml7sXFE6ERCIWPJzw9IIEhgAb/lgke+esdGDVErXJiMjXB1gNLP3eqHXI0F E1rXmbeEf8s+oitWVbcc4jWB5zt8hOkGGkUZL7rpBKp8Xi2IkfVmJfrnYCINQUiNFQ/R lw+okAsP5WXG/hC8vH7+3RKg8x4PZkZfwSpH/UcFtfctxTov2wy7L72rdqk8rs1iikxC XZ5jYh1f18NimeufGp9+S8wU8Phq8dnp1jRqcukzb0UfsodDjOoZzEURYQhGI3vxNrJI utfw== X-Gm-Message-State: APjAAAWf0fEf3frJ6tLbLKdcfXYH2mNMluns8G7uVhb0TpAkpXGXakXg xjOqogYfzaFbBUiot76yjt/CORPwJ18= X-Google-Smtp-Source: APXvYqxYqvXKAzZMCBQ01YDrbv7SOCjuQgQ/6yjBMbKWPdUF9L6evTC//ITdF4g5zjjQF908xgN1xA== X-Received: by 2002:a17:902:bcc2:: with SMTP id o2mr5891739pls.127.1567019141391; Wed, 28 Aug 2019 12:05:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:19 -0700 Message-Id: <20190828190456.30315-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::630 Subject: [Qemu-devel] [PATCH v3 32/69] target/arm: Convert B, BL, BLX (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 133 +++++++++++++++-------------------- target/arm/a32-uncond.decode | 8 +++ target/arm/a32.decode | 8 +++ target/arm/t32.decode | 81 ++++++++++++--------- 4 files changed, 123 insertions(+), 107 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 812ce5037f..fb0e875917 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7519,6 +7519,14 @@ static int t32_expandimm_imm(DisasContext *s, int x) return imm; } =20 +static int t32_branch24(DisasContext *s, int x) +{ + /* Convert J1:J2 at x[22:21] to I2:I1, which involves I=3DJ^~S. */ + x ^=3D !(x < 0) * (3 << 21); + /* Append the final zero. */ + return x << 1; +} + /* * Include the generated decoders. */ @@ -9997,13 +10005,56 @@ static bool trans_LDM_t32(DisasContext *s, arg_lds= t_block *a) return do_ldm(s, a, 2); } =20 +/* + * Branch, branch with link + */ + +static bool trans_B(DisasContext *s, arg_i *a) +{ + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a) +{ + /* This has cond from encoding, required to be outside IT block. */ + if (a->cond >=3D 0xe) { + return false; + } + if (s->condexec_mask) { + unallocated_encoding(s); + return true; + } + arm_skip_unless(s, a->cond); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_BL(DisasContext *s, arg_i *a) +{ + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) +{ + /* For A32, ARCH(5) is checked near the start of the uncond block. */ + if (s->thumb && (a->imm & 2)) { + return false; + } + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_bx_im(s, (read_pc(s) & ~3) + a->imm + !s->thumb); + return true; +} + /* * Legacy decoder. */ =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rn; + unsigned int cond, op1, i, rn; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10171,21 +10222,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) } gen_rfe(s, tmp, tmp2); return; - } else if ((insn & 0x0e000000) =3D=3D 0x0a000000) { - /* branch link and change to thumb (blx ) */ - int32_t offset; - - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, s->base.pc_next); - store_reg(s, 14, tmp); - /* Sign-extend the 24-bit offset */ - offset =3D (((int32_t)insn) << 8) >> 8; - val =3D read_pc(s); - /* offset * 4 + bit24 * 2 + (thumb bit) */ - val +=3D (offset << 2) | ((insn >> 23) & 2) | 1; - /* protected by ARCH(5); above, near the start of uncond block= */ - gen_bx_im(s, val); - return; } else if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10277,23 +10313,10 @@ static void disas_arm_insn(DisasContext *s, unsig= ned int insn) case 0x7: case 0x08: case 0x09: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; case 0xa: case 0xb: - { - int32_t offset; - - /* branch (and link) */ - if (insn & (1 << 24)) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, s->base.pc_next); - store_reg(s, 14, tmp); - } - offset =3D sextract32(insn << 2, 0, 26); - gen_jmp(s, read_pc(s) + offset); - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0xc: case 0xd: case 0xe: @@ -10660,32 +10683,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) if (insn & (1 << 15)) { /* Branches, misc control. */ if (insn & 0x5000) { - /* Unconditional branch. */ - /* signextend(hw1[10:0]) -> offset[:12]. */ - offset =3D ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff; - /* hw1[10:0] -> offset[11:1]. */ - offset |=3D (insn & 0x7ff) << 1; - /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22] - offset[24:22] already have the same value because of the - sign extension above. */ - offset ^=3D ((~insn) & (1 << 13)) << 10; - offset ^=3D ((~insn) & (1 << 11)) << 11; - - if (insn & (1 << 14)) { - /* Branch and link. */ - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); - } - - offset +=3D read_pc(s); - if (insn & (1 << 12)) { - /* b/bl */ - gen_jmp(s, offset); - } else { - /* blx */ - offset &=3D ~(uint32_t)2; - /* thumb2 bx, no need to check */ - gen_bx_im(s, offset); - } + /* Unconditional branch, in decodetree */ + goto illegal_op; } else if (((insn >> 23) & 7) =3D=3D 7) { /* Misc control */ if (insn & (1 << 13)) @@ -10771,24 +10770,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } } } else { - /* Conditional branch. */ - op =3D (insn >> 22) & 0xf; - /* Generate a conditional jump to next instruction. */ - arm_skip_unless(s, op); - - /* offset[11:1] =3D insn[10:0] */ - offset =3D (insn & 0x7ff) << 1; - /* offset[17:12] =3D insn[21:16]. */ - offset |=3D (insn & 0x003f0000) >> 4; - /* offset[31:20] =3D insn[26]. */ - offset |=3D ((int32_t)((insn << 5) & 0x80000000)) >> 11; - /* offset[18] =3D insn[13]. */ - offset |=3D (insn & (1 << 13)) << 5; - /* offset[19] =3D insn[11]. */ - offset |=3D (insn & (1 << 11)) << 8; - - /* jump to the offset */ - gen_jmp(s, read_pc(s) + offset); + /* Conditional branch, in decodetree */ + goto illegal_op; } } else { /* diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 8dee26d3b6..573ac2cf8e 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -21,3 +21,11 @@ # All insns that have 0xf in insn[31:28] are decoded here. # All of those that have a COND field in insn[31:28] are in a32.decode # + +&i !extern imm + +# Branch with Link and Exchange + +%imm24h 0:s24 24:1 !function=3Dtimes_2 + +BLX_i 1111 101 . ........................ &i imm=3D%im= m24h diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 1267a689e2..62c6f8562e 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -520,3 +520,11 @@ SMMLSR .... 0111 0101 .... .... .... 1111 ..= .. @rdamn =20 STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block + +# Branch, branch with link + +%imm26 0:s24 !function=3Dtimes_4 +@branch ---- .... ........................ &i imm=3D%im= m26 + +B .... 1010 ........................ @branch +BL .... 1011 ........................ @branch diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f1e2b934f8..ebc92f2c28 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -284,47 +284,55 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .= ... @rdm %msr_sysm 4:1 8:4 %mrs_sysm 4:1 16:4 %imm16_16_0 16:4 0:12 +%imm21 26:s1 11:1 13:1 16:6 0:11 !function=3Dtimes_2 +&ci cond imm =20 { + # Group insn[25:23] =3D 111, which is cond=3D111x for the branch below, + # or unconditional, which would be illegal for the branch. { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + # Hints + { + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 - # The canonical nop ends in 0000 0000, but the whole rest - # of the space is "reserved hint, behaves as nop". - NOP 1111 0011 1010 1111 1000 0000 ---- ---- - } - # Note that the v7m insn overlaps both the normal and banked insn. - { - MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- + } + # Note that the v7m insn overlaps both the normal and banked insn. + { + MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ &mrs_bank sysm=3D%mrs_sysm - MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg - MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 - } - { - MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ + MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg + MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 + } + { + MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ &msr_bank sysm=3D%msr_sysm - MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg - MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 - } - BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r - { - # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as = for - # every other encoding of SUBS. With v7VE, IMM=3D0 is redefined as ER= ET. - # The distinction between the two only matters for Hyp mode. - ERET 1111 0011 1101 1110 1000 1111 0000 0000 - SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ + MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg + MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 + } + BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r + { + # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works a= s for + # every other encoding of SUBS. With v7VE, IMM=3D0 is redefined as = ERET. + # The distinction between the two only matters for Hyp mode. + ERET 1111 0011 1101 1110 1000 1111 0000 0000 + SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ &s_rri_rot rot=3D0 s=3D1 rd=3D15 rn=3D14 - } - SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i - HVC 1111 0111 1110 .... 1000 .... .... .... \ + } + SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i + HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=3D%imm16_16_0 - UDF 1111 0111 1111 ---- 1010 ---- ---- ---- + UDF 1111 0111 1111 ---- 1010 ---- ---- ---- + } + B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=3D%i= mm21 } =20 # Load/store (register, immediate, literal) @@ -573,3 +581,12 @@ STM_t32 1110 1000 10.0 .... ................ = @ldstm i=3D1 b=3D0 STM_t32 1110 1001 00.0 .... ................ @ldstm i=3D0= b=3D1 LDM_t32 1110 1000 10.1 .... ................ @ldstm i=3D1= b=3D0 LDM_t32 1110 1001 00.1 .... ................ @ldstm i=3D0= b=3D1 + +# Branches + +%imm24 26:s1 13:1 11:1 16:10 0:11 !function=3Dt32_branch24 +@branch24 ................................ &i imm=3D%im= m24 + +B 1111 0. .......... 10.1 ............ @branch24 +BL 1111 0. .......... 11.1 ............ @branch24 +BLX_i 1111 0. .......... 11.0 ............ @branch24 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567021720; cv=none; d=zoho.com; s=zohoarc; b=P/f3hEkGvWNP+2PHE8vndKNQWqidaTmDdA4lDYZdlLhcUG9/LkYmxmvIZyZWSYBsXRQJDtakTwXXnDkStRU2GLvtTsDZziVsqoRIbULQZ9UwrBx/q31WLDjhZl6zsSoUThtj24p4J+SnSBc0syZo9BuohRumlIePY5z0YIW7zIs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567021720; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=l58FUNN+MerXiKJ010yMrqx8XR2Kx9uSnwDhJ/Yfh7g=; b=U1ESURuAwh19TSPCBBWD3LMzam7Dd7AOtA8kp87kLKMqnrcC5xRB1oJ/8fMIs+MjknNYQdNdEpTJjW1Ol1wLL9wVKC4MFEr4OjAb+zZlx+2aJU8K68+DT2FTNdShOMaAD4ubiu3gVJU1Kh5f4ns4s/xsBCAQKZ+UtUDloOPqlOI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567021720258328.80376051259157; Wed, 28 Aug 2019 12:48:40 -0700 (PDT) Received: from localhost ([::1]:41618 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33vp-0002Vk-If for importer@patchew.org; Wed, 28 Aug 2019 15:48:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38191) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33GS-0003lM-OV for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33GO-0000MV-Fq for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:52 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:40504) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33GK-0000Il-Ky for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:46 -0400 Received: by mail-pl1-x643.google.com with SMTP id h3so393428pls.7 for ; Wed, 28 Aug 2019 12:05:43 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 33/69] target/arm: Convert SVC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 19 +++++++++++++------ target/arm/a32.decode | 4 ++++ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index fb0e875917..eb4384618c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10048,6 +10048,18 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i= *a) return true; } =20 +/* + * Supervisor call + */ + +static bool trans_SVC(DisasContext *s, arg_SVC *a) +{ + gen_set_pc_im(s, s->base.pc_next); + s->svc_imm =3D a->imm; + s->base.is_jmp =3D DISAS_SWI; + return true; +} + /* * Legacy decoder. */ @@ -10315,6 +10327,7 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) case 0x09: case 0xa: case 0xb: + case 0xf: /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; case 0xc: @@ -10330,12 +10343,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) goto illegal_op; } break; - case 0xf: - /* swi */ - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm =3D extract32(insn, 0, 24); - s->base.is_jmp =3D DISAS_SWI; - break; default: illegal_op: unallocated_encoding(s); diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 62c6f8562e..0bd952c069 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -528,3 +528,7 @@ LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:1= 6 &ldst_block =20 B .... 1010 ........................ @branch BL .... 1011 ........................ @branch + +# Supervisor call + +SVC ---- 1111 imm:24 &i --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567021778; cv=none; d=zoho.com; s=zohoarc; b=cb20NeKjj8esNmETb1jRwKvHq+hL9QeERO0z8AhipjH4dbEHz51LRe6rjvEpCRexvo/f/UTMcgLMPG/Zsn8pQ6XbKfnQ1fdtFNvT7yEPqsMtTGLHnOh+uDnsE8Cb7XC3Roa5r2fdyTyvOGnk6ZEOUgSPcs3c8mYWvA9/oSLJqWg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567021778; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=34LoZAdS2gtCHWez6TvCJj37+KovuRDH5DtlgNazQ6w=; b=lez2/9GO2khXvIyEuqUKF1NQMlJEiLi9mkpq3ECOhUKn/hYGWREmiKIAi+OvMNp0w/2ZZPR4sVKP51S6pLNr+aOBsvDbA0gr5k7r63YWOdJaCpW7udfUflwwIMAs0vfOr9iEFIH8UFT453uQ80/Tmq7j0dJX14a0ZynUY4cvJNA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567021777963675.3611277921954; Wed, 28 Aug 2019 12:49:37 -0700 (PDT) Received: from localhost ([::1]:41644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33wm-0003m7-97 for importer@patchew.org; Wed, 28 Aug 2019 15:49:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38282) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33GV-0003of-AS for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33GT-0000PF-1g for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:55 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:40505) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33GS-0000JH-Ki for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:52 -0400 Received: by mail-pf1-x441.google.com with SMTP id w16so386330pfn.7 for ; Wed, 28 Aug 2019 12:05:45 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=34LoZAdS2gtCHWez6TvCJj37+KovuRDH5DtlgNazQ6w=; b=u6mVM36HxXa6wugMJsSdKsXKJxuRaiXRxnYiIXOJOxlpdC5lvcMFrIpXUj/xsI0S3h DKpmREXDwNBezxjRxrRVvKma8L9WKNzvZCRDy39VJQHhaBCz1I1Yv/qT1HbyP1V9bkxl Mv8jrBeyGW9kvtdCezC/t2/CH9F4AVrlNMtfiP2OlS4XXNRy/6bywSX8Vhsryl4muyOD ByXHzfNpCGPkZN6Xq8axMHHNBn+pFjg04/eO2qP1xsV9I07eCBg5hV/zSd2DZXhuX9g/ NqSv0glqnKRiT9dljgTBDp+8JAaI2Iaj1DWGP+Apd8D7oydnHYFhGA3ErMSVTmeQpRf2 Nk4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=34LoZAdS2gtCHWez6TvCJj37+KovuRDH5DtlgNazQ6w=; b=JVBrTbvu2Kk7dzjzctFfsIlDa+ig2MGR+dIjpE4IsoKEkAEavLQ1yy+STHpveVpLUq gY/4vZIAqro6Q6Rb9NsR+wzCVhR5/SYLuF53oa7bkVVJjDOkr9WaV3RRiWrzWP/V3vZR wnIOiSuqbXSLZc9OHn7s3MEopl9TPozJDYMCK6wz1/5+/ibbqyQhFe2/R/zCUHSS+12h PnGSAbX83/NHqNIeWVq+xCaKClYKdPxP3qhvLZo7Z9pa+49HVTaGcDOd2vMZFzgUQUMR n6r7HfEiHKmtdFkCgF5mbO2/WNnM+lhUJO/sosRnaMFeCOHYcecHOnKWSVN8v5V5ihsK ivRQ== X-Gm-Message-State: APjAAAUjUCM0m/DOZ5WAqxvU5a7sUnB/fZ1/S8lMFdNPWILavRygbHxz Y1SOf2tdA4/pdW3Q9VlRJcmMMar5eI0= X-Google-Smtp-Source: APXvYqyQTVnfAlTVpo/HGBxPNEBBRvz1cE/2zrDdH6lMWVcoJ2T4ZCYz3xxAWAnnnNDjbIbK/JEiHg== X-Received: by 2002:a63:e602:: with SMTP id g2mr4786330pgh.224.1567019143477; Wed, 28 Aug 2019 12:05:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:21 -0700 Message-Id: <20190828190456.30315-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 34/69] target/arm: Convert RFE and SRS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Fix SRS decode; reject RFE and SRS for m-profile. --- target/arm/translate.c | 154 +++++++++++++++-------------------- target/arm/a32-uncond.decode | 8 ++ target/arm/t32.decode | 12 +++ 3 files changed, 85 insertions(+), 89 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index eb4384618c..46e3f946d5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10060,16 +10060,75 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) return true; } =20 +/* + * Unconditional system instructions + */ + +static bool trans_RFE(DisasContext *s, arg_RFE *a) +{ + int32_t offset; + TCGv_i32 addr, t1, t2; + + if (!ENABLE_ARCH_6 || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + unallocated_encoding(s); + return true; + } + + addr =3D load_reg(s, a->rn); + + switch (a->pu) { + case 0: offset =3D -4; break; /* DA */ + case 1: offset =3D 0; break; /* IA */ + case 2: offset =3D -8; break; /* DB */ + case 3: offset =3D 4; break; /* IB */ + default: + g_assert_not_reached(); + } + tcg_gen_addi_i32(addr, addr, offset); + + /* Load PC into tmp and CPSR into tmp2. */ + t1 =3D tcg_temp_new_i32(); + gen_aa32_ld32u(s, t1, addr, get_mem_index(s)); + tcg_gen_addi_i32(addr, addr, 4); + t2 =3D tcg_temp_new_i32(); + gen_aa32_ld32u(s, t2, addr, get_mem_index(s)); + + if (a->w) { + /* Base writeback. */ + switch (a->pu) { + case 0: offset =3D -8; break; + case 1: offset =3D 4; break; + case 2: offset =3D -4; break; + case 3: offset =3D 0; break; + } + tcg_gen_addi_i32(addr, addr, offset); + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } + gen_rfe(s, t1, t2); + return true; +} + +static bool trans_SRS(DisasContext *s, arg_SRS *a) +{ + if (!ENABLE_ARCH_6 || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_srs(s, a->mode, a->pu, a->w); + return true; +} + /* * Legacy decoder. */ =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, op1, i, rn; - TCGv_i32 tmp; - TCGv_i32 tmp2; - TCGv_i32 addr; + unsigned int cond, op1; =20 /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -10188,52 +10247,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) default: goto illegal_op; } - } else if ((insn & 0x0e5fffe0) =3D=3D 0x084d0500) { - /* srs */ - ARCH(6); - gen_srs(s, (insn & 0x1f), (insn >> 23) & 3, insn & (1 << 21)); - return; - } else if ((insn & 0x0e50ffe0) =3D=3D 0x08100a00) { - /* rfe */ - int32_t offset; - if (IS_USER(s)) - goto illegal_op; - ARCH(6); - rn =3D (insn >> 16) & 0xf; - addr =3D load_reg(s, rn); - i =3D (insn >> 23) & 3; - switch (i) { - case 0: offset =3D -4; break; /* DA */ - case 1: offset =3D 0; break; /* IA */ - case 2: offset =3D -8; break; /* DB */ - case 3: offset =3D 4; break; /* IB */ - default: abort(); - } - if (offset) - tcg_gen_addi_i32(addr, addr, offset); - /* Load PC into tmp and CPSR into tmp2. */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - tcg_gen_addi_i32(addr, addr, 4); - tmp2 =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - if (insn & (1 << 21)) { - /* Base writeback. */ - switch (i) { - case 0: offset =3D -8; break; - case 1: offset =3D 4; break; - case 2: offset =3D -4; break; - case 3: offset =3D 0; break; - default: abort(); - } - if (offset) - tcg_gen_addi_i32(addr, addr, offset); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - gen_rfe(s, tmp, tmp2); - return; } else if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10396,7 +10409,6 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; - TCGv_i32 tmp2; TCGv_i32 addr; int op; =20 @@ -10540,44 +10552,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) goto illegal_op; } } else { - /* Load/store multiple, RFE, SRS. */ - if (((insn >> 23) & 1) =3D=3D ((insn >> 24) & 1)) { - /* RFE, SRS: not available in user mode or on M profile */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - if (insn & (1 << 20)) { - /* rfe */ - addr =3D load_reg(s, rn); - if ((insn & (1 << 24)) =3D=3D 0) - tcg_gen_addi_i32(addr, addr, -8); - /* Load PC into tmp and CPSR into tmp2. */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - tcg_gen_addi_i32(addr, addr, 4); - tmp2 =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - if (insn & (1 << 21)) { - /* Base writeback. */ - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, 4); - } else { - tcg_gen_addi_i32(addr, addr, -4); - } - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - gen_rfe(s, tmp, tmp2); - } else { - /* srs */ - gen_srs(s, (insn & 0x1f), (insn & (1 << 24)) ? 1 : 2, - insn & (1 << 21)); - } - } else { - /* Load/store multiple, in decodetree */ - goto illegal_op; - } + /* Load/store multiple, RFE, SRS, in decodetree */ + goto illegal_op; } break; case 5: diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 573ac2cf8e..64548a93e2 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -29,3 +29,11 @@ %imm24h 0:s24 24:1 !function=3Dtimes_2 =20 BLX_i 1111 101 . ........................ &i imm=3D%im= m24h + +# System Instructions + +&rfe rn w pu +&srs mode w pu + +RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe +SRS 1111 100 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ebc92f2c28..c8a8aeceee 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -582,6 +582,18 @@ STM_t32 1110 1001 00.0 .... ................ = @ldstm i=3D0 b=3D1 LDM_t32 1110 1000 10.1 .... ................ @ldstm i=3D1= b=3D0 LDM_t32 1110 1001 00.1 .... ................ @ldstm i=3D0= b=3D1 =20 +&rfe !extern rn w pu +@rfe .... .... .. w:1 . rn:4 ................ &rfe + +RFE 1110 1000 00.1 .... 1100000000000000 @rfe pu=3D2 +RFE 1110 1001 10.1 .... 1100000000000000 @rfe pu=3D1 + +&srs !extern mode w pu +@srs .... .... .. w:1 . .... ........... mode:5 &srs + +SRS 1110 1000 00.0 1101 1100 0000 000. .... @srs pu=3D2 +SRS 1110 1001 10.0 1101 1100 0000 000. .... @srs pu=3D1 + # Branches =20 %imm24 26:s1 13:1 11:1 16:10 0:11 !function=3Dt32_branch24 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Fhqpr1ZM66JaZ1pn92il8bSyyclZ16JqoBnLn1JZUIU=; b=M3WlVDKIPbZwvn6YFjebxm5TvA0Uk9i9lcquKa8GF1oTzf9U+FbExZKWY3ixDj5dKI 2dPf+CDEqxhaO/hfOo7+6cMEgcfvA+ULqt3klTGY/5iWEZWM9JSvBFqVazFnPpviDZkC lYwAYeHVUTvtro4Vkr33fr6GA2wHJnr8kgskuQkI9rs9qiyThcq2L6s6Dso3salQsQtK CYoa3kCyf2RmB0UpVFCS7TY6uIionGp72syXgwoKlbAtqiOJZBkMqJQrxWBNuclbKdg5 o6+To+3yxK8WkWvxPdbyFlAwYhCP2yJID6FIT781d8BE9/d3qSTx34SHmRjq39WoRj/i G2mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Fhqpr1ZM66JaZ1pn92il8bSyyclZ16JqoBnLn1JZUIU=; b=I333Yj4t/+b7Ff+g6b4I3edPYLF7xLYmXSk9UAjy1GtEc0C9glcE3ER3GCAszIUxkT yVUIDIr0xIMGSEU6Xhdo1nsxyOFwplVVemr8rZ9yZKdnBlBNEC69hmfig8rUyY+/gJ5o 6wC2DIxSMbdG2ats3nYXT/tseT8LDJc+B02Mwbd6nHTUgYugKCTR6GZjdFZEmDPc7/bK 2uPBYU0aZ4eyxUixbANcrpZp3qixm/zGPEDudJ/my1FgpeEnb+vk2q272EKkzeV51SOf Nk41l48a6JO/FrNfIb1Igmt4FUdYfJhMZz/SWvMYPMgfDAnohsgcayDP8GmCwiD4t9so YHEQ== X-Gm-Message-State: APjAAAW8goKw+aDYo6T/opKtMDc+WglJlOj9b/i2C+ZZ8NvwyPMEQiiJ dBX8OD4tISjlcyd+B6hTzM50Psrf/50= X-Google-Smtp-Source: APXvYqzjRbJCFqf8XgtAs7KOpF+O/tg0Mmdl3Yq3ypfhunWqvkgbEF82GG9vgW5wRov9hRoZ3fZq0g== X-Received: by 2002:a17:902:788b:: with SMTP id q11mr5863834pll.308.1567019144866; Wed, 28 Aug 2019 12:05:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:22 -0700 Message-Id: <20190828190456.30315-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62a Subject: [Qemu-devel] [PATCH v3 35/69] target/arm: Convert Clear-Exclusive, Barriers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- v3: Check m-profile for all; fix missing isa check for ISB; fix thumb isa check for CLREX and DSB. --- target/arm/translate.c | 127 ++++++++++++++++------------------- target/arm/a32-uncond.decode | 10 +++ target/arm/t32.decode | 10 +++ 3 files changed, 78 insertions(+), 69 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 46e3f946d5..003b8ac414 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10122,6 +10122,63 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a) return true; } =20 +/* + * Clear-Exclusive, Barriers + */ + +static bool trans_CLREX(DisasContext *s, arg_CLREX *a) +{ + if (s->thumb + ? !ENABLE_ARCH_7 && !arm_dc_feature(s, ARM_FEATURE_M) + : !ENABLE_ARCH_6K) { + return false; + } + gen_clrex(s); + return true; +} + +static bool trans_DSB(DisasContext *s, arg_DSB *a) +{ + if (!ENABLE_ARCH_7 && !arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + return true; +} + +static bool trans_DMB(DisasContext *s, arg_DMB *a) +{ + return trans_DSB(s, NULL); +} + +static bool trans_ISB(DisasContext *s, arg_ISB *a) +{ + if (!ENABLE_ARCH_7 && !arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + /* + * We need to break the TB after this insn to execute + * self-modifying code correctly and also to take + * any pending interrupts immediately. + */ + gen_goto_tb(s, 0, s->base.pc_next); + return true; +} + +static bool trans_SB(DisasContext *s, arg_SB *a) +{ + if (!dc_isar_feature(aa32_sb, s)) { + return false; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->base.pc_next); + return true; +} + /* * Legacy decoder. */ @@ -10215,38 +10272,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) s->base.is_jmp =3D DISAS_UPDATE; } return; - } else if ((insn & 0x0fffff00) =3D=3D 0x057ff000) { - switch ((insn >> 4) & 0xf) { - case 1: /* clrex */ - ARCH(6K); - gen_clrex(s); - return; - case 4: /* dsb */ - case 5: /* dmb */ - ARCH(7); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - return; - case 6: /* isb */ - /* We need to break the TB after this insn to execute - * self-modifying code correctly and also to take - * any pending interrupts immediately. - */ - gen_goto_tb(s, 0, s->base.pc_next); - return; - case 7: /* sb */ - if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { - goto illegal_op; - } - /* - * TODO: There is no speculation barrier opcode - * for TCG; MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); - return; - default: - goto illegal_op; - } } else if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10707,43 +10732,7 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) gen_set_psr_im(s, offset, 0, imm); } break; - case 3: /* Special control operations. */ - if (!arm_dc_feature(s, ARM_FEATURE_V7) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - op =3D (insn >> 4) & 0xf; - switch (op) { - case 2: /* clrex */ - gen_clrex(s); - break; - case 4: /* dsb */ - case 5: /* dmb */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - break; - case 6: /* isb */ - /* We need to break the TB after this insn - * to execute self-modifying code correctly - * and also to take any pending interrupts - * immediately. - */ - gen_goto_tb(s, 0, s->base.pc_next); - break; - case 7: /* sb */ - if ((insn & 0xf) || !dc_isar_feature(aa32_sb, = s)) { - goto illegal_op; - } - /* - * TODO: There is no speculation barrier opcode - * for TCG; MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); - break; - default: - goto illegal_op; - } - break; + case 3: /* Special control operations, in decodetree */ case 4: /* bxj, in decodetree */ goto illegal_op; case 5: /* Exception return. */ diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 64548a93e2..c7e9df8030 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -22,6 +22,7 @@ # All of those that have a COND field in insn[31:28] are in a32.decode # =20 +&empty !extern &i !extern imm =20 # Branch with Link and Exchange @@ -37,3 +38,12 @@ BLX_i 1111 101 . ........................ = &i imm=3D%imm24h =20 RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe SRS 1111 100 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs + +# Clear-Exclusive, Barriers + +# QEMU does not require the option field for the barriers. +CLREX 1111 0101 0111 1111 1111 0000 0001 1111 +DSB 1111 0101 0111 1111 1111 0000 0100 ---- +DMB 1111 0101 0111 1111 1111 0000 0101 ---- +ISB 1111 0101 0111 1111 1111 0000 0110 ---- +SB 1111 0101 0111 1111 1111 0000 0111 0000 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c8a8aeceee..18c268e712 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -305,6 +305,16 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ..= .. @rdm # of the space is "reserved hint, behaves as nop". NOP 1111 0011 1010 1111 1000 0000 ---- ---- } + + # Miscelaneous control + { + CLREX 1111 0011 1011 1111 1000 1111 0010 1111 + DSB 1111 0011 1011 1111 1000 1111 0100 ---- + DMB 1111 0011 1011 1111 1000 1111 0101 ---- + ISB 1111 0011 1011 1111 1000 1111 0110 ---- + SB 1111 0011 1011 1111 1000 1111 0111 0000 + } + # Note that the v7m insn overlaps both the normal and banked insn. { MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567020820; cv=none; d=zoho.com; s=zohoarc; b=obQtNTVbGvfM3OJGg418NAIPXLd5FZ272S8dpT4hLIOMvlJLMYzdcwyBhO4EXHNKJRfs2iUGlYPZ1pqsGwcgyIYc2RjpswIIRoVJZGJerHDc7bUfpvvZhQ4yjaIPHn/6AAluhh1j9yPnSkl2YP+wjLCRNRXE88G2RUEgdg03kVg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567020820; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=0UvFhmNUqeBm7S5PhfAWHzrVJNihnGpoWwY5zvTyQDs=; b=ky/7Fsf2Cc/1dgCPEW28zss5kxi6Uy24M4fufX8V84HAgkzM/Y+l/zINzWN6COuuiYOkD3mRs+IvdsDP8BF1uoE+Inzjqrgvu6UuZUqNb248OnuK5FLguyjOH+q14tMMlPFYP4mWqxBAZhm6S8DytY661qM5Rf1VstS/YlKxBJk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567020820747800.7196539439768; Wed, 28 Aug 2019 12:33:40 -0700 (PDT) Received: from localhost ([::1]:41348 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33hI-00051Q-U5 for importer@patchew.org; Wed, 28 Aug 2019 15:33:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38261) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33GU-0003oD-Vq for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33GS-0000Ot-S9 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:54 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:41815) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33GS-0000Lg-FX for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:52 -0400 Received: by mail-pf1-x442.google.com with SMTP id 196so383047pfz.8 for ; Wed, 28 Aug 2019 12:05:47 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0UvFhmNUqeBm7S5PhfAWHzrVJNihnGpoWwY5zvTyQDs=; b=EuZDt+IatzaWgfhJhmSkmKy0ATcSDm4jLpqyZEuVA3aDJrnwSPtsHRHq4FuMGhpYDk Y+IEWriZzphYgE8T30UOQt5hUQbyG8Bx5/1EEXSGcq3oI75Bg+gmcYxV4d/qa83A4o/G ZcMEzr3YwngwUYoRFDYv0oGhPTAUzz4DOCXtxXtivxg7fVgQJpp7d7Z3UeL/BhmhkliM hY0VTvoIVf+ZIU21alKPuPsthyP3JUxbIEOzeeI3nb/JOaRA/UENtjqrtYnJ8DwT/odq 6TRvAc9Y3jIHE46XR5Aw9o1crMpUy1ADkHZVTZwqgZ8z+FssHm1pXJqgtXYa5DqFyrAI PmVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0UvFhmNUqeBm7S5PhfAWHzrVJNihnGpoWwY5zvTyQDs=; b=g2oy7BmG1fT8PEHunm4UyxzvkD0KsqHWgGT+fH/+zoIRbtShO7vvtbgaHUTY3JKEIR d8CWqLQZeqPZD4chAnbVec49aEHq3tc3b+wnjOrtsQ7FBju9vtxGT+145GRsp4TL3qM8 pBfoRiPBeyZPeWElvKXihmzhVTjzqlQDh6JshZY8hmKH/5kFj2EHSp9nycElQsx5EL4N 750V6bXOLLXh6Ueh3Mb/8JVWy81DSdEusZQEKq7PbTZM+NRaMDsrwkhH3FVxPrc52tEC hPi/r6GETanDBYnaLYliAyp3+KLP9aqFY6UgFIaokEEAzA2yglBRsnrKvTFItX2q70Pl 38/Q== X-Gm-Message-State: APjAAAX12IDWf1VYCDp+glaC9hcUhSwrqvy6qkbjT5OcOcMqCslMovlZ xit7ubojShu72KpdHIkXGi42VuWQRDw= X-Google-Smtp-Source: APXvYqwwfmCxA6nxq4geT+4G2n5D36xEhSf6Asbe8O8FHJ4Mf4mgNJsYf9t2LHdkMgdsOlHs67i7HQ== X-Received: by 2002:a17:90a:feb:: with SMTP id 98mr5455811pjz.55.1567019146203; Wed, 28 Aug 2019 12:05:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:23 -0700 Message-Id: <20190828190456.30315-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 36/69] target/arm: Convert CPS (privileged) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Reject for m-profile; add TODO for unpredictable arguments. Sort the T32 decode adjacent to the hint space. --- target/arm/translate.c | 91 ++++++++++++++++-------------------- target/arm/a32-uncond.decode | 3 ++ target/arm/t32.decode | 5 ++ 3 files changed, 48 insertions(+), 51 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 003b8ac414..e8764a88ae 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10122,6 +10122,44 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a) return true; } =20 +static bool trans_CPS(DisasContext *s, arg_CPS *a) +{ + uint32_t mask, val; + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + /* Implemented as NOP in user mode. */ + return true; + } + /* TODO: There are quite a lot of UNPREDICTABLE argument combinations.= */ + + mask =3D val =3D 0; + if (a->imod & 2) { + if (a->A) { + mask |=3D CPSR_A; + } + if (a->I) { + mask |=3D CPSR_I; + } + if (a->F) { + mask |=3D CPSR_F; + } + if (a->imod & 1) { + val |=3D mask; + } + } + if (a->M) { + mask |=3D CPSR_M; + val |=3D a->mode; + } + if (mask) { + gen_set_psr_im(s, mask, 0, val); + } + return true; +} + /* * Clear-Exclusive, Barriers */ @@ -10298,31 +10336,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) ARCH(5TE); } else if ((insn & 0x0f000010) =3D=3D 0x0e000010) { /* Additional coprocessor register transfer. */ - } else if ((insn & 0x0ff10020) =3D=3D 0x01000000) { - uint32_t mask; - uint32_t val; - /* cps (privileged) */ - if (IS_USER(s)) - return; - mask =3D val =3D 0; - if (insn & (1 << 19)) { - if (insn & (1 << 8)) - mask |=3D CPSR_A; - if (insn & (1 << 7)) - mask |=3D CPSR_I; - if (insn & (1 << 6)) - mask |=3D CPSR_F; - if (insn & (1 << 18)) - val |=3D mask; - } - if (insn & (1 << 17)) { - mask |=3D CPSR_M; - val |=3D (insn & 0x1f); - } - if (mask) { - gen_set_psr_im(s, mask, 0, val); - } - return; } goto illegal_op; } @@ -10431,7 +10444,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, ui= nt32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 addr; @@ -10707,31 +10719,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) case 0: /* msr cpsr, in decodetree */ case 1: /* msr spsr, in decodetree */ goto illegal_op; - case 2: /* cps, nop-hint. */ - /* nop hints in decodetree */ - /* Implemented as NOP in user mode. */ - if (IS_USER(s)) - break; - offset =3D 0; - imm =3D 0; - if (insn & (1 << 10)) { - if (insn & (1 << 7)) - offset |=3D CPSR_A; - if (insn & (1 << 6)) - offset |=3D CPSR_I; - if (insn & (1 << 5)) - offset |=3D CPSR_F; - if (insn & (1 << 9)) - imm =3D CPSR_A | CPSR_I | CPSR_F; - } - if (insn & (1 << 8)) { - offset |=3D 0x1f; - imm |=3D (insn & 0x1f); - } - if (offset) { - gen_set_psr_im(s, offset, 0, imm); - } - break; + case 2: /* cps, nop-hint, in decodetree */ + goto illegal_op; case 3: /* Special control operations, in decodetree */ case 4: /* bxj, in decodetree */ goto illegal_op; diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index c7e9df8030..de611e8aff 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -35,9 +35,12 @@ BLX_i 1111 101 . ........................ = &i imm=3D%imm24h =20 &rfe rn w pu &srs mode w pu +&cps mode imod M A I F =20 RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe SRS 1111 100 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs +CPS 1111 0001 0000 imod:2 M:1 0 0000 000 A:1 I:1 F:1 0 mode:5= \ + &cps =20 # Clear-Exclusive, Barriers =20 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 18c268e712..fc3e7db4b5 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -44,6 +44,7 @@ &bfi !extern rd rn lsb msb &sat !extern rd rn satimm imm sh &pkh !extern rd rn rm imm tb +&cps !extern mode imod M A I F =20 # Data-processing (register) =20 @@ -306,6 +307,10 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ..= .. @rdm NOP 1111 0011 1010 1111 1000 0000 ---- ---- } =20 + # If imod =3D=3D '00' && M =3D=3D '0' then SEE "Hint instructions", ab= ove. + CPS 1111 0011 1010 1111 1000 0 imod:2 M:1 A:1 I:1 F:1 mode:5 \ + &cps + # Miscelaneous control { CLREX 1111 0011 1011 1111 1000 1111 0010 1111 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 37/69] target/arm: Convert SETEND X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 22 +++++++++++++--------- target/arm/a32-uncond.decode | 4 ++++ 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index e8764a88ae..f81f369544 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10217,6 +10217,18 @@ static bool trans_SB(DisasContext *s, arg_SB *a) return true; } =20 +static bool trans_SETEND(DisasContext *s, arg_SETEND *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + if (a->E !=3D (s->be_data =3D=3D MO_BE)) { + gen_helper_setend(cpu_env); + s->base.is_jmp =3D DISAS_UPDATE; + } + return true; +} + /* * Legacy decoder. */ @@ -10302,15 +10314,7 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) return; /* v7MP: Unallocated memory hint: must NOP */ } =20 - if ((insn & 0x0ffffdff) =3D=3D 0x01010000) { - ARCH(6); - /* setend */ - if (((insn >> 9) & 1) !=3D !!(s->be_data =3D=3D MO_BE)) { - gen_helper_setend(cpu_env); - s->base.is_jmp =3D DISAS_UPDATE; - } - return; - } else if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { + if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ if (extract32(s->c15_cpar, 1, 1)) { diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index de611e8aff..32253b4f9a 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -24,6 +24,7 @@ =20 &empty !extern &i !extern imm +&setend E =20 # Branch with Link and Exchange =20 @@ -50,3 +51,6 @@ DSB 1111 0101 0111 1111 1111 0000 0100 ---- DMB 1111 0101 0111 1111 1111 0000 0101 ---- ISB 1111 0101 0111 1111 1111 0000 0110 ---- SB 1111 0101 0111 1111 1111 0000 0111 0000 + +# Set Endianness +SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 38/69] target/arm: Convert PLI, PLD, PLDW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 37 +++++++++++++++++++----------------- target/arm/a32-uncond.decode | 10 ++++++++++ 2 files changed, 30 insertions(+), 17 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index f81f369544..c55bd1e563 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10229,6 +10229,26 @@ static bool trans_SETEND(DisasContext *s, arg_SETE= ND *a) return true; } =20 +/* + * Preload instructions + * All are nops, contingent on the appropriate arch level. + */ + +static bool trans_PLD(DisasContext *s, arg_PLD *a) +{ + return ENABLE_ARCH_5TE; +} + +static bool trans_PLDW(DisasContext *s, arg_PLD *a) +{ + return arm_dc_feature(s, ARM_FEATURE_V7MP); +} + +static bool trans_PLI(DisasContext *s, arg_PLD *a) +{ + return ENABLE_ARCH_7; +} + /* * Legacy decoder. */ @@ -10289,23 +10309,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) } return; } - if (((insn & 0x0f30f000) =3D=3D 0x0510f000) || - ((insn & 0x0f30f010) =3D=3D 0x0710f000)) { - if ((insn & (1 << 22)) =3D=3D 0) { - /* PLDW; v7MP */ - if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { - goto illegal_op; - } - } - /* Otherwise PLD; v5TE+ */ - ARCH(5TE); - return; - } - if (((insn & 0x0f70f000) =3D=3D 0x0450f000) || - ((insn & 0x0f70f010) =3D=3D 0x0650f000)) { - ARCH(7); - return; /* PLI; V7 */ - } if (((insn & 0x0f700000) =3D=3D 0x04100000) || ((insn & 0x0f700010) =3D=3D 0x06100000)) { if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 32253b4f9a..ddc5edfa5e 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -54,3 +54,13 @@ SB 1111 0101 0111 1111 1111 0000 0111 0000 =20 # Set Endianness SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend + +# Preload instructions + +PLD 1111 0101 -101 ---- 1111 ---- ---- ---- # (imm, lit) 5= te +PLDW 1111 0101 -001 ---- 1111 ---- ---- ---- # (imm, lit) 7= mp +PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7 + +PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5= te +PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7= mp +PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 39/69] target/arm: Convert Unallocated memory hint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 8 -------- target/arm/a32-uncond.decode | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index c55bd1e563..07547f7b6c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10309,14 +10309,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) } return; } - if (((insn & 0x0f700000) =3D=3D 0x04100000) || - ((insn & 0x0f700010) =3D=3D 0x06100000)) { - if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { - goto illegal_op; - } - return; /* v7MP: Unallocated memory hint: must NOP */ - } - if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index ddc5edfa5e..60ccfc598d 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -64,3 +64,11 @@ PLI 1111 0100 -101 ---- 1111 ---- ---- ----= # (imm, lit) 7 PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5= te PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7= mp PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7 + +# Unallocated memory hints +# +# Since these are v7MP nops, and PLDW is v7MP and implemented as nop, +# (ab)use the PLDW helper. + +PLDW 1111 0100 -001 ---- ---- ---- ---- ---- +PLDW 1111 0110 -001 ---- ---- ---- ---0 ---- --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567022199; cv=none; d=zoho.com; s=zohoarc; b=b98naFFL2yCVy8z74FXuJeXN7zJs8Dr3CFdDXC16t0i0SmxAQS7o7MjSPBjRpUFtz7XCfXN6gIVxUKJi9sUAThxwYjwHvG6rG0wnvWZKn97Ziy4HEf1+1cGq34a39G3OmWifY9iTDw6RNg4nsIuLqorhVla8zePQldtoqukhJr4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567022199; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=wIySDhGsNWmiBe1mxSZk+IQzzrYDWNTA5+8A0wQT8Vc=; b=IkM51FkzuiNzn0ikX38+/0iWh8Z6IbuHpycjK2ytLs+vGFQW/zeUHibfOJXc6aW3eSVGbzOU/kgNU0KPkkKhCDCDGziQm/wG2eVvKVGLNvCmefVc8C/1Pi45QuHJGExQA3mN5xclz06Uclcp9vIIKV/OoSyrgvJ0COlcKiwEpGk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567022199758126.85317681983372; Wed, 28 Aug 2019 12:56:39 -0700 (PDT) Received: from localhost ([::1]:41804 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i343a-0004EF-50 for importer@patchew.org; Wed, 28 Aug 2019 15:56:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38371) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33GX-0003q4-Su for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33GT-0000Pl-B9 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:57 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:41791) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33GS-0000O4-Ty for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:53 -0400 Received: by mail-pl1-x62a.google.com with SMTP id m9so391048pls.8 for ; Wed, 28 Aug 2019 12:05:52 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wIySDhGsNWmiBe1mxSZk+IQzzrYDWNTA5+8A0wQT8Vc=; b=gPvYayY6eKCqOn1gIybOGYzSOEUhbEcFWyeUhcQZbLA642f4bJp+or/HNpe7+CtDU4 3hFuNxEwK4dBV5dGADHN3A1UaUzM39Nzj7Clks0DDebgqp55KrjA0QWWw9MleF2Nn5w4 CoFkfm4bEVE2HUCY5tgQslImqmLPADbpRHyA22oVmn0gmurk6OWGCjypi6UQctrfucVx zzRAeoaMGD0uSaaVCOO4dhyeNb8KhIRR+OIfJQ5THnsayQSRcU8oEd17DTcfbDSuuJkV IArw2QXR5zVGBB8bhKvftz1HA51OHWMySBpIxyLLG09/BnCV+YjwjNRlcuZNDOJVhPP2 ADvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wIySDhGsNWmiBe1mxSZk+IQzzrYDWNTA5+8A0wQT8Vc=; b=uW+uK1AB3toU7tfAEkhH3p+9ccje2L1vzqgyeOO3w5+wYK/hIk+4e2BmCe7igFYpCg yoRv466i8wDGlCjA83hEQXSDMNPHC+Xq/2oqxCEu9dWE23SHYjstqpMZDHq2NFzHGy5B cBbi8OKeK8O8UoJzy6eFHySUfor0gsFZyq4UOLRd/f03UT8or+1E1iC9RBCtGAHl3pY0 LU4keJYF9vtq9Ry+Iejr71aqABBy1lpBD0FI5pTrNLxTKtN1vHH15RfAaIIPM0/0SuDO eJphcDiohn6T09aRearb494cwbLUcikY1Zq9A3M0+yiyVAFKt7PC1UcMjOYKs2LfrKtN uLiQ== X-Gm-Message-State: APjAAAVmFTwY+yh2LgQdRFJQkawelQ5L3ZdYoenLackLXvSZCFe8Zmrr NVuAcBl7M+IP0Jf4Iu21KemvDHlVUW8= X-Google-Smtp-Source: APXvYqxOmyFGoVS9V2iHqUTNS0j7hwi3U1d+yhbe5D/h6E4WhqDAdalSYFnab0kKJ3g2578fDjskrw== X-Received: by 2002:a17:902:ff02:: with SMTP id f2mr5392599plj.99.1567019151318; Wed, 28 Aug 2019 12:05:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:27 -0700 Message-Id: <20190828190456.30315-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62a Subject: [Qemu-devel] [PATCH v3 40/69] target/arm: Convert Table Branch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 57 +++++++++++++++++++++++++----------------- target/arm/t32.decode | 8 +++++- 2 files changed, 41 insertions(+), 24 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 07547f7b6c..92b3a66e05 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10048,6 +10048,37 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i= *a) return true; } =20 +static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) +{ + TCGv_i32 addr, tmp; + + tmp =3D load_reg(s, a->rm); + if (half) { + tcg_gen_add_i32(tmp, tmp, tmp); + } + addr =3D load_reg(s, a->rn); + tcg_gen_add_i32(addr, addr, tmp); + + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), + half ? MO_UW | s->be_data : MO_UB); + tcg_temp_free_i32(addr); + + tcg_gen_add_i32(tmp, tmp, tmp); + tcg_gen_addi_i32(tmp, tmp, read_pc(s)); + store_reg(s, 15, tmp); + return true; +} + +static bool trans_TBB(DisasContext *s, arg_tbranch *a) +{ + return op_tbranch(s, a, false); +} + +static bool trans_TBH(DisasContext *s, arg_tbranch *a) +{ + return op_tbranch(s, a, true); +} + /* * Supervisor call */ @@ -10443,9 +10474,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, ui= nt32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rm, rs; - TCGv_i32 tmp; - TCGv_i32 addr; + uint32_t rd, rn, rs; int op; =20 /* @@ -10491,7 +10520,6 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) rn =3D (insn >> 16) & 0xf; rs =3D (insn >> 12) & 0xf; rd =3D (insn >> 8) & 0xf; - rm =3D insn & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ @@ -10564,25 +10592,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) /* Load/store exclusive, in decodetree */ goto illegal_op; } else if ((insn & (7 << 5)) =3D=3D 0) { - /* Table Branch. */ - addr =3D load_reg(s, rn); - tmp =3D load_reg(s, rm); - tcg_gen_add_i32(addr, addr, tmp); - if (insn & (1 << 4)) { - /* tbh */ - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); - } else { /* tbb */ - tcg_temp_free_i32(tmp); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); - } - tcg_temp_free_i32(addr); - tcg_gen_shli_i32(tmp, tmp, 1); - tcg_gen_addi_i32(tmp, tmp, read_pc(s)); - store_reg(s, 15, tmp); + /* Table Branch, in decodetree */ + goto illegal_op; } else { /* Load/store exclusive, load-acq/store-rel, in decodetree= */ goto illegal_op; diff --git a/target/arm/t32.decode b/target/arm/t32.decode index fc3e7db4b5..24482e0eeb 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -489,7 +489,7 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... ........= @ldstd_ri8 w=3D0 p=3D1 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 =20 -# Load/Store Exclusive and Load-Acquire/Store-Release +# Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch =20 @strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \ &strex rt2=3D15 imm=3D%imm8x4 @@ -533,6 +533,12 @@ LDA 1110 1000 1101 .... .... 1111 1010 11= 11 @ldrex_0 LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 =20 +&tbranch rn rm +@tbranch .... .... .... rn:4 .... .... .... rm:4 &tbranch + +TBB 1110 1000 1101 .... 1111 0000 0000 .... @tbranch +TBH 1110 1000 1101 .... 1111 0000 0001 .... @tbranch + # Parallel addition and subtraction =20 SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567021851; cv=none; d=zoho.com; s=zohoarc; b=ibd3TCYC6YVMC2ak/mSyk/6grzHwy02w7ZT46RjkNE1rkvNfYXHcxJQyHSmZY9kzlncRP2pc/mTfKcYeapK6i6nIZYwgeWL4pESPdnDnrHQyuB4PXmSLMd/JRRF5/ST6Ilnd6rr8R9UfWTuDx0FUpTJ1FF8M2xvzCszP+Ft1DPI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567021851; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ENB9E1VePGgEvpljqAX8EyWULibUwHF2u0OAo21pbuU=; b=CCKgW9gk85tqbheP/Gq9Iz21JhJW3GY9yKRkqkpmCMv5g/tNuy3YhHrdf2CmclVN3uWVJSt2ki4VlsPEnefY1dN5RfPXGiWNIDOrn6Zf8LEdEMBJH2HOBs0pqZWXCmZV0xm7Rq3xbZIs4R3vojaQ76R8EX/oipmKM/zjv5LQMHo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567021851112194.3208450894317; Wed, 28 Aug 2019 12:50:51 -0700 (PDT) Received: from localhost ([::1]:41668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33xr-00054i-2x for importer@patchew.org; Wed, 28 Aug 2019 15:50:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38368) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33GX-0003q2-RJ for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33GU-0000Q7-4P for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:57 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:37137) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33GT-0000Ps-Ux for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:54 -0400 Received: by mail-pl1-x643.google.com with SMTP id bj8so402909plb.4 for ; Wed, 28 Aug 2019 12:05:53 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ENB9E1VePGgEvpljqAX8EyWULibUwHF2u0OAo21pbuU=; b=DO6gaC//GIpneYcXV+mDdDit5od2Vlkcx53NuOuHBPR4okk6WvHoj5+PfDKc7Ems7d Q7eCVQ6l4Bi/TDsbXOchcucDrNf7V5PTS5wO45ulcaM8INtUyclH3XnO+SkT24Sn3bwU nZv0ObJWh0G4l8czS5jdNmSxAcwl2Qf4gRdEeTzOFBQJrcsuGCY0IT+Yo4KRm8VS/3Iq cVZ0KoWOVYvnJpVWLUbpqzqCbRCLAq0Lc9LlKH0AkyeKJuJ5U0nm+3TBS3dIOASyB6d7 4xgYcN3OY5JGZclRkWwPphnc9Ma7QUcRkICGWGjDGKqmio5cHlBmpQqxqkc9JzmTB4lJ 02+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ENB9E1VePGgEvpljqAX8EyWULibUwHF2u0OAo21pbuU=; b=Vp68NeJ3F9J3O0v97HWuwqYJZHPDAufWuyLanHowLmjCscuy2GQM9aVVl5zihkmgi1 Q2/DPl2rIrHN0ZGQefL95Bky6HEq3btK+OQ97pGI17wz66bxZ69ZFrN/j9EVwoU4FThb tr5sNE/Wtr4PSK+Kjzw5QUSWvfMod5sGXUkOHIpMnap7R33pItblpzxjwcTqcG25ZO/L HEnA97p4V8QGGLoU2HGMJmLkt8/HBqdlEsmvBgRlqiTf4rwnNlQHsjF9WbsZF6y4sdSe QLRmJWZYXXTkeU3ZkJTVbOUYWJRT23D88Ch3BBi+rYRtdd95bVf8IRawZxgkm1klFvUX xqbg== X-Gm-Message-State: APjAAAUnlsfWn4jh7URSv3jDiBjgzcJfTDWGnFHL9F9eqw7p/VEkLnH7 caby6zc1egnHcpfx+OJuWOCQEO8Uf0Q= X-Google-Smtp-Source: APXvYqwrtBIVAgI+JViajIuxpLiNxc3HcEIRWKHeFLBKE3VA+tFuhbgq1i9MB0jNovELoHS9euI6QQ== X-Received: by 2002:a17:902:24c:: with SMTP id 70mr5709334plc.331.1567019152568; Wed, 28 Aug 2019 12:05:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:28 -0700 Message-Id: <20190828190456.30315-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 41/69] target/arm: Convert SG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 51 ++++++++++++++++++++++++------------------ target/arm/t32.decode | 5 ++++- 2 files changed, 33 insertions(+), 23 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 92b3a66e05..52da7f4fa8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8441,6 +8441,34 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a) return true; } =20 +static bool trans_SG(DisasContext *s, arg_SG *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + /* + * SG (v8M only) + * The bulk of the behaviour for this instruction is implemented + * in v7m_handle_execute_nsc(), which deals with the insn when + * it is executed by a CPU in non-secure state from memory + * which is Secure & NonSecure-Callable. + * Here we only need to handle the remaining cases: + * * in NS memory (including the "security extension not + * implemented" case) : NOP + * * in S memory but CPU already secure (clear IT bits) + * We know that the attribute for the memory this insn is + * in must match the current CPU state, because otherwise + * get_phys_addr_pmsav8 would have generated an exception. + */ + if (s->v8m_secure) { + /* Like the IT insn, we don't need to generate any code */ + s->condexec_cond =3D 0; + s->condexec_mask =3D 0; + } + return true; +} + /* * Load/store register index */ @@ -10530,28 +10558,7 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) * - load/store doubleword, load/store exclusive, ldacq/strel, * table branch, TT. */ - if (insn =3D=3D 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M)= && - arm_dc_feature(s, ARM_FEATURE_V8)) { - /* 0b1110_1001_0111_1111_1110_1001_0111_111 - * - SG (v8M only) - * The bulk of the behaviour for this instruction is imple= mented - * in v7m_handle_execute_nsc(), which deals with the insn = when - * it is executed by a CPU in non-secure state from memory - * which is Secure & NonSecure-Callable. - * Here we only need to handle the remaining cases: - * * in NS memory (including the "security extension not - * implemented" case) : NOP - * * in S memory but CPU already secure (clear IT bits) - * We know that the attribute for the memory this insn is - * in must match the current CPU state, because otherwise - * get_phys_addr_pmsav8 would have generated an exception. - */ - if (s->v8m_secure) { - /* Like the IT insn, we don't need to generate any cod= e */ - s->condexec_cond =3D 0; - s->condexec_mask =3D 0; - } - } else if (insn & 0x01200000) { + if (insn & 0x01200000) { /* load/store dual, in decodetree */ goto illegal_op; } else if ((insn & (1 << 23)) =3D=3D 0) { diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 24482e0eeb..2b30a767fe 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -487,7 +487,10 @@ STRD_ri_t32 1110 1001 .100 .... .... .... .......= . @ldstd_ri8 w=3D0 p=3D1 LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=3D= 0 p=3D1 =20 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 -LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 +{ + SG 1110 1001 0111 1111 1110 1001 01111111 + LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 +} =20 # Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch =20 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zQWrs3An1QMtHJ2W4jZK3gQeIav2dkJ4+fToZUQZoOI=; b=n14kUCs+FUs+v/ojGQSd9viKzyRP0l4QSRqB7VdWfADDg72eGCU208XWqaxAEbHJ0H vt6B+McnL+dTc3mNfnz3U4+tE7vaw3eZehQ1TaFpRxpiGSrXKjjKu3hKej45m8rRK7TW B4/2fA8DQocP1raSSEGf50CQvopECXY98veLUCMZX74rCR165+N4nJlTUUD0kalJ3Gdj O5rQ+8twwfMKmN3oWbQXvml1fesmGYAuA3NnYepsJnzRirKOLBGgD//FYPUDxjnf7UOW rqw24FNEKngam1Yxg/K3MmFsKjsULZH63uqHb1eoqSPfD8TcOjGxraqinu+5iZFv2QCl x/hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zQWrs3An1QMtHJ2W4jZK3gQeIav2dkJ4+fToZUQZoOI=; b=qWE5HaSBWQ4cc5eZ7SDhnYluJ8Hw/md2W2k0QN3jjtHPkQTtT2r4gM2l8LrlzYdJme JAcGQvi6wNm1Jvzq7XCPyz84usy+wzEjWA8ozCxqb2CE4amnWLfzdJzCnNCoR7bIvqDp Dns5gCBZSQC6fmHix4J1Cpe31Zf35SAvkt85QIBH0meR+DbD++V//dr+u6RqmzUDaX3N Rrm6A+AKiTr9Ypi3sNyGRIUKdCxRfe9cAWhiqhnEEy7MlsRod3AKwXJjAq2uAvbQL2Au nyy96k7Ia+pBU4EtG6UqwsAKP4bH6Hsj+OEqpJMDQty/pC/JpdYCyql/L2Fo3Aqc7hzY MQfQ== X-Gm-Message-State: APjAAAXO5L93Z0aM2S3PMJ4jyI0QaYHpB0LwTtDylWOnKlit6/DGOEKM ocL7SQvQDIqCRHr2GHFdUYjehhojx+w= X-Google-Smtp-Source: APXvYqwXe0tlIrcFsVQ0CUF2UIRASjs+8DOnlGzAkYJTfytVqtYGppulOzPdSHaTq0dm3qRSl3DhOA== X-Received: by 2002:a17:902:8649:: with SMTP id y9mr5448781plt.252.1567019153746; Wed, 28 Aug 2019 12:05:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:29 -0700 Message-Id: <20190828190456.30315-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 42/69] target/arm: Convert TT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding. --- target/arm/translate.c | 90 ++++++++++++++---------------------------- target/arm/t32.decode | 5 ++- 2 files changed, 34 insertions(+), 61 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 52da7f4fa8..05aa998640 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8469,6 +8469,33 @@ static bool trans_SG(DisasContext *s, arg_SG *a) return true; } =20 +static bool trans_TT(DisasContext *s, arg_TT *a) +{ + TCGv_i32 addr, tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + if (a->rd =3D=3D 13 || a->rd =3D=3D 15 || a->rn =3D=3D 15) { + /* We UNDEF for these UNPREDICTABLE cases */ + unallocated_encoding(s); + return true; + } + if (a->A && !s->v8m_secure) { + /* This case is UNDEFINED. */ + unallocated_encoding(s); + return true; + } + + addr =3D load_reg(s, a->rn); + tmp =3D tcg_const_i32((a->A << 1) | a->T); + gen_helper_v7m_tt(tmp, cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + store_reg(s, a->rd, tmp); + return true; +} + /* * Load/store register index */ @@ -10502,7 +10529,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, ui= nt32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rs; + uint32_t rn; int op; =20 /* @@ -10546,70 +10573,13 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) /* fall back to legacy decoder */ =20 rn =3D (insn >> 16) & 0xf; - rs =3D (insn >> 12) & 0xf; - rd =3D (insn >> 8) & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ abort(); case 4: - if (insn & (1 << 22)) { - /* 0b1110_100x_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store doubleword, load/store exclusive, ldacq/strel, - * table branch, TT. - */ - if (insn & 0x01200000) { - /* load/store dual, in decodetree */ - goto illegal_op; - } else if ((insn & (1 << 23)) =3D=3D 0) { - /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store exclusive word - * - TT (v8M only) - */ - if (rs =3D=3D 15) { - if (!(insn & (1 << 20)) && - arm_dc_feature(s, ARM_FEATURE_M) && - arm_dc_feature(s, ARM_FEATURE_V8)) { - /* 0b1110_1000_0100_xxxx_1111_xxxx_xxxx_xxxx - * - TT (v8M only) - */ - bool alt =3D insn & (1 << 7); - TCGv_i32 addr, op, ttresp; - - if ((insn & 0x3f) || rd =3D=3D 13 || rd =3D=3D 15 = || rn =3D=3D 15) { - /* we UNDEF for these UNPREDICTABLE cases */ - goto illegal_op; - } - - if (alt && !s->v8m_secure) { - goto illegal_op; - } - - addr =3D load_reg(s, rn); - op =3D tcg_const_i32(extract32(insn, 6, 2)); - ttresp =3D tcg_temp_new_i32(); - gen_helper_v7m_tt(ttresp, cpu_env, addr, op); - tcg_temp_free_i32(addr); - tcg_temp_free_i32(op); - store_reg(s, rd, ttresp); - break; - } - goto illegal_op; - } - /* Load/store exclusive, in decodetree */ - goto illegal_op; - } else if ((insn & (7 << 5)) =3D=3D 0) { - /* Table Branch, in decodetree */ - goto illegal_op; - } else { - /* Load/store exclusive, load-acq/store-rel, in decodetree= */ - goto illegal_op; - } - } else { - /* Load/store multiple, RFE, SRS, in decodetree */ - goto illegal_op; - } - break; + /* All in decodetree */ + goto illegal_op; case 5: /* All in decodetree */ goto illegal_op; diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 2b30a767fe..91ba4ca7ae 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -508,7 +508,10 @@ STRD_ri_t32 1110 1001 .110 .... .... .... .......= . @ldstd_ri8 w=3D1 p=3D1 @ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \ &ldrex imm=3D0 =20 -STREX 1110 1000 0100 .... .... .... .... .... @strex_i +{ + TT 1110 1000 0100 rn:4 1111 rd:4 A:1 T:1 000000 + STREX 1110 1000 0100 .... .... .... .... .... @strex_i +} STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0 STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0 STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567021097; cv=none; d=zoho.com; s=zohoarc; b=nR15BpAHOXBL8JCNKmc1ic89uYd5epXjZSiVf1R7/EX/9P4SFMZRdnxoHcUO2tBL6Jzge1g2GdCLjs0dWQH7oZQXbi7BoYWxQHowB0Imeu+T1jTS/dCMrgrfyyk2UkGHsfhSpq+y6r8OOpiD71IPG0PAr0yYl6eDUEvUNrLfefI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567021097; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=lWF0DHMsOHSMFqAdjC4WeFAcJm0Twlq0AR5wryvISQ8=; b=jhvUp0/pDTZgYSEkPX6id3j59Q++eNlsQUf+NtSLNNLg53TuKE9FRU0o/E2cp0A+GYD+4ZeIXu0aKNidrPlsUC1L9DCyC2vfUyCiU6niGFd8ANY8tmP6Bus8YCcVMRx8ZKbCq37q25WZIfLMIeYHmK7dFvr814uZx3yvid53t28= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567021097141980.7079047230221; Wed, 28 Aug 2019 12:38:17 -0700 (PDT) Received: from localhost ([::1]:41436 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33ln-0001EI-Nb for importer@patchew.org; Wed, 28 Aug 2019 15:38:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38434) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Ga-0003qD-27 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33GX-0000TX-VL for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:59 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:38455) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33GX-0000Rz-E9 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:57 -0400 Received: by mail-pf1-x443.google.com with SMTP id o70so392945pfg.5 for ; Wed, 28 Aug 2019 12:05:56 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lWF0DHMsOHSMFqAdjC4WeFAcJm0Twlq0AR5wryvISQ8=; b=TACIcgiX8ImKdL0b8tY2JoEJzHK0lg+9uAjWlVwaPBAeXmuQyscMD5mM4ZUbbnOCEv 0/2a3A7LVSR4VBS8myVaf+ovAlMNjmdMxsufDQaSgTP35iASkBeAfE1s6CebkGHrdc6E q7jVAmarN7VdchWl3MTAbmo635kD+m2YTfJalfliyFVpw7Q6hH4K1BC0GFiSj5kWK782 N1eDCoCDWfbyls2Kh4sPJzx+PIW5tuSzAHwPTS3FLeGfmdUoQRtKtTBYGTmFYLdciQEY IMHhEO0cOzE9y20vfeNhoQnupAOrzaqmZpJL3fW6VVKiUErXY0Q+0TSLIYCn/Wy3vFwE E69A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lWF0DHMsOHSMFqAdjC4WeFAcJm0Twlq0AR5wryvISQ8=; b=e6XZnckBsJOnV3oFHhkjZP+C/NtyK1EgcrqkFjwuuloHytbyznfZTSF2sdPzBrCHrH g6OW3p1ZWOx+2NJyZUQ8EnaA1R3Sl69/Q0mIM7yg5QEiVVoh70CGsW9j25gvbRvbvut3 ArwqPcrDLWI9cYK8i5iJ9aCayEjMNLqZp65WuJ/WyZVgg5psb4jrWrGbb+qVfVM1H0Em tS91fTcisxuB5TzzwE0QOxX3VYRyTFwACJ4bdjearYPQxJA87B499oaQpbiYV7g4Ymqw tcCukTqxISYuFascR3hUDGtvsNeMyClYOIHOd1KdUZEUEBbdTb0a1MGlqXMB+KBgO8Yk sX5g== X-Gm-Message-State: APjAAAXr9nmgLR1dWjn13LB+M0eCFz9V/0ZQIyi9ACxFp8N4Xt8U1jmQ HyoAsz+X5olKBP4n5sM+XvhrK9uWark= X-Google-Smtp-Source: APXvYqx8L8Vjv4/Ex6OMFq4J9ZUTar0F2mn7Oe3el1vdS8F7IRgDDWYmJiEIh7aN9gopOu+/vcVhiw== X-Received: by 2002:a63:f048:: with SMTP id s8mr4721869pgj.26.1567019154922; Wed, 28 Aug 2019 12:05:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:30 -0700 Message-Id: <20190828190456.30315-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 43/69] target/arm: Simplify disas_thumb2_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fold away all of the cases that now just goto illegal_op, because all of their internal bits are now in decodetree. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 79 ++---------------------------------------- 1 file changed, 3 insertions(+), 76 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 05aa998640..5bb1d13a3d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10529,9 +10529,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, ui= nt32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rn; - int op; - /* * ARMv6-M supports a limited subset of Thumb2 instructions. * Other Thumb1 architectures allow only 32-bit @@ -10572,34 +10569,10 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) } /* fall back to legacy decoder */ =20 - rn =3D (insn >> 16) & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ abort(); - case 4: - /* All in decodetree */ - goto illegal_op; - case 5: - /* All in decodetree */ - goto illegal_op; - case 13: /* Misc data processing. */ - op =3D ((insn >> 22) & 6) | ((insn >> 7) & 1); - if (op < 4 && (insn & 0xf000) !=3D 0xf000) - goto illegal_op; - switch (op) { - case 0: /* Register controlled shift, in decodetree */ - case 1: /* Sign/zero extend, in decodetree */ - case 2: /* SIMD add/subtract, in decodetree */ - case 3: /* Other data processing, in decodetree */ - goto illegal_op; - case 4: case 5: - /* 32-bit multiply. Sum of absolute differences, in decodetre= e */ - goto illegal_op; - case 6: case 7: /* 64-bit multiply, Divide, in decodetree */ - goto illegal_op; - } - break; case 6: case 7: case 14: case 15: /* Coprocessor. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { @@ -10628,6 +10601,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) } =20 if (arm_dc_feature(s, ARM_FEATURE_VFP)) { + uint32_t rn =3D (insn >> 16) & 0xf; TCGv_i32 fptr =3D load_reg(s, rn); =20 if (extract32(insn, 20, 1)) { @@ -10686,50 +10660,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } } break; - case 8: case 9: case 10: case 11: - if (insn & (1 << 15)) { - /* Branches, misc control. */ - if (insn & 0x5000) { - /* Unconditional branch, in decodetree */ - goto illegal_op; - } else if (((insn >> 23) & 7) =3D=3D 7) { - /* Misc control */ - if (insn & (1 << 13)) - goto illegal_op; - - if (insn & (1 << 26)) { - /* hvc, smc, in decodetree */ - goto illegal_op; - } else { - op =3D (insn >> 20) & 7; - switch (op) { - case 0: /* msr cpsr, in decodetree */ - case 1: /* msr spsr, in decodetree */ - goto illegal_op; - case 2: /* cps, nop-hint, in decodetree */ - goto illegal_op; - case 3: /* Special control operations, in decodetree */ - case 4: /* bxj, in decodetree */ - goto illegal_op; - case 5: /* Exception return. */ - case 6: /* MRS, in decodetree */ - case 7: /* MSR, in decodetree */ - goto illegal_op; - } - } - } else { - /* Conditional branch, in decodetree */ - goto illegal_op; - } - } else { - /* - * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx - * - Data-processing (modified immediate, plain binary immedi= ate) - * All in decodetree. - */ - goto illegal_op; - } - break; case 12: if ((insn & 0x01100000) =3D=3D 0x01000000) { if (disas_neon_ls_insn(s, insn)) { @@ -10737,14 +10667,11 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) } break; } - /* Load/store single data item, in decodetree */ goto illegal_op; default: - goto illegal_op; + illegal_op: + unallocated_encoding(s); } - return; -illegal_op: - unallocated_encoding(s); } =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567021339; cv=none; d=zoho.com; s=zohoarc; b=MtgQnlBPToCpBV+XVw1tDr8hQ6IQ1xSvD1KuUx+ZSQKfRAYsKe26V1iHhUaTuWdYb+vszROPN091pxQtS1wm8zqTALVugCC2fbgFkJsX7Xx51R1daMogbTmL4cKN6gVO2J+KHy0mzsI9szMWMMkq+6KgSlyJtNGT10lX+zveues= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567021339; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=KXE4hVmZacLzuX33iQjpmlKGdB6TuKckRZ/72v9bQQk=; b=OQKKcmXFrRY2uDgOX0oHNPLBDILDSjfuY0GtSVfSxy9yBa8+1tzvuOxgC/eOD0OXglPly5uN38GXruqy0W05wNuc5s6jjlvo2PDJr6SGETJRx1H6ow5M4PiPol12k54mATxVExOQRHl6NqtCpz0jp/jTo2t1DG73XoFu7GvhiqU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156702133911481.4390399401342; Wed, 28 Aug 2019 12:42:19 -0700 (PDT) Received: from localhost ([::1]:41500 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33ph-0004q9-Dl for importer@patchew.org; Wed, 28 Aug 2019 15:42:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38462) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Ga-0003qI-UF for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33GY-0000U2-9h for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:00 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:38456) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33GX-0000SS-Rx for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:58 -0400 Received: by mail-pf1-x444.google.com with SMTP id o70so392977pfg.5 for ; Wed, 28 Aug 2019 12:05:57 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KXE4hVmZacLzuX33iQjpmlKGdB6TuKckRZ/72v9bQQk=; b=aZgHwgh+b1xKZZtQAGid0XF1L78eoFZxH2DTxeTOIsYWoJP2Y0opJz/1ZYDqzw78Jz nAEOvqRuJm+03kz1scei3OiHgYQrIYetucMk1sNcgyqsWOKSJUzdcKAsecDOXBlhnion ettg6m91Ugt1fPOPck2h1RPCAALyTpkEV+5cdfUFzykq2aM9bXrhn6oYUNFYHrS0MPXS qd6hSbuo0FFYtP6HW2ocz6pfGqpstxmvVCyOK0Hp64EBiI8c1cZm+JpWdlGUCkmGEW+S h8uF7Q+bgraJcDcpbhBuLzKEGCcdZPPXJMO834wUOoSRpAaLjP70uwjPe4LUw5CfpNu7 aa3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KXE4hVmZacLzuX33iQjpmlKGdB6TuKckRZ/72v9bQQk=; b=GiP1ZSOsGvXV9ZLd0F5JNdxiYsgss/9Ov+HlSQCn/tIcHExPT7JNjSD2B0YpsTPpTB Cca7/Efg3ztF+WFQFb6A8jX6iI1fkjRKTAwwUIr/YzyT7y9E1AAeeo7l9Q9USuAiTqvi oInkoZiypa1G6iaKzhewJsrN9p/R/L77u8tXNumJhor4iHANxEGMppQWlhrILO+SzSJF CInSGroV/CbQH1aWZB9g6RZ7OvjfxwKp8dwjQ5eqGuw6pmlqM2Yupn4XVr1byliEZ6Vt OFO0QprnEifcILCVzMS3XcyqvxzDqMOJ1yonkC2n7v+vz+bX8DKbdRAVcqZXjBacnnIy YaKA== X-Gm-Message-State: APjAAAWg+44MRTwoWkQXtSbd+vx1vw4eWiaJW7Wxv5kcypb7iZrBgn0a Dsz8y1itoIvFnNbP5dAAyngyUXN9ci0= X-Google-Smtp-Source: APXvYqwn1bfRjNrpkAJArOeHbpgYgvViSdiUyreUxGNpm2zdvqSG7IlxwGFSygl+NebHGRJBrq/OYg== X-Received: by 2002:aa7:9516:: with SMTP id b22mr6494250pfp.106.1567019156208; Wed, 28 Aug 2019 12:05:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:31 -0700 Message-Id: <20190828190456.30315-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 44/69] target/arm: Simplify disas_arm_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fold away all of the cases that now just goto illegal_op, because all of their internal bits are now in decodetree. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 69 ++++++++++-------------------------------- 1 file changed, 16 insertions(+), 53 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5bb1d13a3d..defbcf68db 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10341,7 +10341,7 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a) =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, op1; + unsigned int cond =3D insn >> 28; =20 /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -10351,7 +10351,6 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) default_exception_el(s)); return; } - cond =3D insn >> 28; =20 if (cond =3D=3D 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we @@ -10416,11 +10415,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) goto illegal_op; } return; - } else if ((insn & 0x0fe00000) =3D=3D 0x0c400000) { - /* Coprocessor double register transfer. */ - ARCH(5TE); - } else if ((insn & 0x0f000010) =3D=3D 0x0e000010) { - /* Additional coprocessor register transfer. */ } goto illegal_op; } @@ -10435,55 +10429,24 @@ static void disas_arm_insn(DisasContext *s, unsig= ned int insn) } /* fall back to legacy decoder */ =20 - if ((insn & 0x0f900000) =3D=3D 0x03000000) { - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - } else if ((insn & 0x0f900000) =3D=3D 0x01000000 - && (insn & 0x00000090) !=3D 0x00000090) { - /* miscellaneous instructions */ - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - } else if (((insn & 0x0e000000) =3D=3D 0 && - (insn & 0x00000090) !=3D 0x90) || - ((insn & 0x0e000000) =3D=3D (1 << 25))) { - /* Data-processing (reg, reg-shift-reg, imm). */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - /* other instructions */ - op1 =3D (insn >> 24) & 0xf; - switch(op1) { - case 0x0: - case 0x1: - case 0x4: - case 0x5: - case 0x6: - case 0x7: - case 0x08: - case 0x09: - case 0xa: - case 0xb: - case 0xf: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - case 0xc: - case 0xd: - case 0xe: - if (((insn >> 8) & 0xe) =3D=3D 10) { - /* VFP. */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - } else if (disas_coproc_insn(s, insn)) { - /* Coprocessor. */ + switch ((insn >> 24) & 0xf) { + case 0xc: + case 0xd: + case 0xe: + if (((insn >> 8) & 0xe) =3D=3D 10) { + /* VFP. */ + if (disas_vfp_insn(s, insn)) { goto illegal_op; } - break; - default: - illegal_op: - unallocated_encoding(s); - break; + } else if (disas_coproc_insn(s, insn)) { + /* Coprocessor. */ + goto illegal_op; } + break; + default: + illegal_op: + unallocated_encoding(s); + break; } } =20 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567022328; cv=none; d=zoho.com; s=zohoarc; b=b4/bA6A2R5AdAkdUSjSHndrmNwGOyuMRTLXmihtO6KO55Un7YaIzPnFyn359X/3xwSbK3b4bPajtVUkFqxrIMWpdSTsF+pDLMixAEJ8P0rnfW1L4zMGirLLeVvBKw2COSBXGkC9SUrNrb0OUrj4vhj566VpU1lytQ5c5dehDviA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567022328; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=0SMzf99NHPKkTWoLRfHeddqKK5zZsCfVSTziSkomW74=; b=YhIyP5zS71b9Iv1qSZvKFd7ij+ScjFGpmSKqt1zwv6KPPC8NnkFJbXEJlnwE+CFVTDEW/qLpEr0LRgz0JPjPo/57p4jvmgh3WKU15Bo+rL3XyE5s+V8GTHTxxeh5COHQ5uBT/MgIEZXVxww8WIlBe7hAzrn2JDlIkvq4PwY4oLM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567022328611203.65757157032033; Wed, 28 Aug 2019 12:58:48 -0700 (PDT) Received: from localhost ([::1]:41852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i345Z-0006c8-Qj for importer@patchew.org; Wed, 28 Aug 2019 15:58:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38498) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Gd-0003rT-R4 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33GZ-0000Uc-9j for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:01 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:39732) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33GY-0000Ty-Sb for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:05:59 -0400 Received: by mail-pg1-x541.google.com with SMTP id u17so220173pgi.6 for ; Wed, 28 Aug 2019 12:05:58 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0SMzf99NHPKkTWoLRfHeddqKK5zZsCfVSTziSkomW74=; b=o9athz1cN8z7ysn/AeMY5z5p05i0NYludTqS5KfjUvY/ksbmAKVtnkPO+dMxoC8BkN 54pGppMXIu8Gac8IRrN5YF+puPLOEQCOOFxJsPHt/9Qc3jGGqQOxPRWeqTpasKgTeV9x xehdyziK1ZaTSCtkXloiJ/RmFbXAHGP01PGS5IlGEYFKOi8GiVLLCtaQ1TVjz/yr522l np7FI2oXUPspoZXrhpVwNJi5XIfWZunr8LAmXrPpDR0g0PyGpJYYd1nAZNq5X4KQ2L3B hjaIMCC05Sh/3PL4Y5wWVnJHQOgUkYobvyxyw5ljFBT8mSXtAXSeVXgcq2O8Rnjmgp3Z mAWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0SMzf99NHPKkTWoLRfHeddqKK5zZsCfVSTziSkomW74=; b=qG8nFSCliEtCZambEaXVoQ0olMAAHSWqbGWQ4AXAKN2w89pZHMci7vGWlRhJbKJT59 o3Qp8oLG8ELi0/voNNAq2dWBUVrx+u24+rNBuH6MsEimgNcPy9CqbSY+rgkJzJDixjRX yb3gjxG/vek1mpj8H5YMA+lmKxqOChqPZ20Z1o3bNJYVl0tWFe8GbGvDvOD9YTpOFOU0 v0rEzh6vGddi9vUFcpIZ3/0Wv8SUM0hJUm11UQEqkW/Jep6JsJauq5o8uwuo0mkmi5Ka mXYsfR+q4hvxA6JYuQGCjcCXDWOqaPUrvK6b2GfZQN93KgWorUi+trd5eaIh40KJPXMf feOA== X-Gm-Message-State: APjAAAVmNH88gmi0YHloMNWHVuPlhJk4TGYRuiN+lK7YLU8FpND15f5z DHieCb3WiREQysLBykuspyrQzkZa4rA= X-Google-Smtp-Source: APXvYqzoR15oM1Its0m0jFu81d6wASEy4qOO5mQ8BMnAN3DebyJJQ/rA3gBmbKR6keAhxgva6yimlQ== X-Received: by 2002:a62:b415:: with SMTP id h21mr6525106pfn.198.1567019157501; Wed, 28 Aug 2019 12:05:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:32 -0700 Message-Id: <20190828190456.30315-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 45/69] target/arm: Add skeleton for T16 decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 6 ++++++ target/arm/Makefile.objs | 6 ++++++ target/arm/t16.decode | 20 ++++++++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 target/arm/t16.decode diff --git a/target/arm/translate.c b/target/arm/translate.c index defbcf68db..106ef08ada 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7534,6 +7534,7 @@ static int t32_branch24(DisasContext *s, int x) #include "decode-a32.inc.c" #include "decode-a32-uncond.inc.c" #include "decode-t32.inc.c" +#include "decode-t16.inc.c" =20 /* Helpers to swap operands for reverse-subtract. */ static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) @@ -10646,6 +10647,11 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) TCGv_i32 tmp2; TCGv_i32 addr; =20 + if (disas_t16(s, insn)) { + return; + } + /* fall back to legacy decoder */ + switch (insn >> 12) { case 0: case 1: =20 diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 7806b4dac0..cf26c16f5f 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -43,12 +43,18 @@ target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32= .decode $(DECODETREE) $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ "GEN", $(TARGET_DIR)$@) =20 +target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETRE= E) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c target/arm/translate.o: target/arm/decode-a32.inc.c target/arm/translate.o: target/arm/decode-a32-uncond.inc.c target/arm/translate.o: target/arm/decode-t32.inc.c +target/arm/translate.o: target/arm/decode-t16.inc.c =20 obj-y +=3D tlb_helper.o debug_helper.o obj-y +=3D translate.o op_helper.o diff --git a/target/arm/t16.decode b/target/arm/t16.decode new file mode 100644 index 0000000000..e954f61fe4 --- /dev/null +++ b/target/arm/t16.decode @@ -0,0 +1,20 @@ +# Thumb1 instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567022626; cv=none; d=zoho.com; s=zohoarc; b=G6rJN94sIGp+mHj8vEHJ0THMG/h3F/CfkmKiejFTr8Iap1gP/c3SGdIyi7pZF5pb/fqMSaHt/MwdFh/IYD5aba+GrDlWG7Qq7blwsl4thGqCX4kkj8pJovM9atiqgGhkzbyCJ9PrQ0hnfuiTUOZGIuOJOzU7vzzlMAf/kqpKuXs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567022626; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=t8j2uFjRrAOGYvd6SrvO/WjrxGa54I8yRPsCcXnl5DA=; b=gt8+cqK8Jcw1va1J3uJWuovVasHUXwRHuAkJBfrdRQ8sy79YGghwn9HII2BWDr1JI7KgcBWt7+a9G61rOG7ACQOpUacJ/ZunWe2ute9Yle1oSA02uAXtout6SdV1w3CKzAQSwBnlsYeJRG/xdHJPlZoqbzNg7ewQimYnuljHHMg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567022626789259.1386590235078; Wed, 28 Aug 2019 13:03:46 -0700 (PDT) Received: from localhost ([::1]:41932 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i34AO-0002IQ-OE for importer@patchew.org; Wed, 28 Aug 2019 16:03:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38517) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Ge-0003rl-U7 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33Ga-0000VT-Io for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:03 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:37137) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33Ga-0000Ul-7e for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:00 -0400 Received: by mail-pl1-x642.google.com with SMTP id bj8so403025plb.4 for ; Wed, 28 Aug 2019 12:05:59 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:05:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=t8j2uFjRrAOGYvd6SrvO/WjrxGa54I8yRPsCcXnl5DA=; b=QudNO0mvTHe2PPngOWNMXRhR0gmyjjz62Hr2e6kKN3SFMahpK2bAoM8s2p1IfouNsL UzxvXZW+pVB+rqOgEiUvjBvHiN7wds47BQhnlRKwayJWFIzOjuaepYrR8Ppvw2kZrbAU YN+bZ5RP3EEW2JkHMBtbQrPUpCYcOZ5sryUU6HgevkPzlmfKuMMmGl0cm9Gnq+Md1WT8 ES/MpTHovlyQqzPFdALEd5JZc1rBcX6C4P9pzjlWCF465rAb+9fhBzhly1k3TGToqTPC 1CVmV0omWTyUy1EN/JZRY2xyqHZts/YMQb1iESh7N6duUCS1E9GmrMxg+VccPZd6H5Db 0mGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t8j2uFjRrAOGYvd6SrvO/WjrxGa54I8yRPsCcXnl5DA=; b=NY5qQSFM7cD8aiWmYOOM7gT/klFWL/TJ8Oa0doxgyil96kSzxs6i7I9gkg9c1Yb3EI dYfnvnYV+FQ94O8Ph635MK+H+d+yJsAdYfX2hSvNi+l2NlwmaUMPfPfzp0rMREFcB6hb gUB/ROaAz2nHCjr7NvOS0ziA5At27n75C6tMPFsqG5JXLUIpHTqaEeaH+dPb2d3jdQ0X RyahyOHIYzU1HWpwFHUywnvgrwjXmkOr3lheLIihVdGjuRoNBYuRCYyGXrFuArFoWqXs hByEwClgqm6Nsnoezdji1dOVa4R9UGQEgcTVspb7yOtqiPA+jHhGEkme86esvq0/Etbk mOkA== X-Gm-Message-State: APjAAAXQwOqw5uCLTwT/g3XUo840FaGyehVnViA8DZwsW9ynW50GAoHk /8LUDqxe2HDyt8Aa/IjzQNyvI4M9TvM= X-Google-Smtp-Source: APXvYqylzgSNSDnuxrKLkN5njy+5XI5nml+Wd4z2u5hcR1XRYpZoMQWvm/6CVHxMoSp1pJE+9uR69w== X-Received: by 2002:a17:902:7592:: with SMTP id j18mr5785837pll.186.1567019158562; Wed, 28 Aug 2019 12:05:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:33 -0700 Message-Id: <20190828190456.30315-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 46/69] target/arm: Convert T16 data-processing (two low regs) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 152 ++--------------------------------------- target/arm/t16.decode | 36 ++++++++++ 2 files changed, 43 insertions(+), 145 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 106ef08ada..6e841c346f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -445,13 +445,6 @@ static inline void gen_logic_CC(TCGv_i32 var) tcg_gen_mov_i32(cpu_ZF, var); } =20 -/* T0 +=3D T1 + CF. */ -static void gen_adc(TCGv_i32 t0, TCGv_i32 t1) -{ - tcg_gen_add_i32(t0, t0, t1); - tcg_gen_add_i32(t0, t0, cpu_CF); -} - /* dest =3D T0 + T1 + CF. */ static void gen_add_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) { @@ -7527,6 +7520,11 @@ static int t32_branch24(DisasContext *s, int x) return x << 1; } =20 +static int t16_setflags(DisasContext *s) +{ + return s->condexec_mask =3D=3D 0; +} + /* * Include the generated decoders. */ @@ -10838,145 +10836,9 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) =20 /* * 0b0100_00xx_xxxx_xxxx - * - Data-processing (two low registers) + * - Data-processing (two low registers), in decodetree */ - rd =3D insn & 7; - rm =3D (insn >> 3) & 7; - op =3D (insn >> 6) & 0xf; - if (op =3D=3D 2 || op =3D=3D 3 || op =3D=3D 4 || op =3D=3D 7) { - /* the shift/rotate ops want the operands backwards */ - val =3D rm; - rm =3D rd; - rd =3D val; - val =3D 1; - } else { - val =3D 0; - } - - if (op =3D=3D 9) { /* neg */ - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else if (op !=3D 0xf) { /* mvn doesn't read its first operand */ - tmp =3D load_reg(s, rd); - } else { - tmp =3D NULL; - } - - tmp2 =3D load_reg(s, rm); - switch (op) { - case 0x0: /* and */ - tcg_gen_and_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0x1: /* eor */ - tcg_gen_xor_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0x2: /* lsl */ - if (s->condexec_mask) { - gen_shl(tmp2, tmp2, tmp); - } else { - gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x3: /* lsr */ - if (s->condexec_mask) { - gen_shr(tmp2, tmp2, tmp); - } else { - gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x4: /* asr */ - if (s->condexec_mask) { - gen_sar(tmp2, tmp2, tmp); - } else { - gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x5: /* adc */ - if (s->condexec_mask) { - gen_adc(tmp, tmp2); - } else { - gen_adc_CC(tmp, tmp, tmp2); - } - break; - case 0x6: /* sbc */ - if (s->condexec_mask) { - gen_sub_carry(tmp, tmp, tmp2); - } else { - gen_sbc_CC(tmp, tmp, tmp2); - } - break; - case 0x7: /* ror */ - if (s->condexec_mask) { - tcg_gen_andi_i32(tmp, tmp, 0x1f); - tcg_gen_rotr_i32(tmp2, tmp2, tmp); - } else { - gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x8: /* tst */ - tcg_gen_and_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - rd =3D 16; - break; - case 0x9: /* neg */ - if (s->condexec_mask) - tcg_gen_neg_i32(tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - break; - case 0xa: /* cmp */ - gen_sub_CC(tmp, tmp, tmp2); - rd =3D 16; - break; - case 0xb: /* cmn */ - gen_add_CC(tmp, tmp, tmp2); - rd =3D 16; - break; - case 0xc: /* orr */ - tcg_gen_or_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xd: /* mul */ - tcg_gen_mul_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xe: /* bic */ - tcg_gen_andc_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xf: /* mvn */ - tcg_gen_not_i32(tmp2, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp2); - val =3D 1; - rm =3D rd; - break; - } - if (rd !=3D 16) { - if (val) { - store_reg(s, rm, tmp2); - if (op !=3D 0xf) - tcg_temp_free_i32(tmp); - } else { - store_reg(s, rd, tmp); - tcg_temp_free_i32(tmp2); - } - } else { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - } - break; + goto illegal_op; =20 case 5: /* load/store register offset. */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index e954f61fe4..44e7250c55 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -18,3 +18,39 @@ # # This file is processed by scripts/decodetree.py # + +&s_rrr_shi !extern s rd rn rm shim shty +&s_rrr_shr !extern s rn rd rm rs shty +&s_rri_rot !extern s rn rd imm rot +&s_rrrr !extern s rd rn rm ra + +# Set S if the instruction is outside of an IT block. +%s !function=3Dt16_setflags + +# Data-processing (two low registers) + +%reg_0 0:3 + +@lll_noshr ...... .... rm:3 rd:3 \ + &s_rrr_shi %s rn=3D%reg_0 shim=3D0 shty=3D0 +@xll_noshr ...... .... rm:3 rn:3 \ + &s_rrr_shi s=3D1 rd=3D0 shim=3D0 shty=3D0 +@lxl_shr ...... .... rs:3 rd:3 \ + &s_rrr_shr %s rm=3D%reg_0 rn=3D0 + +AND_rrri 010000 0000 ... ... @lll_noshr +EOR_rrri 010000 0001 ... ... @lll_noshr +MOV_rxrr 010000 0010 ... ... @lxl_shr shty=3D0 # LSL +MOV_rxrr 010000 0011 ... ... @lxl_shr shty=3D1 # LSR +MOV_rxrr 010000 0100 ... ... @lxl_shr shty=3D2 # ASR +ADC_rrri 010000 0101 ... ... @lll_noshr +SBC_rrri 010000 0110 ... ... @lll_noshr +MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3D3 # ROR +TST_xrri 010000 1000 ... ... @xll_noshr +RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=3D0 rot= =3D0 +CMP_xrri 010000 1010 ... ... @xll_noshr +CMN_xrri 010000 1011 ... ... @xll_noshr +ORR_rrri 010000 1100 ... ... @lll_noshr +MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=3D%reg_0 ra= =3D0 +BIC_rrri 010000 1110 ... ... @lll_noshr +MVN_rxri 010000 1111 ... ... @lll_noshr --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 47/69] target/arm: Convert T16 load/store (register offset) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 51 ++---------------------------------------- target/arm/t16.decode | 15 +++++++++++++ 2 files changed, 17 insertions(+), 49 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 6e841c346f..73b4ac8efb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10841,55 +10841,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) goto illegal_op; =20 case 5: - /* load/store register offset. */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - rm =3D (insn >> 6) & 7; - op =3D (insn >> 9) & 7; - addr =3D load_reg(s, rn); - tmp =3D load_reg(s, rm); - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - - if (op < 3) { /* store */ - tmp =3D load_reg(s, rd); - } else { - tmp =3D tcg_temp_new_i32(); - } - - switch (op) { - case 0: /* str */ - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - break; - case 1: /* strh */ - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - break; - case 2: /* strb */ - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16B= it); - break; - case 3: /* ldrsb */ - gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - break; - case 4: /* ldr */ - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - break; - case 5: /* ldrh */ - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - break; - case 6: /* ldrb */ - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - break; - case 7: /* ldrsh */ - gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - break; - } - if (op >=3D 3) { /* load */ - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; + /* load/store register offset, in decodetree */ + goto illegal_op; =20 case 6: /* load/store word immediate offset */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 44e7250c55..83fe4363c7 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&ldst_rr !extern p w u rn rt rm shimm shtype =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -54,3 +55,17 @@ ORR_rrri 010000 1100 ... ... @lll_nos= hr MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=3D%reg_0 ra= =3D0 BIC_rrri 010000 1110 ... ... @lll_noshr MVN_rxri 010000 1111 ... ... @lll_noshr + +# Load/store (register offset) + +@ldst_rr ....... rm:3 rn:3 rt:3 \ + &ldst_rr p=3D1 w=3D0 u=3D1 shimm=3D0 shtype=3D0 + +STR_rr 0101 000 ... ... ... @ldst_rr +STRH_rr 0101 001 ... ... ... @ldst_rr +STRB_rr 0101 010 ... ... ... @ldst_rr +LDRSB_rr 0101 011 ... ... ... @ldst_rr +LDR_rr 0101 100 ... ... ... @ldst_rr +LDRH_rr 0101 101 ... ... ... @ldst_rr +LDRB_rr 0101 110 ... ... ... @ldst_rr +LDRSH_rr 0101 111 ... ... ... @ldst_rr --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.05.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:06:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kwRo4zZzHNj2f8dsvm1cnawVi86AhDJJQQALYH4bbvo=; b=RxbwHwdaNXVghcwQxxv2AhEAgUCdq06Zam78cjeGv2zovSoZTyCduTZGZyddgatOxY VZ6kGBKtsdCi44JXVAjf87ZODnUcyCX2wQ/pxR5aDWWWiApvgdDnfy+GZlqrbDzyWMrE dMl/VpkBOEkNNpma9HfeRWofcBWkJ9aaqTpcz1xkN0Ym/OP6e+1PykGBbfJ/H/17uFSn fAWBbadEzT3QI1rifD48scQMgVQQjiixIUsaKYw1dHWE4eKoGJXfuRQisKf3s+UfblYC lGUMThWP4Diwkrl1ZjIMdjQHz0IAJH5YluVfJ3wNrG8I7T7g/JHcl7dKWPYL4hB6iOXZ 1qGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kwRo4zZzHNj2f8dsvm1cnawVi86AhDJJQQALYH4bbvo=; b=eUq/krBSJbzEC3jXKEf5EkMQewV5CnPRpb26ujbViMSSWbvtMCbZmgInYZdT7sAm7y 0p4wi/hKyP5Lo9CVwNIUlHGs1njuF2RUcmkhPHuMROiJBE/zEYbJNy/J+yoBKSqJxPXj s0/snaBFAxawCehrTHJfK1HBGXyAEkqu7cQDvCe9L05ZTFk7OA2TKHbbRbochhe4UJLN NydyncR+Alfi8FglpCTJAf+PL+AD/ugZmmtIHHF4Dzjp8FUfo7XML/M4ZslA0dD+0Y/w wN97q1yjXHCKuSsuUOQkX3kUutG+y41wX0WMwy0TqibmjMUpP2PmtS3KldwGATfrEGlk ptRA== X-Gm-Message-State: APjAAAWwvn7NlHzPDsDHj136zw2GM5sAFVA/ZURUj33ruHfZ57kjcvd0 t+cxaEzCmRgTxMAQv3dklzkMTzaTzhE= X-Google-Smtp-Source: APXvYqzY+FObHV9HFL+LRR2ji2p/lI0wWZe42rTGy5Rfl4UJp+gkaWSlwIuDB1bS2ky6iREwWmNbPg== X-Received: by 2002:a17:902:e407:: with SMTP id ci7mr5967774plb.326.1567019161183; Wed, 28 Aug 2019 12:06:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:35 -0700 Message-Id: <20190828190456.30315-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 48/69] target/arm: Convert T16 load/store (immediate offset) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 94 +++--------------------------------------- target/arm/t16.decode | 33 +++++++++++++++ 2 files changed, 38 insertions(+), 89 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 73b4ac8efb..8e182f338c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10840,97 +10840,13 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) */ goto illegal_op; =20 - case 5: - /* load/store register offset, in decodetree */ + case 5: /* load/store register offset, in decodetree */ + case 6: /* load/store word immediate offset, in decodetree */ + case 7: /* load/store byte immediate offset, in decodetree */ + case 8: /* load/store halfword immediate offset, in decodetree */ + case 9: /* load/store from stack, in decodetree */ goto illegal_op; =20 - case 6: - /* load/store word immediate offset */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - addr =3D load_reg(s, rn); - val =3D (insn >> 4) & 0x7c; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 7: - /* load/store byte immediate offset */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - addr =3D load_reg(s, rn); - val =3D (insn >> 6) & 0x1f; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16B= it); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 8: - /* load/store halfword immediate offset */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - addr =3D load_reg(s, rn); - val =3D (insn >> 5) & 0x3e; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 9: - /* load/store from stack */ - rd =3D (insn >> 8) & 7; - addr =3D load_reg(s, 13); - val =3D (insn & 0xff) * 4; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - case 10: /* * 0b1010_xxxx_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 83fe4363c7..1cf79789ac 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ldst_rr !extern p w u rn rt rm shimm shtype +&ldst_ri !extern p w u rn rt imm =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -69,3 +70,35 @@ LDR_rr 0101 100 ... ... ... @ldst_rr LDRH_rr 0101 101 ... ... ... @ldst_rr LDRB_rr 0101 110 ... ... ... @ldst_rr LDRSH_rr 0101 111 ... ... ... @ldst_rr + +# Load/store word/byte (immediate offset) + +%imm5_6x4 6:5 !function=3Dtimes_4 + +@ldst_ri_1 ..... imm:5 rn:3 rt:3 \ + &ldst_ri p=3D1 w=3D0 u=3D1 +@ldst_ri_4 ..... ..... rn:3 rt:3 \ + &ldst_ri p=3D1 w=3D0 u=3D1 imm=3D%imm5_6x4 + +STR_ri 01100 ..... ... ... @ldst_ri_4 +LDR_ri 01101 ..... ... ... @ldst_ri_4 +STRB_ri 01110 ..... ... ... @ldst_ri_1 +LDRB_ri 01111 ..... ... ... @ldst_ri_1 + +# Load/store halfword (immediate offset) + +%imm5_6x2 6:5 !function=3Dtimes_2 +@ldst_ri_2 ..... ..... rn:3 rt:3 \ + &ldst_ri p=3D1 w=3D0 u=3D1 imm=3D%imm5_6x2 + +STRH_ri 10000 ..... ... ... @ldst_ri_2 +LDRH_ri 10001 ..... ... ... @ldst_ri_2 + +# Load/store (SP-relative) + +%imm8_0x4 0:8 !function=3Dtimes_4 +@ldst_spec_i ..... rt:3 ........ \ + &ldst_ri p=3D1 w=3D0 u=3D1 imm=3D%imm8_0x4 + +STR_ri 10010 ... ........ @ldst_spec_i rn=3D13 +LDR_ri 10011 ... ........ @ldst_spec_i rn=3D13 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::629 Subject: [Qemu-devel] [PATCH v3 49/69] target/arm: Convert T16 add pc/sp (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 +----------- target/arm/t16.decode | 7 +++++++ 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 8e182f338c..d8dfddaea3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10845,19 +10845,9 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) case 7: /* load/store byte immediate offset, in decodetree */ case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ + case 10: /* add PC/SP (immediate), in decodetree */ goto illegal_op; =20 - case 10: - /* - * 0b1010_xxxx_xxxx_xxxx - * - Add PC/SP (immediate) - */ - rd =3D (insn >> 8) & 7; - val =3D (insn & 0xff) * 4; - tmp =3D add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val); - store_reg(s, rd, tmp); - break; - case 11: /* misc */ op =3D (insn >> 8) & 0xf; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 1cf79789ac..71b3e8f02e 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&ri !extern rd imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm =20 @@ -102,3 +103,9 @@ LDRH_ri 10001 ..... ... ... @ldst_r= i_2 =20 STR_ri 10010 ... ........ @ldst_spec_i rn=3D13 LDR_ri 10011 ... ........ @ldst_spec_i rn=3D13 + +# Add PC/SP (immediate) + +ADR 10100 rd:3 ........ imm=3D%imm8_0x4 +ADD_rri 10101 rd:3 ........ \ + &s_rri_rot rn=3D13 s=3D0 rot=3D0 imm=3D%imm8_0x4 # SP --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567023032; cv=none; d=zoho.com; s=zohoarc; b=F682Gga+rz2d/bbxHFIMrnaPwQnUdWyqH4az8Hpxg6xa4yDuSyOGNwdC/X+/t+Fnf3ENa2+HFHmLR8MRnHDUHkD/aVrVOrwE8KpkVYyMKAnyjjHPz/dWn+D3ETR2eY01m+fg45faCTw2pbuENfuqMmlEIAcwGs9lJAmKCdJx6Ms= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567023032; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=6MCGFTmei0/LomQ5kSqH0JJCmj9qk8EmtY5FJ9APNto=; b=GdhZeUfp1dueUf8CCB3OmROEZjI6UROXEEQIU1ELg8Pf2Zd65Cdc963OJ2gY9DRwn9JGQNtJovgb8j0IX/x0/fK9nXMHTHwif80vYDWEN3Zu80A2xCS/1FtZbMoRAMerWpOAgQE8FUMZ6I/R/9Km3LBs0kdYzGmUFG0SrYxLGm4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567023032694134.33624985294614; Wed, 28 Aug 2019 13:10:32 -0700 (PDT) Received: from localhost ([::1]:42042 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i34H1-0001hh-8P for importer@patchew.org; Wed, 28 Aug 2019 16:10:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38595) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Gl-0003tx-4t for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33Gi-0000bE-Q3 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:10 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:43540) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33Gg-0000XV-Oe for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:07 -0400 Received: by mail-pf1-x444.google.com with SMTP id v12so375599pfn.10 for ; Wed, 28 Aug 2019 12:06:05 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.06.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:06:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6MCGFTmei0/LomQ5kSqH0JJCmj9qk8EmtY5FJ9APNto=; b=erxTp27yilKFTy0BE4fI3n4xYC6VEA9GgNc62jBB4wz8rvfhJVisEGTZkdKL4yWr04 IRf0W6tJaeTvppRPHulBluNwX9LsstOyDoZtKmhFOpa4RQvJ6NFULZIJKPXnHhw+wHyw iNhLwG0HbndKrWSpeYork+qk4vMDYhvcIHvz59A7b+DPHuHSsn79DIxyCC9CYOfDHT97 mDo7JTIW3P22xKkBo/LSVgGcgTM4+vzntLqaPVT48LAGKRxtgzAblbWSrQj0gzrHazWN +jM14njb5N3s1DNHUv/tKc9UNQSEVzVTLyYFK5SFGjxeRLKkN9Niyf2UBuXZ24awk72Y LDrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6MCGFTmei0/LomQ5kSqH0JJCmj9qk8EmtY5FJ9APNto=; b=nnRwS+PSHMc3iIEEBEAqwvau/Dg4nE46kWUD0aly5Fw0aibz603oUpab3kr1fVzEVV yRVWzgB/x3CKMIuB6ROHIfHkYvInBR2C3qgQ2Q60D66ZOwhlPxLUgYL0t/0crBTTEbEJ gVaS7gRXRe0ytzxDzIwHmKCqqrM22HykVjc8v0FzH3SFYeCbgzysEq6I/wzExGf2KsHY ID3rYtS0EL16jW7X9XvkOQqnVQZCsgpIS850uwbG04LxmQZ7evDnJ7mg1LBBGHaDTUB0 iiYSuD2nOvtmJfw7qwpuDE3Vy1ACOq1UyqCDzlSvBUBFk4aWd3Cliof6nEartQq7zh4J f78g== X-Gm-Message-State: APjAAAWV1wdaIuAs+DGI5cAc/B2/BWlVi0NZI43Q3NubqCF3PY81O7Wl l1uMP4FGg+0s0A5I2Ik7RMY/qc0k/6o= X-Google-Smtp-Source: APXvYqxRivS6oW1ySuCEG7Pk+DKc/MmeDR1LxETeA4z1Etl7uZ9bSBcA3cnFoAO5XIn3QEZlEZGBDg== X-Received: by 2002:a63:de4c:: with SMTP id y12mr4873135pgi.264.1567019163712; Wed, 28 Aug 2019 12:06:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:37 -0700 Message-Id: <20190828190456.30315-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 50/69] target/arm: Convert T16 load/store multiple X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 48 ++++++++---------------------------------- target/arm/t16.decode | 8 +++++++ 2 files changed, 17 insertions(+), 39 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d8dfddaea3..b6ee123bf5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10059,6 +10059,14 @@ static bool trans_LDM_t32(DisasContext *s, arg_lds= t_block *a) return do_ldm(s, a, 2); } =20 +static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback is conditional on the base register not being loaded. */ + a->w =3D !(a->list & (1 << a->rn)); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return do_ldm(s, a, 1); +} + /* * Branch, branch with link */ @@ -10846,6 +10854,7 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ case 10: /* add PC/SP (immediate), in decodetree */ + case 12: /* load/store multiple, in decodetree */ goto illegal_op; =20 case 11: @@ -11069,45 +11078,6 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) } break; =20 - case 12: - { - /* load/store multiple */ - TCGv_i32 loaded_var =3D NULL; - rn =3D (insn >> 8) & 0x7; - addr =3D load_reg(s, rn); - for (i =3D 0; i < 8; i++) { - if (insn & (1 << i)) { - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i =3D=3D rn) { - loaded_var =3D tmp; - } else { - store_reg(s, i, tmp); - } - } else { - /* store */ - tmp =3D load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - /* advance to the next address */ - tcg_gen_addi_i32(addr, addr, 4); - } - } - if ((insn & (1 << rn)) =3D=3D 0) { - /* base reg not in list: base register writeback */ - store_reg(s, rn, addr); - } else { - /* base reg in list: if load, complete it now */ - if (insn & (1 << 11)) { - store_reg(s, rn, loaded_var); - } - tcg_temp_free_i32(addr); - } - break; - } case 13: /* conditional branch or swi */ cond =3D (insn >> 8) & 0xf; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 71b3e8f02e..a7a437f930 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -26,6 +26,7 @@ &ri !extern rd imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&ldst_block !extern rn i b u w list =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -109,3 +110,10 @@ LDR_ri 10011 ... ........ @ldst_= spec_i rn=3D13 ADR 10100 rd:3 ........ imm=3D%imm8_0x4 ADD_rri 10101 rd:3 ........ \ &s_rri_rot rn=3D13 s=3D0 rot=3D0 imm=3D%imm8_0x4 # SP + +# Load/store multiple + +@ldstm ..... rn:3 list:8 &ldst_block i=3D1 b=3D0 u= =3D0 w=3D1 + +STM 11000 ... ........ @ldstm +LDM_t16 11001 ... ........ @ldstm --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 51/69] target/arm: Convert T16 add/sub (3 low, 2 low and imm) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++------------------------ target/arm/t16.decode | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 24 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b6ee123bf5..fa6892d6af 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10668,31 +10668,9 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) * 0b0001_1xxx_xxxx_xxxx * - Add, subtract (three low registers) * - Add, subtract (two low registers and immediate) + * In decodetree. */ - rn =3D (insn >> 3) & 7; - tmp =3D load_reg(s, rn); - if (insn & (1 << 10)) { - /* immediate */ - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, (insn >> 6) & 7); - } else { - /* reg */ - rm =3D (insn >> 6) & 7; - tmp2 =3D load_reg(s, rm); - } - if (insn & (1 << 9)) { - if (s->condexec_mask) - tcg_gen_sub_i32(tmp, tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - } else { - if (s->condexec_mask) - tcg_gen_add_i32(tmp, tmp, tmp2); - else - gen_add_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); + goto illegal_op; } else { /* shift immediate */ rm =3D (insn >> 3) & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index a7a437f930..2b5f368d31 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -117,3 +117,19 @@ ADD_rri 10101 rd:3 ........ \ =20 STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm + +# Add/subtract (three low registers) + +@addsub_3 ....... rm:3 rn:3 rd:3 \ + &s_rrr_shi %s shim=3D0 shty=3D0 + +ADD_rrri 0001100 ... ... ... @addsub_3 +SUB_rrri 0001101 ... ... ... @addsub_3 + +# Add/subtract (two low registers and immediate) + +@addsub_2i ....... imm:3 rn:3 rd:3 \ + &s_rri_rot %s rot=3D0 + +ADD_rri 0001 110 ... ... ... @addsub_2i +SUB_rri 0001 111 ... ... ... @addsub_2i --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.06.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:06:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W7Njx5fsc6fJoAUaqNSP00kDYpcwXysWT9wttSWRibc=; b=i86swx/FRswyTONOGwgCLPvgXcsrnuxF+v5duHhig19ZSjEUOoSVB9V1wmd9Gzp+Z0 JVGHiLBiKYm4oKHQIRmacAQBangR9QOC5w3zE2CyRuZ0nl0763Gy2tXPvLE7HqwSfDTe UwljaqJXyFbiBd0Ci1Py9DsmjZ76uLF1xxt/YeOv4nzC9j23copESWdXEy7gBjyGiX3U iOeyLovCFgjmTJ36aqbNTvwBgrqu3h+Py8PYypvCiFKgXj8T3KR6bTBl1zxvVWGexVDB qXRKhFLDcEh9NR9ZA1YuMbAWUwMt3UezksUzckd5QSR5qKPRNndhcr0XPw2C8eSd3zdF l3uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W7Njx5fsc6fJoAUaqNSP00kDYpcwXysWT9wttSWRibc=; b=LU7RX7dheXWZO5CyqLIBmTe2oX6fTlSPYTs+OT0x+754YwVjf+8H76R8In2tVZNY/Y oo+N6mQEAHBnce5/03LMgh0kYlh9OF3HgCTV8oV8eKqyW0djDTJH40Yy0k9n/Qa9fern 7+7Zyi5M2XDY9bH6pm5XQIOafH8C/HqPQ9GKt41MG+gyjRxNYX6PCvDntHB+SZmX5zMW Z/9Y13/ssk23YZaQILhHOYY6zk34kf0+oCK3slz/CKfqYb2jgHe71Hc4Er6zO/ppIWbb bNNrvH8ozgy4lRHuzYlG5+NIKqXRGHm8MXaK1uDSPJBEGhhE8fC8C0rHJ4dSUGjSaRx3 GbJw== X-Gm-Message-State: APjAAAXrtDiEI8W87zQjXdF/jRqu3+N8NV6Plur74s0o320tv6r0UDfw Oev1vxS7Tj1p9cjbp3CnrtAX2gMoLzw= X-Google-Smtp-Source: APXvYqyUCsYUocGIijXSnXNrrf3ewYJqCzIt7ytDcNcAQciyhlvIrzMOWw/oGaQI+W0mjYBCUmkXxg== X-Received: by 2002:a17:902:b18b:: with SMTP id s11mr6003928plr.1.1567019166144; Wed, 28 Aug 2019 12:06:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:39 -0700 Message-Id: <20190828190456.30315-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 52/69] target/arm: Convert T16 one low register and immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 44 ++---------------------------------------- target/arm/t16.decode | 11 +++++++++++ 2 files changed, 13 insertions(+), 42 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index fa6892d6af..d4d7d99da8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10682,48 +10682,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) store_reg(s, rd, tmp); } break; - case 2: case 3: - /* - * 0b001x_xxxx_xxxx_xxxx - * - Add, subtract, compare, move (one low register and immediate) - */ - op =3D (insn >> 11) & 3; - rd =3D (insn >> 8) & 0x7; - if (op =3D=3D 0) { /* mov */ - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, insn & 0xff); - if (!s->condexec_mask) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - } else { - tmp =3D load_reg(s, rd); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, insn & 0xff); - switch (op) { - case 1: /* cmp */ - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - break; - case 2: /* add */ - if (s->condexec_mask) - tcg_gen_add_i32(tmp, tmp, tmp2); - else - gen_add_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; - case 3: /* sub */ - if (s->condexec_mask) - tcg_gen_sub_i32(tmp, tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; - } - } - break; + case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ + goto illegal_op; case 4: if (insn & (1 << 11)) { rd =3D (insn >> 8) & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 2b5f368d31..0654275e68 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -133,3 +133,14 @@ SUB_rrri 0001101 ... ... ... @addsu= b_3 =20 ADD_rri 0001 110 ... ... ... @addsub_2i SUB_rri 0001 111 ... ... ... @addsub_2i + +# Add, subtract, compare, move (one low register and immediate) + +%reg_8 8:3 +@arith_1i ..... rd:3 imm:8 \ + &s_rri_rot rot=3D0 rn=3D%reg_8 + +MOV_rxi 00100 ... ........ @arith_1i %s +CMP_xri 00101 ... ........ @arith_1i s=3D1 +ADD_rri 00110 ... ........ @arith_1i %s +SUB_rri 00111 ... ........ @arith_1i %s --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 53/69] target/arm: Convert T16 branch and exchange X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 70 +++++++++++++++++------------------------- target/arm/t16.decode | 10 ++++++ 2 files changed, 39 insertions(+), 41 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d4d7d99da8..cd39329e5c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8338,7 +8338,7 @@ static bool trans_BX(DisasContext *s, arg_BX *a) if (!ENABLE_ARCH_4T) { return false; } - gen_bx(s, load_reg(s, a->rm)); + gen_bx_excret(s, load_reg(s, a->rm)); return true; } =20 @@ -8365,6 +8365,32 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *= a) return true; } =20 +/* + * BXNS/BLXNS: only exist for v8M with the security extensions, + * and always UNDEF if NonSecure. We don't implement these in + * the user-only mode either (in theory you can use them from + * Secure User mode but they are too tied in to system emulation). + */ +static bool trans_BXNS(DisasContext *s, arg_BXNS *a) +{ + if (!s->v8m_secure || IS_USER_ONLY) { + unallocated_encoding(s); + } else { + gen_bxns(s, a->rm); + } + return true; +} + +static bool trans_BLXNS(DisasContext *s, arg_BLXNS *a) +{ + if (!s->v8m_secure || IS_USER_ONLY) { + unallocated_encoding(s); + } else { + gen_blxns(s, a->rm); + } + return true; +} + static bool trans_CLZ(DisasContext *s, arg_CLZ *a) { TCGv_i32 tmp; @@ -10733,49 +10759,11 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) } break; case 3: - { /* 0b0100_0111_xxxx_xxxx * - branch [and link] exchange thumb register + * In decodetree */ - bool link =3D insn & (1 << 7); - - if (insn & 3) { - goto undef; - } - if (link) { - ARCH(5); - } - if ((insn & 4)) { - /* BXNS/BLXNS: only exists for v8M with the - * security extensions, and always UNDEF if NonSecure. - * We don't implement these in the user-only mode - * either (in theory you can use them from Secure User - * mode but they are too tied in to system emulation.) - */ - if (!s->v8m_secure || IS_USER_ONLY) { - goto undef; - } - if (link) { - gen_blxns(s, rm); - } else { - gen_bxns(s, rm); - } - break; - } - /* BLX/BX */ - tmp =3D load_reg(s, rm); - if (link) { - val =3D (uint32_t)s->base.pc_next | 1; - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, val); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - } else { - /* Only BX works as exception-return, not BLX */ - gen_bx_excret(s, tmp); - } - break; - } + goto illegal_op; } break; } diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 0654275e68..edddbfb9b8 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ri !extern rd imm +&r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list @@ -144,3 +145,12 @@ MOV_rxi 00100 ... ........ @arith= _1i %s CMP_xri 00101 ... ........ @arith_1i s=3D1 ADD_rri 00110 ... ........ @arith_1i %s SUB_rri 00111 ... ........ @arith_1i %s + +# Branch and exchange + +@branchr .... .... . rm:4 ... &r + +BX 0100 0111 0 .... 000 @branchr +BLX_r 0100 0111 1 .... 000 @branchr +BXNS 0100 0111 0 .... 100 @branchr +BLXNS 0100 0111 1 .... 100 @branchr --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v3 54/69] target/arm: Convert T16 add, compare, move (two high registers) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 49 ++---------------------------------------- target/arm/t16.decode | 10 +++++++++ 2 files changed, 12 insertions(+), 47 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index cd39329e5c..cf19f1f777 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10722,55 +10722,10 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) store_reg(s, rd, tmp); break; } - if (insn & (1 << 10)) { - /* 0b0100_01xx_xxxx_xxxx - * - data processing extended, branch and exchange - */ - rd =3D (insn & 7) | ((insn >> 4) & 8); - rm =3D (insn >> 3) & 0xf; - op =3D (insn >> 8) & 3; - switch (op) { - case 0: /* add */ - tmp =3D load_reg(s, rd); - tmp2 =3D load_reg(s, rm); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rd =3D=3D 13) { - /* ADD SP, SP, reg */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } - break; - case 1: /* cmp */ - tmp =3D load_reg(s, rd); - tmp2 =3D load_reg(s, rm); - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - break; - case 2: /* mov/cpy */ - tmp =3D load_reg(s, rm); - if (rd =3D=3D 13) { - /* MOV SP, reg */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } - break; - case 3: - /* 0b0100_0111_xxxx_xxxx - * - branch [and link] exchange thumb register - * In decodetree - */ - goto illegal_op; - } - break; - } =20 /* - * 0b0100_00xx_xxxx_xxxx - * - Data-processing (two low registers), in decodetree + * - Data-processing (two low registers), in decodetree + * - data processing extended, branch and exchange, in decodetree */ goto illegal_op; =20 diff --git a/target/arm/t16.decode b/target/arm/t16.decode index edddbfb9b8..5a570484e3 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -146,6 +146,16 @@ CMP_xri 00101 ... ........ @arith= _1i s=3D1 ADD_rri 00110 ... ........ @arith_1i %s SUB_rri 00111 ... ........ @arith_1i %s =20 +# Add, compare, move (two high registers) + +%reg_0_7 7:1 0:3 +@addsub_2h .... .... . rm:4 ... \ + &s_rrr_shi rd=3D%reg_0_7 rn=3D%reg_0_7 shim=3D0 shty=3D0 + +ADD_rrri 0100 0100 . .... ... @addsub_2h s=3D0 +CMP_xrri 0100 0101 . .... ... @addsub_2h s=3D1 +MOV_rxri 0100 0110 . .... ... @addsub_2h s=3D0 + # Branch and exchange =20 @branchr .... .... . rm:4 ... &r --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v3 55/69] target/arm: Convert T16 adjust sp (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 ++------------- target/arm/t16.decode | 9 +++++++++ 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index cf19f1f777..b7e2c72f35 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10742,19 +10742,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) /* misc */ op =3D (insn >> 8) & 0xf; switch (op) { - case 0: - /* - * 0b1011_0000_xxxx_xxxx - * - ADD (SP plus immediate) - * - SUB (SP minus immediate) - */ - tmp =3D load_reg(s, 13); - val =3D (insn & 0x7f) * 4; - if (insn & (1 << 7)) - val =3D -(int32_t)val; - tcg_gen_addi_i32(tmp, tmp, val); - store_sp_checked(s, tmp); - break; + case 0: /* add/sub (sp, immediate), in decodetree */ + goto illegal_op; =20 case 2: /* sign/zero extend. */ ARCH(6); diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 5a570484e3..b425b86795 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -156,6 +156,15 @@ ADD_rrri 0100 0100 . .... ... @addsu= b_2h s=3D0 CMP_xrri 0100 0101 . .... ... @addsub_2h s=3D1 MOV_rxri 0100 0110 . .... ... @addsub_2h s=3D0 =20 +# Adjust SP (immediate) + +%imm7_0x4 0:7 !function=3Dtimes_4 +@addsub_sp_i .... .... . ....... \ + &s_rri_rot s=3D0 rd=3D13 rn=3D13 rot=3D0 imm=3D%imm7_0x4 + +ADD_rri 1011 0000 0 ....... @addsub_sp_i +SUB_rri 1011 0000 1 ....... @addsub_sp_i + # Branch and exchange =20 @branchr .... .... . rm:4 ... &r --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567023670; cv=none; d=zoho.com; s=zohoarc; b=RDhJ+u0N9HdlDSq1ICpxRX2JqcQPqzFqvBnzehsFBm7eAJvR7AmwreqOZC574vIn28Sn5eVPy5HXKeF46VC330RNlv7Q0POKBs3WVR+7KXs4OMEdPJ07qxs0pabr8eSeWAOHZBgZ5O7R9IJ+n53K6RFB0mftkuz6dCkyKTYGptM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567023670; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=q6ZBPK/r46XKCIwGfPMSrv2j4FjJhwF0lhuCFM2qD0g=; b=msMCbLpVkhIkqspTpgYj5q8DrSy6EBNC5eSuLqXeZvmqiMGIo9iydOemTlnDsmz8/kdZw+4nSDnRDlOE8qAyc0lDFo+DNzWqpUDCacCzuurhRcNr14ImdkhoUCAej2MG75qk5Vyyr9V4GAmeC86Ev2b7KcdtqncUwxNR11/Vntc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567023670488448.27114524719207; Wed, 28 Aug 2019 13:21:10 -0700 (PDT) Received: from localhost ([::1]:42228 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i34RI-0004Ps-Ts for importer@patchew.org; Wed, 28 Aug 2019 16:21:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38787) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Gs-0003xQ-9J for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33Gp-0000hI-9X for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:17 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:45363) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33Go-0000dD-2o for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:14 -0400 Received: by mail-pl1-x644.google.com with SMTP id y8so379891plr.12 for ; Wed, 28 Aug 2019 12:06:12 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.06.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:06:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q6ZBPK/r46XKCIwGfPMSrv2j4FjJhwF0lhuCFM2qD0g=; b=k7kCCIS7vEOzkHCTGD2WO4hMI8GfkWXqtLwck4aKUq0RgcgPhPhUU+k+Pp4NHn7WGE Ugjr/t0+UFtJ6d9qUm2GY5F8kxxBrmy1m7E0j8b95yRvnlLIZD2ezxzT4ygfXq8szAzd oint15XZvtVhNXNlPqidLPfHKmHPE9hv4rmhfWQkRLtVLoQyGO6Ru6RqE0IPzkGFJ5OO Yfwsi3c5xxozhog1nHJ3O9Iouj/rh2hw+Ju199z0OeES4KCygpGQ67fFHNvZA/ZPN/dI mSYEJL9tkorg/8vem2Gh/vuyOBe6F6wcM4WfHq6vxfRLUVA6PGDKRhHLQy8MEcaSPTMv Phfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q6ZBPK/r46XKCIwGfPMSrv2j4FjJhwF0lhuCFM2qD0g=; b=V0Bd5Q3C+VywAPz1LSSjVj0nTNJzwLP117ZjPB84wHZgyCrh9ZFDwVK3jiloRjzBtq KrVM7KstAMbXVcIZC42zCkAIeK6Lv93ka61rDvLNZe1IBTVrwReQHPIt8aXJ5GdPthAD ddMLKtAvaM/nXIfhDyiESUh+vbaAycPS7uYJ2UX2LTaliT9R65oeIXypcveit4rEBYYe cTho4hH+IlCyohRDl9h3n1R8DIqVEt2l+MfaoHYa4CWHJU4sx5ksBXuc9UiuNGhCtrck EfCLKEYHL7vC37B/DM48+MMnOCiXZn/thjahLOC0s77mYazlE6VOYG1aZMnE+3SHMBwp Ii7Q== X-Gm-Message-State: APjAAAVC+VQsphv2lediNj5ESW9TZM52ssVBDOvxzDKrKbs0mnXW3hD4 xk81R51o5Ek4QeLnFwkGRKIj+8zn+mg= X-Google-Smtp-Source: APXvYqya8B5gljGA+0HPniyMBWFwHICkZEr1KG3Pf3ON2jD34pgoiSzFQhdC0RIMwg7kyGXCf76KWA== X-Received: by 2002:a17:902:1a6:: with SMTP id b35mr5655285plb.228.1567019170976; Wed, 28 Aug 2019 12:06:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:43 -0700 Message-Id: <20190828190456.30315-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v3 56/69] target/arm: Convert T16, extract X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.c | 14 +------------- target/arm/t16.decode | 10 ++++++++++ 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b7e2c72f35..d06ec48ab9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10743,21 +10743,9 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) op =3D (insn >> 8) & 0xf; switch (op) { case 0: /* add/sub (sp, immediate), in decodetree */ + case 2: /* sign/zero extend, in decodetree */ goto illegal_op; =20 - case 2: /* sign/zero extend. */ - ARCH(6); - rd =3D insn & 7; - rm =3D (insn >> 3) & 7; - tmp =3D load_reg(s, rm); - switch ((insn >> 6) & 3) { - case 0: gen_sxth(tmp); break; - case 1: gen_sxtb(tmp); break; - case 2: gen_uxth(tmp); break; - case 3: gen_uxtb(tmp); break; - } - store_reg(s, rd, tmp); - break; case 4: case 5: case 0xc: case 0xd: /* * 0b1011_x10x_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index b425b86795..b5b5086e8a 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&rrr_rot !extern rd rn rm rot &ri !extern rd imm &r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype @@ -173,3 +174,12 @@ BX 0100 0111 0 .... 000 @branc= hr BLX_r 0100 0111 1 .... 000 @branchr BXNS 0100 0111 0 .... 100 @branchr BLXNS 0100 0111 1 .... 100 @branchr + +# Extend + +@extend .... .... .. rm:3 rd:3 &rrr_rot rn=3D15 rot=3D0 + +SXTAH 1011 0010 00 ... ... @extend +SXTAB 1011 0010 01 ... ... @extend +UXTAH 1011 0010 10 ... ... @extend +UXTAB 1011 0010 11 ... ... @extend --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.06.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:06:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sXpbzk4XyeAvgkyELetXWo1a4Xmvrd+/ykw0k9l5t7I=; b=CMTj6+GHWPzs68ULrhbI44cIyFv4/xbbuBXa7TRuQijsXp7rCrjEUgYvivg+Nw1/Ru LcnOoeIn1ImyL22J3LFJqcaX2Upr9xv48OyhbiP9KUkNxAETBeLnyjcLVugvA5UMzE9q 6jBjHvwHztx4YiT+eIUzY+FB29AX5fZaaKtXtedfVguJDImXllG+NwSbMy/T3cmlVsM6 TQbzupbQprSJ3gz8hcOPnYsNdnnhPBOIYCakqntSQSCRHJhi69ZPP+BHk/S4HEtoTvqV Wa5Qp70NdZoNCzb2RPTCwhSgFwoiDTPek3lSg3tt5kvSvxRkQMMwgstQ2Slvwb1Kcci2 9MYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sXpbzk4XyeAvgkyELetXWo1a4Xmvrd+/ykw0k9l5t7I=; b=JQrUVIF+qM8b+t7iCCvxPl8wiw1fRTqEZt8Xr/3qUZzjfNxLDHZa1zHA2TcqD1ngvu 7p6FUpw1h/pLjcQJJyq2rd5NYJVOdQBw3ePDr/HWTYPH6C9kpdnTj1lDDHV4ASm7EObX nzPe/TIny0GteE3/W0rcVyqcRxSxbKQsgovefXxEC1EO9zmGCYGE1DyXvehxyYEifQSA Jp6z9+OJwvD7y6mTXLvjQLK1gn0K4dNfYtw5Pb2zLrUmHw+uLmFjVoG7oAFGR4RxXm3F zHLohmI+WNhyEkXPgCpfzVSqzAPZzkuT2mKZ/TXtOwgkUVktujGd89agbFHplmBx/PB8 lqEA== X-Gm-Message-State: APjAAAXdCOrQb9OQQAoy8JYhIj1unCqFaFXAYKeUdPyNhz2onG9YEh7P 82Yy6ra43JSWPlVTmKYieMVFsa063Hg= X-Google-Smtp-Source: APXvYqwixP0b6vUzFhn3ni3JwcFcaPhfYVZ3clYHE/27d80QeRgyjBkNfmizm/QfA+Zkrei1cz17xQ== X-Received: by 2002:a63:a302:: with SMTP id s2mr4800116pge.125.1567019172264; Wed, 28 Aug 2019 12:06:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:44 -0700 Message-Id: <20190828190456.30315-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 57/69] target/arm: Convert T16, Change processor state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a check for ARMv6 in trans_CPS. We had this correct in the T16 path, but had previously forgotten the check on the A32 and T32 paths. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v3: Fix cps architecture checks. Rename s/v6m/v7m/g --- target/arm/translate.c | 84 +++++++++++++++++++----------------------- target/arm/t16.decode | 12 ++++++ 2 files changed, 50 insertions(+), 46 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d06ec48ab9..1dacae1a5b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7470,6 +7470,11 @@ static int negate(DisasContext *s, int x) return -x; } =20 +static int plus_2(DisasContext *s, int x) +{ + return x + 2; +} + static int times_2(DisasContext *s, int x) { return x * 2; @@ -10245,7 +10250,7 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) { uint32_t mask, val; =20 - if (arm_dc_feature(s, ARM_FEATURE_M)) { + if (!ENABLE_ARCH_6 || arm_dc_feature(s, ARM_FEATURE_M)) { return false; } if (IS_USER(s)) { @@ -10279,6 +10284,36 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) return true; } =20 +static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a) +{ + TCGv_i32 tmp, addr; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + /* Implemented as NOP in user mode. */ + return true; + } + + tmp =3D tcg_const_i32(a->im); + /* FAULTMASK */ + if (a->F) { + addr =3D tcg_const_i32(19); + gen_helper_v7m_msr(cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + } + /* PRIMASK */ + if (a->I) { + addr =3D tcg_const_i32(16); + gen_helper_v7m_msr(cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + } + tcg_temp_free_i32(tmp); + gen_lookup_tb(s); + return true; +} + /* * Clear-Exclusive, Barriers */ @@ -10885,51 +10920,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) break; } =20 - case 6: - switch ((insn >> 5) & 7) { - case 2: - /* setend */ - ARCH(6); - if (((insn >> 3) & 1) !=3D !!(s->be_data =3D=3D MO_BE)) { - gen_helper_setend(cpu_env); - s->base.is_jmp =3D DISAS_UPDATE; - } - break; - case 3: - /* cps */ - ARCH(6); - if (IS_USER(s)) { - break; - } - if (arm_dc_feature(s, ARM_FEATURE_M)) { - tmp =3D tcg_const_i32((insn & (1 << 4)) !=3D 0); - /* FAULTMASK */ - if (insn & 1) { - addr =3D tcg_const_i32(19); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - } - /* PRIMASK */ - if (insn & 2) { - addr =3D tcg_const_i32(16); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - } - tcg_temp_free_i32(tmp); - gen_lookup_tb(s); - } else { - if (insn & (1 << 4)) { - shift =3D CPSR_A | CPSR_I | CPSR_F; - } else { - shift =3D 0; - } - gen_set_psr_im(s, ((insn & 7) << 6), 0, shift); - } - break; - default: - goto undef; - } - break; + case 6: /* setend, cps; in decodetree */ + goto illegal_op; =20 default: goto undef; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index b5b5086e8a..032902a1f4 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -29,6 +29,8 @@ &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list +&setend !extern E +&cps !extern mode imod M A I F =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -183,3 +185,13 @@ SXTAH 1011 0010 00 ... ... @extend SXTAB 1011 0010 01 ... ... @extend UXTAH 1011 0010 10 ... ... @extend UXTAB 1011 0010 11 ... ... @extend + +# Change processor state + +%imod 4:1 !function=3Dplus_2 + +SETEND 1011 0110 010 1 E:1 000 &setend +{ + CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=3D0 M=3D0 %imod + CPS_v7m 1011 0110 011 im:1 00 I:1 F:1 +} --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::52d Subject: [Qemu-devel] [PATCH v3 58/69] target/arm: Convert T16, Reverse bytes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 18 +++--------------- target/arm/t16.decode | 9 +++++++++ 2 files changed, 12 insertions(+), 15 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 1dacae1a5b..ec5b095bd1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10707,7 +10707,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rn, rd, shift, cond; + uint32_t val, op, rm, rd, shift, cond; int32_t offset; int i; TCGv_i32 tmp; @@ -10904,20 +10904,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) break; } =20 - /* Otherwise this is rev */ - ARCH(6); - rn =3D (insn >> 3) & 0x7; - rd =3D insn & 0x7; - tmp =3D load_reg(s, rn); - switch (op1) { - case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_rev16(tmp, tmp); break; - case 3: gen_revsh(tmp, tmp); break; - default: - g_assert_not_reached(); - } - store_reg(s, rd, tmp); - break; + /* Otherwise this is rev, in decodetree */ + goto illegal_op; } =20 case 6: /* setend, cps; in decodetree */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 032902a1f4..19a442b894 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrr_rot !extern rd rn rm rot +&rr !extern rd rm &ri !extern rd imm &r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype @@ -195,3 +196,11 @@ SETEND 1011 0110 010 1 E:1 000 &setend CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=3D0 M=3D0 %imod CPS_v7m 1011 0110 011 im:1 00 I:1 F:1 } + +# Reverse bytes + +@rdm .... .... .. rm:3 rd:3 &rr + +REV 1011 1010 00 ... ... @rdm +REV16 1011 1010 01 ... ... @rdm +REVSH 1011 1010 11 ... ... @rdm --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.06.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:06:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HN5caKoOORxiigixHNAW+6u13INbJ94cJ6ViPIOo+M0=; b=ueJY2T8d/n0lymoCa2wSKjX+q7S6okwtey5AQiz8K8aKHYfFa7SYGJJMa0k64KrFfr rdIEygtubUsh7sdtrIPmyJrBSyh49urZ7g0WL39rbet6tQninGFvnsbhDrZRJeErmVKI yaVmDFD2zuMID2qrYM0a0CnWdG9RHO0ziPdkzhGItNSGX+0rKPSWFZUDkmPyW6qthDjo VBMbcLuQ48204BRESN39RS7uSXAY5QRttsTR5WIlEo7MY/OP/wdz7BVqu9zi0qGtYECV Jqk00zpvCrP1Lv9IhsboavwdHrea3M81tEt9kLHGKxtZJsNNgDxJnfXtx7K/Dxy1kLST xyxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HN5caKoOORxiigixHNAW+6u13INbJ94cJ6ViPIOo+M0=; b=G+Z6Zha0HikOBJK6jQpPNeTh6w4sC/e05RIIucLiVln3qL0f1d5PtWkvYWKX1rcyzZ AMeU68RZAxpXhQ5nYmGXAnVwUM91mppMaeh7VV91eMcgGGS5suQw1qPx3qsrvAAOjLcB qftltiD5zP2KxKWTOgu//72uBabSOYXfjLATPIhS/CNOvHG4c57TC14p2RPXiO7z6b80 tNEqyzUb+oCWaeg/r7cQSPs+jdg+6OdbUBiTTn79HgH1VsJ12uFIEn5qDmtQZQnD5Mdw z9q5AGguwStAyY4ZFTz8byK5LbJoOgC68nvpantCSVadzxssqimNc/GlvQCjsBVWdF/9 xpHg== X-Gm-Message-State: APjAAAX6QfOMDAYeBydQhZcDQAkbz18OZocquK95rzO84sLOrz3qSLKq y1dIm1UrNNqMedhhSobHpPtUfnwlrW4= X-Google-Smtp-Source: APXvYqwEN+FSg8IeBVjfQvHTkAjeVQsYaOCi2ITksVhCKkiYiY9bxqokI5dzpEPeACZuavOooQL/wg== X-Received: by 2002:a17:902:b191:: with SMTP id s17mr5975793plr.121.1567019174831; Wed, 28 Aug 2019 12:06:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:46 -0700 Message-Id: <20190828190456.30315-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 59/69] target/arm: Convert T16, nop hints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 3 +-- target/arm/t16.decode | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ec5b095bd1..1bbfea8ea4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10868,8 +10868,7 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) =20 case 15: /* IT, nop-hint. */ if ((insn & 0xf) =3D=3D 0) { - gen_nop_hint(s, (insn >> 4) & 0xf); - break; + goto illegal_op; /* nop hint, in decodetree */ } /* * IT (If-Then) diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 19a442b894..5829b9a58c 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -19,6 +19,7 @@ # This file is processed by scripts/decodetree.py # =20 +&empty !extern &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot @@ -204,3 +205,19 @@ SETEND 1011 0110 010 1 E:1 000 &setend REV 1011 1010 00 ... ... @rdm REV16 1011 1010 01 ... ... @rdm REVSH 1011 1010 11 ... ... @rdm + +# Hints + +{ + YIELD 1011 1111 0001 0000 + WFE 1011 1111 0010 0000 + WFI 1011 1111 0011 0000 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1011 1111 0100 0000 + # SEVL 1011 1111 0101 0000 + + # The canonical nop has the second nibble as 0000, but the whole of the + # rest of the space is a reserved hint, behaves as nop. + NOP 1011 1111 ---- 0000 +} --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567022434; cv=none; d=zoho.com; s=zohoarc; b=LOBwuwWFVuWE1M0KToIOA5cvXC0thP3BpstqF3hevQaYgRsWbcDZ7dhGYXa3aV5fwKc1f1/pDf/T8X5K/0wz0OYvpha7BkCLoWP9gfiA7Jo661Vu2kUEQDwq0AvMdAl4jbmUuBzRFwCkh+1uWVN4YrTqNmNm5lYiy9djQcEEwTQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567022434; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=YeIFIe6n+qNkaqMNDbQLOQi6RqvsGYoOCEwWlKiQ2C8=; b=Y0WS6KvE65bS2/t1//9kqH61WuFPkKCF+9I1IYq4dDAKe/iYcnlPs5B5nWYH8wxwiFpejAH6WtCFz3HjyvfiEiqjk/NKaJNzGudkGf3fAfA8SWRWCWQELh4FfdNRnQB3wGwa6JQnCGR03u2LPcQfNHFeUdgX1Z4GFL/8K1Adriw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567022434889644.723517001628; Wed, 28 Aug 2019 13:00:34 -0700 (PDT) Received: from localhost ([::1]:41882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i347G-0008OH-7y for importer@patchew.org; Wed, 28 Aug 2019 16:00:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38878) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Gw-00040k-GO for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33Gu-0000ke-D7 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:22 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:43309) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33Gs-0000iM-M7 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:19 -0400 Received: by mail-pg1-x544.google.com with SMTP id k3so209653pgb.10 for ; Wed, 28 Aug 2019 12:06:17 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.06.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:06:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YeIFIe6n+qNkaqMNDbQLOQi6RqvsGYoOCEwWlKiQ2C8=; b=cGFI9v+yYvM7OyVOL802yWUrQ+heODsU5521ukAB2ZrcogJj/fekfXMGfX6jwwqIug t6/VBxuZm/i4bI1YnI8BXxoeMAuKeR8DaQ/R/HFcFTX0FVvmQ0eynQU01zauTeUT7eF/ kPamqgGP+WZ8zH85efEalIvJRrYrrHg8+kH7yC1IQYlFbxGfvfn69o5Aa+RJvDbqXKfL s0kxKZQ/guVv+gXgT6E2PPpPAgEpeu81TNf+JZ4uEfS9ZoXix3MOE+1La8/U8zfF4c7T U6MjisURYrKUJOaLtQLmrD9ziLZeReo86PcVX3s+Cs0y4tS/doh9mFXDlT7A7TlyOW9y Y3jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YeIFIe6n+qNkaqMNDbQLOQi6RqvsGYoOCEwWlKiQ2C8=; b=U2EiYX7ZlGfo2viLU5zIjKjJiaaXq8gLy23nDchPCuHIrNvdwULgUKCLIrvJqHB5oq 0oGsISoODgdTm14W9D2BokD299p/XNKQz3KTeQmStjfMg1wxSYwoXEY/KCJhT07VF01n gsQGqzcC6X2DbW6P5U4DCkMxWzcNJid3/oflaRgSoC9uMp2aVq1cB2w5W9ZwiDXoLYKY e8wQAUhjL8MRHT0KtAvbwAXDnVw6ASmbP7OARFArIzBcHopX2YamvtaXokt9/UQ/40Ap IJhFkOomacqh4wTEWV2xZgrKTeBsdDD44Js2yX3cUhx10T2gig9ttjUO9IsnG2g9znas FR2Q== X-Gm-Message-State: APjAAAUv6BdHSluFvOYOj8m0w6xTcX8/tJhSGsjR540GtnmHbuxNwV3M RAFoE4Oc/wzdAyKBSwGm3L6cEWD0mSw= X-Google-Smtp-Source: APXvYqxmtq0TKe6qHkp80fK/yuhXBmX9264XVMKfuufMSDOW0SyXqmkCUtn/6exbTO56OfogSiBoqw== X-Received: by 2002:a65:5003:: with SMTP id f3mr4798865pgo.335.1567019175981; Wed, 28 Aug 2019 12:06:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:47 -0700 Message-Id: <20190828190456.30315-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 60/69] target/arm: Split gen_nop_hint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that all callers pass a constant value, split the switch statement into the individual trans_* functions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 67 +++++++++++++++--------------------------- 1 file changed, 24 insertions(+), 43 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 1bbfea8ea4..c7d7834440 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3042,46 +3042,6 @@ static void gen_exception_return(DisasContext *s, TC= Gv_i32 pc) gen_rfe(s, pc, load_cpu_field(spsr)); } =20 -/* - * For WFI we will halt the vCPU until an IRQ. For WFE and YIELD we - * only call the helper when running single threaded TCG code to ensure - * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we - * just skip this instruction. Currently the SEV/SEVL instructions - * which are *one* of many ways to wake the CPU from WFE are not - * implemented so we can't sleep like WFI does. - */ -static void gen_nop_hint(DisasContext *s, int val) -{ - switch (val) { - /* When running in MTTCG we don't generate jumps to the yield and - * WFE helpers as it won't affect the scheduling of other vCPUs. - * If we wanted to more completely model WFE/SEV so we don't busy - * spin unnecessarily we would need to do something more involved. - */ - case 1: /* yield */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp =3D DISAS_YIELD; - } - break; - case 3: /* wfi */ - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp =3D DISAS_WFI; - break; - case 2: /* wfe */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp =3D DISAS_WFE; - } - break; - case 4: /* sev */ - case 5: /* sevl */ - /* TODO: Implement SEV, SEVL and WFE. May help SMP performance. = */ - default: /* nop */ - break; - } -} - #define CPU_V001 cpu_V0, cpu_V0, cpu_V1 =20 static inline void gen_neon_add(int size, TCGv_i32 t0, TCGv_i32 t1) @@ -8168,19 +8128,40 @@ DO_SMLAWX(SMLAWT, 1, 1) =20 static bool trans_YIELD(DisasContext *s, arg_YIELD *a) { - gen_nop_hint(s, 1); + /* + * When running single-threaded TCG code, use the helper to ensure that + * the next round-robin scheduled vCPU gets a crack. When running in + * MTTCG we don't generate jumps to the helper as it won't affect the + * scheduling of other vCPUs. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp =3D DISAS_YIELD; + } return true; } =20 static bool trans_WFE(DisasContext *s, arg_WFE *a) { - gen_nop_hint(s, 2); + /* + * When running single-threaded TCG code, use the helper to ensure that + * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we + * just skip this instruction. Currently the SEV/SEVL instructions, + * which are *one* of many ways to wake the CPU from WFE, are not + * implemented so we can't sleep like WFI does. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp =3D DISAS_WFE; + } return true; } =20 static bool trans_WFI(DisasContext *s, arg_WFI *a) { - gen_nop_hint(s, 3); + /* For WFI, halt the vCPU until an IRQ. */ + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp =3D DISAS_WFI; return true; } =20 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567022228; cv=none; d=zoho.com; s=zohoarc; b=i3NwTM7J412q0TPEbSLFJEOVur9Oo2cgbHkekyxWKXgAcODcwOoCK2eepqmFt0P1oYVOyeCGdjgBtVattf7Q1m/nWBi4gUisgbayP78XDV/zdnFcHO7VBfD5eARvuHwxVrCXqWtAxQJ64Ivy0t5JavreySbEihT1GyPbNjVjPUY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567022228; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Zg8dzU0/CFYfa/kdfJbWaGoOPylTikiwN65K71SZiLc=; b=K4va/7Y15pIUhSyxcHVFA22T0X6mV1Cl1Ysll9ryDv5dUFWtTkj352DNg4F3pSC20b5T+Su/EzelytVO8Z1aH0Ppivski10Csa5jmzRnKuIkhUDkSUSPxxOe7NP/49FH870hY4wWlgl/WVTIisL9iyXxxuvqvEuuk4Si3iHF4BQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567022228717344.07320191169106; Wed, 28 Aug 2019 12:57:08 -0700 (PDT) Received: from localhost ([::1]:41812 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i3443-0004mi-8V for importer@patchew.org; Wed, 28 Aug 2019 15:57:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38920) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33Gz-00041W-E7 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33Gu-0000l2-Rm for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:23 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:39448) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33Gt-0000iv-Id for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:20 -0400 Received: by mail-pf1-x42a.google.com with SMTP id y200so390956pfb.6 for ; Wed, 28 Aug 2019 12:06:18 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.06.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:06:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Zg8dzU0/CFYfa/kdfJbWaGoOPylTikiwN65K71SZiLc=; b=uKQHazugJxEVXAFBp+BiR4/sgmEW8QSorrKeZ3Yx2yLLK2xwROlnI+wVUtKN/TVEcp bnH4EhcPwQ3RixW0GhMFALQKMo5BN77kFGvP6M/igpGBDvIQAmb9k6DHWVlJyKKwrLU3 Xs+jUFddsX3OTH16kbVnFS4vB002s/BZIm9mVwMis9Urie68HkNYUDCKS8rzB/rYK8pi Z02WsIG30NfYrlgyP6WLBrd6Vbun8dhMFnmR4CYCxUL1FuFynjo2UnaNQUv54v8Ajnzk zdgE8qAqTgs5rBIeOF/GjBVMGaW8vGRAPygFLWMOL8ZUkxA13GeKOok+SNhaGP6HgBYo RbPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Zg8dzU0/CFYfa/kdfJbWaGoOPylTikiwN65K71SZiLc=; b=TK7ka90ep5P6YWjZO+3gXfVO6sqp1noQA4x1l8iAVTtoBfeoyMIOUdW84raUrVoAln 6Qj5wL63oUBpLTkV7eH3TTov53tvqY5gMAOZhPx5xIprsOS1n5ez2dB1pyAidKhYLty2 J2bHg6GprT8oo/hdogx/iP2ucgCqTQnogyOu+/tLTpKKTKWKaVZkv+EZKmpsC6zYPTQO lJpTT/PfOiKqAsBaCXEklAcnMs2Uukuv6YdcBS3ddhSXCPCGDCzVcCejiXW6aReff7zg yzEOUZpCjcjNa54uUQSGYE50z2Rd3bPtqMVhx0VkfTSXy1hHN9bcuHGBXlE5VbwxRuHg eolQ== X-Gm-Message-State: APjAAAVkCROqPdfH+Sfnoy3CK/12pBXiCCxmMF5sE/TNgvGoOBYChQrj Wx4PofoJFq8Ghy9nHSLAbhYPLDMMk2E= X-Google-Smtp-Source: APXvYqzWWT+x1KVF+KeBlpIAeF8AHxpkNBPFKPF2QIEAEywdaKurEwAhxLdPSY0WKFFY/G/3ydhVJQ== X-Received: by 2002:a62:7996:: with SMTP id u144mr6564180pfc.228.1567019177273; Wed, 28 Aug 2019 12:06:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:48 -0700 Message-Id: <20190828190456.30315-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PATCH v3 61/69] target/arm: Convert T16, push and pop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 83 ++++++------------------------------------ target/arm/t16.decode | 10 +++++ 2 files changed, 22 insertions(+), 71 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index c7d7834440..5ee4dfe3a2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7490,6 +7490,16 @@ static int t16_setflags(DisasContext *s) return s->condexec_mask =3D=3D 0; } =20 +static int t16_push_list(DisasContext *s, int x) +{ + return (x & 0xff) | (x & 0x100) << (14 - 8); +} + +static int t16_pop_list(DisasContext *s, int x) +{ + return (x & 0xff) | (x & 0x100) << (15 - 8); +} + /* * Include the generated decoders. */ @@ -10690,7 +10700,6 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) { uint32_t val, op, rm, rd, shift, cond; int32_t offset; - int i; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10763,76 +10772,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) goto illegal_op; =20 case 4: case 5: case 0xc: case 0xd: - /* - * 0b1011_x10x_xxxx_xxxx - * - push/pop - */ - addr =3D load_reg(s, 13); - if (insn & (1 << 8)) - offset =3D 4; - else - offset =3D 0; - for (i =3D 0; i < 8; i++) { - if (insn & (1 << i)) - offset +=3D 4; - } - if ((insn & (1 << 11)) =3D=3D 0) { - tcg_gen_addi_i32(addr, addr, -offset); - } - - if (s->v8m_stackcheck) { - /* - * Here 'addr' is the lower of "old SP" and "new SP"; - * if this is a pop that starts below the limit and ends - * above it, it is UNKNOWN whether the limit check trigger= s; - * we choose to trigger. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - for (i =3D 0; i < 8; i++) { - if (insn & (1 << i)) { - if (insn & (1 << 11)) { - /* pop */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, i, tmp); - } else { - /* push */ - tmp =3D load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - /* advance to the next address. */ - tcg_gen_addi_i32(addr, addr, 4); - } - } - tmp =3D NULL; - if (insn & (1 << 8)) { - if (insn & (1 << 11)) { - /* pop pc */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - /* don't set the pc until the rest of the instruction - has completed */ - } else { - /* push lr */ - tmp =3D load_reg(s, 14); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_gen_addi_i32(addr, addr, 4); - } - if ((insn & (1 << 11)) =3D=3D 0) { - tcg_gen_addi_i32(addr, addr, -offset); - } - /* write back the new stack pointer */ - store_reg(s, 13, addr); - /* set the new PC value */ - if ((insn & 0x0900) =3D=3D 0x0900) { - store_reg_from_load(s, 15, tmp); - } - break; + /* push/pop, in decodetree */ + goto illegal_op; =20 case 1: case 3: case 9: case 11: /* czb */ rm =3D insn & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 5829b9a58c..55fadce223 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -221,3 +221,13 @@ REVSH 1011 1010 11 ... ... @rdm # rest of the space is a reserved hint, behaves as nop. NOP 1011 1111 ---- 0000 } + +# Push and Pop + +%push_list 0:9 !function=3Dt16_push_list +%pop_list 0:9 !function=3Dt16_pop_list + +STM 1011 010 ......... \ + &ldst_block i=3D0 b=3D1 u=3D0 w=3D1 rn=3D13 list=3D%push_l= ist +LDM_t16 1011 110 ......... \ + &ldst_block i=3D1 b=3D0 u=3D0 w=3D1 rn=3D13 list=3D%pop_li= st --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567022708; cv=none; d=zoho.com; s=zohoarc; b=Cfy3mHiPJGU9uQagnd2cF+WrVuLpFd5w5IsgfE3lM8oLBpKHAoJ9DD6/Euwpo/rfV6tGmrYncwQGmzYhBnlbzVwCPHsCpYcZSKa7LlxshB2hyo8zcyCBq/U2O+C9D0j1urzc8cALVUtzGzSl9lbZUb0tyVxqTycoAhxr0vskn30= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567022708; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=0cedwX4DK0/sfFpeHztWA8eKQ1Bah4RqDcJrQgER7Gk=; b=HpSvTPN6s6BLe6zP6StZly+mSCu3aJbaZzYqQqamo80N/BnE7qPAFeCcOtd8MKyM7GMKKaNb5ggZnEET/J1YLYeRKwVfAF6kEk7osxIzk3wsD19Rg0AuBWxudnP6Rj4O8UFjSONUkQJHBDaRjNlABPCQ6F1k4nytn4ZKijWwVaE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567022708431447.16500816184407; Wed, 28 Aug 2019 13:05:08 -0700 (PDT) Received: from localhost ([::1]:41952 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i34Bm-0003fv-UY for importer@patchew.org; Wed, 28 Aug 2019 16:05:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38923) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33H0-00041Y-E4 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33Gw-0000lh-EC for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:24 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:40936) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33Gu-0000js-JN for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:20 -0400 Received: by mail-pg1-x541.google.com with SMTP id w10so218118pgj.7 for ; Wed, 28 Aug 2019 12:06:19 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 62/69] target/arm: Convert T16, Conditional branches, Supervisor call X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 +++----------------------- target/arm/t16.decode | 12 ++++++++++++ 2 files changed, 15 insertions(+), 23 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5ee4dfe3a2..854c9fe10d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10698,7 +10698,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rd, shift, cond; + uint32_t val, op, rm, rd, shift; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10837,28 +10837,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) } break; =20 - case 13: - /* conditional branch or swi */ - cond =3D (insn >> 8) & 0xf; - if (cond =3D=3D 0xe) - goto undef; - - if (cond =3D=3D 0xf) { - /* swi */ - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm =3D extract32(insn, 0, 8); - s->base.is_jmp =3D DISAS_SWI; - break; - } - /* generate a conditional jump to next instruction */ - arm_skip_unless(s, cond); - - /* jump to the offset */ - val =3D read_pc(s); - offset =3D ((int32_t)insn << 24) >> 24; - val +=3D offset << 1; - gen_jmp(s, val); - break; + case 13: /* conditional branch or swi, in decodetree */ + goto illegal_op; =20 case 14: if (insn & (1 << 11)) { diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 55fadce223..cbc64f4e48 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -28,11 +28,13 @@ &rr !extern rd rm &ri !extern rd imm &r !extern rm +&i !extern imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list &setend !extern E &cps !extern mode imod M A I F +&ci !extern cond imm =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -231,3 +233,13 @@ STM 1011 010 ......... \ &ldst_block i=3D0 b=3D1 u=3D0 w=3D1 rn=3D13 list=3D%push_l= ist LDM_t16 1011 110 ......... \ &ldst_block i=3D1 b=3D0 u=3D0 w=3D1 rn=3D13 list=3D%pop_li= st + +# Conditional branches, Supervisor call + +%imm8_0x2 0:s8 !function=3Dtimes_2 + +{ + UDF 1101 1110 ---- ---- + SVC 1101 1111 imm:8 &i + B_cond_thumb 1101 cond:4 ........ &ci imm=3D%imm8_0x2 +} --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::431 Subject: [Qemu-devel] [PATCH v3 63/69] target/arm: Convert T16, Miscellaneous 16-bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Split firstcond & mask within trans_IT. --- target/arm/translate.c | 111 +++++++++++++---------------------------- target/arm/t16.decode | 29 +++++++---- 2 files changed, 54 insertions(+), 86 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 854c9fe10d..5fb0e2066b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10163,6 +10163,18 @@ static bool trans_TBH(DisasContext *s, arg_tbranch= *a) return op_tbranch(s, a, true); } =20 +static bool trans_CBZ(DisasContext *s, arg_CBZ *a) +{ + TCGv_i32 tmp =3D load_reg(s, a->rn); + + arm_gen_condlabel(s); + tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE, + tmp, 0, s->condlabel); + tcg_temp_free_i32(tmp); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + /* * Supervisor call */ @@ -10394,6 +10406,27 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a) return ENABLE_ARCH_7; } =20 +/* + * If-then + */ + +static bool trans_IT(DisasContext *s, arg_IT *a) +{ + int cond_mask =3D a->cond_mask; + + /* + * No actual code generated for this insn, just setup state. + * + * Combinations of firstcond and mask which set up an 0b1111 + * condition are UNPREDICTABLE; we take the CONSTRAINED + * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, + * i.e. both meaning "execute always". + */ + s->condexec_cond =3D (cond_mask >> 4) & 0xe; + s->condexec_mask =3D cond_mask & 0x1f; + return true; +} + /* * Legacy decoder. */ @@ -10760,83 +10793,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ case 10: /* add PC/SP (immediate), in decodetree */ + case 11: /* misc, in decodetree */ case 12: /* load/store multiple, in decodetree */ - goto illegal_op; - - case 11: - /* misc */ - op =3D (insn >> 8) & 0xf; - switch (op) { - case 0: /* add/sub (sp, immediate), in decodetree */ - case 2: /* sign/zero extend, in decodetree */ - goto illegal_op; - - case 4: case 5: case 0xc: case 0xd: - /* push/pop, in decodetree */ - goto illegal_op; - - case 1: case 3: case 9: case 11: /* czb */ - rm =3D insn & 7; - tmp =3D load_reg(s, rm); - arm_gen_condlabel(s); - if (insn & (1 << 11)) - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel); - else - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel); - tcg_temp_free_i32(tmp); - offset =3D ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3; - gen_jmp(s, read_pc(s) + offset); - break; - - case 15: /* IT, nop-hint. */ - if ((insn & 0xf) =3D=3D 0) { - goto illegal_op; /* nop hint, in decodetree */ - } - /* - * IT (If-Then) - * - * Combinations of firstcond and mask which set up an 0b1111 - * condition are UNPREDICTABLE; we take the CONSTRAINED - * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, - * i.e. both meaning "execute always". - */ - s->condexec_cond =3D (insn >> 4) & 0xe; - s->condexec_mask =3D insn & 0x1f; - /* No actual code generated for this insn, just setup state. = */ - break; - - case 0xe: /* bkpt */ - { - int imm8 =3D extract32(insn, 0, 8); - ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true)); - break; - } - - case 0xa: /* rev, and hlt */ - { - int op1 =3D extract32(insn, 6, 2); - - if (op1 =3D=3D 2) { - /* HLT */ - int imm6 =3D extract32(insn, 0, 6); - - gen_hlt(s, imm6); - break; - } - - /* Otherwise this is rev, in decodetree */ - goto illegal_op; - } - - case 6: /* setend, cps; in decodetree */ - goto illegal_op; - - default: - goto undef; - } - break; - case 13: /* conditional branch or swi, in decodetree */ goto illegal_op; =20 @@ -10892,7 +10850,6 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) } return; illegal_op: -undef: unallocated_encoding(s); } =20 diff --git a/target/arm/t16.decode b/target/arm/t16.decode index cbc64f4e48..f128110dee 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -211,19 +211,30 @@ REVSH 1011 1010 11 ... ... @rdm # Hints =20 { - YIELD 1011 1111 0001 0000 - WFE 1011 1111 0010 0000 - WFI 1011 1111 0011 0000 + { + YIELD 1011 1111 0001 0000 + WFE 1011 1111 0010 0000 + WFI 1011 1111 0011 0000 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1011 1111 0100 0000 - # SEVL 1011 1111 0101 0000 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1011 1111 0100 0000 + # SEVL 1011 1111 0101 0000 =20 - # The canonical nop has the second nibble as 0000, but the whole of the - # rest of the space is a reserved hint, behaves as nop. - NOP 1011 1111 ---- 0000 + # The canonical nop has the second nibble as 0000, but the whole of the + # rest of the space is a reserved hint, behaves as nop. + NOP 1011 1111 ---- 0000 + } + IT 1011 1111 cond_mask:8 } =20 +# Miscellaneous 16-bit instructions + +%imm6_9_3 9:1 3:5 !function=3Dtimes_2 + +HLT 1011 1010 10 imm:6 &i +BKPT 1011 1110 imm:8 &i +CBZ 1011 nz:1 0.1 ..... rn:3 imm=3D%imm6_9_3 + # Push and Pop =20 %push_list 0:9 !function=3Dt16_push_list --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v3 64/69] target/arm: Convert T16, shift immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.c | 26 ++------------------------ target/arm/t16.decode | 8 ++++++++ 2 files changed, 10 insertions(+), 24 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5fb0e2066b..dd292b3042 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10731,7 +10731,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rd, shift; + uint32_t val, rd; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10743,29 +10743,7 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) /* fall back to legacy decoder */ =20 switch (insn >> 12) { - case 0: case 1: - - rd =3D insn & 7; - op =3D (insn >> 11) & 3; - if (op =3D=3D 3) { - /* - * 0b0001_1xxx_xxxx_xxxx - * - Add, subtract (three low registers) - * - Add, subtract (two low registers and immediate) - * In decodetree. - */ - goto illegal_op; - } else { - /* shift immediate */ - rm =3D (insn >> 3) & 7; - shift =3D (insn >> 6) & 0x1f; - tmp =3D load_reg(s, rm); - gen_arm_shift_im(tmp, op, shift, s->condexec_mask =3D=3D 0); - if (!s->condexec_mask) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - } - break; + case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree = */ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ goto illegal_op; case 4: diff --git a/target/arm/t16.decode b/target/arm/t16.decode index f128110dee..79a1d66d6c 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -126,6 +126,14 @@ ADD_rri 10101 rd:3 ........ \ STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm =20 +# Shift (immediate) + +@shift_i ..... shim:5 rm:3 rd:3 &s_rrr_shi %s rn=3D%reg_0 + +MOV_rxri 000 00 ..... ... ... @shift_i shty=3D0 # LSL +MOV_rxri 000 01 ..... ... ... @shift_i shty=3D1 # LSR +MOV_rxri 000 10 ..... ... ... @shift_i shty=3D2 # ASR + # Add/subtract (three low registers) =20 @addsub_3 ....... rm:3 rn:3 rd:3 \ --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.06.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:06:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ijHYxCUn6f0ZOEbuhhCiCPGi01F+vFhNmSbEgOS+/68=; b=vqHQQrXGPGevYm38GhQ67ZOa0a/PVes8aUV0mGiHniBhkDzKBG8RTmPdSixRXGGj8B nmjmF9+KOViNCTK6GYNRBv6pxQuVDh71NHSoxxdZllQK9BN1lbKcGjBQ3Y3g9SEqlThN S+MYgHJ7JWqVx/3D43TXqOz7JbhTfeS9N+amhptFeqqFSxZXRuAJe7jv5A92qHMLrc5J ySfzS00gkazwf2cXMq5fUEtiYvn6/KMAVALs5b3wCsCekfSau/kW40kqhCneXBr9woOx DozSFl3zj4z9M6WjMbArPFXLOTyChYQ9kvP3MlEze6r6mWm7x6PPGJx2PmI1eXSVQQo1 F4Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ijHYxCUn6f0ZOEbuhhCiCPGi01F+vFhNmSbEgOS+/68=; b=ahKqU9F7BOclZuLmbbuLxGuJwSxPJxVFVJjZ+VprZNGpVBJv/6ENQ1LGbXXbYpLuos /w3G/2OjYRwImDycm8UPJYDxencGsQ2UC+QVHyz/Iq8bl54OfU3QV0LKcZqK+G5b9+4J r3pyH65u40ewVwWGvcdoiCdkq5fpVC202YmRn6HaxnBYOQxdYj6Pzg8nm+bKyzG1Glct mdX3DpJr8F8/+ZDIkpGUNeKfxOicUMAdfSZahod6rtv10xfBTrWmKeI+s2mQzXLemMKR mFmsyJ1bIo20aLxtyryfxZsKkDYemMnT1jJPYcD7+81WddLUW4ccpuJMhBoPdZouRVL0 4rTg== X-Gm-Message-State: APjAAAWZ5HAOYqu/C2bA+QZezIBNSVdWl+bSkAf3MABG1ShD7HExnazw LhM47MgFH95wGU4qjODAXpOhInFwOx0= X-Google-Smtp-Source: APXvYqygtfIv+SGMZvwX9jAcDcdTLzaRoFk0K9alxqK3kCoLIQ36fH+8wS9I5Nimdf9bNobyZQQL3w== X-Received: by 2002:a17:902:74c7:: with SMTP id f7mr1749065plt.263.1567019181992; Wed, 28 Aug 2019 12:06:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:52 -0700 Message-Id: <20190828190456.30315-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 65/69] target/arm: Convert T16, load (literal) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 42 ++---------------------------------------- target/arm/t16.decode | 4 ++++ 2 files changed, 6 insertions(+), 40 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index dd292b3042..fe9f7e4f42 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -963,14 +963,6 @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, = TCGv_i32 val, \ TCGv_i32 a32, int index) \ { \ gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \ -} \ -static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \ - TCGv_i32 val, \ - TCGv_i32 a32, int index, \ - ISSInfo issinfo) \ -{ \ - gen_aa32_ld##SUFF(s, val, a32, index); \ - disas_set_da_iss(s, OPC, issinfo); \ } =20 #define DO_GEN_ST(SUFF, OPC) \ @@ -978,14 +970,6 @@ static inline void gen_aa32_st##SUFF(DisasContext *s, = TCGv_i32 val, \ TCGv_i32 a32, int index) \ { \ gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \ -} \ -static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \ - TCGv_i32 val, \ - TCGv_i32 a32, int index, \ - ISSInfo issinfo) \ -{ \ - gen_aa32_st##SUFF(s, val, a32, index); \ - disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \ } =20 static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) @@ -1034,9 +1018,7 @@ static inline void gen_aa32_st64(DisasContext *s, TCG= v_i64 val, gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data); } =20 -DO_GEN_LD(8s, MO_SB) DO_GEN_LD(8u, MO_UB) -DO_GEN_LD(16s, MO_SW) DO_GEN_LD(16u, MO_UW) DO_GEN_LD(32u, MO_UL) DO_GEN_ST(8, MO_UB) @@ -10731,11 +10713,10 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, rd; + uint32_t val; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 addr; =20 if (disas_t16(s, insn)) { return; @@ -10745,26 +10726,7 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) switch (insn >> 12) { case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree = */ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ - goto illegal_op; - case 4: - if (insn & (1 << 11)) { - rd =3D (insn >> 8) & 7; - /* load pc-relative. Bit 1 of PC is ignored. */ - addr =3D add_reg_for_lit(s, 15, (insn & 0xff) * 4); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), - rd | ISSIs16Bit); - tcg_temp_free_i32(addr); - store_reg(s, rd, tmp); - break; - } - - /* - * - Data-processing (two low registers), in decodetree - * - data processing extended, branch and exchange, in decodetree - */ - goto illegal_op; - + case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree= */ case 5: /* load/store register offset, in decodetree */ case 6: /* load/store word immediate offset, in decodetree */ case 7: /* load/store byte immediate offset, in decodetree */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 79a1d66d6c..0b4da411e0 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -113,6 +113,10 @@ LDRH_ri 10001 ..... ... ... @ldst_= ri_2 STR_ri 10010 ... ........ @ldst_spec_i rn=3D13 LDR_ri 10011 ... ........ @ldst_spec_i rn=3D13 =20 +# Load (PC-relative) + +LDR_ri 01001 ... ........ @ldst_spec_i rn=3D15 + # Add PC/SP (immediate) =20 ADR 10100 rd:3 ........ imm=3D%imm8_0x4 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567023212; cv=none; d=zoho.com; s=zohoarc; b=NmAdaIKPL3qCrynqu4WmdXSS6Hos6c0BEei11hhIcFQSo8KYKxfQokDpUBYDSTdbf+LpFeLDGPXYph83D62Xt5mEhaZBshVn07u70viS8A6bpPOf7qMvL2N+ELFp8bMIkICCvutELEt/Fw20sPBu8GuxDfmHUs60AW7UtplWR5U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567023212; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Lx+8GdSOm4AFV3gPcXa/Gz1WHaL2tglqVzn+6pptTZA=; b=TkRriQXYYbDlHRfTz4eNHAAVN2NMewvPlwfqi5w3M/L47jI1coLZwOxsaLy7rVxrXq8hYh1C2G58MwfP7juT6s8XymQpUKntXbtubvGINTrHfgaoQ8M3MMA48CXwARw/AnloD0zBmJy/x7ziAy3Ux8LUc8P4Cn1XCoftUpChw/4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567023212593266.66343777995223; Wed, 28 Aug 2019 13:13:32 -0700 (PDT) Received: from localhost ([::1]:42090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i34Jt-0004P6-AH for importer@patchew.org; Wed, 28 Aug 2019 16:13:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39034) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33H3-00044u-7f for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33H0-0000pC-TA for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:28 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:39459) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33H0-0000mv-Dt for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:26 -0400 Received: by mail-pf1-x435.google.com with SMTP id y200so391139pfb.6 for ; Wed, 28 Aug 2019 12:06:24 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.06.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:06:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Lx+8GdSOm4AFV3gPcXa/Gz1WHaL2tglqVzn+6pptTZA=; b=EwFti39eQXHd8pj+7tYzrtWdwD06ZkjllFuQS6SE/1jq89J3rlwXZBViLNyNVTSfx+ rnMNhskIAtiyZKBufQMiCXj6GD2OXMqNybObMG4TZNpxyPc9Byd/KB+WBLHY9uBil2xv Pnvpp39xJym8N5egXpnaKYRfvHx3EchvNodm0YseCXClxud0tX2fKiz7wcOOYLQF4s0u 4f8wg06d/XSddypNw0DSpLGhALIF4FR6JwBMrQCFVBadlmnzV459sNklCekm+oeZKaLC iVbNtDNXpXKf8SHnYMdwm17bnCISmmYDm2RxVFfPXnsZfhQRPY52ZrtX8HAc+uZ97e6f bXAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Lx+8GdSOm4AFV3gPcXa/Gz1WHaL2tglqVzn+6pptTZA=; b=Rozzib62CIyEDPWx5WHRGD8dvfRuTxvctBVmpTkErUouMDtzvpG8+ss0DpmWq0kdun GecgYQ3a0LV2KZVNU9CLBS5uMhgm60NvpEgSDwfZYjy2AucdvfxyKVoCvvjMc/O0mGgK JL47GcSPyDPn50i/XoIQFcLl0zAAomy1+NH0xrKoe5GF2uiMtjyZNRX/GUItLg9S7Dni e8pz8gsTfY37Zc5lroMH4j0dqU+bB4GeqWd2Hj5WN8ThV8tbhqY8Vv9synvEtoUAJrjJ Unvdhpfc1HkvbGcHp88IzQu76eiiJ/J/Lp2+bu6Is6ShSZmhq2ZRrnkmhfSP3oCTyEWN D/jQ== X-Gm-Message-State: APjAAAVvy1dTLtQNeRXJkKl6vDjBfaSKDrMWBgrpl36LMYFumJe4+WDr Et0mM6JY0Ic+JwYatYVIFWqxHTOdNhw= X-Google-Smtp-Source: APXvYqxO445495BGlIVyjWle21YmKjTicegIqNUxPk33IqMkOmvKRFYeNS9BD5ofM+WMhPkSIX78PA== X-Received: by 2002:a62:1858:: with SMTP id 85mr6656045pfy.120.1567019183524; Wed, 28 Aug 2019 12:06:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:53 -0700 Message-Id: <20190828190456.30315-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::435 Subject: [Qemu-devel] [PATCH v3 66/69] target/arm: Convert T16, Unconditional branch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 9 ++------- target/arm/t16.decode | 6 ++++++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index fe9f7e4f42..574a791461 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10713,7 +10713,6 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10757,12 +10756,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) gen_bx(s, tmp); break; } - /* unconditional branch */ - val =3D read_pc(s); - offset =3D ((int32_t)insn << 21) >> 21; - val +=3D offset << 1; - gen_jmp(s, val); - break; + /* unconditional branch, in decodetree */ + goto illegal_op; =20 case 15: /* thumb_insn_is_16bit() ensures we can't get here for diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 0b4da411e0..a4c89dba61 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -266,3 +266,9 @@ LDM_t16 1011 110 ......... \ SVC 1101 1111 imm:8 &i B_cond_thumb 1101 cond:4 ........ &ci imm=3D%imm8_0x2 } + +# Unconditional Branch + +%imm11_0x2 0:s11 !function=3Dtimes_2 + +B 11100 ........... &i imm=3D%imm11_0x2 --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567023174; cv=none; d=zoho.com; s=zohoarc; b=jhnsyozQNFepzP+B8dOMbkKPOsyVcAaVuW4l2HTFEVE8tL7snoCF1wPuuXrhxWpJbnjOWukUB9os7wRN9pNJqpfwwXNMdDeRL1ODHJnJigvcbdK93SP4mq1h+4O49r/AEzppUzRI0BbM5V7chT1LARhJemDB8YDkNeky97JDxAo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567023174; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=o8JoQg7nIgQDPaTkLH+nSqJkD4bKhobBAH7LTYEZxrk=; b=Fjg5r91Jl62DAPbZoPhrMZP+lXGRgbe1jYs3kU7Lg9JxXUnUFu3o/UW0YB/XDepta4WJMWYiOffp4eqdXkVpWgqCffgRQvTkNzqSh4J4S2oYnekkp0X6F3f/SiFBZm2Ib7MRTV+YvNndsyGEFFYnvlQHNS+sbhBPYrupUIQwMm4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567023174131584.4267108104373; Wed, 28 Aug 2019 13:12:54 -0700 (PDT) Received: from localhost ([::1]:42084 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i34JD-0003oZ-V6 for importer@patchew.org; Wed, 28 Aug 2019 16:12:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39078) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33H6-00048w-J4 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33H2-0000qN-He for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:30 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:43847) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33H1-0000nl-3P for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:27 -0400 Received: by mail-pl1-x62e.google.com with SMTP id 4so388729pld.10 for ; Wed, 28 Aug 2019 12:06:26 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.06.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:06:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=o8JoQg7nIgQDPaTkLH+nSqJkD4bKhobBAH7LTYEZxrk=; b=NHC7+M6myA6feaow8W9JrU4sOasU5/M9Ry6++rHR3Qf2joDZZAjOlrwyHxNHmGOMhw WNpO5yEpH3/12OCcdFHNKTuPZdcvxM9TP52jsj+YUTYWVI951jWAPwUt1QJVT6wkUQBu DedXtsqLqvuNGjvvHsZBZPpa6vCIIwIoyHO+41fJb8UmcN3qq/2ePJHPD8l6q7Jvgb/s ATXL1mpcdzfVBtaP+HkIECCUhAEcAq2odX87EaYmUmEnrmjOpyt1JVycVpuZ/kprGvE0 Ksl75NvWiOr4btIGizZ2zvtPQkuw5zn4GK2mBN1K+8wCD44/PyWVy9FUfzbrFoRXx4WV c74Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=o8JoQg7nIgQDPaTkLH+nSqJkD4bKhobBAH7LTYEZxrk=; b=dDzLsi3psci/IY/TA1rqxN4ufB/WiKKoTV11JHfrtgkuzkK6VzHKVHk4leXZ5g8zj/ YFLEg24pRKp6CwUeAzHDBuKsYOX0RKb+1bVbpNPkPGEfVDdIuJtmAXFiJnGUlFsjS0IV FCTGzE6yE2nV82l0H6F3R3US4OvakDTVnGp83YtlMOvh702l7VnNsvgDqBRat9Qsw7QF x1vEEI+nnEBLZd5Ce4mHHsWoMOLIr2jrn+yVoMxQ8Yb4YZr82Z+ZTHz0SOst1Ni8gEQ5 UTGOpq1O5h5TrRPvTFXBf6et2iXtzJ2sbckw6vr2lWih3YP07ifBOellZrEfLdvebmMV +Lmg== X-Gm-Message-State: APjAAAVtHuCkq9yGPRTXCx0+hp+LvLJV+w+PRQs8Wai2NNtCA10MeskT iVUixVX38iO7VPdI4vSfkli1ly2pwdw= X-Google-Smtp-Source: APXvYqzudfvFW4Xs7QfETMsqqqcPFbuFW+Iix1qxnyb+1qG0dMbm7Q/GaKjEfhDJQ/ST9TXtqDK63g== X-Received: by 2002:a17:902:eb:: with SMTP id a98mr5544096pla.75.1567019184572; Wed, 28 Aug 2019 12:06:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:54 -0700 Message-Id: <20190828190456.30315-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62e Subject: [Qemu-devel] [PATCH v3 67/69] target/arm: Convert T16, long branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 85 ++++++++++++++++++------------------------ target/arm/t16.decode | 7 ++++ 2 files changed, 43 insertions(+), 49 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 574a791461..424a8354c1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10114,6 +10114,40 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i= *a) return true; } =20 +static bool trans_BL_BLX_prefix(DisasContext *s, arg_BL_BLX_prefix *a) +{ + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + tcg_gen_movi_i32(cpu_R[14], read_pc(s) + (a->imm << 12)); + return true; +} + +static bool trans_BL_suffix(DisasContext *s, arg_BL_suffix *a) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + tcg_gen_addi_i32(tmp, cpu_R[14], (a->imm << 1) | 1); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_bx(s, tmp); + return true; +} + +static bool trans_BLX_suffix(DisasContext *s, arg_BLX_suffix *a) +{ + TCGv_i32 tmp; + + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + if (!ENABLE_ARCH_5) { + return false; + } + tmp =3D tcg_temp_new_i32(); + tcg_gen_addi_i32(tmp, cpu_R[14], a->imm << 1); + tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_bx(s, tmp); + return true; +} + static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) { TCGv_i32 addr, tmp; @@ -10713,10 +10747,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - int32_t offset; - TCGv_i32 tmp; - TCGv_i32 tmp2; - if (disas_t16(s, insn)) { return; } @@ -10735,53 +10765,10 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) case 11: /* misc, in decodetree */ case 12: /* load/store multiple, in decodetree */ case 13: /* conditional branch or swi, in decodetree */ - goto illegal_op; - case 14: - if (insn & (1 << 11)) { - /* thumb_insn_is_16bit() ensures we can't get here for - * a Thumb2 CPU, so this must be a thumb1 split BL/BLX: - * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF) - */ - assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - ARCH(5); - offset =3D ((insn & 0x7ff) << 1); - tmp =3D load_reg(s, 14); - tcg_gen_addi_i32(tmp, tmp, offset); - tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); - - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next | 1); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - break; - } - /* unconditional branch, in decodetree */ - goto illegal_op; - case 15: - /* thumb_insn_is_16bit() ensures we can't get here for - * a Thumb2 CPU, so this must be a thumb1 split BL/BLX. - */ - assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - - if (insn & (1 << 11)) { - /* 0b1111_1xxx_xxxx_xxxx : BL suffix */ - offset =3D ((insn & 0x7ff) << 1) | 1; - tmp =3D load_reg(s, 14); - tcg_gen_addi_i32(tmp, tmp, offset); - - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next | 1); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - } else { - /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */ - uint32_t uoffset =3D ((int32_t)insn << 21) >> 9; - - tcg_gen_movi_i32(cpu_R[14], read_pc(s) + uoffset); - } - break; + /* branches, in decodetree */ + goto illegal_op; } return; illegal_op: diff --git a/target/arm/t16.decode b/target/arm/t16.decode index a4c89dba61..43b9a267a1 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -272,3 +272,10 @@ LDM_t16 1011 110 ......... \ %imm11_0x2 0:s11 !function=3Dtimes_2 =20 B 11100 ........... &i imm=3D%imm11_0x2 + +# thumb_insn_is_16bit() ensures we won't be decoding these as +# T16 instructions for a Thumb2 CPU, so these patterns must be +# a Thumb1 split BL/BLX. +BLX_suffix 11101 imm:11 &i +BL_BLX_prefix 11110 imm:s11 &i +BL_suffix 11111 imm:11 &i --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.06.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:06:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AjmucdomfKxGM6hnf1R57zZqrIKHMIhApG2eFqmaHBc=; b=hD/ClnCCAfC+KrJCN3zA1EKEPJN/d9DDbG8Bp84tKpcHJTnJsIwyao2XyYMTIg2y/3 evkaafRRRCoL/ipAI5gLnCAtGxPunDFIBR8dxFDtIYT0a+oLEZWYKJTLWnPNhMlDutH7 /JAo2o7sdp9qddEo6PuDZX2+SPpubW7pIHPY/4TRhfO9LiVCkMyukUxiOpXAXxa1P0xi FgpkGIAV8m+XYbnDxSY2dUVVygxGsBedLTerZkSZEMwTtYpPVEc1GEJ/CpLkl17ZLj3Y pz9PA+IJ3RPv/3yyhaAEzk0LFE8L1GJGPWEcNQ6kdG5vQGeI9oZaY0cuJ6kaRUud2PVQ FWOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AjmucdomfKxGM6hnf1R57zZqrIKHMIhApG2eFqmaHBc=; b=p+GB5kHYeA8wj1b48DR9ALiHGXdqXusnwyP1LZ2Szr3A6E4pTQ0bwdb9Yz6FrWXnCD qlffQ/+RLP7vlJu1syg6h7MzW6831uynIhLr6icnC37rdTdzth+phI9VnJOkHkcvNlB/ OtrkNgAWMCSSBrZkzBODk8VmQAGhU1lOLw+7ncMC5Am9BvDTtCvR2FWPfCgp6sqSPz3r 0vY70F5OL1YKLH2RtFUtzqp15VLnAD8oiAk40EDzC6OJg9CJ5Uci3gxzidWSI2MkeBlQ D9qV649DH9SbHtCSyuC1ZZ47DPjSyDIsnsW2oRqehbDIlaBHvjYpIvoTvN0Fi7WsbbOF k5ew== X-Gm-Message-State: APjAAAVulD13Xs9mtm04nFLUmm7/0asjLi0RVRJBSBVLcsNzbtWMplro +do7dSrvPf35kKTjgKdwvkbdWKBd7fU= X-Google-Smtp-Source: APXvYqxZstl043K3i1YM53QVjxhJ2OOre9QAQtxBfwVJ8KjRmQqtEBzdNXTTgCRuKfLxbINefEebKg== X-Received: by 2002:a17:90a:b395:: with SMTP id e21mr5788048pjr.76.1567019185680; Wed, 28 Aug 2019 12:06:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:55 -0700 Message-Id: <20190828190456.30315-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 68/69] target/arm: Clean up disas_thumb_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that everything is converted, remove the rest of the legacy decode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 27 ++------------------------- 1 file changed, 2 insertions(+), 25 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 424a8354c1..5a9a6d3a1e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10747,32 +10747,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - if (disas_t16(s, insn)) { - return; + if (!disas_t16(s, insn)) { + unallocated_encoding(s); } - /* fall back to legacy decoder */ - - switch (insn >> 12) { - case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree = */ - case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ - case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree= */ - case 5: /* load/store register offset, in decodetree */ - case 6: /* load/store word immediate offset, in decodetree */ - case 7: /* load/store byte immediate offset, in decodetree */ - case 8: /* load/store halfword immediate offset, in decodetree */ - case 9: /* load/store from stack, in decodetree */ - case 10: /* add PC/SP (immediate), in decodetree */ - case 11: /* misc, in decodetree */ - case 12: /* load/store multiple, in decodetree */ - case 13: /* conditional branch or swi, in decodetree */ - case 14: - case 15: - /* branches, in decodetree */ - goto illegal_op; - } - return; -illegal_op: - unallocated_encoding(s); } =20 static bool insn_crosses_page(CPUARMState *env, DisasContext *s) --=20 2.17.1 From nobody Tue May 7 03:27:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567022780; cv=none; d=zoho.com; s=zohoarc; b=Gm8aDCQPK4Zj8oaUj5WhUUDfTMF5iCWV5BAXETN/xXO+r/dSdxZuKmISbINEmHfoAAqmtDn/sYClIJXg8wY5TXrdqQvtyS2Tp4MxQ0JusP7x0JKLfrjwtWy0PJfZbAi5GFBSs4UBAl8J+1+5K/+nzcnC+gNPrMn8brKXAlGDsPk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567022780; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=gHxh7NJ9ZDQD5ad3sh/ZYrxo8RnJxM/j1QAWPCspKQ8=; b=hqoHmwRIAv4lRKGkTq2MtApCzICXobVg1ticc1RHNeI4JSXx1pirdDN7UOQJdtVnHujRgjsjyuVDPOp5lToxihiqRlYYT/Mn9yFvWrfJvT4n61+/UMeIvjQbWy5zByNZDqDrqjGn2Ut8joWLHzitLcGLTWd0KumbUXcjo3zzLq8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567022780514260.8554249133646; Wed, 28 Aug 2019 13:06:20 -0700 (PDT) Received: from localhost ([::1]:41966 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i34Cw-0004ub-Um for importer@patchew.org; Wed, 28 Aug 2019 16:06:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39109) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i33H8-0004AC-0z for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i33H6-0000sm-KD for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:33 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:43394) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i33H5-0000pv-4m for qemu-devel@nongnu.org; Wed, 28 Aug 2019 15:06:32 -0400 Received: by mail-pl1-x642.google.com with SMTP id 4so388790pld.10 for ; Wed, 28 Aug 2019 12:06:28 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f27sm2967944pgm.60.2019.08.28.12.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2019 12:06:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gHxh7NJ9ZDQD5ad3sh/ZYrxo8RnJxM/j1QAWPCspKQ8=; b=jCb+9M3HZ8mMyUcbr7jvJ4BKrD6Mldz8iF22quWO5UNM3T/caBgOkNaKkOuP52mdkS rpSC6bnPRLSF4UbTvKiLJBnNEC7WFDphwL7+qjnRMJbc5oTuVRIohGQZmyDOKd//ok/+ kVJ+qq/XY+xVG7Y5uOrht+zJDeYwyt6P59/kib/Pqns+ZbnC4mLU8k0tI/OQuhGfEgsN Sy3xYwHe0ihKhfCaLwVakpplAGcFr03tWd/8fj5d4P9xVOVzsXmmIqI7ZNBSWbrX7vMd w6lW6dJ97hImbuQ2TatuJdvL/ppt6ZCyHLCOXjreefGXr77s/iMcuzBQtTlHg6NnYMO2 S9LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gHxh7NJ9ZDQD5ad3sh/ZYrxo8RnJxM/j1QAWPCspKQ8=; b=jLeEECvhbI3WBQ3VPy6Qt7z3Z/ZXHlOpzk3VlyGyO6ZkFsa2fmZ52GtXZrNM88rgSk PQHT/+ZNSl+TjaeU/divPjWUw48qYpmWH7b5Jt3nGgOPGfmmQ94Plwu/5jHQnqN6lVAX KXhPt8QXdeEI/PsoxUBlDxPyzh/I2NDkoMcCIM+wodlzdnnKc4YywPtZ3V7qY73FC7EV NPmHQaiwWxSHjAD6AjtPa0SYzeeRMC1UCjr52c33oSLTXQtAvjuRtOVGMFQDdF8V+urR fVBkqQbnM2EDs1Cqky9zzzjt9SAlvl2X1HWnKov11oy2oRWPVMFMN8aUzlRF5Y1RmG+/ uVxA== X-Gm-Message-State: APjAAAUIXYZFoEjh6o3nu5VuF0jTJoXkNj5uE9yG61TAyKYDn7gkMbWs 4yg/ObKhiNn8+TOHROdzGLSqZvnBHOE= X-Google-Smtp-Source: APXvYqyMVJVO9vo6O1Edw5z188wJGJzrUTjqjTqXwv0ORnN/YWpuVeqSgzjuZFrUfrI6c75KZ5ftgQ== X-Received: by 2002:a17:902:ff02:: with SMTP id f2mr5394995plj.99.1567019187200; Wed, 28 Aug 2019 12:06:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 12:04:56 -0700 Message-Id: <20190828190456.30315-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org> References: <20190828190456.30315-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 69/69] target/arm: Inline gen_bx_im into callers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There are only two remaining uses of gen_bx_im. In each case, we know the destination mode -- not changing in the case of gen_jmp or changing in the case of trans_BLX_i. Use this to simplify the surrounding code. For trans_BLX_i, use gen_jmp for the actual branch. For gen_jmp, use gen_set_pc_im to set up the single-step. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 +++++++------------------- 1 file changed, 7 insertions(+), 19 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5a9a6d3a1e..253f9f4142 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -765,21 +765,6 @@ static inline void gen_set_pc_im(DisasContext *s, targ= et_ulong val) tcg_gen_movi_i32(cpu_R[15], val); } =20 -/* Set PC and Thumb state from an immediate address. */ -static inline void gen_bx_im(DisasContext *s, uint32_t addr) -{ - TCGv_i32 tmp; - - s->base.is_jmp =3D DISAS_JUMP; - if (s->thumb !=3D (addr & 1)) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, addr & 1); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb)); - tcg_temp_free_i32(tmp); - } - tcg_gen_movi_i32(cpu_R[15], addr & ~1); -} - /* Set PC and Thumb state from var. var is marked as dead. */ static inline void gen_bx(DisasContext *s, TCGv_i32 var) { @@ -2706,9 +2691,8 @@ static inline void gen_jmp (DisasContext *s, uint32_t= dest) { if (unlikely(is_singlestepping(s))) { /* An indirect jump so that we still trigger the debug exception. = */ - if (s->thumb) - dest |=3D 1; - gen_bx_im(s, dest); + gen_set_pc_im(s, dest); + s->base.is_jmp =3D DISAS_JUMP; } else { gen_goto_tb(s, 0, dest); } @@ -10105,12 +10089,16 @@ static bool trans_BL(DisasContext *s, arg_i *a) =20 static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) { + TCGv_i32 tmp; + /* For A32, ARCH(5) is checked near the start of the uncond block. */ if (s->thumb && (a->imm & 2)) { return false; } tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); - gen_bx_im(s, (read_pc(s) & ~3) + a->imm + !s->thumb); + tmp =3D tcg_const_i32(!s->thumb); + store_cpu_field(tmp, thumb); + gen_jmp(s, (read_pc(s) & ~3) + a->imm); return true; } =20 --=20 2.17.1