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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id 81sm6325753pfx.111.2019.08.24.14.34.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Aug 2019 14:34:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QLLa7oQzyNor8g5gTrV1Ih0+YyC/eiYlSSeR+q2HgEY=; b=En1UUyrgUGT8iUh8n38uG58R3mBWmOF+zjaCpwoX6dTbq+TV/nuUJZy6g/2anJlf0m yz0Hmnb/aP7EsFJmjumP7523NCkpzJ3/hmzD4IDSb1y5yfJDfj6lKos/8KhW5GZxCcoV B0eTUU0g2G2I6csQmH+HlydAbkFWopqhhzTKTcRZxkHjgvsJf0ns1B5plu7ogbsng9P4 K3oTPml3fGYrncaScbYKL5uWIeYzQnyVAjckioCO732603remXhLPzQvzcuMoN7VSwNN DYgBjcBfQb/GFEGiJJyccA9WQHme3MxNhPMBd6FrmczzbznsA+nbELNgF5mIZDo4/oLU /gYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QLLa7oQzyNor8g5gTrV1Ih0+YyC/eiYlSSeR+q2HgEY=; b=tBfWrOh7hJeOOpM3r+ywxMZmz8GfCQOatRXtPXFyIouuilFUdqriQoyLIUl5dB2y1w 2BxjuX9SqAgbu6WXLqnxvFBWjETqEVwhTBVKUg6DEzr1PBASmFPtEQ6XG3ifRiLw8Gun IpQe0aD0DkT/hwwft2bw8B9a4hfVMI6XXehikGUzK+cKg0UC+qg+1mP7yuNDEYLRakCO jqwftMcv4QzF+pG/RoFUdXY333yZrD2nVBpbdFVxayRYAHsy5gfG/E6tlNXg7AqO2Nkr 6qhD6h1s+cFqR4iDLwWEl+0eJfb4x1OYtLyGk5Uk4d0G2F6SZvFdXhGlNZqguG79CIUO sW6A== X-Gm-Message-State: APjAAAVIxhDoiAzTP3dVihwGeqPmQie6PIaSOxj2Xv0nPZtSVCNTAdIx SrJ4Ng44Hc5iu4wlKHPTNLaBtfn9mog= X-Google-Smtp-Source: APXvYqzJyOCP37Tvq/hhE8kaF/4yp4yt38bEJcZR56jdXlxAVn/zYkIcHarrCC2EoUDA+jOvzvV3Qw== X-Received: by 2002:a62:35c6:: with SMTP id c189mr12431590pfa.96.1566682495598; Sat, 24 Aug 2019 14:34:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 24 Aug 2019 14:34:46 -0700 Message-Id: <20190824213451.31118-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190824213451.31118-1-richard.henderson@linaro.org> References: <20190824213451.31118-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 1/6] exec: Move user-only watchpoint stubs inline X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Let the user-only watchpoint stubs resolve to empty inline functions. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- include/hw/core/cpu.h | 23 +++++++++++++++++++++++ exec.c | 26 ++------------------------ 2 files changed, 25 insertions(+), 24 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 77fca95a40..6de688059d 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1070,12 +1070,35 @@ static inline bool cpu_breakpoint_test(CPUState *cp= u, vaddr pc, int mask) return false; } =20 +#ifdef CONFIG_USER_ONLY +static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr l= en, + int flags, CPUWatchpoint **watchpo= int) +{ + return -ENOSYS; +} + +static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, + vaddr len, int flags) +{ + return -ENOSYS; +} + +static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, + CPUWatchpoint *wp) +{ +} + +static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) +{ +} +#else int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint); int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, int flags); void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint= ); void cpu_watchpoint_remove_all(CPUState *cpu, int mask); +#endif =20 /** * cpu_get_address_space: diff --git a/exec.c b/exec.c index 53a15b7ad7..31fb75901f 100644 --- a/exec.c +++ b/exec.c @@ -1062,28 +1062,7 @@ static void breakpoint_invalidate(CPUState *cpu, tar= get_ulong pc) } #endif =20 -#if defined(CONFIG_USER_ONLY) -void cpu_watchpoint_remove_all(CPUState *cpu, int mask) - -{ -} - -int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, - int flags) -{ - return -ENOSYS; -} - -void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) -{ -} - -int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, - int flags, CPUWatchpoint **watchpoint) -{ - return -ENOSYS; -} -#else +#ifndef CONFIG_USER_ONLY /* Add a watchpoint. */ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint) @@ -1173,8 +1152,7 @@ static inline bool cpu_watchpoint_address_matches(CPU= Watchpoint *wp, =20 return !(addr > wpend || wp->vaddr > addrend); } - -#endif +#endif /* !CONFIG_USER_ONLY */ =20 /* Add a breakpoint. */ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, --=20 2.17.1 From nobody Fri May 3 06:04:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566682870; cv=none; d=zoho.com; s=zohoarc; b=NcdJIE/2PuJuyhbo1y7lOWHrS6iUExx37jCTPJgQ31XXI1+oguGHwh2nHTUqQDK3XtSCNqNRFYNo5+I909M7RleNe5DJf623ESa98T/Do+4O0TdI8XxVcY/G3Ap3fi6dkNn/DYB29l6qQt8FliniM/af8TGw32GlCO4iQDxjryY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id 81sm6325753pfx.111.2019.08.24.14.34.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Aug 2019 14:34:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4hy82QgJUYjjhSQJRivLUVd+yZYge9fg7c759/kiQtk=; b=r6nbMQmcsQngIJjNGcIIA3MBEIbWepuenJmElHgdCfEI77FMfVJXrGuwbAyXSO0FsX JEQwxU9awFnukcky7YvXV+T94J/5w09OtobnOqhHLAcKg41NouPeMO5HLR968sv88xOc dXG13rnadC69C7pKcF7nZsatTAtyViq6wnCM9FMxaChUL1sOvvnaGgrnFowQlk8s+UgQ h+BlgE3xdoOFax7SnjR7wjVvPZG/7rymlIDCBtKkWxlhqerVJZTDPMCeBa9EQc3ZKkvP U/1z5lztBG6m45HMd00KD6xADGMUc8yV77seml4VAMu8hADsIblcOGDj3J/l4lQ0N8eQ JMwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4hy82QgJUYjjhSQJRivLUVd+yZYge9fg7c759/kiQtk=; b=rg1KiDz4kl4GnZzs+wJya6gFmVsDt9lHJncq4bd1BN9CuAMIrGyzIuZY055gJkoz6h X+XV4Nu8Y+oK7vLqAjw1OdlUqyzLwU4a6qnye8Lzh2upu5W7vsIHgkxqwhlOeUTC81sg pD2+E/t1vLUrdj7TYjNdpaZrrWfMjiXM+2diwK8V61af1IPpZ/8K52xvt9be0a3qC+T8 yizPeQ513y+2LG5xPDtLrriw9cvEa8/rrSPwHhYs/aG2H/7mQMZHnk8fAfCO1wff+1HO Hvybc4cz00bB/4T1s2KXDgjxaqJuKtb81g4b1axNDPclO4dSFhSA33F05aWoJG1QOH8z r03w== X-Gm-Message-State: APjAAAV+R4Lws9o7MBVh/LElY5UGagRtC4VlrfOXF/ZWDOBEh3tRfGUQ CLClTyaByqhCBO2rsfiiYyEADesfR/k= X-Google-Smtp-Source: APXvYqyOTSvn+cgIXvJjzDIsV/kDwQrGmeu5o7kmsRiFIFQyXrVbDFKPBr4aRzzT8UFagobkJKA4zg== X-Received: by 2002:a62:e515:: with SMTP id n21mr12541230pff.186.1566682497057; Sat, 24 Aug 2019 14:34:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 24 Aug 2019 14:34:47 -0700 Message-Id: <20190824213451.31118-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190824213451.31118-1-richard.henderson@linaro.org> References: <20190824213451.31118-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::436 Subject: [Qemu-devel] [PATCH 2/6] exec: Factor out core logic of check_watchpoint() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: David Hildenbrand We want to perform the same checks in probe_write() to trigger a cpu exit before doing any modifications. We'll have to pass a PC. Signed-off-by: David Hildenbrand Reviewed-by: Richard Henderson Message-Id: <20190823100741.9621-9-david@redhat.com> [rth: Use vaddr for len, like other watchpoint functions; Move user-only stub to static inline.] Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 7 +++++++ exec.c | 26 ++++++++++++++++++-------- 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6de688059d..7bd8bed5b2 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1091,6 +1091,11 @@ static inline void cpu_watchpoint_remove_by_ref(CPUS= tate *cpu, static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) { } + +static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr l= en, + MemTxAttrs atr, int fl, uintptr_t = ra) +{ +} #else int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint); @@ -1098,6 +1103,8 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, int flags); void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint= ); void cpu_watchpoint_remove_all(CPUState *cpu, int mask); +void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, + MemTxAttrs attrs, int flags, uintptr_t ra); #endif =20 /** diff --git a/exec.c b/exec.c index 31fb75901f..cb6f5763dc 100644 --- a/exec.c +++ b/exec.c @@ -2789,11 +2789,10 @@ static const MemoryRegionOps notdirty_mem_ops =3D { }; =20 /* Generate a debug exception if a watchpoint has been hit. */ -static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int fl= ags) +void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, + MemTxAttrs attrs, int flags, uintptr_t ra) { - CPUState *cpu =3D current_cpu; CPUClass *cc =3D CPU_GET_CLASS(cpu); - target_ulong vaddr; CPUWatchpoint *wp; =20 assert(tcg_enabled()); @@ -2804,17 +2803,17 @@ static void check_watchpoint(int offset, int len, M= emTxAttrs attrs, int flags) cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); return; } - vaddr =3D (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; - vaddr =3D cc->adjust_watchpoint_address(cpu, vaddr, len); + + addr =3D cc->adjust_watchpoint_address(cpu, addr, len); QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - if (cpu_watchpoint_address_matches(wp, vaddr, len) + if (cpu_watchpoint_address_matches(wp, addr, len) && (wp->flags & flags)) { if (flags =3D=3D BP_MEM_READ) { wp->flags |=3D BP_WATCHPOINT_HIT_READ; } else { wp->flags |=3D BP_WATCHPOINT_HIT_WRITE; } - wp->hitaddr =3D vaddr; + wp->hitaddr =3D MAX(addr, wp->vaddr); wp->hitattrs =3D attrs; if (!cpu->watchpoint_hit) { if (wp->flags & BP_CPU && @@ -2829,11 +2828,14 @@ static void check_watchpoint(int offset, int len, M= emTxAttrs attrs, int flags) if (wp->flags & BP_STOP_BEFORE_ACCESS) { cpu->exception_index =3D EXCP_DEBUG; mmap_unlock(); - cpu_loop_exit(cpu); + cpu_loop_exit_restore(cpu, ra); } else { /* Force execution of one insn next time. */ cpu->cflags_next_tb =3D 1 | curr_cflags(); mmap_unlock(); + if (ra) { + cpu_restore_state(cpu, ra, true); + } cpu_loop_exit_noexc(cpu); } } @@ -2843,6 +2845,14 @@ static void check_watchpoint(int offset, int len, Me= mTxAttrs attrs, int flags) } } =20 +static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int fl= ags) +{ + CPUState *cpu =3D current_cpu; + vaddr addr =3D (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; + + cpu_check_watchpoint(cpu, addr, len, attrs, flags, 0); +} + /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, so these check for a hit then pass through to the normal out-of-line phys routines. */ --=20 2.17.1 From nobody Fri May 3 06:04:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566682632; cv=none; d=zoho.com; s=zohoarc; b=jjpwOF33G8wnkQ81hQvLLN3dyGKQElqH6ZLjyVHMVQAW37nxn87XwOaMwXnMJtoXKrcwOAw8rYVQaNikBj8EHLZtsgta6NdLa/iBMqnhpyCLFSGdTdfRFIZZxaH4m0oCJWj3qdbGZotiQM+GUYamxOed3EDt4Txgt0U9EE0BBxI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566682632; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=WeS2D0cuVBKG8KKN1319ExUviIRkQlB9pnf5dIabrik=; b=SQW1njoqDKlP4cRqZ/Co63Yhlo1evEMKOfp0aRIVdU12+T1kPqMyxg5yyCrXmPnwCap9gM3TtXaD8i1GHJeq6fPj8XyjXWGUfKNos98a12MZuyRCAdTs8OM62PWbYr3BAQzW1C+SHAA30OLsUV8znxfnoiXcBeo1dphwlhLrQcA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566682632487761.0570006051117; Sat, 24 Aug 2019 14:37:12 -0700 (PDT) Received: from localhost ([::1]:39488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i1dih-0002Ld-2O for importer@patchew.org; Sat, 24 Aug 2019 17:37:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36366) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i1dgg-0001M3-IH for qemu-devel@nongnu.org; Sat, 24 Aug 2019 17:35:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i1dge-00035V-GB for qemu-devel@nongnu.org; Sat, 24 Aug 2019 17:35:06 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:34517) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i1dga-000309-Mg for qemu-devel@nongnu.org; Sat, 24 Aug 2019 17:35:02 -0400 Received: by mail-pg1-x544.google.com with SMTP id n9so7993992pgc.1 for ; Sat, 24 Aug 2019 14:34:59 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id 81sm6325753pfx.111.2019.08.24.14.34.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Aug 2019 14:34:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WeS2D0cuVBKG8KKN1319ExUviIRkQlB9pnf5dIabrik=; b=K+zZB3g3oTOEl5WyWli9IBHhbLuqQRpHdRGCOnqGGGhZ0cIhYDgwtGfK9oqNkLInuJ FrSuT2d1xCl1BaVyKgVkBJxpuucGgm4KlHbgU+Cr8fY7FaCviFmBoR2QqHR/F+RirVba oWWtC/DDGAOu9YAgjgu9d0kQUrw8VT7rd1NiIamOnaT4IftqZ4ptRWH2OEkdk4aOequs q+DFSLKlZlI+dtO/T1MnAhprYtJkinQBQ8h3Ege4qTgESoU8wG2ps2saKW9xp2mxCfj7 S8KNMRRHV8kCxDjM84VHe7ycXx2YYVczDjvvLPNpt6mJfHQhT+BKz2YkrBBr5hNAy9tZ EPLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WeS2D0cuVBKG8KKN1319ExUviIRkQlB9pnf5dIabrik=; b=k+57ISL9yQbqgczwimWAB7VktSqL6xmTfi4hUCGWEbPuC8y3LW9XDqiNVfm5MeLCc3 /3r06QwRpFj7TOoyTByg7hk+FfHHwBE32L9oLD6FPBKXgrhtOalx6sMMtnt2iQiqg8qS znKBaz0l8cFaFRUJreP8l9cmqXXCt839fz8oVEKpBreCoysliMhwK+sh73Bxv0lwSdWN /bSmZsQjc48Ax/+uxUvRKyiLrQqalXF3T+zpMCBPRoluKPdWGayq4cG7uGqs1AwPgI5v tg1S0q79Ihcn64nZNh2T+5tzl+kQNCKLjKR3gZtdeon9cx+Qg69daokr1x/YiC4TCxP4 a4fA== X-Gm-Message-State: APjAAAUn2d68wp+nIaRrY0loMDnCD1A7wiJmNKxBC4Hw3HSUJ1hPIkyT qwon8unlmFBoGxb8GSYo/4C6qeLlfmc= X-Google-Smtp-Source: APXvYqzoqPwDz1J85W88Z/BmECBKVhna+gulR7lhxZ3s12z81jJMbvuyJI92ig9Y4s2n94AFfP1GNg== X-Received: by 2002:aa7:8a0a:: with SMTP id m10mr12766598pfa.100.1566682498078; Sat, 24 Aug 2019 14:34:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 24 Aug 2019 14:34:48 -0700 Message-Id: <20190824213451.31118-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190824213451.31118-1-richard.henderson@linaro.org> References: <20190824213451.31118-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 3/6] cputlb: Fold TLB_RECHECK into TLB_INVALID_MASK X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We had two different mechanisms to force a recheck of the tlb. Before TLB_RECHECK was introduced, we had a PAGE_WRITE_INV bit that would immediate set TLB_INVALID_MASK, which automatically means that a second check of the tlb entry fails. We can use the same mechanism to handle small pages. Conserve TLB_* bits by removing TLB_RECHECK. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- include/exec/cpu-all.h | 5 +-- accel/tcg/cputlb.c | 86 +++++++++++------------------------------- 2 files changed, 24 insertions(+), 67 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 8323094648..8d07ae23a5 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -329,14 +329,11 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS - 2)) /* Set if TLB entry is an IO callback. */ #define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) -/* Set if TLB entry must have MMU lookup repeated for every access */ -#define TLB_RECHECK (1 << (TARGET_PAGE_BITS - 4)) =20 /* Use this mask to check interception with an alignment mask * in a TCG backend. */ -#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_RECHECK) +#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO) =20 /** * tlb_hit_page: return true if page aligned @addr is a hit against the diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d9787cc893..c9576bebcf 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -732,11 +732,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulo= ng vaddr, =20 address =3D vaddr_page; if (size < TARGET_PAGE_SIZE) { - /* - * Slow-path the TLB entries; we will repeat the MMU check and TLB - * fill on every access. - */ - address |=3D TLB_RECHECK; + /* Repeat the MMU check and TLB fill on every access. */ + address |=3D TLB_INVALID_MASK; } if (attrs.byte_swap) { /* Force the access through the I/O slow path. */ @@ -1026,10 +1023,15 @@ static bool victim_tlb_hit(CPUArchState *env, size_= t mmu_idx, size_t index, victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \ (ADDR) & TARGET_PAGE_MASK) =20 -/* NOTE: this function can trigger an exception */ -/* NOTE2: the returned address is not exactly the physical address: it - * is actually a ram_addr_t (in system mode; the user mode emulation - * version of this function returns a guest virtual address). +/* + * Return a ram_addr_t for the virtual address for execution. + * + * Return -1 if we can't translate and execute from an entire page + * of RAM. This will force us to execute by loading and translating + * one insn at a time, without caching. + * + * NOTE: This function will trigger an exception if the page is + * not executable. */ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) { @@ -1043,19 +1045,20 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env= , target_ulong addr) tlb_fill(env_cpu(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0); index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); + + if (unlikely(entry->addr_code & TLB_INVALID_MASK)) { + /* + * The MMU protection covers a smaller range than a target + * page, so we must redo the MMU check for every insn. + */ + return -1; + } } assert(tlb_hit(entry->addr_code, addr)); } =20 - if (unlikely(entry->addr_code & (TLB_RECHECK | TLB_MMIO))) { - /* - * Return -1 if we can't translate and execute from an entire - * page of RAM here, which will cause us to execute by loading - * and translating one insn at a time, without caching: - * - TLB_RECHECK: means the MMU protection covers a smaller range - * than a target page, so we must redo the MMU check every insn - * - TLB_MMIO: region is not backed by RAM - */ + if (unlikely(entry->addr_code & TLB_MMIO)) { + /* The region is not backed by RAM. */ return -1; } =20 @@ -1180,7 +1183,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, } =20 /* Notice an IO access or a needs-MMU-lookup access */ - if (unlikely(tlb_addr & (TLB_MMIO | TLB_RECHECK))) { + if (unlikely(tlb_addr & TLB_MMIO)) { /* There's really nothing that can be done to support this apart from stop-the-world. */ goto stop_the_world; @@ -1258,6 +1261,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, entry =3D tlb_entry(env, mmu_idx, addr); } tlb_addr =3D code_read ? entry->addr_code : entry->addr_read; + tlb_addr &=3D ~TLB_INVALID_MASK; } =20 /* Handle an IO access. */ @@ -1265,27 +1269,6 @@ load_helper(CPUArchState *env, target_ulong addr, TC= GMemOpIdx oi, if ((addr & (size - 1)) !=3D 0) { goto do_unaligned_access; } - - if (tlb_addr & TLB_RECHECK) { - /* - * This is a TLB_RECHECK access, where the MMU protection - * covers a smaller range than a target page, and we must - * repeat the MMU check here. This tlb_fill() call might - * longjump out if this access should cause a guest exception. - */ - tlb_fill(env_cpu(env), addr, size, - access_type, mmu_idx, retaddr); - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); - - tlb_addr =3D code_read ? entry->addr_code : entry->addr_read; - tlb_addr &=3D ~TLB_RECHECK; - if (!(tlb_addr & ~TARGET_PAGE_MASK)) { - /* RAM access */ - goto do_aligned_access; - } - } - return io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, addr, retaddr, access_type, op); } @@ -1314,7 +1297,6 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, return res & MAKE_64BIT_MASK(0, size * 8); } =20 - do_aligned_access: haddr =3D (void *)((uintptr_t)addr + entry->addend); switch (op) { case MO_UB: @@ -1509,27 +1491,6 @@ store_helper(CPUArchState *env, target_ulong addr, u= int64_t val, if ((addr & (size - 1)) !=3D 0) { goto do_unaligned_access; } - - if (tlb_addr & TLB_RECHECK) { - /* - * This is a TLB_RECHECK access, where the MMU protection - * covers a smaller range than a target page, and we must - * repeat the MMU check here. This tlb_fill() call might - * longjump out if this access should cause a guest exception. - */ - tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, - mmu_idx, retaddr); - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); - - tlb_addr =3D tlb_addr_write(entry); - tlb_addr &=3D ~TLB_RECHECK; - if (!(tlb_addr & ~TARGET_PAGE_MASK)) { - /* RAM access */ - goto do_aligned_access; - } - } - io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, val, addr, retaddr, op); return; @@ -1579,7 +1540,6 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, return; } =20 - do_aligned_access: haddr =3D (void *)((uintptr_t)addr + entry->addend); switch (op) { case MO_UB: --=20 2.17.1 From nobody Fri May 3 06:04:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566682983; cv=none; d=zoho.com; s=zohoarc; b=TkZ8QDURkKC2atottvOnx4LVj3mdCCR0PQbjASL9vgMcjt4H4DYoDVrAb52YyaLnc2JK5IXZ8fEhzLZeycDzcH9QaBcwNDpSzXWQEwy4nAV7Cm9CvZqWX+iglytRIWrDnA0gjHZ/LAng/a2L8Q4VQ8CFf86hD1RmXoImt7+iPK8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566682983; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=YR66lN9SJRv3vsHOK1rmmiRwlMbIQXT9UAQyELpnwsw=; b=gsVjpwjw6IoNTx+leLpewmK15lIYOf/1guEd9B+36GKDlNXP1WCQ64ef/eFKVzJ8tgn73/jgufGJ9WFNA1PWWuH1X3wkTfVRmtfC6Ra1/q3ZO569FoEBXnadp+MKKJ3YCsz/cBkkjq4dz2murNg5bt95PhrAG0TWEA7/XjryRS4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566682983405239.26803715049584; Sat, 24 Aug 2019 14:43:03 -0700 (PDT) Received: from localhost ([::1]:39558 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i1doM-00070f-7N for importer@patchew.org; Sat, 24 Aug 2019 17:43:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36364) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i1dgg-0001M1-HR for qemu-devel@nongnu.org; Sat, 24 Aug 2019 17:35:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i1dge-00035Q-Fl for qemu-devel@nongnu.org; Sat, 24 Aug 2019 17:35:06 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:39755) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i1dga-00030o-La for qemu-devel@nongnu.org; Sat, 24 Aug 2019 17:35:02 -0400 Received: by mail-pg1-x541.google.com with SMTP id u17so7972273pgi.6 for ; Sat, 24 Aug 2019 14:35:00 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id 81sm6325753pfx.111.2019.08.24.14.34.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Aug 2019 14:34:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YR66lN9SJRv3vsHOK1rmmiRwlMbIQXT9UAQyELpnwsw=; b=cJQhfKRkZpkGMvu/sZcc2TJJoFF7oZKHl0mjoITm1AUyZxQUa8ZqR8i0FyDXJDGURr NiZwVOMAGhLnsE5kf97smE49ygFM1oGbPxaGX7g3TBVFO42iy9UiN5WsOPiKFwlmIR6H 3C86Y61Vi+2qPS3fcnRbwDa0JmKtBi4FINO5zVgxefaT6yYsj7brzLy8WSmQskHz9XnN /+1crYanJK9/VUOW/jlJpRHdTHgcQC3JJuAVzxYxqj7ec9VAC5kT8FazXmC28+5Jp0Bx PARj0yHN4FL24a/Ob5E/nal3BMRbE3agXheWBixC1kr0qoerx60n4nKNR9XfUjPf6bI0 qnXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YR66lN9SJRv3vsHOK1rmmiRwlMbIQXT9UAQyELpnwsw=; b=Qm9B6iJ1TpIjaHPvqsor3QvHkVdfiQjvvE+2X/W00KxTFJ6v43BZaVSxJtj3n8Rebo +W0n6sLWbnEyQaRrr3Tbx/AtzRcrS+9z+o6KMGWEjcyyNENiHQSLUXhFf3l9eYtbYPwe LoPjbt8rlG7T/XGjNGK1aSqaN/z9s1hPM0voEoLGCTrr1tbi3aQM50BKlIqed6S3GQtu njilxarLhhcY1DXFsciM+YiunsE6fUhJaVPTcyw0QoNXOAhmLaBZ7yHGct99gLqBFcyd Gb3wLbCic/p6WRFjsJvAaf1WdjB3q0OZYaiTKgqkuo9fveGqgMyyrTQUs3IgBlgrUSPM u9nA== X-Gm-Message-State: APjAAAUZx7XaUw0gjyqXzXZeXzh9X6m2PoLkKNVBMleJshzV/jtigcKt FX609GwK2Mlo8Ey6djRGBom1GENQ28w= X-Google-Smtp-Source: APXvYqyoMzq69F8eVyHt1pF3Cv6dhU4FUqjtr+dZU8Wnvoz7S6xcTKaeIsLzidLDLeibMCIYXxbQmw== X-Received: by 2002:a62:1901:: with SMTP id 1mr12551701pfz.172.1566682499203; Sat, 24 Aug 2019 14:34:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 24 Aug 2019 14:34:49 -0700 Message-Id: <20190824213451.31118-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190824213451.31118-1-richard.henderson@linaro.org> References: <20190824213451.31118-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 4/6] exec: Factor out cpu_watchpoint_address_matches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We want to move the check for watchpoints from memory_region_section_get_iotlb to tlb_set_page_with_attrs. Isolate the loop over watchpoints to an exported function. Rename the existing cpu_watchpoint_address_matches to watchpoint_address_matches, since it doesn't actually have a cpu argument. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- include/hw/core/cpu.h | 7 +++++++ exec.c | 45 ++++++++++++++++++++++++++++--------------- 2 files changed, 36 insertions(+), 16 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 7bd8bed5b2..c7cda65c66 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1096,6 +1096,12 @@ static inline void cpu_check_watchpoint(CPUState *cp= u, vaddr addr, vaddr len, MemTxAttrs atr, int fl, uintptr_t = ra) { } + +static inline int cpu_watchpoint_address_matches(CPUState *cpu, + vaddr addr, vaddr len) +{ + return 0; +} #else int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint); @@ -1105,6 +1111,7 @@ void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUW= atchpoint *watchpoint); void cpu_watchpoint_remove_all(CPUState *cpu, int mask); void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, MemTxAttrs attrs, int flags, uintptr_t ra); +int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); #endif =20 /** diff --git a/exec.c b/exec.c index cb6f5763dc..8575ce51ad 100644 --- a/exec.c +++ b/exec.c @@ -1138,9 +1138,8 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mas= k) * partially or completely with the address range covered by the * access). */ -static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp, - vaddr addr, - vaddr len) +static inline bool watchpoint_address_matches(CPUWatchpoint *wp, + vaddr addr, vaddr len) { /* We know the lengths are non-zero, but a little caution is * required to avoid errors in the case where the range ends @@ -1152,6 +1151,20 @@ static inline bool cpu_watchpoint_address_matches(CP= UWatchpoint *wp, =20 return !(addr > wpend || wp->vaddr > addrend); } + +/* Return flags for watchpoints that match addr + prot. */ +int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len) +{ + CPUWatchpoint *wp; + int ret =3D 0; + + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { + if (watchpoint_address_matches(wp, addr, TARGET_PAGE_SIZE)) { + ret |=3D wp->flags; + } + } + return ret; +} #endif /* !CONFIG_USER_ONLY */ =20 /* Add a breakpoint. */ @@ -1459,7 +1472,7 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu, target_ulong *address) { hwaddr iotlb; - CPUWatchpoint *wp; + int flags, match; =20 if (memory_region_is_ram(section->mr)) { /* Normal RAM. */ @@ -1477,17 +1490,17 @@ hwaddr memory_region_section_get_iotlb(CPUState *cp= u, iotlb +=3D xlat; } =20 - /* Make accesses to pages with watchpoints go via the - watchpoint trap routines. */ - QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) { - /* Avoid trapping reads of pages with a write breakpoint. */ - if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { - iotlb =3D PHYS_SECTION_WATCH + paddr; - *address |=3D TLB_MMIO; - break; - } - } + /* Avoid trapping reads of pages with a write breakpoint. */ + match =3D (prot & PAGE_READ ? BP_MEM_READ : 0) + | (prot & PAGE_WRITE ? BP_MEM_WRITE : 0); + flags =3D cpu_watchpoint_address_matches(cpu, vaddr, TARGET_PAGE_SIZE); + if (flags & match) { + /* + * Make accesses to pages with watchpoints go via the + * watchpoint trap routines. + */ + iotlb =3D PHYS_SECTION_WATCH + paddr; + *address |=3D TLB_MMIO; } =20 return iotlb; @@ -2806,7 +2819,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, = vaddr len, =20 addr =3D cc->adjust_watchpoint_address(cpu, addr, len); QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - if (cpu_watchpoint_address_matches(wp, addr, len) + if (watchpoint_address_matches(wp, addr, len) && (wp->flags & flags)) { if (flags =3D=3D BP_MEM_READ) { wp->flags |=3D BP_WATCHPOINT_HIT_READ; --=20 2.17.1 From nobody Fri May 3 06:04:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566682762; cv=none; d=zoho.com; s=zohoarc; b=UCw/D8ZNn9pde8dmhNXATmivT25tAWUs2Kgm1Cef5qjfhph70fQavtjJl3OERP0zAgBRjJyeM2ptFvjRX2W3xJeYyup7ORau+UBU5TxZsYA697E3rfpOVbVR8b1ZMThjLI4ni03QHNEmwCP42C+eKjoKxAs1zOtoJJIG7YB5N/M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566682762; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=vNEsJcB2kukOuHiyOwZ4ZNcbnZh0P4uvd68CJElB0UM=; b=nJcYdPMkmp4KfjsdUAM/wZL8oFy0j/6QjtXIFnALOAOWu9s49bym+wejilVOwrNCOhJAI7LNf5F+xNFbSPW0McXi9nqTWOhHVaVQ+5yZkJ2jcXkibc+m6sQHloh7Tg6NqGlZJayaRMUqpSxhXgU3OoomPenG9IcjpBMb618UYH4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566682762251129.80187953583538; Sat, 24 Aug 2019 14:39:22 -0700 (PDT) Received: from localhost ([::1]:39524 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i1dkg-0004W5-4g for importer@patchew.org; Sat, 24 Aug 2019 17:39:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36365) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i1dgg-0001M2-Hq for qemu-devel@nongnu.org; Sat, 24 Aug 2019 17:35:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i1dge-00035e-Hm for qemu-devel@nongnu.org; Sat, 24 Aug 2019 17:35:06 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:39704) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i1dgc-00032p-HK for qemu-devel@nongnu.org; Sat, 24 Aug 2019 17:35:04 -0400 Received: by mail-pf1-x443.google.com with SMTP id y200so1357593pfb.6 for ; Sat, 24 Aug 2019 14:35:01 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id 81sm6325753pfx.111.2019.08.24.14.34.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Aug 2019 14:34:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vNEsJcB2kukOuHiyOwZ4ZNcbnZh0P4uvd68CJElB0UM=; b=rgeFwQ2v34ZzDuPDQgHGQsCpSDKPRgIiGSdMipmsbSX+aheUfiumGIqtXKt/j1LaSf W2HHQO/ZHzIZfwYv8VewLyISpxPAcKFuEMH/x692np2eGFG2C2+jm/lquf+SeePGzDiX wKNAChlY4dPRgW9SnrtiMCb00HORwYNqBIbua7c2ZJReJte7u7S9Hvh9L+2+wzrwGVNV ol3Kd+Hltt5amD3xjyCDy18eKAZ3hXPdaNVfpHnjRSvzaYOT/epR51Ww9lw1nQPvvrkq 2a++6bmxMAdWdQSjBa3mHW4KZ6r3Mzuskn575G/4NLJ6DDzBdsS8rq6vv78/K6JkZ1cX UWOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vNEsJcB2kukOuHiyOwZ4ZNcbnZh0P4uvd68CJElB0UM=; b=tajVj3ra7S7ZRNsrXe+Bu6KeUfKRyQZ30i2nJAHNCmlzteY3psDXT4V6G61HPhjhvb 7YPMgBGVMxNk+J0s9pKd/snjps3n9WFvddJuC33Nz9g0xzj0daTvE77GN1QyYoK0IeHo zrqR2OfbbqA2Fiv7qY6bXBMUpNxI6PHGdRQgxsfA6pShMUikWgUdY+RimaP1Lr41fCFN tJPipw8AEdy1+a48DGrzgtZH+ilvfvQCexZNkIjjr+wEUXq2uovRl+KCSm7NPUEfGn6c UfLr3DN+AZ/7gGKfkwAZ6hgQDftNvz+onVrKILDNrcdONBrFKVOLaYAKqwYZoj6wn8kU 5IXw== X-Gm-Message-State: APjAAAW0bxC9iUZBej2Wn83220e/4Ki9AxhW/r8f3EA6xJwuc++7+sBq oGXIh289bL1JQxHn6FEsgKaefWFYr5o= X-Google-Smtp-Source: APXvYqx8451f+uKW+ygQwXO/bVu2qRkRBYiGVddMPsbSjnqsm26zphtmbh8+mu97O89ph1zrqVY5nw== X-Received: by 2002:a17:90a:3266:: with SMTP id k93mr12250768pjb.46.1566682500442; Sat, 24 Aug 2019 14:35:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 24 Aug 2019 14:34:50 -0700 Message-Id: <20190824213451.31118-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190824213451.31118-1-richard.henderson@linaro.org> References: <20190824213451.31118-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 5/6] cputlb: Handle watchpoints via TLB_WATCHPOINT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The raising of exceptions from check_watchpoint, buried inside of the I/O subsystem, is fundamentally broken. We do not have the helper return address with which we can unwind guest state. Replace PHYS_SECTION_WATCH and io_mem_watch with TLB_WATCHPOINT. Move the call to cpu_check_watchpoint into the cputlb helpers where we do have the helper return address. This also allows us to handle watchpoints on RAM to bypass the full i/o access path. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- include/exec/cpu-all.h | 5 +- accel/tcg/cputlb.c | 83 +++++++++++++++++++++++++++--- exec.c | 114 +++-------------------------------------- 3 files changed, 87 insertions(+), 115 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 8d07ae23a5..d2d443c4f9 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -329,11 +329,14 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS - 2)) /* Set if TLB entry is an IO callback. */ #define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) +/* Set if TLB entry contains a watchpoint. */ +#define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS - 4)) =20 /* Use this mask to check interception with an alignment mask * in a TCG backend. */ -#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO) +#define TLB_FLAGS_MASK \ + (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO | TLB_WATCHPOINT) =20 /** * tlb_hit_page: return true if page aligned @addr is a hit against the diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c9576bebcf..f7a414a131 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -710,6 +710,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, hwaddr iotlb, xlat, sz, paddr_page; target_ulong vaddr_page; int asidx =3D cpu_asidx_from_attrs(cpu, attrs); + int wp_flags; =20 assert_cpu_is_self(cpu); =20 @@ -752,6 +753,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, code_address =3D address; iotlb =3D memory_region_section_get_iotlb(cpu, section, vaddr_page, paddr_page, xlat, prot, &addre= ss); + wp_flags =3D cpu_watchpoint_address_matches(cpu, vaddr_page, + TARGET_PAGE_SIZE); =20 index =3D tlb_index(env, mmu_idx, vaddr_page); te =3D tlb_entry(env, mmu_idx, vaddr_page); @@ -805,6 +808,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, tn.addend =3D addend - vaddr_page; if (prot & PAGE_READ) { tn.addr_read =3D address; + if (wp_flags & BP_MEM_READ) { + tn.addr_read |=3D TLB_WATCHPOINT; + } } else { tn.addr_read =3D -1; } @@ -831,6 +837,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, if (prot & PAGE_WRITE_INV) { tn.addr_write |=3D TLB_INVALID_MASK; } + if (wp_flags & BP_MEM_WRITE) { + tn.addr_write |=3D TLB_WATCHPOINT; + } } =20 copy_tlb_helper_locked(te, &tn); @@ -1264,13 +1273,33 @@ load_helper(CPUArchState *env, target_ulong addr, T= CGMemOpIdx oi, tlb_addr &=3D ~TLB_INVALID_MASK; } =20 - /* Handle an IO access. */ + /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + CPUIOTLBEntry *iotlbentry; + + /* For anything that is unaligned, recurse through full_load. */ if ((addr & (size - 1)) !=3D 0) { goto do_unaligned_access; } - return io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], - mmu_idx, addr, retaddr, access_type, op); + + iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + + /* Handle watchpoints. */ + if (unlikely(tlb_addr & TLB_WATCHPOINT)) { + /* On watchpoint hit, this will longjmp out. */ + cpu_check_watchpoint(env_cpu(env), addr, size, + iotlbentry->attrs, BP_MEM_READ, retaddr); + + /* The backing page may or may not require I/O. */ + tlb_addr &=3D ~TLB_WATCHPOINT; + if ((tlb_addr & ~TARGET_PAGE_MASK) =3D=3D 0) { + goto do_aligned_access; + } + } + + /* Handle I/O access. */ + return io_readx(env, iotlbentry, mmu_idx, addr, + retaddr, access_type, op); } =20 /* Handle slow unaligned access (it spans two pages or IO). */ @@ -1297,6 +1326,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, return res & MAKE_64BIT_MASK(0, size * 8); } =20 + do_aligned_access: haddr =3D (void *)((uintptr_t)addr + entry->addend); switch (op) { case MO_UB: @@ -1486,13 +1516,32 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, tlb_addr =3D tlb_addr_write(entry) & ~TLB_INVALID_MASK; } =20 - /* Handle an IO access. */ + /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + CPUIOTLBEntry *iotlbentry; + + /* For anything that is unaligned, recurse through byte stores. */ if ((addr & (size - 1)) !=3D 0) { goto do_unaligned_access; } - io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, - val, addr, retaddr, op); + + iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + + /* Handle watchpoints. */ + if (unlikely(tlb_addr & TLB_WATCHPOINT)) { + /* On watchpoint hit, this will longjmp out. */ + cpu_check_watchpoint(env_cpu(env), addr, size, + iotlbentry->attrs, BP_MEM_WRITE, retaddr); + + /* The backing page may or may not require I/O. */ + tlb_addr &=3D ~TLB_WATCHPOINT; + if ((tlb_addr & ~TARGET_PAGE_MASK) =3D=3D 0) { + goto do_aligned_access; + } + } + + /* Handle I/O access. */ + io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, op); return; } =20 @@ -1504,6 +1553,8 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, uintptr_t index2; CPUTLBEntry *entry2; target_ulong page2, tlb_addr2; + size_t size2; + do_unaligned_access: /* * Ensure the second page is in the TLB. Note that the first page @@ -1511,16 +1562,33 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, * cannot evict the first. */ page2 =3D (addr + size) & TARGET_PAGE_MASK; + size2 =3D (addr + size) & ~TARGET_PAGE_MASK; index2 =3D tlb_index(env, mmu_idx, page2); entry2 =3D tlb_entry(env, mmu_idx, page2); tlb_addr2 =3D tlb_addr_write(entry2); if (!tlb_hit_page(tlb_addr2, page2) && !victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2 & TARGET_PAGE_MASK)) { - tlb_fill(env_cpu(env), page2, size, MMU_DATA_STORE, + tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE, mmu_idx, retaddr); } =20 + /* + * Handle watchpoints. Since this may trap, all checks + * must happen before any store. + */ + if (unlikely(tlb_addr & TLB_WATCHPOINT)) { + cpu_check_watchpoint(env_cpu(env), addr, + -(addr | TARGET_PAGE_MASK), + env_tlb(env)->d[mmu_idx].iotlb[index].att= rs, + BP_MEM_WRITE, retaddr); + } + if (unlikely(tlb_addr2 & TLB_WATCHPOINT)) { + cpu_check_watchpoint(env_cpu(env), page2, size2, + env_tlb(env)->d[mmu_idx].iotlb[index2].at= trs, + BP_MEM_WRITE, retaddr); + } + /* * XXX: not efficient, but simple. * This loop must go in the forward direction to avoid issues @@ -1540,6 +1608,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, return; } =20 + do_aligned_access: haddr =3D (void *)((uintptr_t)addr + entry->addend); switch (op) { case MO_UB: diff --git a/exec.c b/exec.c index 8575ce51ad..ad0f4a598f 100644 --- a/exec.c +++ b/exec.c @@ -193,15 +193,12 @@ typedef struct subpage_t { #define PHYS_SECTION_UNASSIGNED 0 #define PHYS_SECTION_NOTDIRTY 1 #define PHYS_SECTION_ROM 2 -#define PHYS_SECTION_WATCH 3 =20 static void io_mem_init(void); static void memory_map_init(void); static void tcg_log_global_after_sync(MemoryListener *listener); static void tcg_commit(MemoryListener *listener); =20 -static MemoryRegion io_mem_watch; - /** * CPUAddressSpace: all the information a CPU needs about an AddressSpace * @cpu: the CPU whose AddressSpace this is @@ -1472,7 +1469,6 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu, target_ulong *address) { hwaddr iotlb; - int flags, match; =20 if (memory_region_is_ram(section->mr)) { /* Normal RAM. */ @@ -1490,19 +1486,6 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu, iotlb +=3D xlat; } =20 - /* Avoid trapping reads of pages with a write breakpoint. */ - match =3D (prot & PAGE_READ ? BP_MEM_READ : 0) - | (prot & PAGE_WRITE ? BP_MEM_WRITE : 0); - flags =3D cpu_watchpoint_address_matches(cpu, vaddr, TARGET_PAGE_SIZE); - if (flags & match) { - /* - * Make accesses to pages with watchpoints go via the - * watchpoint trap routines. - */ - iotlb =3D PHYS_SECTION_WATCH + paddr; - *address |=3D TLB_MMIO; - } - return iotlb; } #endif /* defined(CONFIG_USER_ONLY) */ @@ -2810,10 +2793,14 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr= , vaddr len, =20 assert(tcg_enabled()); if (cpu->watchpoint_hit) { - /* We re-entered the check after replacing the TB. Now raise - * the debug interrupt so that is will trigger after the - * current instruction. */ + /* + * We re-entered the check after replacing the TB. + * Now raise the debug interrupt so that it will + * trigger after the current instruction. + */ + qemu_mutex_lock_iothread(); cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); + qemu_mutex_unlock_iothread(); return; } =20 @@ -2858,88 +2845,6 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr,= vaddr len, } } =20 -static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int fl= ags) -{ - CPUState *cpu =3D current_cpu; - vaddr addr =3D (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; - - cpu_check_watchpoint(cpu, addr, len, attrs, flags, 0); -} - -/* Watchpoint access routines. Watchpoints are inserted using TLB tricks, - so these check for a hit then pass through to the normal out-of-line - phys routines. */ -static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pda= ta, - unsigned size, MemTxAttrs attrs) -{ - MemTxResult res; - uint64_t data; - int asidx =3D cpu_asidx_from_attrs(current_cpu, attrs); - AddressSpace *as =3D current_cpu->cpu_ases[asidx].as; - - check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ); - switch (size) { - case 1: - data =3D address_space_ldub(as, addr, attrs, &res); - break; - case 2: - data =3D address_space_lduw(as, addr, attrs, &res); - break; - case 4: - data =3D address_space_ldl(as, addr, attrs, &res); - break; - case 8: - data =3D address_space_ldq(as, addr, attrs, &res); - break; - default: abort(); - } - *pdata =3D data; - return res; -} - -static MemTxResult watch_mem_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) -{ - MemTxResult res; - int asidx =3D cpu_asidx_from_attrs(current_cpu, attrs); - AddressSpace *as =3D current_cpu->cpu_ases[asidx].as; - - check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE); - switch (size) { - case 1: - address_space_stb(as, addr, val, attrs, &res); - break; - case 2: - address_space_stw(as, addr, val, attrs, &res); - break; - case 4: - address_space_stl(as, addr, val, attrs, &res); - break; - case 8: - address_space_stq(as, addr, val, attrs, &res); - break; - default: abort(); - } - return res; -} - -static const MemoryRegionOps watch_mem_ops =3D { - .read_with_attrs =3D watch_mem_read, - .write_with_attrs =3D watch_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid =3D { - .min_access_size =3D 1, - .max_access_size =3D 8, - .unaligned =3D false, - }, - .impl =3D { - .min_access_size =3D 1, - .max_access_size =3D 8, - .unaligned =3D false, - }, -}; - static MemTxResult flatview_read(FlatView *fv, hwaddr addr, MemTxAttrs attrs, uint8_t *buf, hwaddr le= n); static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs at= trs, @@ -3115,9 +3020,6 @@ static void io_mem_init(void) memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, NULL, UINT64_MAX); memory_region_clear_global_locking(&io_mem_notdirty); - - memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL, - NULL, UINT64_MAX); } =20 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) @@ -3131,8 +3033,6 @@ AddressSpaceDispatch *address_space_dispatch_new(Flat= View *fv) assert(n =3D=3D PHYS_SECTION_NOTDIRTY); n =3D dummy_section(&d->map, fv, &io_mem_rom); assert(n =3D=3D PHYS_SECTION_ROM); - n =3D dummy_section(&d->map, fv, &io_mem_watch); - assert(n =3D=3D PHYS_SECTION_WATCH); =20 d->phys_map =3D (PhysPageEntry) { .ptr =3D PHYS_MAP_NODE_NIL, .skip = =3D 1 }; =20 --=20 2.17.1 From nobody Fri May 3 06:04:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id 81sm6325753pfx.111.2019.08.24.14.35.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Aug 2019 14:35:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MaPRheG1y5rukm0xNUMPfKKNGnqQD10OMwv720v5bPI=; b=IRBBH0kEUItTpr7/5DkK7rpgZWXEMN/EWz9awnmHsbyDiZF8PoyFGAOliB9eS7W/VZ XA3M8IrxfIBQ7b8+M3km6ObNNEtgl8q2dSJB0n5ivnabU7X9YWQSN7x8Dpnmla9M8oPS qC05fD8ey5UIYzT7p3naFjR/pcouqOSyJOR4uzk1YuG8TsUwxrKNdS2oMD7w2ikECJBF lDn/ku0lrbQWo9e/kvar6E8oJP+6R5GsOIZqcbG7Ekm3W3XxH91A4y6hC/Drxojsf9dZ XjJ724JDTPhzNi41pW2JdyZEGpA+QpiNui1J4LTBfslHIw7J2IjIyKygp95ouN4HUn2D gaaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MaPRheG1y5rukm0xNUMPfKKNGnqQD10OMwv720v5bPI=; b=VJ7ms3BE0QuAt7QalE9H+tIysIjZm0hDMhladWpZsNrxTUqTtXfQg332pnAPxObrRm 8Kj/bZHFuMtY2/2wip9h0y/bKJnH8LHaFhC/115uJYeM67pZGDNhmxOKMqL1sRzzQZC3 z0PGz4rsN/qH8urdW0ysoSHCwuaUnmpxwZP3uWAKlKLWPa48Zg5A163Ry5HPZieqLRKn Nau4xlDmx+S2iIWB9Mv1RmiiH5sydc1iEapEvRhjiQJ8E3FTe64V5+QBDDl5UDj3+IKY 69uBtuGYrff+orM1QRJ+lknSG6MF2512t38jXaVDjEm6Q7CT6U5TLVzwak1DLK3WcBbs af/A== X-Gm-Message-State: APjAAAU2Z+CEE/V+1HdFMghgB6j5HdAtautrvYthDbnV+pQc9gz32JTy EkBYBuxEmHmHLtgf+/7JNSo1Ua8nOAc= X-Google-Smtp-Source: APXvYqzjc/xBh9AjrsE6+yDJ8tu4HdnfIRO97xLtLKHBVR3+ZixgU8VfcfA7Jq50fItF3eCIZ0HeUg== X-Received: by 2002:a17:90a:17aa:: with SMTP id q39mr12013875pja.106.1566682501676; Sat, 24 Aug 2019 14:35:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 24 Aug 2019 14:34:51 -0700 Message-Id: <20190824213451.31118-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190824213451.31118-1-richard.henderson@linaro.org> References: <20190824213451.31118-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::433 Subject: [Qemu-devel] [PATCH 6/6] tcg: Check for watchpoints in probe_write() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: David Hildenbrand Let size > 0 indicate a promise to write to those bytes. Check for write watchpoints in the probed range. Suggested-by: Richard Henderson Signed-off-by: David Hildenbrand Message-Id: <20190823100741.9621-10-david@redhat.com> [rth: Recompute index after tlb_fill; check TLB_WATCHPOINT.] Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f7a414a131..7fc7aa9482 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1086,13 +1086,24 @@ void probe_write(CPUArchState *env, target_ulong ad= dr, int size, int mmu_idx, { uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr =3D tlb_addr_write(entry); =20 - if (!tlb_hit(tlb_addr_write(entry), addr)) { - /* TLB entry is for a different page */ + if (unlikely(!tlb_hit(tlb_addr, addr))) { if (!VICTIM_TLB_HIT(addr_write, addr)) { tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); + /* TLB resize via tlb_fill may have moved the entry. */ + index =3D tlb_index(env, mmu_idx, addr); + entry =3D tlb_entry(env, mmu_idx, addr); } + tlb_addr =3D tlb_addr_write(entry); + } + + /* Handle watchpoints. */ + if ((tlb_addr & TLB_WATCHPOINT) && size > 0) { + cpu_check_watchpoint(env_cpu(env), addr, size, + env_tlb(env)->d[mmu_idx].iotlb[index].attrs, + BP_MEM_WRITE, retaddr); } } =20 --=20 2.17.1