From nobody Sun Apr 28 00:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de ARC-Seal: i=1; a=rsa-sha256; t=1566469557; cv=none; d=zoho.com; s=zohoarc; b=ibRq1eIKZ7a0kYjVhEoDubR75z1a5clJNvLwdnne5TsBFZiKDAjZwr24oIvB+FeHX/d0XSNVTIlKjqaIvDev/PjgfhIYQhTOslJZs69Zb2nihZShpVaf0U3RbqQa16eINBqm+BJQ7+xVTrjM8ICwnEOmq16P5DgrZ9kdMPwUAEM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566469557; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=GTsqVEyoahLFqtXHbQcMV+LcUV0gu3CL297OUf1p/ug=; b=EQ2/KMqUTfNwnoEDyFISfjwdhM40CqoiIRJjGiJXYKnI4ftmieNQnPlkuMnpBtFEarw38Xmlxfnamh3HvBX0Ky61DcdpmafSL6y2xgb7p1pisJXI+g7V51t6DJWTLnIMuA3WAXs7e1WJ0ZfAYwpJIPwOydEouW0jGe+rJLiuk6g= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156646955739367.1328278379533; Thu, 22 Aug 2019 03:25:57 -0700 (PDT) Received: from localhost ([::1]:40178 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0kHz-0001ll-69 for importer@patchew.org; Thu, 22 Aug 2019 06:25:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60925) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0kDI-0005tm-CH for qemu-devel@nongnu.org; Thu, 22 Aug 2019 06:21:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0kDG-0005XM-9a for qemu-devel@nongnu.org; Thu, 22 Aug 2019 06:21:04 -0400 Received: from telepax.uni-paderborn.de ([131.234.189.14]:43882) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0kDF-0005TB-9m for qemu-devel@nongnu.org; Thu, 22 Aug 2019 06:21:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.uni-paderborn.de; s=20170601; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=GTsqVEyoahLFqtXHbQcMV+LcUV0gu3CL297OUf1p/ug=; b=POsPyu9HaaSJH+HZF3Oo+3XVFu u8Vg2D7FQXEHN4n7Fe+jDZGoyx8MzPp5NRlZuOn2xXO/TIEjhIqVMH1w3tCChm3SyYISPLMM7QNJq o4H5FMDmstXIKHh6owiQu8WKSFLaaDJ5ZXcykJYyfv7WnZWOUBB+4MIofwWkhqK/lcYw=; From: Bastian Koppelmann To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 12:20:42 +0200 Message-Id: <20190822102046.8765-2-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190822102046.8765-1-kbastian@mail.uni-paderborn.de> References: <20190822102046.8765-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-IMT-Spam-Score: 0.0 () X-PMX-Version: 6.4.7.2805085, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.8.22.101216, AntiVirus-Engine: 5.63.0, AntiVirus-Data: 2019.8.13.5630000 X-IMT-Authenticated-Sender: uid=kbastian,ou=People,o=upb,c=de X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 131.234.189.14 Subject: [Qemu-devel] [PULL 1/5] target/tricore: Use DisasContextBase API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" this gets rid of the copied fields of TriCore's DisasContext and now uses the shared DisasContextBase, which is necessary for the conversion to translate_loop. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 98 +++++++++++++++++--------------------- 1 file changed, 44 insertions(+), 54 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index dc2a65f3f9..ca67b6cd4c 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -30,6 +30,7 @@ #include "exec/helper-gen.h" =20 #include "tricore-opcodes.h" +#include "exec/translator.h" #include "exec/log.h" =20 /* @@ -64,24 +65,14 @@ static const char *regnames_d[] =3D { }; =20 typedef struct DisasContext { - struct TranslationBlock *tb; - target_ulong pc, saved_pc, next_pc; + DisasContextBase base; + target_ulong pc_succ_insn; uint32_t opcode; - int singlestep_enabled; /* Routine used to access memory */ int mem_idx; uint32_t hflags, saved_hflags; - int bstate; } DisasContext; =20 -enum { - - BS_NONE =3D 0, - BS_STOP =3D 1, - BS_BRANCH =3D 2, - BS_EXCP =3D 3, -}; - enum { MODE_LL =3D 0, MODE_LU =3D 1, @@ -3230,12 +3221,12 @@ static inline void gen_save_pc(target_ulong pc) =20 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { - if (unlikely(ctx->singlestep_enabled)) { + if (unlikely(ctx->base.singlestep_enabled)) { return false; } =20 #ifndef CONFIG_USER_ONLY - return (ctx->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MAS= K); + return (ctx->base.tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAG= E_MASK); #else return true; #endif @@ -3246,10 +3237,10 @@ static inline void gen_goto_tb(DisasContext *ctx, i= nt n, target_ulong dest) if (use_goto_tb(ctx, dest)) { tcg_gen_goto_tb(n); gen_save_pc(dest); - tcg_gen_exit_tb(ctx->tb, n); + tcg_gen_exit_tb(ctx->base.tb, n); } else { gen_save_pc(dest); - if (ctx->singlestep_enabled) { + if (ctx->base.singlestep_enabled) { /* raise exception debug */ } tcg_gen_exit_tb(NULL, 0); @@ -3261,9 +3252,9 @@ static void generate_trap(DisasContext *ctx, int clas= s, int tin) TCGv_i32 classtemp =3D tcg_const_i32(class); TCGv_i32 tintemp =3D tcg_const_i32(tin); =20 - gen_save_pc(ctx->pc); + gen_save_pc(ctx->base.pc_next); gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); - ctx->bstate =3D BS_EXCP; + ctx->base.is_jmp =3D DISAS_NORETURN; =20 tcg_temp_free(classtemp); tcg_temp_free(tintemp); @@ -3275,10 +3266,10 @@ static inline void gen_branch_cond(DisasContext *ct= x, TCGCond cond, TCGv r1, TCGLabel *jumpLabel =3D gen_new_label(); tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); =20 - gen_goto_tb(ctx, 1, ctx->next_pc); + gen_goto_tb(ctx, 1, ctx->pc_succ_insn); =20 gen_set_label(jumpLabel); - gen_goto_tb(ctx, 0, ctx->pc + address * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2); } =20 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv = r1, @@ -3295,9 +3286,9 @@ static void gen_loop(DisasContext *ctx, int r1, int32= _t offset) =20 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); - gen_goto_tb(ctx, 1, ctx->pc + offset); + gen_goto_tb(ctx, 1, ctx->base.pc_next + offset); gen_set_label(l1); - gen_goto_tb(ctx, 0, ctx->next_pc); + gen_goto_tb(ctx, 0, ctx->pc_succ_insn); } =20 static void gen_fcall_save_ctx(DisasContext *ctx) @@ -3306,7 +3297,7 @@ static void gen_fcall_save_ctx(DisasContext *ctx) =20 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); tcg_gen_mov_tl(cpu_gpr_a[10], temp); =20 tcg_temp_free(temp); @@ -3321,7 +3312,7 @@ static void gen_fret(DisasContext *ctx) tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); tcg_gen_mov_tl(cpu_PC, temp); tcg_gen_exit_tb(NULL, 0); - ctx->bstate =3D BS_BRANCH; + ctx->base.is_jmp =3D DISAS_NORETURN; =20 tcg_temp_free(temp); } @@ -3336,12 +3327,12 @@ static void gen_compute_branch(DisasContext *ctx, u= int32_t opc, int r1, /* SB-format jumps */ case OPC1_16_SB_J: case OPC1_32_B_J: - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; case OPC1_32_B_CALL: case OPC1_16_SB_CALL: - gen_helper_1arg(call, ctx->next_pc); - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_helper_1arg(call, ctx->pc_succ_insn); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; case OPC1_16_SB_JZ: gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); @@ -3433,26 +3424,26 @@ static void gen_compute_branch(DisasContext *ctx, u= int32_t opc, int r1, break; /* B-format */ case OPC1_32_B_CALLA: - gen_helper_1arg(call, ctx->next_pc); + gen_helper_1arg(call, ctx->pc_succ_insn); gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; case OPC1_32_B_FCALL: gen_fcall_save_ctx(ctx); - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; case OPC1_32_B_FCALLA: gen_fcall_save_ctx(ctx); gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; case OPC1_32_B_JLA: - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); /* fall through */ case OPC1_32_B_JA: gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; case OPC1_32_B_JL: - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; /* BOL format */ case OPCM_32_BRC_EQ_NEQ: @@ -3551,7 +3542,7 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, int r1, gen_loop(ctx, r2, offset * 2); } else { /* OPC2_32_BRR_LOOPU */ - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); } break; case OPCM_32_BRR_JNE: @@ -3585,7 +3576,7 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, int r1, default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - ctx->bstate =3D BS_BRANCH; + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 =20 @@ -3933,7 +3924,7 @@ static void decode_sr_system(CPUTriCoreState *env, Di= sasContext *ctx) case OPC2_16_SR_RFE: gen_helper_rfe(cpu_env); tcg_gen_exit_tb(NULL, 0); - ctx->bstate =3D BS_BRANCH; + ctx->base.is_jmp =3D DISAS_NORETURN; break; case OPC2_16_SR_DEBUG: /* raise EXCP_DEBUG */ @@ -6557,11 +6548,11 @@ static void decode_rr_idirect(CPUTriCoreState *env,= DisasContext *ctx) tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; case OPC2_32_RR_JLI: - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; case OPC2_32_RR_CALLI: - gen_helper_1arg(call, ctx->next_pc); + gen_helper_1arg(call, ctx->pc_succ_insn); tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; case OPC2_32_RR_FCALLI: @@ -6572,7 +6563,7 @@ static void decode_rr_idirect(CPUTriCoreState *env, D= isasContext *ctx) generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } tcg_gen_exit_tb(NULL, 0); - ctx->bstate =3D BS_BRANCH; + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) @@ -8391,7 +8382,7 @@ static void decode_sys_interrupts(CPUTriCoreState *en= v, DisasContext *ctx) case OPC2_32_SYS_RFE: gen_helper_rfe(cpu_env); tcg_gen_exit_tb(NULL, 0); - ctx->bstate =3D BS_BRANCH; + ctx->base.is_jmp =3D DISAS_NORETURN; break; case OPC2_32_SYS_RFM: if ((ctx->hflags & TRICORE_HFLAG_KUU) =3D=3D TRICORE_HFLAG_SM) { @@ -8404,7 +8395,7 @@ static void decode_sys_interrupts(CPUTriCoreState *en= v, DisasContext *ctx) gen_helper_rfm(cpu_env); gen_set_label(l1); tcg_gen_exit_tb(NULL, 0); - ctx->bstate =3D BS_BRANCH; + ctx->base.is_jmp =3D DISAS_NORETURN; tcg_temp_free(tmp); } else { /* generate privilege trap */ @@ -8790,11 +8781,11 @@ static void decode_opc(CPUTriCoreState *env, DisasC= ontext *ctx, int *is_branch) { /* 16-Bit Instruction */ if ((ctx->opcode & 0x1) =3D=3D 0) { - ctx->next_pc =3D ctx->pc + 2; + ctx->pc_succ_insn =3D ctx->base.pc_next + 2; decode_16Bit_opc(env, ctx); /* 32-Bit Instruction */ } else { - ctx->next_pc =3D ctx->pc + 4; + ctx->pc_succ_insn =3D ctx->base.pc_next + 4; decode_32Bit_opc(env, ctx); } } @@ -8807,33 +8798,32 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) int num_insns =3D 0; =20 pc_start =3D tb->pc; - ctx.pc =3D pc_start; - ctx.saved_pc =3D -1; - ctx.tb =3D tb; - ctx.singlestep_enabled =3D cs->singlestep_enabled; - ctx.bstate =3D BS_NONE; + ctx.base.pc_next =3D pc_start; + ctx.base.tb =3D tb; + ctx.base.singlestep_enabled =3D cs->singlestep_enabled; + ctx.base.is_jmp =3D DISAS_NEXT; ctx.mem_idx =3D cpu_mmu_index(env, false); ctx.hflags =3D (uint32_t)tb->flags; =20 tcg_clear_temp_count(); gen_tb_start(tb); - while (ctx.bstate =3D=3D BS_NONE) { - tcg_gen_insn_start(ctx.pc); + while (ctx.base.is_jmp =3D=3D DISAS_NEXT) { + tcg_gen_insn_start(ctx.base.pc_next); num_insns++; =20 - ctx.opcode =3D cpu_ldl_code(env, ctx.pc); + ctx.opcode =3D cpu_ldl_code(env, ctx.base.pc_next); decode_opc(env, &ctx, 0); =20 if (num_insns >=3D max_insns || tcg_op_buf_full()) { - gen_save_pc(ctx.next_pc); + gen_save_pc(ctx.pc_succ_insn); tcg_gen_exit_tb(NULL, 0); break; } - ctx.pc =3D ctx.next_pc; + ctx.base.pc_next =3D ctx.pc_succ_insn; } =20 gen_tb_end(tb, num_insns); - tb->size =3D ctx.pc - pc_start; + tb->size =3D ctx.base.pc_next - pc_start; tb->icount =3D num_insns; =20 if (tcg_check_temp_count()) { @@ -8845,7 +8835,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.pc - pc_start); + log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start); qemu_log("\n"); qemu_log_unlock(); } --=20 2.23.0 From nobody Sun Apr 28 00:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de ARC-Seal: i=1; a=rsa-sha256; t=1566469801; cv=none; d=zoho.com; s=zohoarc; b=lwWI4OTanjtcHB4fHymEJ7A9+uuRCYlE1cLqnxy6Qq2LRDToCuKeafNVTdjjpV0d6k71ITLeB5G7eqd0sp8HqZP1daDlof9dFnB3B0at/QJv8rfF8xrcteY5QUcmBGkaKboqRWqFigE7AL8BzX/wdj4T08wShvHXXHz1LXioMQs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566469801; 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bh=JSl+zIPnDWkd5HhcZOWxTP9+d89XpieLyFZV892p37o=; b=qsH3Z9dE7e/Mbg/z0umDIlg9+5 bEsRLkUHz6jenb5U8l1poVBd9FV4VPGQvy0aqnsObMSeEr1edMzYVPfcMlWb9LqSoh7qz04b5+ZHT KbWuJjpJIem5bgZ7UJNytzDG4poI4WZqeZ/9ZMXtgnRN1TxQU5+TYo/8BRE93yMatUro=; From: Bastian Koppelmann To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 12:20:43 +0200 Message-Id: <20190822102046.8765-3-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190822102046.8765-1-kbastian@mail.uni-paderborn.de> References: <20190822102046.8765-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-IMT-Spam-Score: 0.0 () X-PMX-Version: 6.4.7.2805085, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.8.22.101216, AntiVirus-Engine: 5.63.0, AntiVirus-Data: 2019.8.13.5630000 X-IMT-Authenticated-Sender: uid=kbastian,ou=People,o=upb,c=de X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 131.234.189.14 Subject: [Qemu-devel] [PULL 2/5] target-tricore: Make env a member of DisasContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" otherwise we have to pass env down through all functions which blocks the usage of translator_loop. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 340 ++++++++++++++++++------------------- 1 file changed, 168 insertions(+), 172 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index ca67b6cd4c..6b10ae5c47 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -66,6 +66,7 @@ static const char *regnames_d[] =3D { =20 typedef struct DisasContext { DisasContextBase base; + CPUTriCoreState *env; target_ulong pc_succ_insn; uint32_t opcode; /* Routine used to access memory */ @@ -369,13 +370,13 @@ static void gen_swapmsk(DisasContext *ctx, int reg, T= CGv ea) These makros also specify in which ISA version the csfr was introduced.= */ #define R(ADDRESS, REG, FEATURE) \ case ADDRESS: \ - if (tricore_feature(env, FEATURE)) { \ + if (tricore_feature(ctx->env, FEATURE)) { \ tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \ } \ break; #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) -static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset) +static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset) { /* since we're caching PSW make this a special case */ if (offset =3D=3D 0xfe04) { @@ -394,7 +395,7 @@ static inline void gen_mfcr(CPUTriCoreState *env, TCGv = ret, int32_t offset) since no execption occurs */ #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ case ADDRESS: \ - if (tricore_feature(env, FEATURE)) { \ + if (tricore_feature(ctx->env, FEATURE)) { \ tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \ } \ break; @@ -403,7 +404,7 @@ static inline void gen_mfcr(CPUTriCoreState *env, TCGv = ret, int32_t offset) watchdog device, we handle endinit protected registers like all-access registers for now. */ #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) -static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv = r1, +static inline void gen_mtcr(DisasContext *ctx, TCGv r1, int32_t offset) { if ((ctx->hflags & TRICORE_HFLAG_KUU) =3D=3D TRICORE_HFLAG_SM) { @@ -1093,7 +1094,7 @@ gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uin= t32_t n) =20 static inline void gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, - uint32_t up_shift, CPUTriCoreState *env) + uint32_t up_shift) { TCGv temp =3D tcg_temp_new(); TCGv temp2 =3D tcg_temp_new(); @@ -1254,7 +1255,7 @@ gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv= arg1_high, TCGv arg2, =20 static inline void gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, - TCGv arg3, uint32_t n, CPUTriCoreState *env) + TCGv arg3, uint32_t n) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); @@ -1952,7 +1953,7 @@ gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uin= t32_t n) =20 static inline void gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, - uint32_t up_shift, CPUTriCoreState *env) + uint32_t up_shift) { TCGv temp =3D tcg_temp_new(); TCGv temp2 =3D tcg_temp_new(); @@ -2107,7 +2108,7 @@ gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv= arg1_high, TCGv arg2, =20 static inline void gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, - TCGv arg3, uint32_t n, CPUTriCoreState *env) + TCGv arg3, uint32_t n) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); @@ -3153,11 +3154,11 @@ static inline void gen_unpack(TCGv rl, TCGv rh, TCG= v r1) } =20 static inline void -gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2) +gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) { TCGv_i64 ret =3D tcg_temp_new_i64(); =20 - if (!tricore_feature(env, TRICORE_FEATURE_131)) { + if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) { gen_helper_dvinit_b_13(ret, cpu_env, r1, r2); } else { gen_helper_dvinit_b_131(ret, cpu_env, r1, r2); @@ -3168,11 +3169,11 @@ gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh= , TCGv r1, TCGv r2) } =20 static inline void -gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2) +gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) { TCGv_i64 ret =3D tcg_temp_new_i64(); =20 - if (!tricore_feature(env, TRICORE_FEATURE_131)) { + if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) { gen_helper_dvinit_h_13(ret, cpu_env, r1, r2); } else { gen_helper_dvinit_h_131(ret, cpu_env, r1, r2); @@ -3584,7 +3585,7 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, int r1, * Functions for decoding instructions */ =20 -static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op= 1) +static void decode_src_opc(DisasContext *ctx, int op1) { int r1; int32_t const4; @@ -3646,7 +3647,7 @@ static void decode_src_opc(CPUTriCoreState *env, Disa= sContext *ctx, int op1) tcg_gen_movi_tl(cpu_gpr_a[r1], const4); break; case OPC1_16_SRC_MOV_E: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { tcg_gen_movi_tl(cpu_gpr_d[r1], const4); tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); } else { @@ -3910,7 +3911,7 @@ static void decode_sro_opc(DisasContext *ctx, int op1) } } =20 -static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx) +static void decode_sr_system(DisasContext *ctx) { uint32_t op2; op2 =3D MASK_OP_SR_OP2(ctx->opcode); @@ -3937,7 +3938,7 @@ static void decode_sr_system(CPUTriCoreState *env, Di= sasContext *ctx) } } =20 -static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx) +static void decode_sr_accu(DisasContext *ctx) { uint32_t op2; uint32_t r1; @@ -3981,7 +3982,7 @@ static void decode_sr_accu(CPUTriCoreState *env, Disa= sContext *ctx) } } =20 -static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) +static void decode_16Bit_opc(DisasContext *ctx) { int op1; int r1, r2; @@ -4012,7 +4013,7 @@ static void decode_16Bit_opc(CPUTriCoreState *env, Di= sasContext *ctx) case OPC1_16_SRC_MOV_E: case OPC1_16_SRC_SH: case OPC1_16_SRC_SHA: - decode_src_opc(env, ctx, op1); + decode_src_opc(ctx, op1); break; /* SRR-format */ case OPC1_16_SRR_ADD: @@ -4097,7 +4098,7 @@ static void decode_16Bit_opc(CPUTriCoreState *env, Di= sasContext *ctx) break; case OPC1_16_SBC_JEQ2: case OPC1_16_SBC_JNE2: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { address =3D MASK_OP_SBC_DISP4(ctx->opcode); const16 =3D MASK_OP_SBC_CONST4_SEXT(ctx->opcode); gen_compute_branch(ctx, op1, 0, 0, const16, address); @@ -4115,7 +4116,7 @@ static void decode_16Bit_opc(CPUTriCoreState *env, Di= sasContext *ctx) /* SBR-format */ case OPC1_16_SBR_JEQ2: case OPC1_16_SBR_JNE2: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { r1 =3D MASK_OP_SBR_S2(ctx->opcode); address =3D MASK_OP_SBR_DISP4(ctx->opcode); gen_compute_branch(ctx, op1, r1, 0, 0, address); @@ -4195,10 +4196,10 @@ static void decode_16Bit_opc(CPUTriCoreState *env, = DisasContext *ctx) break; /* SR-format */ case OPCM_16_SR_SYSTEM: - decode_sr_system(env, ctx); + decode_sr_system(ctx); break; case OPCM_16_SR_ACCU: - decode_sr_accu(env, ctx); + decode_sr_accu(ctx); break; case OPC1_16_SR_JI: r1 =3D MASK_OP_SR_S1D(ctx->opcode); @@ -4218,7 +4219,7 @@ static void decode_16Bit_opc(CPUTriCoreState *env, Di= sasContext *ctx) */ =20 /* ABS-format */ -static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx) +static void decode_abs_ldw(DisasContext *ctx) { int32_t op2; int32_t r1; @@ -4253,7 +4254,7 @@ static void decode_abs_ldw(CPUTriCoreState *env, Disa= sContext *ctx) tcg_temp_free(temp); } =20 -static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx) +static void decode_abs_ldb(DisasContext *ctx) { int32_t op2; int32_t r1; @@ -4286,7 +4287,7 @@ static void decode_abs_ldb(CPUTriCoreState *env, Disa= sContext *ctx) tcg_temp_free(temp); } =20 -static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx) +static void decode_abs_ldst_swap(DisasContext *ctx) { int32_t op2; int32_t r1; @@ -4313,7 +4314,7 @@ static void decode_abs_ldst_swap(CPUTriCoreState *env= , DisasContext *ctx) tcg_temp_free(temp); } =20 -static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ct= x) +static void decode_abs_ldst_context(DisasContext *ctx) { uint32_t op2; int32_t off18; @@ -4339,7 +4340,7 @@ static void decode_abs_ldst_context(CPUTriCoreState *= env, DisasContext *ctx) } } =20 -static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx) +static void decode_abs_store(DisasContext *ctx) { int32_t op2; int32_t r1; @@ -4373,7 +4374,7 @@ static void decode_abs_store(CPUTriCoreState *env, Di= sasContext *ctx) tcg_temp_free(temp); } =20 -static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx) +static void decode_abs_storeb_h(DisasContext *ctx) { int32_t op2; int32_t r1; @@ -4401,7 +4402,7 @@ static void decode_abs_storeb_h(CPUTriCoreState *env,= DisasContext *ctx) =20 /* Bit-format */ =20 -static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx) +static void decode_bit_andacc(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -4442,7 +4443,7 @@ static void decode_bit_andacc(CPUTriCoreState *env, D= isasContext *ctx) } } =20 -static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx) +static void decode_bit_logical_t(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -4476,7 +4477,7 @@ static void decode_bit_logical_t(CPUTriCoreState *env= , DisasContext *ctx) } } =20 -static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx) +static void decode_bit_insert(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -4499,7 +4500,7 @@ static void decode_bit_insert(CPUTriCoreState *env, D= isasContext *ctx) tcg_temp_free(temp); } =20 -static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx) +static void decode_bit_logical_t2(DisasContext *ctx) { uint32_t op2; =20 @@ -4535,7 +4536,7 @@ static void decode_bit_logical_t2(CPUTriCoreState *en= v, DisasContext *ctx) } } =20 -static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx) +static void decode_bit_orand(DisasContext *ctx) { uint32_t op2; =20 @@ -4576,7 +4577,7 @@ static void decode_bit_orand(CPUTriCoreState *env, Di= sasContext *ctx) } } =20 -static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx) +static void decode_bit_sh_logic1(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -4617,7 +4618,7 @@ static void decode_bit_sh_logic1(CPUTriCoreState *env= , DisasContext *ctx) tcg_temp_free(temp); } =20 -static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx) +static void decode_bit_sh_logic2(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -4661,8 +4662,7 @@ static void decode_bit_sh_logic2(CPUTriCoreState *env= , DisasContext *ctx) /* BO-format */ =20 =20 -static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env, - DisasContext *ctx) +static void decode_bo_addrmode_post_pre_base(DisasContext *ctx) { uint32_t op2; uint32_t off10; @@ -4696,13 +4696,13 @@ static void decode_bo_addrmode_post_pre_base(CPUTri= CoreState *env, break; case OPC2_32_BO_CACHEI_WI_SHORTOFF: case OPC2_32_BO_CACHEI_W_SHORTOFF: - if (!tricore_feature(env, TRICORE_FEATURE_131)) { + if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; case OPC2_32_BO_CACHEI_W_POSTINC: case OPC2_32_BO_CACHEI_WI_POSTINC: - if (tricore_feature(env, TRICORE_FEATURE_131)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_131)) { tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -4710,7 +4710,7 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCo= reState *env, break; case OPC2_32_BO_CACHEI_W_PREINC: case OPC2_32_BO_CACHEI_WI_PREINC: - if (tricore_feature(env, TRICORE_FEATURE_131)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_131)) { tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -4821,8 +4821,7 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCo= reState *env, } } =20 -static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env, - DisasContext *ctx) +static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) { uint32_t op2; uint32_t off10; @@ -4932,8 +4931,7 @@ static void decode_bo_addrmode_bitreverse_circular(CP= UTriCoreState *env, tcg_temp_free(temp3); } =20 -static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env, - DisasContext *ctx) +static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx) { uint32_t op2; uint32_t off10; @@ -5067,8 +5065,7 @@ static void decode_bo_addrmode_ld_post_pre_base(CPUTr= iCoreState *env, } } =20 -static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env, - DisasContext *ctx) +static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) { uint32_t op2; uint32_t off10; @@ -5186,8 +5183,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular= (CPUTriCoreState *env, tcg_temp_free(temp3); } =20 -static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env, - DisasContext *ctx) +static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx) { uint32_t op2; uint32_t off10; @@ -5279,8 +5275,7 @@ static void decode_bo_addrmode_stctx_post_pre_base(CP= UTriCoreState *env, tcg_temp_free(temp2); } =20 -static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *= env, - DisasContext *ctx) +static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) { uint32_t op2; uint32_t off10; @@ -5342,7 +5337,7 @@ static void decode_bo_addrmode_ldmst_bitreverse_circu= lar(CPUTriCoreState *env, tcg_temp_free(temp3); } =20 -static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_= t op1) +static void decode_bol_opc(DisasContext *ctx, int32_t op1) { int r1, r2; int32_t address; @@ -5369,7 +5364,7 @@ static void decode_bol_opc(CPUTriCoreState *env, Disa= sContext *ctx, int32_t op1) tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); break; case OPC1_32_BOL_ST_A_LONGOFF: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_L= EUL); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -5379,42 +5374,42 @@ static void decode_bol_opc(CPUTriCoreState *env, Di= sasContext *ctx, int32_t op1) gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); break; case OPC1_32_BOL_LD_B_LONGOFF: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_S= B); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; case OPC1_32_BOL_LD_BU_LONGOFF: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_U= B); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; case OPC1_32_BOL_LD_H_LONGOFF: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_L= ESW); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; case OPC1_32_BOL_LD_HU_LONGOFF: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_L= EUW); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; case OPC1_32_BOL_ST_B_LONGOFF: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_S= B); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; case OPC1_32_BOL_ST_H_LONGOFF: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_L= ESW); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -5426,7 +5421,7 @@ static void decode_bol_opc(CPUTriCoreState *env, Disa= sContext *ctx, int32_t op1) } =20 /* RC format */ -static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ct= x) +static void decode_rc_logical_shift(DisasContext *ctx) { uint32_t op2; int r1, r2; @@ -5493,7 +5488,7 @@ static void decode_rc_logical_shift(CPUTriCoreState *= env, DisasContext *ctx) tcg_temp_free(temp); } =20 -static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rc_accumulator(DisasContext *ctx) { uint32_t op2; int r1, r2; @@ -5693,7 +5688,7 @@ static void decode_rc_accumulator(CPUTriCoreState *en= v, DisasContext *ctx) tcg_temp_free(temp); } =20 -static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *c= tx) +static void decode_rc_serviceroutine(DisasContext *ctx) { uint32_t op2; uint32_t const9; @@ -5713,7 +5708,7 @@ static void decode_rc_serviceroutine(CPUTriCoreState = *env, DisasContext *ctx) } } =20 -static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rc_mul(DisasContext *ctx) { uint32_t op2; int r1, r2; @@ -5751,7 +5746,7 @@ static void decode_rc_mul(CPUTriCoreState *env, Disas= Context *ctx) } =20 /* RCPW format */ -static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rcpw_insert(DisasContext *ctx) { uint32_t op2; int r1, r2; @@ -5790,7 +5785,7 @@ static void decode_rcpw_insert(CPUTriCoreState *env, = DisasContext *ctx) =20 /* RCRW format */ =20 -static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rcrw_insert(DisasContext *ctx) { uint32_t op2; int r1, r3, r4; @@ -5835,7 +5830,7 @@ static void decode_rcrw_insert(CPUTriCoreState *env, = DisasContext *ctx) =20 /* RCR format */ =20 -static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rcr_cond_select(DisasContext *ctx) { uint32_t op2; int r1, r3, r4; @@ -5879,7 +5874,7 @@ static void decode_rcr_cond_select(CPUTriCoreState *e= nv, DisasContext *ctx) } } =20 -static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rcr_madd(DisasContext *ctx) { uint32_t op2; int r1, r3, r4; @@ -5934,7 +5929,7 @@ static void decode_rcr_madd(CPUTriCoreState *env, Dis= asContext *ctx) } } =20 -static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rcr_msub(DisasContext *ctx) { uint32_t op2; int r1, r3, r4; @@ -5991,7 +5986,7 @@ static void decode_rcr_msub(CPUTriCoreState *env, Dis= asContext *ctx) =20 /* RLC format */ =20 -static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, +static void decode_rlc_opc(DisasContext *ctx, uint32_t op1) { int32_t const16; @@ -6013,13 +6008,13 @@ static void decode_rlc_opc(CPUTriCoreState *env, Di= sasContext *ctx, break; case OPC1_32_RLC_MFCR: const16 =3D MASK_OP_RLC_CONST16(ctx->opcode); - gen_mfcr(env, cpu_gpr_d[r2], const16); + gen_mfcr(ctx, cpu_gpr_d[r2], const16); break; case OPC1_32_RLC_MOV: tcg_gen_movi_tl(cpu_gpr_d[r2], const16); break; case OPC1_32_RLC_MOV_64: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { CHECK_REG_PAIR(r2); tcg_gen_movi_tl(cpu_gpr_d[r2], const16); tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); @@ -6039,7 +6034,7 @@ static void decode_rlc_opc(CPUTriCoreState *env, Disa= sContext *ctx, break; case OPC1_32_RLC_MTCR: const16 =3D MASK_OP_RLC_CONST16(ctx->opcode); - gen_mtcr(env, ctx, cpu_gpr_d[r1], const16); + gen_mtcr(ctx, cpu_gpr_d[r1], const16); break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -6047,7 +6042,7 @@ static void decode_rlc_opc(CPUTriCoreState *env, Disa= sContext *ctx, } =20 /* RR format */ -static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr_accumulator(DisasContext *ctx) { uint32_t op2; int r3, r2, r1; @@ -6245,7 +6240,7 @@ static void decode_rr_accumulator(CPUTriCoreState *en= v, DisasContext *ctx) tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); break; case OPC2_32_RR_MOV_64: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { temp =3D tcg_temp_new(); =20 CHECK_REG_PAIR(r3); @@ -6259,7 +6254,7 @@ static void decode_rr_accumulator(CPUTriCoreState *en= v, DisasContext *ctx) } break; case OPC2_32_RR_MOVS_64: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { CHECK_REG_PAIR(r3); tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31); @@ -6389,7 +6384,7 @@ static void decode_rr_accumulator(CPUTriCoreState *en= v, DisasContext *ctx) } } =20 -static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ct= x) +static void decode_rr_logical_shift(DisasContext *ctx) { uint32_t op2; int r3, r2, r1; @@ -6467,7 +6462,7 @@ static void decode_rr_logical_shift(CPUTriCoreState *= env, DisasContext *ctx) tcg_temp_free(temp); } =20 -static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr_address(DisasContext *ctx) { uint32_t op2, n; int r1, r2, r3; @@ -6535,7 +6530,7 @@ static void decode_rr_address(CPUTriCoreState *env, D= isasContext *ctx) } } =20 -static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr_idirect(DisasContext *ctx) { uint32_t op2; int r1; @@ -6566,7 +6561,7 @@ static void decode_rr_idirect(CPUTriCoreState *env, D= isasContext *ctx) ctx->base.is_jmp =3D DISAS_NORETURN; } =20 -static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr_divide(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -6588,7 +6583,7 @@ static void decode_rr_divide(CPUTriCoreState *env, Di= sasContext *ctx) break; case OPC2_32_RR_DVINIT_B: CHECK_REG_PAIR(r3); - gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], + gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_DVINIT_BU: @@ -6599,7 +6594,7 @@ static void decode_rr_divide(CPUTriCoreState *env, Di= sasContext *ctx) tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); /* reset av */ tcg_gen_movi_tl(cpu_PSW_AV, 0); - if (!tricore_feature(env, TRICORE_FEATURE_131)) { + if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) { /* overflow =3D (abs(D[r3+1]) >=3D abs(D[r2])) */ tcg_gen_abs_tl(temp, temp3); tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); @@ -6621,7 +6616,7 @@ static void decode_rr_divide(CPUTriCoreState *env, Di= sasContext *ctx) break; case OPC2_32_RR_DVINIT_H: CHECK_REG_PAIR(r3); - gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], + gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_DVINIT_HU: @@ -6632,7 +6627,7 @@ static void decode_rr_divide(CPUTriCoreState *env, Di= sasContext *ctx) tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16); /* reset av */ tcg_gen_movi_tl(cpu_PSW_AV, 0); - if (!tricore_feature(env, TRICORE_FEATURE_131)) { + if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) { /* overflow =3D (abs(D[r3+1]) >=3D abs(D[r2])) */ tcg_gen_abs_tl(temp, temp3); tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); @@ -6695,14 +6690,14 @@ static void decode_rr_divide(CPUTriCoreState *env, = DisasContext *ctx) gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); break; case OPC2_32_RR_CRC32: - if (tricore_feature(env, TRICORE_FEATURE_161)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_161)) { gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; case OPC2_32_RR_DIV: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_= d[r1], cpu_gpr_d[r2]); } else { @@ -6710,7 +6705,7 @@ static void decode_rr_divide(CPUTriCoreState *env, Di= sasContext *ctx) } break; case OPC2_32_RR_DIV_U: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2]); } else { @@ -6753,7 +6748,7 @@ static void decode_rr_divide(CPUTriCoreState *env, Di= sasContext *ctx) } =20 /* RR1 Format */ -static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr1_mul(DisasContext *ctx) { uint32_t op2; =20 @@ -6867,7 +6862,7 @@ static void decode_rr1_mul(CPUTriCoreState *env, Disa= sContext *ctx) tcg_temp_free(n); } =20 -static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr1_mulq(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -6939,7 +6934,7 @@ static void decode_rr1_mulq(CPUTriCoreState *env, Dis= asContext *ctx) } =20 /* RR2 format */ -static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr2_mul(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -6976,7 +6971,7 @@ static void decode_rr2_mul(CPUTriCoreState *env, Disa= sContext *ctx) } =20 /* RRPW format */ -static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext = *ctx) +static void decode_rrpw_extract_insert(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -7030,7 +7025,7 @@ static void decode_rrpw_extract_insert(CPUTriCoreStat= e *env, DisasContext *ctx) } =20 /* RRR format */ -static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr_cond_select(DisasContext *ctx) { uint32_t op2; int r1, r2, r3, r4; @@ -7076,7 +7071,7 @@ static void decode_rrr_cond_select(CPUTriCoreState *e= nv, DisasContext *ctx) } } =20 -static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr_divide(DisasContext *ctx) { uint32_t op2; =20 @@ -7156,7 +7151,7 @@ static void decode_rrr_divide(CPUTriCoreState *env, D= isasContext *ctx) } =20 /* RRR2 format */ -static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr2_madd(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4; @@ -7208,7 +7203,7 @@ static void decode_rrr2_madd(CPUTriCoreState *env, Di= sasContext *ctx) } } =20 -static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr2_msub(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4; @@ -7260,7 +7255,7 @@ static void decode_rrr2_msub(CPUTriCoreState *env, Di= sasContext *ctx) } =20 /* RRR1 format */ -static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr1_madd(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4, n; @@ -7406,7 +7401,7 @@ static void decode_rrr1_madd(CPUTriCoreState *env, Di= sasContext *ctx) } } =20 -static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr1_maddq_h(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4, n; @@ -7425,19 +7420,19 @@ static void decode_rrr1_maddq_h(CPUTriCoreState *en= v, DisasContext *ctx) switch (op2) { case OPC2_32_RRR1_MADD_Q_32: gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], - cpu_gpr_d[r2], n, 32, env); + cpu_gpr_d[r2], n, 32); break; case OPC2_32_RRR1_MADD_Q_64: CHECK_REG_PAIR(r4); CHECK_REG_PAIR(r3); gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], - n, env); + n); break; case OPC2_32_RRR1_MADD_Q_32_L: tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], - temp, n, 16, env); + temp, n, 16); break; case OPC2_32_RRR1_MADD_Q_64_L: CHECK_REG_PAIR(r4); @@ -7445,12 +7440,12 @@ static void decode_rrr1_maddq_h(CPUTriCoreState *en= v, DisasContext *ctx) tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, - n, env); + n); break; case OPC2_32_RRR1_MADD_Q_32_U: tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], - temp, n, 16, env); + temp, n, 16); break; case OPC2_32_RRR1_MADD_Q_64_U: CHECK_REG_PAIR(r4); @@ -7458,7 +7453,7 @@ static void decode_rrr1_maddq_h(CPUTriCoreState *env,= DisasContext *ctx) tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, - n, env); + n); break; case OPC2_32_RRR1_MADD_Q_32_LL: tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); @@ -7586,7 +7581,7 @@ static void decode_rrr1_maddq_h(CPUTriCoreState *env,= DisasContext *ctx) tcg_temp_free(temp2); } =20 -static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr1_maddsu_h(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4, n; @@ -7744,7 +7739,7 @@ static void decode_rrr1_maddsu_h(CPUTriCoreState *env= , DisasContext *ctx) } } =20 -static void decode_rrr1_msub(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr1_msub(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4, n; @@ -7890,7 +7885,7 @@ static void decode_rrr1_msub(CPUTriCoreState *env, Di= sasContext *ctx) } } =20 -static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr1_msubq_h(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4, n; @@ -7909,19 +7904,19 @@ static void decode_rrr1_msubq_h(CPUTriCoreState *en= v, DisasContext *ctx) switch (op2) { case OPC2_32_RRR1_MSUB_Q_32: gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], - cpu_gpr_d[r2], n, 32, env); + cpu_gpr_d[r2], n, 32); break; case OPC2_32_RRR1_MSUB_Q_64: CHECK_REG_PAIR(r4); CHECK_REG_PAIR(r3); gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], - n, env); + n); break; case OPC2_32_RRR1_MSUB_Q_32_L: tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], - temp, n, 16, env); + temp, n, 16); break; case OPC2_32_RRR1_MSUB_Q_64_L: CHECK_REG_PAIR(r4); @@ -7929,12 +7924,12 @@ static void decode_rrr1_msubq_h(CPUTriCoreState *en= v, DisasContext *ctx) tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, - n, env); + n); break; case OPC2_32_RRR1_MSUB_Q_32_U: tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], - temp, n, 16, env); + temp, n, 16); break; case OPC2_32_RRR1_MSUB_Q_64_U: CHECK_REG_PAIR(r4); @@ -7942,7 +7937,7 @@ static void decode_rrr1_msubq_h(CPUTriCoreState *env,= DisasContext *ctx) tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, - n, env); + n); break; case OPC2_32_RRR1_MSUB_Q_32_LL: tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); @@ -8070,7 +8065,7 @@ static void decode_rrr1_msubq_h(CPUTriCoreState *env,= DisasContext *ctx) tcg_temp_free(temp2); } =20 -static void decode_rrr1_msubad_h(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr1_msubad_h(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4, n; @@ -8229,7 +8224,7 @@ static void decode_rrr1_msubad_h(CPUTriCoreState *env= , DisasContext *ctx) } =20 /* RRRR format */ -static void decode_rrrr_extract_insert(CPUTriCoreState *env, DisasContext = *ctx) +static void decode_rrrr_extract_insert(DisasContext *ctx) { uint32_t op2; int r1, r2, r3, r4; @@ -8286,7 +8281,7 @@ static void decode_rrrr_extract_insert(CPUTriCoreStat= e *env, DisasContext *ctx) } =20 /* RRRW format */ -static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext = *ctx) +static void decode_rrrw_extract_insert(DisasContext *ctx) { uint32_t op2; int r1, r2, r3, r4; @@ -8347,7 +8342,7 @@ static void decode_rrrw_extract_insert(CPUTriCoreStat= e *env, DisasContext *ctx) } =20 /* SYS Format*/ -static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) +static void decode_sys_interrupts(DisasContext *ctx) { uint32_t op2; uint32_t r1; @@ -8408,7 +8403,7 @@ static void decode_sys_interrupts(CPUTriCoreState *en= v, DisasContext *ctx) gen_helper_svlcx(cpu_env); break; case OPC2_32_SYS_RESTORE: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { if ((ctx->hflags & TRICORE_HFLAG_KUU) =3D=3D TRICORE_HFLAG_SM = || (ctx->hflags & TRICORE_HFLAG_KUU) =3D=3D TRICORE_HFLAG_UM1= ) { tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1); @@ -8434,7 +8429,7 @@ static void decode_sys_interrupts(CPUTriCoreState *en= v, DisasContext *ctx) } } =20 -static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) +static void decode_32Bit_opc(DisasContext *ctx) { int op1; int32_t r1, r2, r3; @@ -8453,22 +8448,22 @@ static void decode_32Bit_opc(CPUTriCoreState *env, = DisasContext *ctx) switch (op1) { /* ABS-format */ case OPCM_32_ABS_LDW: - decode_abs_ldw(env, ctx); + decode_abs_ldw(ctx); break; case OPCM_32_ABS_LDB: - decode_abs_ldb(env, ctx); + decode_abs_ldb(ctx); break; case OPCM_32_ABS_LDMST_SWAP: - decode_abs_ldst_swap(env, ctx); + decode_abs_ldst_swap(ctx); break; case OPCM_32_ABS_LDST_CONTEXT: - decode_abs_ldst_context(env, ctx); + decode_abs_ldst_context(ctx); break; case OPCM_32_ABS_STORE: - decode_abs_store(env, ctx); + decode_abs_store(ctx); break; case OPCM_32_ABS_STOREB_H: - decode_abs_storeb_h(env, ctx); + decode_abs_storeb_h(ctx); break; case OPC1_32_ABS_STOREQ: address =3D MASK_OP_ABS_OFF18(ctx->opcode); @@ -8528,44 +8523,44 @@ static void decode_32Bit_opc(CPUTriCoreState *env, = DisasContext *ctx) break; /* Bit-format */ case OPCM_32_BIT_ANDACC: - decode_bit_andacc(env, ctx); + decode_bit_andacc(ctx); break; case OPCM_32_BIT_LOGICAL_T1: - decode_bit_logical_t(env, ctx); + decode_bit_logical_t(ctx); break; case OPCM_32_BIT_INSERT: - decode_bit_insert(env, ctx); + decode_bit_insert(ctx); break; case OPCM_32_BIT_LOGICAL_T2: - decode_bit_logical_t2(env, ctx); + decode_bit_logical_t2(ctx); break; case OPCM_32_BIT_ORAND: - decode_bit_orand(env, ctx); + decode_bit_orand(ctx); break; case OPCM_32_BIT_SH_LOGIC1: - decode_bit_sh_logic1(env, ctx); + decode_bit_sh_logic1(ctx); break; case OPCM_32_BIT_SH_LOGIC2: - decode_bit_sh_logic2(env, ctx); + decode_bit_sh_logic2(ctx); break; /* BO Format */ case OPCM_32_BO_ADDRMODE_POST_PRE_BASE: - decode_bo_addrmode_post_pre_base(env, ctx); + decode_bo_addrmode_post_pre_base(ctx); break; case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR: - decode_bo_addrmode_bitreverse_circular(env, ctx); + decode_bo_addrmode_bitreverse_circular(ctx); break; case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE: - decode_bo_addrmode_ld_post_pre_base(env, ctx); + decode_bo_addrmode_ld_post_pre_base(ctx); break; case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR: - decode_bo_addrmode_ld_bitreverse_circular(env, ctx); + decode_bo_addrmode_ld_bitreverse_circular(ctx); break; case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE: - decode_bo_addrmode_stctx_post_pre_base(env, ctx); + decode_bo_addrmode_stctx_post_pre_base(ctx); break; case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: - decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx); + decode_bo_addrmode_ldmst_bitreverse_circular(ctx); break; /* BOL-format */ case OPC1_32_BOL_LD_A_LONGOFF: @@ -8579,7 +8574,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, Di= sasContext *ctx) case OPC1_32_BOL_LD_HU_LONGOFF: case OPC1_32_BOL_ST_B_LONGOFF: case OPC1_32_BOL_ST_H_LONGOFF: - decode_bol_opc(env, ctx, op1); + decode_bol_opc(ctx, op1); break; /* BRC Format */ case OPCM_32_BRC_EQ_NEQ: @@ -8612,20 +8607,20 @@ static void decode_32Bit_opc(CPUTriCoreState *env, = DisasContext *ctx) break; /* RC Format */ case OPCM_32_RC_LOGICAL_SHIFT: - decode_rc_logical_shift(env, ctx); + decode_rc_logical_shift(ctx); break; case OPCM_32_RC_ACCUMULATOR: - decode_rc_accumulator(env, ctx); + decode_rc_accumulator(ctx); break; case OPCM_32_RC_SERVICEROUTINE: - decode_rc_serviceroutine(env, ctx); + decode_rc_serviceroutine(ctx); break; case OPCM_32_RC_MUL: - decode_rc_mul(env, ctx); + decode_rc_mul(ctx); break; /* RCPW Format */ case OPCM_32_RCPW_MASK_INSERT: - decode_rcpw_insert(env, ctx); + decode_rcpw_insert(ctx); break; /* RCRR Format */ case OPC1_32_RCRR_INSERT: @@ -8650,17 +8645,17 @@ static void decode_32Bit_opc(CPUTriCoreState *env, = DisasContext *ctx) break; /* RCRW Format */ case OPCM_32_RCRW_MASK_INSERT: - decode_rcrw_insert(env, ctx); + decode_rcrw_insert(ctx); break; /* RCR Format */ case OPCM_32_RCR_COND_SELECT: - decode_rcr_cond_select(env, ctx); + decode_rcr_cond_select(ctx); break; case OPCM_32_RCR_MADD: - decode_rcr_madd(env, ctx); + decode_rcr_madd(ctx); break; case OPCM_32_RCR_MSUB: - decode_rcr_msub(env, ctx); + decode_rcr_msub(ctx); break; /* RLC Format */ case OPC1_32_RLC_ADDI: @@ -8673,38 +8668,38 @@ static void decode_32Bit_opc(CPUTriCoreState *env, = DisasContext *ctx) case OPC1_32_RLC_MOV_H: case OPC1_32_RLC_MOVH_A: case OPC1_32_RLC_MTCR: - decode_rlc_opc(env, ctx, op1); + decode_rlc_opc(ctx, op1); break; /* RR Format */ case OPCM_32_RR_ACCUMULATOR: - decode_rr_accumulator(env, ctx); + decode_rr_accumulator(ctx); break; case OPCM_32_RR_LOGICAL_SHIFT: - decode_rr_logical_shift(env, ctx); + decode_rr_logical_shift(ctx); break; case OPCM_32_RR_ADDRESS: - decode_rr_address(env, ctx); + decode_rr_address(ctx); break; case OPCM_32_RR_IDIRECT: - decode_rr_idirect(env, ctx); + decode_rr_idirect(ctx); break; case OPCM_32_RR_DIVIDE: - decode_rr_divide(env, ctx); + decode_rr_divide(ctx); break; /* RR1 Format */ case OPCM_32_RR1_MUL: - decode_rr1_mul(env, ctx); + decode_rr1_mul(ctx); break; case OPCM_32_RR1_MULQ: - decode_rr1_mulq(env, ctx); + decode_rr1_mulq(ctx); break; /* RR2 format */ case OPCM_32_RR2_MUL: - decode_rr2_mul(env, ctx); + decode_rr2_mul(ctx); break; /* RRPW format */ case OPCM_32_RRPW_EXTRACT_INSERT: - decode_rrpw_extract_insert(env, ctx); + decode_rrpw_extract_insert(ctx); break; case OPC1_32_RRPW_DEXTR: r1 =3D MASK_OP_RRPW_S1(ctx->opcode); @@ -8723,48 +8718,48 @@ static void decode_32Bit_opc(CPUTriCoreState *env, = DisasContext *ctx) break; /* RRR Format */ case OPCM_32_RRR_COND_SELECT: - decode_rrr_cond_select(env, ctx); + decode_rrr_cond_select(ctx); break; case OPCM_32_RRR_DIVIDE: - decode_rrr_divide(env, ctx); + decode_rrr_divide(ctx); break; /* RRR2 Format */ case OPCM_32_RRR2_MADD: - decode_rrr2_madd(env, ctx); + decode_rrr2_madd(ctx); break; case OPCM_32_RRR2_MSUB: - decode_rrr2_msub(env, ctx); + decode_rrr2_msub(ctx); break; /* RRR1 format */ case OPCM_32_RRR1_MADD: - decode_rrr1_madd(env, ctx); + decode_rrr1_madd(ctx); break; case OPCM_32_RRR1_MADDQ_H: - decode_rrr1_maddq_h(env, ctx); + decode_rrr1_maddq_h(ctx); break; case OPCM_32_RRR1_MADDSU_H: - decode_rrr1_maddsu_h(env, ctx); + decode_rrr1_maddsu_h(ctx); break; case OPCM_32_RRR1_MSUB_H: - decode_rrr1_msub(env, ctx); + decode_rrr1_msub(ctx); break; case OPCM_32_RRR1_MSUB_Q: - decode_rrr1_msubq_h(env, ctx); + decode_rrr1_msubq_h(ctx); break; case OPCM_32_RRR1_MSUBAD_H: - decode_rrr1_msubad_h(env, ctx); + decode_rrr1_msubad_h(ctx); break; /* RRRR format */ case OPCM_32_RRRR_EXTRACT_INSERT: - decode_rrrr_extract_insert(env, ctx); + decode_rrrr_extract_insert(ctx); break; /* RRRW format */ case OPCM_32_RRRW_EXTRACT_INSERT: - decode_rrrw_extract_insert(env, ctx); + decode_rrrw_extract_insert(ctx); break; /* SYS format */ case OPCM_32_SYS_INTERRUPTS: - decode_sys_interrupts(env, ctx); + decode_sys_interrupts(ctx); break; case OPC1_32_SYS_RSTV: tcg_gen_movi_tl(cpu_PSW_V, 0); @@ -8777,16 +8772,16 @@ static void decode_32Bit_opc(CPUTriCoreState *env, = DisasContext *ctx) } } =20 -static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_br= anch) +static void decode_opc(DisasContext *ctx, int *is_branch) { /* 16-Bit Instruction */ if ((ctx->opcode & 0x1) =3D=3D 0) { ctx->pc_succ_insn =3D ctx->base.pc_next + 2; - decode_16Bit_opc(env, ctx); + decode_16Bit_opc(ctx); /* 32-Bit Instruction */ } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 4; - decode_32Bit_opc(env, ctx); + decode_32Bit_opc(ctx); } } =20 @@ -8804,6 +8799,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) ctx.base.is_jmp =3D DISAS_NEXT; ctx.mem_idx =3D cpu_mmu_index(env, false); ctx.hflags =3D (uint32_t)tb->flags; + ctx.env =3D env; =20 tcg_clear_temp_count(); gen_tb_start(tb); @@ -8812,7 +8808,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) num_insns++; =20 ctx.opcode =3D cpu_ldl_code(env, ctx.base.pc_next); - decode_opc(env, &ctx, 0); + decode_opc(&ctx, 0); =20 if (num_insns >=3D max_insns || tcg_op_buf_full()) { gen_save_pc(ctx.pc_succ_insn); --=20 2.23.0 From nobody Sun Apr 28 00:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 22 Aug 2019 06:21:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.uni-paderborn.de; s=20170601; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=Udo5UNzRaPQGVA87Ml0p/xu1ugcYhhbjqb9ss0Zd6CU=; b=tV7Y8FISZ1nhlOKJhvMXuhCy84 PKxYbFFRdGesBhj+2pl+8BczwCKvWinZ85xmFxDRLEseIN/ZTZZqL9xi/azv93CPBTKeqFK6ORQW3 M4jn1RV0gdqy1tygt+yidb6gSbbRu+fUnmPf/XBCCsEWxobAxuC4CFns//XWUK9Alz8Y=; From: Bastian Koppelmann To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 12:20:44 +0200 Message-Id: <20190822102046.8765-4-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190822102046.8765-1-kbastian@mail.uni-paderborn.de> References: <20190822102046.8765-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-IMT-Spam-Score: 0.0 () X-PMX-Version: 6.4.7.2805085, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.8.22.101216, AntiVirus-Engine: 5.63.0, AntiVirus-Data: 2019.8.13.5630000 X-IMT-Authenticated-Sender: uid=kbastian,ou=People,o=upb,c=de X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 131.234.189.14 Subject: [Qemu-devel] [PULL 3/5] target/tricore: Use translate_loop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 118 +++++++++++++++++++++++-------------- 1 file changed, 74 insertions(+), 44 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 6b10ae5c47..5fb42abe35 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8772,7 +8772,7 @@ static void decode_32Bit_opc(DisasContext *ctx) } } =20 -static void decode_opc(DisasContext *ctx, int *is_branch) +static void decode_opc(DisasContext *ctx) { /* 16-Bit Instruction */ if ((ctx->opcode & 0x1) =3D=3D 0) { @@ -8785,57 +8785,87 @@ static void decode_opc(DisasContext *ctx, int *is_b= ranch) } } =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) +static void tricore_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs) { + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUTriCoreState *env =3D cs->env_ptr; - DisasContext ctx; - target_ulong pc_start; - int num_insns =3D 0; - - pc_start =3D tb->pc; - ctx.base.pc_next =3D pc_start; - ctx.base.tb =3D tb; - ctx.base.singlestep_enabled =3D cs->singlestep_enabled; - ctx.base.is_jmp =3D DISAS_NEXT; - ctx.mem_idx =3D cpu_mmu_index(env, false); - ctx.hflags =3D (uint32_t)tb->flags; - ctx.env =3D env; - - tcg_clear_temp_count(); - gen_tb_start(tb); - while (ctx.base.is_jmp =3D=3D DISAS_NEXT) { - tcg_gen_insn_start(ctx.base.pc_next); - num_insns++; - - ctx.opcode =3D cpu_ldl_code(env, ctx.base.pc_next); - decode_opc(&ctx, 0); - - if (num_insns >=3D max_insns || tcg_op_buf_full()) { - gen_save_pc(ctx.pc_succ_insn); - tcg_gen_exit_tb(NULL, 0); - break; + ctx->mem_idx =3D cpu_mmu_index(env, false); + ctx->hflags =3D (uint32_t)ctx->base.tb->flags; +} + +static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + +static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(ctx->base.pc_next); +} + +static bool tricore_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, + const CPUBreakpoint *bp) +{ + return false; +} + +static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cpu) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPUTriCoreState *env =3D cpu->env_ptr; + + ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); + decode_opc(ctx); + ctx->base.pc_next =3D ctx->pc_succ_insn; + + if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { + target_ulong page_start; + + page_start =3D ctx->base.pc_first & TARGET_PAGE_MASK; + if (ctx->base.pc_next - page_start >=3D TARGET_PAGE_SIZE) { + ctx->base.is_jmp =3D DISAS_TOO_MANY; } - ctx.base.pc_next =3D ctx.pc_succ_insn; } +} =20 - gen_tb_end(tb, num_insns); - tb->size =3D ctx.base.pc_next - pc_start; - tb->icount =3D num_insns; +static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - if (tcg_check_temp_count()) { - printf("LEAK at %08x\n", env->PC); + switch (ctx->base.is_jmp) { + case DISAS_TOO_MANY: + gen_goto_tb(ctx, 0, ctx->base.pc_next); + break; + case DISAS_NORETURN: + break; + default: + g_assert_not_reached(); } +} =20 -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif +static void tricore_tr_disas_log(const DisasContextBase *dcbase, CPUState = *cpu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); +} + +static const TranslatorOps tricore_tr_ops =3D { + .init_disas_context =3D tricore_tr_init_disas_context, + .tb_start =3D tricore_tr_tb_start, + .insn_start =3D tricore_tr_insn_start, + .breakpoint_check =3D tricore_tr_breakpoint_check, + .translate_insn =3D tricore_tr_translate_insn, + .tb_stop =3D tricore_tr_tb_stop, + .disas_log =3D tricore_tr_disas_log, +}; + + +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) +{ + DisasContext ctx; + translator_loop(&tricore_tr_ops, &ctx.base, cs, tb, max_insns); } =20 void --=20 2.23.0 From nobody Sun Apr 28 00:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de ARC-Seal: i=1; a=rsa-sha256; t=1566469545; cv=none; d=zoho.com; s=zohoarc; b=DVckgcHMOJpjDddYzghGPLstIy9UV/yRzs+5+mVwiGJHUOvGtUcK4FRW54Dl89XpB+y5pYmXgxz3SBJ3x1xmwzv9mS8oLSVuUUT/P1ybScMGevtJzeqK1lqw9RyohWOYN+t9Gx6+l9vfc5UgZeazk1dOfLVeEE0//owPMrGixt0= ARC-Message-Signature: i=1; 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bh=jINiFwIgkBzloBCN5JnJbGmPZ+sUY/qCCm2bVfZUztY=; b=u36unjx77MGxQxiN8m3B+WOuTd tDG4kpY1auMwsamKZZPacN80yNxBEo7cKKhVIZu7LJDAaQUL/JO9Lh8ZI9Cwns2MLLkdlOGdtX/g0 2rHzbdQ/MG4Y7eNo81awFvrjLTyIhkUz201R3aroGPblGInS90AfhQQiXPIJEe5BsYUk=; From: Bastian Koppelmann To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 12:20:45 +0200 Message-Id: <20190822102046.8765-5-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190822102046.8765-1-kbastian@mail.uni-paderborn.de> References: <20190822102046.8765-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-IMT-Spam-Score: 0.0 () X-PMX-Version: 6.4.7.2805085, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.8.22.101216, AntiVirus-Engine: 5.63.0, AntiVirus-Data: 2019.8.13.5630000 X-IMT-Authenticated-Sender: uid=kbastian,ou=People,o=upb,c=de X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 131.234.189.14 Subject: [Qemu-devel] [PULL 4/5] target/tricore: Implement a qemu excptions helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" this helper is only used to raise qemu specific exceptions. We use this helper to raise it on breakpoints. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/tricore/helper.h | 1 + target/tricore/op_helper.c | 7 +++++++ target/tricore/translate.c | 20 +++++++++++++++++++- 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/target/tricore/helper.h b/target/tricore/helper.h index b64780c37d..78176aa17a 100644 --- a/target/tricore/helper.h +++ b/target/tricore/helper.h @@ -153,3 +153,4 @@ DEF_HELPER_2(psw_write, void, env, i32) DEF_HELPER_1(psw_read, i32, env) /* Exceptions */ DEF_HELPER_3(raise_exception_sync, noreturn, env, i32, i32) +DEF_HELPER_2(qemu_excp, noreturn, env, i32) diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 9476d10d00..32c2bc1699 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -107,6 +107,13 @@ static void raise_exception_sync_helper(CPUTriCoreStat= e *env, uint32_t class, raise_exception_sync_internal(env, class, tin, pc, 0); } =20 +void helper_qemu_excp(CPUTriCoreState *env, uint32_t excp) +{ + CPUState *cs =3D env_cpu(env); + cs->exception_index =3D excp; + cpu_loop_exit(cs); +} + /* Addressing mode helper */ =20 static uint16_t reverse16(uint16_t val) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 5fb42abe35..88b2840ad1 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -3261,6 +3261,15 @@ static void generate_trap(DisasContext *ctx, int cla= ss, int tin) tcg_temp_free(tintemp); } =20 +static void generate_qemu_excp(DisasContext *ctx, int excp) +{ + TCGv_i32 tmp =3D tcg_const_i32(excp); + gen_save_pc(ctx->base.pc_next); + gen_helper_qemu_excp(cpu_env, tmp); + ctx->base.is_jmp =3D DISAS_NORETURN; + tcg_temp_free(tmp); +} + static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r= 1, TCGv r2, int16_t address) { @@ -8808,7 +8817,16 @@ static void tricore_tr_insn_start(DisasContextBase *= dcbase, CPUState *cpu) static bool tricore_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, const CPUBreakpoint *bp) { - return false; + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + generate_qemu_excp(ctx, EXCP_DEBUG); + /* + * The address covered by the breakpoint must be included in + * [tb->pc, tb->pc + tb->size) in order to for it to be + * properly cleared -- thus we increment the PC here so that + * the logic setting tb->size below does the right thing. + */ + ctx->base.pc_next +=3D 4; + return true; } =20 static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cpu) --=20 2.23.0 From nobody Sun Apr 28 00:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de ARC-Seal: i=1; a=rsa-sha256; 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bh=sAfZKs3HXjlWqyQKXWkeuMVNCnEjK93bR+6+xewVvnQ=; b=NzoaWSnppenv4SfSQc7bEs1grC k4ASidRu8f0uSj7XK78VjA7PvHtERkBf4rjQbZ63y0vv9hcYWnGgEOkKTABN/e5ofQ2na4uZh4bu7 uovTEOYj+aiaDHNmNCi7/TBfgtZwYWBbhIk4Mh1txntFByPwJTVHv0695VBUu3C69nKw=; From: Bastian Koppelmann To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 12:20:46 +0200 Message-Id: <20190822102046.8765-6-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190822102046.8765-1-kbastian@mail.uni-paderborn.de> References: <20190822102046.8765-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-IMT-Spam-Score: 0.0 () X-PMX-Version: 6.4.7.2805085, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.8.22.101216, AntiVirus-Engine: 5.63.0, AntiVirus-Data: 2019.8.13.5630000 X-IMT-Authenticated-Sender: uid=kbastian,ou=People,o=upb,c=de X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 131.234.189.14 Subject: [Qemu-devel] [PULL 5/5] target/tricore: Fix tricore_tr_translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" we now fetch 2 bytes first, check whether we have a 32 bit insn, and only t= hen fetch another 2 bytes. We also make sure that a 16 bit insn that still fits into the current page does not end up in the next page. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 47 +++++++++++++++++++++++++++----------- 1 file changed, 34 insertions(+), 13 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 88b2840ad1..4f10407477 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8781,17 +8781,9 @@ static void decode_32Bit_opc(DisasContext *ctx) } } =20 -static void decode_opc(DisasContext *ctx) +static bool tricore_insn_is_16bit(uint32_t insn) { - /* 16-Bit Instruction */ - if ((ctx->opcode & 0x1) =3D=3D 0) { - ctx->pc_succ_insn =3D ctx->base.pc_next + 2; - decode_16Bit_opc(ctx); - /* 32-Bit Instruction */ - } else { - ctx->pc_succ_insn =3D ctx->base.pc_next + 4; - decode_32Bit_opc(ctx); - } + return (insn & 0x1) =3D=3D 0; } =20 static void tricore_tr_init_disas_context(DisasContextBase *dcbase, @@ -8829,20 +8821,49 @@ static bool tricore_tr_breakpoint_check(DisasContex= tBase *dcbase, CPUState *cpu, return true; } =20 +static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) +{ + /* + * Return true if the insn at ctx->base.pc_next might cross a page bou= ndary. + * (False positives are OK, false negatives are not.) + * Our caller ensures we are only called if dc->base.pc_next is less t= han + * 4 bytes from the page boundary, so we cross the page if the first + * 16 bits indicate that this is a 32 bit insn. + */ + uint16_t insn =3D cpu_lduw_code(env, ctx->base.pc_next); + + return !tricore_insn_is_16bit(insn); +} + + static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUTriCoreState *env =3D cpu->env_ptr; + uint16_t insn_lo; + bool is_16bit; =20 - ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); - decode_opc(ctx); + insn_lo =3D cpu_lduw_code(env, ctx->base.pc_next); + is_16bit =3D tricore_insn_is_16bit(insn_lo); + if (is_16bit) { + ctx->opcode =3D insn_lo; + ctx->pc_succ_insn =3D ctx->base.pc_next + 2; + decode_16Bit_opc(ctx); + } else { + uint32_t insn_hi =3D cpu_lduw_code(env, ctx->base.pc_next + 2); + ctx->opcode =3D insn_hi << 16 | insn_lo; + ctx->pc_succ_insn =3D ctx->base.pc_next + 4; + decode_32Bit_opc(ctx); + } ctx->base.pc_next =3D ctx->pc_succ_insn; =20 if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { target_ulong page_start; =20 page_start =3D ctx->base.pc_first & TARGET_PAGE_MASK; - if (ctx->base.pc_next - page_start >=3D TARGET_PAGE_SIZE) { + if (ctx->base.pc_next - page_start >=3D TARGET_PAGE_SIZE + || (ctx->base.pc_next - page_start >=3D TARGET_PAGE_SIZE - 3 + && insn_crosses_page(env, ctx))) { ctx->base.is_jmp =3D DISAS_TOO_MANY; } } --=20 2.23.0