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X-Received-From: 2607:f8b0:4864:20::c44 Subject: [Qemu-devel] [RFC PATCH v4 01/75] target/i386: Push rex_r into DisasContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Treat this value the same as we do for rex_b and rex_x. Signed-off-by: Richard Henderson --- target/i386/translate.c | 85 +++++++++++++++++++++-------------------- 1 file changed, 44 insertions(+), 41 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 5cd74ad639..3aac84e5b0 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -43,10 +43,12 @@ #define CODE64(s) ((s)->code64) #define REX_X(s) ((s)->rex_x) #define REX_B(s) ((s)->rex_b) +#define REX_R(s) ((s)->rex_r) #else #define CODE64(s) 0 #define REX_X(s) 0 #define REX_B(s) 0 +#define REX_R(s) 0 #endif =20 #ifdef TARGET_X86_64 @@ -98,7 +100,7 @@ typedef struct DisasContext { #ifdef TARGET_X86_64 int lma; /* long mode active */ int code64; /* 64 bit code segment */ - int rex_x, rex_b; + int rex_x, rex_b, rex_r; #endif int vex_l; /* vex vector length */ int vex_v; /* vex vvvv register, without 1's complement. */ @@ -3037,7 +3039,7 @@ static const struct SSEOpHelper_eppi sse_op_table7[25= 6] =3D { }; =20 static void gen_sse(CPUX86State *env, DisasContext *s, int b, - target_ulong pc_start, int rex_r) + target_ulong pc_start) { int b1, op1_offset, op2_offset, is_xmm, val; int modrm, mod, rm, reg; @@ -3107,8 +3109,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, =20 modrm =3D x86_ldub_code(env, s); reg =3D ((modrm >> 3) & 7); - if (is_xmm) - reg |=3D rex_r; + if (is_xmm) { + reg |=3D REX_R(s); + } mod =3D (modrm >> 6) & 3; if (sse_fn_epp =3D=3D SSE_SPECIAL) { b |=3D (b1 << 8); @@ -3642,7 +3645,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, tcg_gen_ld16u_tl(s->T0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(= val))); } - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); gen_op_mov_reg_v(s, ot, reg, s->T0); break; case 0x1d6: /* movq ea, xmm */ @@ -3686,7 +3689,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, offsetof(CPUX86State, fpregs[rm].mmx)); gen_helper_pmovmskb_mmx(s->tmp2_i32, cpu_env, s->ptr0); } - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); tcg_gen_extu_i32_tl(cpu_regs[reg], s->tmp2_i32); break; =20 @@ -3698,7 +3701,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, } modrm =3D x86_ldub_code(env, s); rm =3D modrm & 7; - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; if (b1 >=3D 2) { goto unknown_op; @@ -3774,7 +3777,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, /* Various integer extensions at 0f 38 f[0-f]. */ b =3D modrm | (b1 << 8); modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); =20 switch (b) { case 0x3f0: /* crc32 Gd,Eb */ @@ -4128,7 +4131,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, b =3D modrm; modrm =3D x86_ldub_code(env, s); rm =3D modrm & 7; - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; if (b1 >=3D 2) { goto unknown_op; @@ -4148,7 +4151,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, rm =3D (modrm & 7) | REX_B(s); if (mod !=3D 3) gen_lea_modrm(env, s, modrm); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); val =3D x86_ldub_code(env, s); switch (b) { case 0x14: /* pextrb */ @@ -4317,7 +4320,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, /* Various integer extensions at 0f 3a f[0-f]. */ b =3D modrm | (b1 << 8); modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); =20 switch (b) { case 0x3f0: /* rorx Gy,Ey, Ib */ @@ -4491,14 +4494,15 @@ static target_ulong disas_insn(DisasContext *s, CPU= State *cpu) TCGMemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; - int rex_w, rex_r; target_ulong pc_start =3D s->base.pc_next; + int rex_w; =20 s->pc_start =3D s->pc =3D pc_start; s->override =3D -1; #ifdef TARGET_X86_64 s->rex_x =3D 0; s->rex_b =3D 0; + s->rex_r =3D 0; s->x86_64_hregs =3D false; #endif s->rip_offset =3D 0; /* for relative ip address */ @@ -4511,7 +4515,6 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) =20 prefixes =3D 0; rex_w =3D -1; - rex_r =3D 0; =20 next_byte: b =3D x86_ldub_code(env, s); @@ -4555,9 +4558,9 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) if (CODE64(s)) { /* REX prefix */ rex_w =3D (b >> 3) & 1; - rex_r =3D (b & 0x4) << 1; + s->rex_r =3D (b & 0x4) << 1; s->rex_x =3D (b & 0x2) << 2; - REX_B(s) =3D (b & 0x1) << 3; + s->rex_b =3D (b & 0x1) << 3; /* select uniform byte register addressing */ s->x86_64_hregs =3D true; goto next_byte; @@ -4590,8 +4593,8 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) if (s->x86_64_hregs) { goto illegal_op; } + s->rex_r =3D (~vex2 >> 4) & 8; #endif - rex_r =3D (~vex2 >> 4) & 8; if (b =3D=3D 0xc5) { /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode = byte */ vex3 =3D vex2; @@ -4681,7 +4684,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) switch(f) { case 0: /* OP Ev, Gv */ modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; rm =3D (modrm & 7) | REX_B(s); if (mod !=3D 3) { @@ -4703,7 +4706,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 1: /* OP Gv, Ev */ modrm =3D x86_ldub_code(env, s); mod =3D (modrm >> 6) & 3; - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); rm =3D (modrm & 7) | REX_B(s); if (mod !=3D 3) { gen_lea_modrm(env, s, modrm); @@ -5123,7 +5126,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) ot =3D mo_b_d(b, dflag); =20 modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); =20 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_op_mov_v_reg(s, ot, s->T1, reg); @@ -5195,7 +5198,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x6b: ot =3D dflag; modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); if (b =3D=3D 0x69) s->rip_offset =3D insn_const_size(ot); else if (b =3D=3D 0x6b) @@ -5247,7 +5250,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x1c1: /* xadd Ev, Gv */ ot =3D mo_b_d(b, dflag); modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; gen_op_mov_v_reg(s, ot, s->T0, reg); if (mod =3D=3D 3) { @@ -5279,7 +5282,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) =20 ot =3D mo_b_d(b, dflag); modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; oldv =3D tcg_temp_new(); newv =3D tcg_temp_new(); @@ -5501,7 +5504,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x89: /* mov Gv, Ev */ ot =3D mo_b_d(b, dflag); modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); =20 /* generate a generic store */ gen_ldst_modrm(env, s, modrm, ot, reg, 1); @@ -5527,7 +5530,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x8b: /* mov Ev, Gv */ ot =3D mo_b_d(b, dflag); modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); =20 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_op_mov_reg_v(s, ot, reg, s->T0); @@ -5577,7 +5580,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) s_ot =3D b & 8 ? MO_SIGN | ot : ot; =20 modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; rm =3D (modrm & 7) | REX_B(s); =20 @@ -5616,7 +5619,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) mod =3D (modrm >> 6) & 3; if (mod =3D=3D 3) goto illegal_op; - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); { AddressParts a =3D gen_lea_modrm_0(env, s, modrm); TCGv ea =3D gen_lea_modrm_1(s, a); @@ -5698,7 +5701,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x87: /* xchg Ev, Gv */ ot =3D mo_b_d(b, dflag); modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; if (mod =3D=3D 3) { rm =3D (modrm & 7) | REX_B(s); @@ -5735,7 +5738,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) do_lxx: ot =3D dflag !=3D MO_16 ? MO_32 : MO_16; modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; if (mod =3D=3D 3) goto illegal_op; @@ -5818,7 +5821,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) modrm =3D x86_ldub_code(env, s); mod =3D (modrm >> 6) & 3; rm =3D (modrm & 7) | REX_B(s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); if (mod !=3D 3) { gen_lea_modrm(env, s, modrm); opreg =3D OR_TMP0; @@ -6669,7 +6672,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) } ot =3D dflag; modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); gen_cmovcc1(env, s, ot, b, modrm, reg); break; =20 @@ -6819,7 +6822,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) do_btx: ot =3D dflag; modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; rm =3D (modrm & 7) | REX_B(s); gen_op_mov_v_reg(s, MO_32, s->T1, reg); @@ -6924,7 +6927,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x1bd: /* bsr / lzcnt */ ot =3D dflag; modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_extu(ot, s->T0); =20 @@ -7686,7 +7689,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) d_ot =3D dflag; =20 modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; rm =3D (modrm & 7) | REX_B(s); =20 @@ -7760,7 +7763,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) goto illegal_op; ot =3D dflag !=3D MO_16 ? MO_32 : MO_16; modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); t0 =3D tcg_temp_local_new(); gen_update_cc_op(s); @@ -7801,7 +7804,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) modrm =3D x86_ldub_code(env, s); if (s->flags & HF_MPX_EN_MASK) { mod =3D (modrm >> 6) & 3; - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); if (prefixes & PREFIX_REPZ) { /* bndcl */ if (reg >=3D 4 @@ -7891,7 +7894,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) modrm =3D x86_ldub_code(env, s); if (s->flags & HF_MPX_EN_MASK) { mod =3D (modrm >> 6) & 3; - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); if (mod !=3D 3 && (prefixes & PREFIX_REPZ)) { /* bndmk */ if (reg >=3D 4 @@ -8005,7 +8008,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) * are assumed to be 1's, regardless of actual values. */ rm =3D (modrm & 7) | REX_B(s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); if (CODE64(s)) ot =3D MO_64; else @@ -8059,7 +8062,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) * are assumed to be 1's, regardless of actual values. */ rm =3D (modrm & 7) | REX_B(s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); if (CODE64(s)) ot =3D MO_64; else @@ -8102,7 +8105,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) mod =3D (modrm >> 6) & 3; if (mod =3D=3D 3) goto illegal_op; - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); /* generate a generic store */ gen_ldst_modrm(env, s, modrm, ot, reg, 1); break; @@ -8328,7 +8331,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) goto illegal_op; =20 modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); =20 if (s->prefix & PREFIX_DATA) { ot =3D MO_16; @@ -8356,7 +8359,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x1c2: case 0x1c4 ... 0x1c6: case 0x1d0 ... 0x1fe: - gen_sse(env, s, b, pc_start, rex_r); + gen_sse(env, s, b, pc_start); break; default: goto unknown_op; --=20 2.20.1