From nobody Thu May 2 08:40:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566405483; cv=none; d=zoho.com; s=zohoarc; b=ULCAsTSsQPa1FEMx8+Xup7vLEMeKC3RWbU3PkfzDVtnfjYNKC1vyqeh3FC5KX3fZvHZRlydz1DdBNrFjp0q6NG3ntkixs7jvlY9D4UcAY9ond5SNWNr47e+aRDYD1zAsMOymIsEWQtVRW0/SaFr93mden7mjnU+gkL6yuKXYVAQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566405483; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To:ARC-Authentication-Results; bh=qm51q/KKQDYF1KNCOirjdphMGwzTzDlEt+JS0SDABQQ=; b=We9mdLOBLxegksmIiO6A9toJgSLwxpibKSJHKjAWg1i8S/hlDbRZ7+GBaJOgufnsku+iEfcp0cuSAgH4L7sYDUzh7t1ebLzwagyl7kGSRulb4wZIAnrTFueR4QMY4EgZZmZGOlLywLm153NSDJIuC0cvnLKEeq7yygaAcCrgK6M= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156640548337544.07943895150936; Wed, 21 Aug 2019 09:38:03 -0700 (PDT) Received: from localhost ([::1]:50428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0TcS-0002u1-7V for importer@patchew.org; Wed, 21 Aug 2019 12:37:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59113) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0TZh-0006Y3-Ub for qemu-devel@nongnu.org; Wed, 21 Aug 2019 12:35:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0TTU-0002FI-4K for qemu-devel@nongnu.org; Wed, 21 Aug 2019 12:28:41 -0400 Received: from serv1.kernkonzept.com ([2a01:4f8:1c1c:b490::2]:44095 helo=mx.kernkonzept.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0TTT-0002F0-HS; Wed, 21 Aug 2019 12:28:39 -0400 Received: from [95.90.100.178] (helo=tweek.dd1.int.kernkonzept.com) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) id 1i0TTS-00084n-Cz; Wed, 21 Aug 2019 18:28:38 +0200 From: Georg Kotheimer To: qemu-devel@nongnu.org Date: Wed, 21 Aug 2019 18:28:31 +0200 Message-Id: <20190821162831.27811-1-georg.kotheimer@kernkonzept.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a01:4f8:1c1c:b490::2 Subject: [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, Georg Kotheimer Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The size of the FPU registers depends solely on the floating point extensions supported by the target architecture. However, in the previous implementation the floating point register size was derived from whether the target architecture is 32-bit or 64-bit. To allow RVF without RVD, changes to riscv_gdb_get_fpu() and riscv_gdb_set_fpu() were necessary. Signed-off-by: Georg Kotheimer Reviewed-by: Alistair Francis Reviewed-by: Jim Wilson --- configure | 4 ++-- target/riscv/gdbstub.c | 45 ++++++++++++++++++++++++------------------ 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/configure b/configure index 714e7fb6a1..44ee953022 100755 --- a/configure +++ b/configure @@ -7596,14 +7596,14 @@ case "$target_name" in TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv mttcg=3Dyes - gdb_xml_files=3D"riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-c= sr.xml" + gdb_xml_files=3D"riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-f= pu.xml riscv-32bit-csr.xml" target_compiler=3D$cross_cc_riscv32 ;; riscv64) TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv mttcg=3Dyes - gdb_xml_files=3D"riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-c= sr.xml" + gdb_xml_files=3D"riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-f= pu.xml riscv-64bit-csr.xml" target_compiler=3D$cross_cc_riscv64 ;; sh4|sh4eb) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 27be93279b..89b2543c9d 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -303,19 +303,22 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_= t *mem_buf, int n) static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) { if (n < 32) { - return gdb_get_reg64(mem_buf, env->fpr[n]); + if (env->misa & RVD) { + return gdb_get_reg64(mem_buf, env->fpr[n]); + } + return gdb_get_reg32(mem_buf, env->fpr[n]); /* there is hole between ft11 and fflags in fpu.xml */ } else if (n < 36 && n > 32) { target_ulong val =3D 0; int result; /* - * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP - * register 33, so we recalculate the map index. + * CSR_FFLAGS is at index 1 in the csr space, and gdb says it is FP + * register 33, so we recalculate the csr index. * This also works for CSR_FRM and CSR_FCSR. */ - result =3D riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0); + result =3D riscv_csrrw_debug(env, n - 33 + CSR_FFLAGS, &val, 0, 0); if (result =3D=3D 0) { - return gdb_get_regl(mem_buf, val); + return gdb_get_reg32(mem_buf, val); } } return 0; @@ -324,20 +327,25 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint= 8_t *mem_buf, int n) static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) { if (n < 32) { - env->fpr[n] =3D ldq_p(mem_buf); /* always 64-bit */ - return sizeof(uint64_t); + if (env->misa & RVD) { + env->fpr[n] =3D ldq_p(mem_buf); + return sizeof(uint64_t); + } else { + env->fpr[n] =3D ldl_p(mem_buf); + return sizeof(uint32_t); + } /* there is hole between ft11 and fflags in fpu.xml */ } else if (n < 36 && n > 32) { - target_ulong val =3D ldtul_p(mem_buf); + target_ulong val =3D ldl_p(mem_buf); int result; /* - * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP - * register 33, so we recalculate the map index. + * CSR_FFLAGS is at index 1 in the csr space, and gdb says it is FP + * register 33, so we recalculate the csr index. * This also works for CSR_FRM and CSR_FCSR. */ - result =3D riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1); + result =3D riscv_csrrw_debug(env, n - 33 + CSR_FFLAGS, NULL, val, = -1); if (result =3D=3D 0) { - return sizeof(target_ulong); + return sizeof(uint32_t); } } return 0; @@ -375,20 +383,19 @@ void riscv_cpu_register_gdb_regs_for_features(CPUStat= e *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; -#if defined(TARGET_RISCV32) - if (env->misa & RVF) { + + if (env->misa & RVD) { + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, + 36, "riscv-64bit-fpu.xml", 0); + } else if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } =20 +#if defined(TARGET_RISCV32) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 4096, "riscv-32bit-csr.xml", 0); #elif defined(TARGET_RISCV64) - if (env->misa & RVF) { - gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 36, "riscv-64bit-fpu.xml", 0); - } - gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 4096, "riscv-64bit-csr.xml", 0); #endif --=20 2.20.1