From nobody Sun Feb 8 14:35:21 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1566379512; cv=none; d=zoho.com; s=zohoarc; b=Myrs2DNVu3V0OEgxIY7Q9h+kFVcOBWRSDmuzzplUjRYcs3fypNW00Wnn+4At5GBMKdv9pfm5BKCkc8a5RzCB/BpK4R9z9fkmBofD3YQe06HQI9oJSjCyywPPpW/r9AuGhWqVBP/lgzXDfzdgxkKAWZOPqa6m+XzmRMmon8fOd6E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566379512; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=nyCSWmWwwzEc0TYK6kO+mPFp02LioDf7IEM7Xz4hd4k=; b=LL3X0wGu5G+31TAvb9ncZFdHTE18gPcdeEHNGx1OKXaUDZjQUGT1VCfLLIVwXx7JeCJwQ3hSRkX/1nYdSlWodt0OScBUKqMskpWH8r/Gw1k5LoC1imo9Yq2zAcm3jwY3YeFg60FBjhO1Mbib/nNK7DvLskzw0dVAMOkRAJc2HPA= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15663795121459.755017426221457; Wed, 21 Aug 2019 02:25:12 -0700 (PDT) Received: from localhost ([::1]:46392 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0Mrd-00009F-7C for importer@patchew.org; Wed, 21 Aug 2019 05:25:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36865) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0Mpb-0006DT-U3 for qemu-devel@nongnu.org; Wed, 21 Aug 2019 05:23:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0Mpa-0001BU-Jz for qemu-devel@nongnu.org; Wed, 21 Aug 2019 05:23:03 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39420) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0Mpa-0001B0-Bn; Wed, 21 Aug 2019 05:23:02 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id AA571106BB20; Wed, 21 Aug 2019 09:23:01 +0000 (UTC) Received: from t460s.redhat.com (unknown [10.36.118.29]) by smtp.corp.redhat.com (Postfix) with ESMTP id 069C25C22C; Wed, 21 Aug 2019 09:22:59 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Wed, 21 Aug 2019 11:22:50 +0200 Message-Id: <20190821092252.26541-3-david@redhat.com> In-Reply-To: <20190821092252.26541-1-david@redhat.com> References: <20190821092252.26541-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.64]); Wed, 21 Aug 2019 09:23:01 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v1 2/4] s390x/tcg: Introduce probe_read_access() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Florian Weimer , Thomas Huth , David Hildenbrand , Cornelia Huck , Stefano Brivio , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Let's introduce a helper to probe read access (by actually reading a piece of data of every page) and add a comment why this might not be 100% safe in all scenarios. Once we actually run into that issue, we'll have to think of something else. Signed-off-by: David Hildenbrand --- target/s390x/internal.h | 2 ++ target/s390x/mem_helper.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/target/s390x/internal.h b/target/s390x/internal.h index c243fa725b..bdb833c525 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -354,6 +354,8 @@ void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1, uin= tptr_t ra); =20 /* mem_helper.c */ target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr); +void probe_read_access(CPUS390XState *env, uint64_t addr, uint64_t len, + uintptr_t ra); void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len, uintptr_t ra); =20 diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 7819aca15d..4e9d126e2c 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -2612,6 +2612,40 @@ uint32_t HELPER(cu42)(CPUS390XState *env, uint32_t r= 1, uint32_t r2, uint32_t m3) decode_utf32, encode_utf16); } =20 +/* + * Make sure the read access is permitted and TLB entries are created. In + * very rare cases it might happen that the actual accesses might need + * new MMU translations. If the page tables were changed in between, we + * might still trigger a fault. However, this seems to barely happen, so we + * can ignore this for now. + */ +void probe_read_access(CPUS390XState *env, uint64_t addr, uint64_t len, + uintptr_t ra) +{ +#ifdef CONFIG_USER_ONLY + if (!guest_addr_valid(addr) || !guest_addr_valid(addr + len - 1) || + page_check_range(addr, len, PAGE_READ) < 0) { + s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra); + } +#else + while (len) { + const uint64_t pagelen =3D -(addr | -TARGET_PAGE_MASK); + const uint64_t curlen =3D MIN(pagelen, len); + + cpu_ldub_data_ra(env, addr, ra); + addr =3D wrap_address(env, addr + curlen); + len -=3D curlen; + } +#endif +} + +/* + * Make sure the write access is permitted and TLB entries are created. In + * very rare cases it might happen that the actual accesses might need + * new MMU translations - especially, on LAP protected pages. If the page + * tables were changed in between, we might still trigger a fault. However, + * this seems to barely happen, so we can ignore this for now. + */ void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len, uintptr_t ra) { --=20 2.21.0