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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id k22sm21690743pfk.157.2019.08.20.14.07.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2019 14:07:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2a32Mx4gC1OivU2H0L4/pxSm6z4s7e5vqER4g0XWBWE=; b=t4+CpH7WoO1dpaFtXxZANjvR5GIyBQhRXlcRqDOe68NTVxSVzNUYX6lb1xMam3RFy5 MKPTNUGdrYPcNGbeR+AK7caD7kT3/5EDhg5gIPnVxc7r+xcBmfnTaoFs3uM0tEcWBQxZ N9N9zRsklrw9kQB7IxHR21/Fvn6uhH10cVuEMhBtgSR2J9n+nPrNMYo47eHyq+9jECXx jZmeb5okvneBbIk0ud0fjL1U5Rrl11z5Z6WQGK597gqmlX6rDiD+DUqMLTl9b7KIQpzc GibmOpEyz4fAI3AYuP8O3Z6wTVFRE29Ihp9iUBK/BQRGy1e6W9CMRrBDs4YfU2DazTnd v+pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2a32Mx4gC1OivU2H0L4/pxSm6z4s7e5vqER4g0XWBWE=; b=T/m59ccQSvwqDnmE4gZlVH4YeYJxIhtK2Opqn/A9A16XzgoRBnAgGyJerork/5+3LL zmzfhcf56tJRcDAm/Z+i+uH9Ts76rygwseXVe34IciX6s0WgVEtRoCiQ3/rkG21UeQ6u oLUPDgx4B4Gj8/mr8okIIAtnCL3RaOaDDI6wt6l5b+StplfcfE57rwfld5i76JAKA2Rh +VIytsVJQvi2itYCGjl3tGCBykuIm/xUB06EDOSchaLgbE9Rf8SJsxDHJ96WNpJ/zXR+ CpynTvyi0QymP80A4yx8VPgfm+uvEhlYxOduRSRvH9JlG4kpmw1093lrnjnvY9vDEhBH yUuw== X-Gm-Message-State: APjAAAU56a3sajvheSkkTxios70mfsHFO21Wfkk3RwSFQHvyuwgkSlt8 udgYTO9EpBHpf/axZkN6keC8iltFXXQ= X-Google-Smtp-Source: APXvYqzKky0E8Gr58dsdTP1Cq5p0trRTwZxQBJk9VmyO1VJ6WPO2Ay7UXgUC3U0Sw7lu504NZWxXDw== X-Received: by 2002:a63:4e05:: with SMTP id c5mr6304272pgb.396.1566335245652; Tue, 20 Aug 2019 14:07:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 20 Aug 2019 14:07:05 -0700 Message-Id: <20190820210720.18976-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190820210720.18976-1-richard.henderson@linaro.org> References: <20190820210720.18976-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v5 02/17] target/arm: Split out rebuild_hflags_a64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Create a function to compute the values of the TBFLAG_A64 bits that will be cached. For now, the env->hflags variable is not used, and the results are fed back to cpu_get_tb_cpu_state. Signed-off-by: Richard Henderson --- target/arm/helper.c | 131 +++++++++++++++++++++++--------------------- 1 file changed, 69 insertions(+), 62 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f2c6419369..02cb43cf58 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11032,6 +11032,71 @@ static uint32_t rebuild_hflags_common(CPUARMState = *env, int fp_el, return flags; } =20 +static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, + ARMMMUIdx mmu_idx) +{ + ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); + ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); + uint32_t flags =3D 0; + uint64_t sctlr; + int tbii, tbid; + + flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); + + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + if (regime_el(env, stage1) < 2) { + ARMVAParameters p1 =3D aa64_va_parameters_both(env, -1, stage1); + tbid =3D (p1.tbi << 1) | p0.tbi; + tbii =3D tbid & ~((p1.tbid << 1) | p0.tbid); + } else { + tbid =3D p0.tbi; + tbii =3D tbid & !p0.tbid; + } + + flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); + + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { + int sve_el =3D sve_exception_el(env, el); + uint32_t zcr_len; + + /* + * If SVE is disabled, but FP is enabled, + * then the effective len is 0. + */ + if (sve_el !=3D 0 && fp_el =3D=3D 0) { + zcr_len =3D 0; + } else { + zcr_len =3D sve_zcr_len_for_el(env, el); + } + flags =3D FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); + flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); + } + + sctlr =3D arm_sctlr(env, el); + + if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + } + } + + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { + /* Note that SCTLR_EL[23].BT =3D=3D SCTLR_BT1. */ + if (sctlr & (el =3D=3D 0 ? SCTLR_BT0 : SCTLR_BT1)) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, BT, 1); + } + } + + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -11041,67 +11106,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, uint32_t flags =3D 0; =20 if (is_a64(env)) { - ARMCPU *cpu =3D env_archcpu(env); - uint64_t sctlr; - *pc =3D env->pc; - flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); - - /* Get control bits for tagged addresses. */ - { - ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); - ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; - - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - if (regime_el(env, stage1) < 2) { - ARMVAParameters p1 =3D aa64_va_parameters_both(env, -1, st= age1); - tbid =3D (p1.tbi << 1) | p0.tbi; - tbii =3D tbid & ~((p1.tbid << 1) | p0.tbid); - } else { - tbid =3D p0.tbi; - tbii =3D tbid & !p0.tbid; - } - - flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); - flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - int sve_el =3D sve_exception_el(env, current_el); - uint32_t zcr_len; - - /* If SVE is disabled, but FP is enabled, - * then the effective len is 0. - */ - if (sve_el !=3D 0 && fp_el =3D=3D 0) { - zcr_len =3D 0; - } else { - zcr_len =3D sve_zcr_len_for_el(env, current_el); - } - flags =3D FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); - flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); - } - - sctlr =3D arm_sctlr(env, current_el); - - if (cpu_isar_feature(aa64_pauth, cpu)) { - /* - * In order to save space in flags, we record only whether - * pauth is "inactive", meaning all insns are implemented as - * a nop, or "active" when some action must be performed. - * The decision of which action to take is left to a helper. - */ - if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB= )) { - flags =3D FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); - } - } - - if (cpu_isar_feature(aa64_bti, cpu)) { - /* Note that SCTLR_EL[23].BT =3D=3D SCTLR_BT1. */ - if (sctlr & (current_el =3D=3D 0 ? SCTLR_BT0 : SCTLR_BT1)) { - flags =3D FIELD_DP32(flags, TBFLAG_A64, BT, 1); - } + flags =3D rebuild_hflags_a64(env, current_el, fp_el, mmu_idx); + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags =3D FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } } else { @@ -11121,9 +11128,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); } - } =20 - flags =3D rebuild_hflags_common(env, fp_el, mmu_idx, flags); + flags =3D rebuild_hflags_common(env, fp_el, mmu_idx, flags); + } =20 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: --=20 2.17.1