From nobody Sun May 19 04:34:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1566318691; cv=none; d=zoho.com; s=zohoarc; b=hrln+j4MvXqS6Hk95wDNNkPBxojd48tusvQiswm1B27NxXaiERRVMp3tHawsdBY8KQKUo+xEIAFH9Y2SkGSr4IF0/Grjf7HaG5TWtkKk/Bx/yF6idyY1ZCbM8LAUQ62r864BGf8Jxni667i1Qgm8wkivOy5AgW2y0ZTli/qs3zU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566318691; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To:ARC-Authentication-Results; bh=mE2bL7HIdjIU+QL2BMEeld2degiSF7KJ/wWkqZJQZXg=; b=IApaQpiwfe3skdlRNBaUNK2iHYW4pSTMpc2UylUf/N5P3vw6GujDCu6huWCPk5UeAQjUzDuludeZlXAvdHmvqiefpxhvnzIMb46Tq/jN6SlmNHyvvjV7+ruAwzgtqkAOueBf0snHax17GxQszQGuW3PFVCOT4GudRqYywbkIR+Q= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566318691585322.1473731770951; Tue, 20 Aug 2019 09:31:31 -0700 (PDT) Received: from localhost ([::1]:39584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i072g-0004EY-Id for importer@patchew.org; Tue, 20 Aug 2019 12:31:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45502) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i071i-0003lh-Bq for qemu-devel@nongnu.org; Tue, 20 Aug 2019 12:30:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i071g-0005Y1-Rh for qemu-devel@nongnu.org; Tue, 20 Aug 2019 12:30:29 -0400 Received: from mx1.redhat.com ([209.132.183.28]:33058) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i071g-0005WZ-K9 for qemu-devel@nongnu.org; Tue, 20 Aug 2019 12:30:28 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 40BFD102BB36 for ; Tue, 20 Aug 2019 16:30:27 +0000 (UTC) Received: from localhost.localdomain.com (ovpn-204-111.brq.redhat.com [10.40.204.111]) by smtp.corp.redhat.com (Postfix) with ESMTPS id EE6E160BF4; Tue, 20 Aug 2019 16:30:17 +0000 (UTC) From: Julia Suvorova To: qemu-devel@nongnu.org Date: Tue, 20 Aug 2019 18:30:05 +0200 Message-Id: <20190820163005.1880-1-jusual@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.64]); Tue, 20 Aug 2019 16:30:27 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2] virtio-pci: Add Function Level Reset support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Williamson , Julia Suvorova , mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Using FLR becomes convenient in cases where resetting the bus is impractical, for example, when debugging the behavior of individual functions. Signed-off-by: Julia Suvorova --- Requires definition of 4.2 machines: Based-on: <20190724103524.20916-1-cohuck@redhat.com> v2: Add compatibility property "x-pcie-flr-init" hw/core/machine.c | 4 +++- hw/virtio/virtio-pci.c | 10 ++++++++++ hw/virtio/virtio-pci.h | 4 ++++ 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 83cd1bfeec..829ada099e 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -27,7 +27,9 @@ #include "hw/pci/pci.h" #include "hw/mem/nvdimm.h" =20 -GlobalProperty hw_compat_4_1[] =3D {}; +GlobalProperty hw_compat_4_1[] =3D { + { "virtio-pci", "x-pcie-flr-init", "off" }, +}; const size_t hw_compat_4_1_len =3D G_N_ELEMENTS(hw_compat_4_1); =20 GlobalProperty hw_compat_4_0[] =3D { diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 8babd92e59..0075b3e2af 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -601,6 +601,10 @@ static void virtio_write_config(PCIDevice *pci_dev, ui= nt32_t address, =20 pci_default_write_config(pci_dev, address, val, len); =20 + if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) { + pcie_cap_flr_write_config(pci_dev, address, val, len); + } + if (range_covers_byte(address, len, PCI_COMMAND) && !(pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { virtio_pci_stop_ioeventfd(proxy); @@ -1777,6 +1781,10 @@ static void virtio_pci_realize(PCIDevice *pci_dev, E= rror **errp) pcie_ats_init(pci_dev, 256); } =20 + if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) { + /* Set Function Level Reset capability bit */ + pcie_cap_flr_init(pci_dev); + } } else { /* * make future invocations of pci_is_express() return false @@ -1844,6 +1852,8 @@ static Property virtio_pci_properties[] =3D { VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true), DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_INIT_PM_BIT, true), + DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags, + VIRTIO_PCI_FLAG_INIT_FLR_BIT, true), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h index 292275acb1..e2eaaa9182 100644 --- a/hw/virtio/virtio-pci.h +++ b/hw/virtio/virtio-pci.h @@ -44,6 +44,7 @@ enum { VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, VIRTIO_PCI_FLAG_INIT_PM_BIT, + VIRTIO_PCI_FLAG_INIT_FLR_BIT, }; =20 /* Need to activate work-arounds for buggy guests at vmstate load. */ @@ -80,6 +81,9 @@ enum { /* Init Power Management */ #define VIRTIO_PCI_FLAG_INIT_PM (1 << VIRTIO_PCI_FLAG_INIT_PM_BIT) =20 +/* Init Function Level Reset capability */ +#define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT) + typedef struct { MSIMessage msg; int virq; --=20 2.21.0