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X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PATCH v2 60/68] target/arm: Convert T16, push and pop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 83 ++++++------------------------------------ target/arm/t16.decode | 10 +++++ 2 files changed, 22 insertions(+), 71 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9e0345adf7..5f876290ba 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7494,6 +7494,16 @@ static int t16_setflags(DisasContext *s) return s->condexec_mask =3D=3D 0; } =20 +static int t16_push_list(DisasContext *s, int x) +{ + return (x & 0xff) | (x & 0x100) << (14 - 8); +} + +static int t16_pop_list(DisasContext *s, int x) +{ + return (x & 0xff) | (x & 0x100) << (15 - 8); +} + /* * Include the generated decoders. */ @@ -10591,7 +10601,6 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) { uint32_t val, op, rm, rd, shift, cond; int32_t offset; - int i; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10664,76 +10673,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) goto illegal_op; =20 case 4: case 5: case 0xc: case 0xd: - /* - * 0b1011_x10x_xxxx_xxxx - * - push/pop - */ - addr =3D load_reg(s, 13); - if (insn & (1 << 8)) - offset =3D 4; - else - offset =3D 0; - for (i =3D 0; i < 8; i++) { - if (insn & (1 << i)) - offset +=3D 4; - } - if ((insn & (1 << 11)) =3D=3D 0) { - tcg_gen_addi_i32(addr, addr, -offset); - } - - if (s->v8m_stackcheck) { - /* - * Here 'addr' is the lower of "old SP" and "new SP"; - * if this is a pop that starts below the limit and ends - * above it, it is UNKNOWN whether the limit check trigger= s; - * we choose to trigger. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - for (i =3D 0; i < 8; i++) { - if (insn & (1 << i)) { - if (insn & (1 << 11)) { - /* pop */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, i, tmp); - } else { - /* push */ - tmp =3D load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - /* advance to the next address. */ - tcg_gen_addi_i32(addr, addr, 4); - } - } - tmp =3D NULL; - if (insn & (1 << 8)) { - if (insn & (1 << 11)) { - /* pop pc */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - /* don't set the pc until the rest of the instruction - has completed */ - } else { - /* push lr */ - tmp =3D load_reg(s, 14); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_gen_addi_i32(addr, addr, 4); - } - if ((insn & (1 << 11)) =3D=3D 0) { - tcg_gen_addi_i32(addr, addr, -offset); - } - /* write back the new stack pointer */ - store_reg(s, 13, addr); - /* set the new PC value */ - if ((insn & 0x0900) =3D=3D 0x0900) { - store_reg_from_load(s, 15, tmp); - } - break; + /* push/pop, in decodetree */ + goto illegal_op; =20 case 1: case 3: case 9: case 11: /* czb */ rm =3D insn & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index d5b046d105..d731402036 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -221,3 +221,13 @@ REVSH 1011 1010 11 ... ... @rdm # rest of the space is a reserved hint, behaves as nop. NOP 1011 1111 ---- 0000 } + +# Push and Pop + +%push_list 0:9 !function=3Dt16_push_list +%pop_list 0:9 !function=3Dt16_pop_list + +STM 1011 010 ......... \ + &ldst_block i=3D0 b=3D1 u=3D0 w=3D1 rn=3D13 list=3D%push_l= ist +LDM_t16 1011 110 ......... \ + &ldst_block i=3D1 b=3D0 u=3D0 w=3D1 rn=3D13 list=3D%pop_li= st --=20 2.17.1