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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:37:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2Kulh9+xu3WIHTQp568/rqttxBdLC2HThk9gtIjvuts=; b=bcDdgqJgtfww91QUIwvYvDmy1SzpiaiU7oJ0yEBY+oshoiBQJ00X3efqYkGkapY2uT RkWzqYsT+io2tz0G/A0PbLYULvV8ZyJWpnmPgmgYXNJkWeHUI/OPTfinbfXINrpH1nyG 74C0j15KycMM6MvVHsAVv4h+BLTKIPZ2rhi3yp1q2IIRMAW2yykbeJLLRAB1z5J8yzpC PhV3qIJ8mv8ONN75al+TKMLnvCTf+nyHbdRLlF1MSbSs6VXZga7n5WsskSNRUnk3K4cy Bq0VeuLzDZXL0KPko1KnXlQkRFAUN4KDyvCZQQf48vvKD9ziKjkeRNo0TVi5iInbfYdM T9aA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2Kulh9+xu3WIHTQp568/rqttxBdLC2HThk9gtIjvuts=; b=pWFi0uqCepJ6QoWNbGK0ztthQsML7JyZwpdMDAuB8dVIpkLMSb/4F7ZQPVytYdPRcK kmKNnLaKxJrFIpQbi48UlbWe4K/ppY+Oy4oIK4/iIOe6YOO6EwACwbh9RpKW2ERGeOnF si/KLsSb/YURLGGfSDkECNo+ISgTQyo//8WIvEJAawbbqmyNf2I0bMNmdNMKwZ3pGxUz 1jGu9fL/YBzXKDrvY/ORL5pAJmP+T15wCTMhOMW8h3gizTnTTcGixnEizk32BskTYycV czplNQCLXEnaDi79FiBSQwuyQPiEX2pBZacVdcwFzW6YezTBGYoJZto8+gQUpQSi2T2p qI6w== X-Gm-Message-State: APjAAAVU3+nn2+YuzxzyR4drU7vWdIQDA4hOSOzg1zvwNUCnCRoxrwnr 1qkGb/CPl0MDgXBzow7ag4oJz6JDoZs= X-Google-Smtp-Source: APXvYqyKJAHpJg7XEacRqWZFd6gkBoWMupi7CNCqdO3DF/zcD5RkEWtj0SXLqUsxmhO0yYSnUyvX+w== X-Received: by 2002:a63:3203:: with SMTP id y3mr22150875pgy.191.1566250678807; Mon, 19 Aug 2019 14:37:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:48 -0700 Message-Id: <20190819213755.26175-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 01/68] target/arm: Use store_reg_from_load in thumb2 code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This function already includes the test for an interworking write to PC from a load. Change the T32 LDM implementation to match the A32 LDM implementation. For LDM, the reordering of the tests does not change valid behaviour because the only case that differs is has rn =3D=3D 15, which is UNPREDICTABLE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d948757131..db69d998eb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9714,13 +9714,11 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) /* Load. */ tmp =3D tcg_temp_new_i32(); gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i =3D=3D 15) { - gen_bx_excret(s, tmp); - } else if (i =3D=3D rn) { + if (i =3D=3D rn) { loaded_var =3D tmp; loaded_base =3D 1; } else { - store_reg(s, i, tmp); + store_reg_from_load(s, i, tmp); } } else { /* Store. */ @@ -10854,11 +10852,7 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tcg_temp_free_i32(addr); goto illegal_op; } - if (rs =3D=3D 15) { - gen_bx_excret(s, tmp); - } else { - store_reg(s, rs, tmp); - } + store_reg_from_load(s, rs, tmp); } else { /* Store. */ tmp =3D load_reg(s, rs); --=20 2.17.1 From nobody Fri May 3 06:53:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566250985; cv=none; d=zoho.com; s=zohoarc; b=D99LeXGa0u3LDHUKmeNj8fDUmgCfuTCTh2eERkd+c5uWZlQDHFhQeaQiC2qgCeeAgOMVEy5xP3bJgmm3akBu+7uV2cPv9XeFeYpfduxhdH1cTYaqYelgDRBRuX9hmKhzY6rMBpOe6xF/9P6WSp9tkrUei11IXkt8J3KsJ/68Pgo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566250985; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Lk8BfvHlK27e0gTYQ9ZvQ9xJX5SjXjlYlXz2Xz9pa/E=; b=d49gUQmu7G+jp18dvuMQCr5/FWOiIEXo5JvIpLYboxXGhlAgF+1tPIcxlA2QN1eIpei8qTgD3QXSWwvoWz6n2RtVDT64ikfblFIKwTWo540E0MGpWDKnom0Qkp85sSFwyAxK3iFCBkIdiH5SVCrTMbw2lVrQkcv1dJvxi90vMTs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566250985717883.4161869242739; Mon, 19 Aug 2019 14:43:05 -0700 (PDT) Received: from localhost ([::1]:58976 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpQe-0007jY-9M for importer@patchew.org; Mon, 19 Aug 2019 17:43:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58454) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpLn-0001AI-Bi for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpLl-0005yB-Lf for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:03 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:47035) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpLl-0005xa-G0 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:01 -0400 Received: by mail-pg1-x542.google.com with SMTP id m3so1914663pgv.13 for ; Mon, 19 Aug 2019 14:38:01 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.37.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:37:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Lk8BfvHlK27e0gTYQ9ZvQ9xJX5SjXjlYlXz2Xz9pa/E=; b=jUNWfg2JTViv2fix6PZzGp0t1W7scoz+UR0bxYVGWrHznfKiCzy2XwTqvKrR6YQh4j gi/Lex9NfNxyOzHOUQMPpVIcgXdcOuLFJ0o9ul2/MzrK4rXJq6VqYZYdPBiMb00gpiZM JCDbQEgRPoMKxs5QYoB1GdDdl4QNwttpoJ6rzwP47jitpJki0PX50lUaLjLBY6z+t44I qwF6DPhEcmIVqV5YDBAm3Wtl2ouHW6wekL9UsRtEGPK9eThdMaq9XuCVLWhvdZVmzXwv jgtdOa2K7nEhcXsvOJkyWEdzWJEFcx/qfqImcjMn00dq21LeR4HFMiWfQX0n5A8J8qCk +8cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Lk8BfvHlK27e0gTYQ9ZvQ9xJX5SjXjlYlXz2Xz9pa/E=; b=sL+09IAPl0MWffsiHJBSd+eaC/5816SCaFcEikdpRu3TS7/87NzLh2xxhwj8Mk1eTL j4S8y0bKfEFArCX6nSfgF2WNKdDv2LrkrmqtPdkX52BStE0eGUIR9m3gvo2b9KkuLgkd VRhA8/CVOV6vjMeuII8eFn0RcNx5q5R3zog/Kaku8z9DwPIIw4CC2O96vlhgYdbKCBSt QJN8oWud2GMFxzV50FWacw9mxLUTqAngCa2+w7C39yGkohrLdZq8dWN/hdWWhak+CNuU lX3Sp3pk3yXQ+YzRNCRe2e3A6T4kJhIYa5wi9inmlnBcXPUOm8gVl1sl8n1v4US0iEZ8 lvkQ== X-Gm-Message-State: APjAAAXepAhBEJfgheeKRP7BjHvxNPsPVL47FeiC90eiXkEL44+yo86N ysqDwxRpvNO5hcPcAYiLHZgqOp4h+FM= X-Google-Smtp-Source: APXvYqwYTOrYgJfeqSSXZKA8jkQpd8+4/oaIhN9TVyKIknWIa7I7JvWd9deYzoUwsWQBWPl1sJuzpw== X-Received: by 2002:a63:2252:: with SMTP id t18mr21883402pgm.5.1566250680149; Mon, 19 Aug 2019 14:38:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:49 -0700 Message-Id: <20190819213755.26175-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 02/68] target/arm: Add stubs for aa32 decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the infrastructure that will become the new decoder. No instructions adjusted so far. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.c | 31 ++++++++++++++++++++++++++++++- target/arm/Makefile.objs | 18 ++++++++++++++++++ target/arm/a32-uncond.decode | 23 +++++++++++++++++++++++ target/arm/a32.decode | 23 +++++++++++++++++++++++ target/arm/t32.decode | 20 ++++++++++++++++++++ 5 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 target/arm/a32-uncond.decode create mode 100644 target/arm/a32.decode create mode 100644 target/arm/t32.decode diff --git a/target/arm/translate.c b/target/arm/translate.c index db69d998eb..c759fe0797 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7661,6 +7661,18 @@ static void arm_skip_unless(DisasContext *s, uint32_= t cond) arm_gen_test_cc(cond ^ 1, s->condlabel); } =20 +/* + * Include the generated decoders. + */ + +#include "decode-a32.inc.c" +#include "decode-a32-uncond.inc.c" +#include "decode-t32.inc.c" + +/* + * Legacy decoder. + */ + static void disas_arm_insn(DisasContext *s, unsigned int insn) { unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; @@ -7679,7 +7691,8 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) return; } cond =3D insn >> 28; - if (cond =3D=3D 0xf){ + + if (cond =3D=3D 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we * choose to UNDEF. In ARMv5 and above the space is used * for miscellaneous unconditional instructions. @@ -7687,6 +7700,11 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) ARCH(5); =20 /* Unconditional instructions. */ + if (disas_a32_uncond(s, insn)) { + return; + } + /* fall back to legacy decoder */ + if (((insn >> 25) & 7) =3D=3D 1) { /* NEON Data processing. */ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { @@ -7901,6 +7919,12 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) next instruction */ arm_skip_unless(s, cond); } + + if (disas_a32(s, insn)) { + return; + } + /* fall back to legacy decoder */ + if ((insn & 0x0f900000) =3D=3D 0x03000000) { if ((insn & (1 << 21)) =3D=3D 0) { ARCH(6T2); @@ -9386,6 +9410,11 @@ static void disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) ARCH(6T2); } =20 + if (disas_t32(s, insn)) { + return; + } + /* fall back to legacy decoder */ + rn =3D (insn >> 16) & 0xf; rs =3D (insn >> 12) & 0xf; rd =3D (insn >> 8) & 0xf; diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 5cafc1eb6c..7806b4dac0 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -28,9 +28,27 @@ target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/a= rm/vfp-uncond.decode $(D $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\ "GEN", $(TARGET_DIR)$@) =20 +target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETRE= E) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.deco= de $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETRE= E) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c +target/arm/translate.o: target/arm/decode-a32.inc.c +target/arm/translate.o: target/arm/decode-a32-uncond.inc.c +target/arm/translate.o: target/arm/decode-t32.inc.c =20 obj-y +=3D tlb_helper.o debug_helper.o obj-y +=3D translate.o op_helper.o diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode new file mode 100644 index 0000000000..8dee26d3b6 --- /dev/null +++ b/target/arm/a32-uncond.decode @@ -0,0 +1,23 @@ +# A32 unconditional instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# All insns that have 0xf in insn[31:28] are decoded here. +# All of those that have a COND field in insn[31:28] are in a32.decode +# diff --git a/target/arm/a32.decode b/target/arm/a32.decode new file mode 100644 index 0000000000..a3e6e8c1c2 --- /dev/null +++ b/target/arm/a32.decode @@ -0,0 +1,23 @@ +# A32 conditional instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# All of the insn that have a COND field in insn[31:28] are here. +# All insns that have 0xf in insn[31:28] are in a32-uncond.decode. +# diff --git a/target/arm/t32.decode b/target/arm/t32.decode new file mode 100644 index 0000000000..ac01fb6958 --- /dev/null +++ b/target/arm/t32.decode @@ -0,0 +1,20 @@ +# Thumb2 instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# --=20 2.17.1 From nobody Fri May 3 06:53:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566250874; cv=none; d=zoho.com; s=zohoarc; b=n3rWSwWm7MheszwZggVLLu+IZuZYFWspZNwSbqriytlrddYMFr5Ly3JF5CH3+IDPal9zjn1PPxWan3gGjGiwMnyNJT3+GHpSyzL3NntlKPiXtw57OXNEPqAShJqA85M8a0xvO4HkD9q6xkHSe2BPXMB/OT4ZnT6t292Xi24qK44= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566250874; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=QIkenGimVRi/Plae7Rw1++VDbOCShjtnkN1KcI6L2k4=; b=au5TaDO8H6Ww7r13DbF/aFO7gvfaJBOIvjhhyAz76MRy7uyQPXouhdSXIo/RI8ftjpJUvmVfuv2kkTlnou5aR4QTfSLdEvyc+WrWWGWwWBVia4RhMHcgZbJtwzfTgXn52I4/ZbGbrAt4wKW6BBtkVNa7ZquwS2SH5o7KDePBjYg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566250874572249.6688275028264; Mon, 19 Aug 2019 14:41:14 -0700 (PDT) Received: from localhost ([::1]:58906 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpOr-0004fy-5x for importer@patchew.org; Mon, 19 Aug 2019 17:41:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58491) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpLp-0001ER-IO for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpLn-0005zP-Lq for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:05 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:39674) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpLn-0005yq-EO for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:03 -0400 Received: by mail-pf1-x441.google.com with SMTP id f17so1943579pfn.6 for ; Mon, 19 Aug 2019 14:38:03 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QIkenGimVRi/Plae7Rw1++VDbOCShjtnkN1KcI6L2k4=; b=Ma302CXnDvBvFDlsJ1ASzvwZWQdepTRMZojxPkgr1azkyT9L3bKyX/epEb9VpPWNyY LK+X2aenBG8stSLs19kItzgkilHZ97LLZDgTuiWQr7hR2XtV+Pf4YxQkKD2XnthhXMXs hY14rW3s3OEf6rqt+eHI/9frbLXx5PQKCgsA6+5Si2+FLfwWg7GsNhZFJQXT/3Es8zYc ROyIC3F1pxm8IEtFSyX8Nd4GqDEfCc7Tn4RhHKxjG1M9W28UPQN+TdYp0/v/ufcDvCND rTso3NYWnJkdcNTip2TaIXVKs4EvQ3j4pETuATKtqTqZMBnz0iTZ1ocQzdEvZY+SQOAa Vn/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QIkenGimVRi/Plae7Rw1++VDbOCShjtnkN1KcI6L2k4=; b=tEfug4rrV4f7pZo+tddlBdd2e1uJ5ouRIQM3Fx2NwiIADo3gz0WEYKKDO5m5beMVHC 33TOxBuxJ0neo9eDF1giD5EO4mrvNRkWg8yr2qML3OkFOdqdsD4XbDL9qS7GM2W5ZwCN AvRyprSj633obpYGSQdPFhfnlqfnDPgVVKRcJfHAEIeK1gEXb6eRyDp1yWT4vrocJM0j QAsBvfh29WTV1zl7FRrI1mCBIiEz3vUUGX4xK1kOL22T0mVYrrs1be/g8K+NIs5k66O1 0gV1xlUB5qt44RtYj/twe3Zc7N5+l/ry+3kkql9nZ5uB4XusnPgXFS65kLgzT6igOdw/ dy2Q== X-Gm-Message-State: APjAAAXoXhvOrGHZaD0y5wkcRfuHS8NTgRG+S4xPDMYUWDR8DeyUBYz4 veINxT7qP0UKsspkbzKFMwyO5yq5Opc= X-Google-Smtp-Source: APXvYqwhfciRGrOTo8ja89ByPITok85KXyCZfbxf6MwKdOXp/tBKOG3bsYVAccbdCSoFiapSS/hw5g== X-Received: by 2002:a63:fe17:: with SMTP id p23mr21746489pgh.103.1566250681535; Mon, 19 Aug 2019 14:38:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:50 -0700 Message-Id: <20190819213755.26175-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v2 03/68] target/arm: Convert Data Processing (register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 229 ++++++++++++++++++++++++++++++++++------- target/arm/a32.decode | 28 +++++ target/arm/t32.decode | 43 ++++++++ 3 files changed, 264 insertions(+), 36 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index c759fe0797..be8e7685e3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7669,6 +7669,197 @@ static void arm_skip_unless(DisasContext *s, uint32= _t cond) #include "decode-a32-uncond.inc.c" #include "decode-t32.inc.c" =20 +/* Helpers to swap operands for reverse-subtract. */ +static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_sub_i32(dst, b, a); +} + +static void gen_rsb_CC(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) +{ + gen_sub_CC(dst, b, a); +} + +static void gen_rsc(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b) +{ + gen_sub_carry(dest, b, a); +} + +static void gen_rsc_CC(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b) +{ + gen_sbc_CC(dest, b, a); +} + +/* + * Helpers for the data processing routines. + * + * After the computation store the results back. + * This may be suppressed altogether (STREG_NONE), require a runtime + * check against the stack limits (STREG_SP_CHECK), or generate an + * exception return. Oh, or store into a register. + * + * Always return true, indicating success for a trans_* function. + */ +typedef enum { + STREG_NONE, + STREG_NORMAL, + STREG_SP_CHECK, + STREG_EXC_RET, +} StoreRegKind; + +static bool store_reg_kind(DisasContext *s, int rd, + TCGv_i32 val, StoreRegKind kind) +{ + switch (kind) { + case STREG_NONE: + tcg_temp_free_i32(val); + return true; + case STREG_NORMAL: + /* See ALUWritePC: Interworking only from a32 mode. */ + if (s->thumb) { + store_reg(s, rd, val); + } else { + store_reg_bx(s, rd, val); + } + return true; + case STREG_SP_CHECK: + store_sp_checked(s, val); + return true; + case STREG_EXC_RET: + gen_exception_return(s, val); + return true; + } + g_assert_not_reached(); +} + +/* + * Data Processing (register) + * + * Operate, with set flags, one register source, + * one immediate shifted register source, and a destination. + */ +static bool op_s_rrr_shi(DisasContext *s, arg_s_rrr_shi *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp2 =3D load_reg(s, a->rm); + gen_arm_shift_im(tmp2, a->shty, a->shim, logic_cc); + tmp1 =3D load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxr_shi(DisasContext *s, arg_s_rrr_shi *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp; + + tmp =3D load_reg(s, a->rm); + gen_arm_shift_im(tmp, a->shty, a->shim, logic_cc); + + gen(tmp, tmp); + if (logic_cc) { + gen_logic_CC(tmp); + } + return store_reg_kind(s, a->rd, tmp, kind); +} + +#define DO_ANY3(NAME, OP, L, K) \ + static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ + { StoreRegKind k =3D (K); return op_s_rrr_shi(s, a, OP, L, k); } + +#define DO_ANY2(NAME, OP, L, K) \ + static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ + { StoreRegKind k =3D (K); return op_s_rxr_shi(s, a, OP, L, k); } + +#define DO_CMP2(NAME, OP, L) \ + static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ + { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } + +DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) +DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) +DO_ANY3(ORR, tcg_gen_or_i32, a->s, STREG_NORMAL) +DO_ANY3(BIC, tcg_gen_andc_i32, a->s, STREG_NORMAL) + +DO_ANY3(RSB, a->s ? gen_rsb_CC : gen_rsb, false, STREG_NORMAL) +DO_ANY3(ADC, a->s ? gen_adc_CC : gen_add_carry, false, STREG_NORMAL) +DO_ANY3(SBC, a->s ? gen_sbc_CC : gen_sub_carry, false, STREG_NORMAL) +DO_ANY3(RSC, a->s ? gen_rsc_CC : gen_rsc, false, STREG_NORMAL) + +DO_CMP2(TST, tcg_gen_and_i32, true) +DO_CMP2(TEQ, tcg_gen_xor_i32, true) +DO_CMP2(CMN, gen_add_CC, false) +DO_CMP2(CMP, gen_sub_CC, false) + +DO_ANY3(ADD, a->s ? gen_add_CC : tcg_gen_add_i32, false, + a->rd =3D=3D 13 && a->rn =3D=3D 13 ? STREG_SP_CHECK : STREG_NORMAL) + +DO_ANY3(SUB, a->s ? gen_sub_CC : tcg_gen_sub_i32, false, + ({ + StoreRegKind ret =3D STREG_NORMAL; + if (a->rd =3D=3D 15 && a->s) { + /* + * See ALUExceptionReturn: + * In User mode, UNPREDICTABLE; we choose UNDEF. + * In Hyp mode, UNDEFINED. + */ + if (IS_USER(s) || s->current_el =3D=3D 2) { + return false; + } + /* There is no writeback of nzcv to PSTATE. */ + a->s =3D 0; + ret =3D STREG_EXC_RET; + } else if (a->rd =3D=3D 13 && a->rn =3D=3D 13) { + ret =3D STREG_SP_CHECK; + } + ret; + })) + +DO_ANY2(MOV, tcg_gen_mov_i32, a->s, + ({ + StoreRegKind ret =3D STREG_NORMAL; + if (a->rd =3D=3D 15 && a->s) { + /* + * See ALUExceptionReturn: + * In User mode, UNPREDICTABLE; we choose UNDEF. + * In Hyp mode, UNDEFINED. + */ + if (IS_USER(s) || s->current_el =3D=3D 2) { + return false; + } + /* There is no writeback of nzcv to PSTATE. */ + a->s =3D 0; + ret =3D STREG_EXC_RET; + } else if (a->rd =3D=3D 13) { + ret =3D STREG_SP_CHECK; + } + ret; + })) + +DO_ANY2(MVN, tcg_gen_not_i32, a->s, STREG_NORMAL) + +/* + * ORN is only available with T32, so there is no register-shifted-register + * form of the insn. Using the DO_ANY3 macro would create an unused funct= ion. + */ +static bool trans_ORN_rrri(DisasContext *s, arg_s_rrr_shi *a) +{ + return op_s_rrr_shi(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); +} + +#undef DO_ANY3 +#undef DO_ANY2 +#undef DO_CMP2 + /* * Legacy decoder. */ @@ -9277,13 +9468,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uin= t32_t pc, uint32_t insn) return true; } =20 -/* Return true if this is a Thumb-2 logical op. */ -static int -thumb2_logic_op(int op) -{ - return (op < 8); -} - /* Generate code for a Thumb-2 data processing operation. If CONDS is non= zero then set condition code flags based on the result of the operation. If SHIFTER_OUT is nonzero then set the carry flag for logical operations @@ -9371,8 +9555,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32= _t insn) TCGv_i32 addr; TCGv_i64 tmp64; int op; - int shiftop; - int conds; int logic_cc; =20 /* @@ -9802,33 +9984,8 @@ static void disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) store_reg(s, rd, tmp); } else { /* Data processing register constant shift. */ - if (rn =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp =3D load_reg(s, rn); - } - tmp2 =3D load_reg(s, rm); - - shiftop =3D (insn >> 4) & 3; - shift =3D ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); - conds =3D (insn & (1 << 20)) !=3D 0; - logic_cc =3D (conds && thumb2_logic_op(op)); - gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); - if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2)) - goto illegal_op; - tcg_temp_free_i32(tmp2); - if (rd =3D=3D 13 && - ((op =3D=3D 2 && rn =3D=3D 15) || - (op =3D=3D 8 && rn =3D=3D 13) || - (op =3D=3D 13 && rn =3D=3D 13))) { - /* MOV SP, ... or ADD SP, SP, ... or SUB SP, SP, ... */ - store_sp_checked(s, tmp); - } else if (rd !=3D 15) { - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } break; case 13: /* Misc data processing. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index a3e6e8c1c2..b23e83f17c 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -21,3 +21,31 @@ # All of the insn that have a COND field in insn[31:28] are here. # All insns that have 0xf in insn[31:28] are in a32-uncond.decode. # + +&s_rrr_shi s rd rn rm shim shty + +# Data-processing (register) + +@s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \ + &s_rrr_shi +@s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \ + &s_rrr_shi rn=3D0 +@S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \ + &s_rrr_shi s=3D1 rd=3D0 + +AND_rrri .... 000 0000 . .... .... ..... .. 0 .... @s_rrr_shi +EOR_rrri .... 000 0001 . .... .... ..... .. 0 .... @s_rrr_shi +SUB_rrri .... 000 0010 . .... .... ..... .. 0 .... @s_rrr_shi +RSB_rrri .... 000 0011 . .... .... ..... .. 0 .... @s_rrr_shi +ADD_rrri .... 000 0100 . .... .... ..... .. 0 .... @s_rrr_shi +ADC_rrri .... 000 0101 . .... .... ..... .. 0 .... @s_rrr_shi +SBC_rrri .... 000 0110 . .... .... ..... .. 0 .... @s_rrr_shi +RSC_rrri .... 000 0111 . .... .... ..... .. 0 .... @s_rrr_shi +TST_xrri .... 000 1000 1 .... 0000 ..... .. 0 .... @S_xrr_shi +TEQ_xrri .... 000 1001 1 .... 0000 ..... .. 0 .... @S_xrr_shi +CMP_xrri .... 000 1010 1 .... 0000 ..... .. 0 .... @S_xrr_shi +CMN_xrri .... 000 1011 1 .... 0000 ..... .. 0 .... @S_xrr_shi +ORR_rrri .... 000 1100 . .... .... ..... .. 0 .... @s_rrr_shi +MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi +BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi +MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ac01fb6958..7068596b99 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -18,3 +18,46 @@ # # This file is processed by scripts/decodetree.py # + +&s_rrr_shi !extern s rd rn rm shim shty + +# Data-processing (register) + +%imm5_12_6 12:3 6:2 + +@s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \ + &s_rrr_shi shim=3D%imm5_12_6 +@s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \ + &s_rrr_shi shim=3D%imm5_12_6 rn=3D0 +@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \ + &s_rrr_shi shim=3D%imm5_12_6 s=3D1 rd=3D0 + +{ + TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi + AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi +} +BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi +{ + MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi + ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi +} +{ + MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi + ORN_rrri 1110101 0011 . .... 0 ... .... .... .... @s_rrr_shi +} +{ + TEQ_xrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi + EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi +} +# PKHBT, PKHTB at opc1 =3D 0110 +{ + CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi + ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi +} +ADC_rrri 1110101 1010 . .... 0 ... .... .... .... @s_rrr_shi +SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi +{ + CMP_xrri 1110101 1101 1 .... 0 ... 1111 .... .... @S_xrr_shi + SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi +} +RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi --=20 2.17.1 From nobody Fri May 3 06:53:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v2 04/68] target/arm: Convert Data Processing (reg-shifted-reg) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 74 ++++++++++++++++++++++++++++++------------ target/arm/a32.decode | 27 +++++++++++++++ target/arm/t32.decode | 6 ++++ 3 files changed, 87 insertions(+), 20 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index be8e7685e3..a32fe4b222 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7773,17 +7773,66 @@ static bool op_s_rxr_shi(DisasContext *s, arg_s_rrr= _shi *a, return store_reg_kind(s, a->rd, tmp, kind); } =20 +/* + * Data-processing (register-shifted register) + * + * Operate, with set flags, one register source, + * one register shifted register source, and a destination. + */ +static bool op_s_rrr_shr(DisasContext *s, arg_s_rrr_shr *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp1 =3D load_reg(s, a->rs); + tmp2 =3D load_reg(s, a->rm); + gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); + tmp1 =3D load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxr_shr(DisasContext *s, arg_s_rrr_shr *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp1 =3D load_reg(s, a->rs); + tmp2 =3D load_reg(s, a->rm); + gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); + + gen(tmp2, tmp2); + if (logic_cc) { + gen_logic_CC(tmp2); + } + return store_reg_kind(s, a->rd, tmp2, kind); +} + #define DO_ANY3(NAME, OP, L, K) \ static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ - { StoreRegKind k =3D (K); return op_s_rrr_shi(s, a, OP, L, k); } + { StoreRegKind k =3D (K); return op_s_rrr_shi(s, a, OP, L, k); } \ + static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \ + { StoreRegKind k =3D (K); return op_s_rrr_shr(s, a, OP, L, k); } =20 #define DO_ANY2(NAME, OP, L, K) \ static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ - { StoreRegKind k =3D (K); return op_s_rxr_shi(s, a, OP, L, k); } + { StoreRegKind k =3D (K); return op_s_rxr_shi(s, a, OP, L, k); } \ + static bool trans_##NAME##_rxrr(DisasContext *s, arg_s_rrr_shr *a) \ + { StoreRegKind k =3D (K); return op_s_rxr_shr(s, a, OP, L, k); } =20 #define DO_CMP2(NAME, OP, L) \ static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ - { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } + { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } \ + static bool trans_##NAME##_xrrr(DisasContext *s, arg_s_rrr_shr *a) \ + { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } =20 DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) @@ -9555,7 +9604,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32= _t insn) TCGv_i32 addr; TCGv_i64 tmp64; int op; - int logic_cc; =20 /* * ARMv6-M supports a limited subset of Thumb2 instructions. @@ -9993,22 +10041,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) if (op < 4 && (insn & 0xf000) !=3D 0xf000) goto illegal_op; switch (op) { - case 0: /* Register controlled shift. */ - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - if ((insn & 0x70) !=3D 0) - goto illegal_op; - /* - * 0b1111_1010_0xxx_xxxx_1111_xxxx_0000_xxxx: - * - MOV, MOVS (register-shifted register), flagsetting - */ - op =3D (insn >> 21) & 3; - logic_cc =3D (insn & (1 << 20)) !=3D 0; - gen_arm_shift_reg(tmp, op, tmp2, logic_cc); - if (logic_cc) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - break; + case 0: /* Register controlled shift, in decodetree */ + goto illegal_op; case 1: /* Sign/zero extend. */ op =3D (insn >> 20) & 7; switch (op) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index b23e83f17c..8e0fb06d05 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -23,6 +23,7 @@ # =20 &s_rrr_shi s rd rn rm shim shty +&s_rrr_shr s rn rd rm rs shty =20 # Data-processing (register) =20 @@ -49,3 +50,29 @@ ORR_rrri .... 000 1100 . .... .... ..... .. 0 ..= .. @s_rrr_shi MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi + +# Data-processing (register-shifted register) + +@s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \ + &s_rrr_shr +@s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \ + &s_rrr_shr rn=3D0 +@S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \ + &s_rrr_shr rd=3D0 s=3D1 + +AND_rrrr .... 000 0000 . .... .... .... 0 .. 1 .... @s_rrr_shr +EOR_rrrr .... 000 0001 . .... .... .... 0 .. 1 .... @s_rrr_shr +SUB_rrrr .... 000 0010 . .... .... .... 0 .. 1 .... @s_rrr_shr +RSB_rrrr .... 000 0011 . .... .... .... 0 .. 1 .... @s_rrr_shr +ADD_rrrr .... 000 0100 . .... .... .... 0 .. 1 .... @s_rrr_shr +ADC_rrrr .... 000 0101 . .... .... .... 0 .. 1 .... @s_rrr_shr +SBC_rrrr .... 000 0110 . .... .... .... 0 .. 1 .... @s_rrr_shr +RSC_rrrr .... 000 0111 . .... .... .... 0 .. 1 .... @s_rrr_shr +TST_xrrr .... 000 1000 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +TEQ_xrrr .... 000 1001 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +CMP_xrrr .... 000 1010 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +CMN_xrrr .... 000 1011 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .... @s_rrr_shr +MOV_rxrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr +BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr +MVN_rxrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 7068596b99..f0a73fa003 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -20,6 +20,7 @@ # =20 &s_rrr_shi !extern s rd rn rm shim shty +&s_rrr_shr !extern s rn rd rm rs shty =20 # Data-processing (register) =20 @@ -61,3 +62,8 @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... ....= @s_rrr_shi SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi } RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi + +# Data-processing (register-shifted register) + +MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ + &s_rrr_shr rn=3D0 --=20 2.17.1 From nobody Fri May 3 06:53:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CTcKHXTSkonFgTQBSIs2aPmAFQHyFZz0bv/+Iu71uEU=; b=JWHyi6o9Tu0e9m8VAeTEwXq0YyOxuTTzxek+RbG0YQXs00MTOEy1VVHepP/eOrLSeb ZqIIVifZVqTim8scB1SWqsVeURb01dNkCTdLNtAGdr6h79Usuxk06fmnVAZy8kgYnWmw 2fuNT+32grZv0whE4bS6W6BeYqWFG/D+YnNUAof9Q6lHYdJdPFV/JgUmIAljxPP9ZLoN 3oB7c+MhxQ28UafXldUZg6rBLGlueHzlFJzcCN5bVJ8/ggDlyInH27vXp35aSYIgHpJy ecA2RTolnOfCCMntGuSW9oz6v0k30T/gNg5BWd4mY6MZ2X6IdlaEvlOlSB96RjsKlBCY cSqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CTcKHXTSkonFgTQBSIs2aPmAFQHyFZz0bv/+Iu71uEU=; b=eeqmzR/6ZaFz0jPq+BMU+TNg+THL6yUmLDSW44Q5AfrYqNDwQ1KJBfjPM613MmN/HO QtauuHtffjUwrNCwdb1PPu7Bb2LKEu4h3Ji6sDz64GN2mUEHJUglLkp99rfYduXkND1N 09rrifkclCFuCwlCzs9z0uI1I/T/KYGRtmo7AoZdr4XMKgVJ8Ph7jsZcG0g75ImbytUu lHiNsnSk1NspCeR6ACXXklhFBGzx3+hoqxpC21MAlE2SsgCSJZ7+mnkAqgVYg0QikLLA RJDo9E/xUg927dhjhiiFfXk7WGY5sl5cSJYEzVLuDqzu6zjAEb1SEOmRVhz31ivy1MB6 xmRg== X-Gm-Message-State: APjAAAVKQbXnXv4C4et2xETmz/KYhyb477UkEdoIZcx364fISAEC+PVe KFNNtIy/E0bbxrSycbShfL4VpQ/s+NA= X-Google-Smtp-Source: APXvYqzD1U9d9qP4gWzbaUav49Xw6rHcX21ebLBrMA7KmcY2vqq6XI27T8oQYclzmSTg4yDPR2K5sw== X-Received: by 2002:a17:90a:3465:: with SMTP id o92mr22409284pjb.20.1566250683627; Mon, 19 Aug 2019 14:38:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:52 -0700 Message-Id: <20190819213755.26175-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::432 Subject: [Qemu-devel] [PATCH v2 05/68] target/arm: Convert Data Processing (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 449 +++++++++++------------------------------ target/arm/a32.decode | 29 +++ target/arm/t32.decode | 42 ++++ 3 files changed, 186 insertions(+), 334 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index a32fe4b222..b5af38bf84 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -439,12 +439,6 @@ static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) tcg_temp_free_i32(t1); } =20 -/* Set CF to the top bit of var. */ -static void gen_set_CF_bit31(TCGv_i32 var) -{ - tcg_gen_shri_i32(cpu_CF, var, 31); -} - /* Set N and Z flags from var. */ static inline void gen_logic_CC(TCGv_i32 var) { @@ -857,25 +851,6 @@ void arm_gen_test_cc(int cc, TCGLabel *label) arm_free_cc(&cmp); } =20 -static const uint8_t table_logic_cc[16] =3D { - 1, /* and */ - 1, /* xor */ - 0, /* sub */ - 0, /* rsb */ - 0, /* add */ - 0, /* adc */ - 0, /* sbc */ - 0, /* rsc */ - 1, /* andl */ - 1, /* xorl */ - 0, /* cmp */ - 0, /* cmn */ - 1, /* orr */ - 1, /* mov */ - 1, /* bic */ - 1, /* mvn */ -}; - static inline void gen_set_condexec(DisasContext *s) { if (s->condexec_mask) { @@ -7661,6 +7636,48 @@ static void arm_skip_unless(DisasContext *s, uint32_= t cond) arm_gen_test_cc(cond ^ 1, s->condlabel); } =20 + +/* + * Constant expanders for the decoders. + */ + +static int times_2(DisasContext *s, int x) +{ + return x * 2; +} + +/* Return only the rotation part of T32ExpandImm. */ +static int t32_expandimm_rot(DisasContext *s, int x) +{ + return x & 0xc00 ? extract32(x, 7, 5) : 0; +} + +/* Return the unrotated immediate from T32ExpandImm. */ +static int t32_expandimm_imm(DisasContext *s, int x) +{ + int imm =3D extract32(x, 0, 8); + + switch (extract32(x, 8, 4)) { + case 0: /* XY */ + /* Nothing to do. */ + break; + case 1: /* 00XY00XY */ + imm *=3D 0x00010001; + break; + case 2: /* XY00XY00 */ + imm *=3D 0x01000100; + break; + case 3: /* XYXYXYXY */ + imm *=3D 0x01010101; + break; + default: + /* Rotated constant. */ + imm |=3D 0x80; + break; + } + return imm; +} + /* * Include the generated decoders. */ @@ -7816,23 +7833,82 @@ static bool op_s_rxr_shr(DisasContext *s, arg_s_rrr= _shr *a, return store_reg_kind(s, a->rd, tmp2, kind); } =20 +/* + * Data-processing (immediate) + * + * Operate, with set flags, one register source, + * one rotated immediate, and a destination. + * + * Note that logic_cc && a->rot setting CF based on the msb of the + * immediate is the reason why we must pass in the unrotated form + * of the immediate. + */ +static bool op_s_rri_rot(DisasContext *s, arg_s_rri_rot *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + uint32_t imm; + + imm =3D ror32(a->imm, a->rot); + if (logic_cc && a->rot) { + tcg_gen_movi_i32(cpu_CF, imm >> 31); + } + tmp2 =3D tcg_const_i32(imm); + tmp1 =3D load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxi_rot(DisasContext *s, arg_s_rri_rot *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp; + uint32_t imm; + + imm =3D ror32(a->imm, a->rot); + if (logic_cc && a->rot) { + tcg_gen_movi_i32(cpu_CF, imm >> 31); + } + tmp =3D tcg_const_i32(imm); + + gen(tmp, tmp); + if (logic_cc) { + gen_logic_CC(tmp); + } + return store_reg_kind(s, a->rd, tmp, kind); +} + #define DO_ANY3(NAME, OP, L, K) \ static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ { StoreRegKind k =3D (K); return op_s_rrr_shi(s, a, OP, L, k); } \ static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \ - { StoreRegKind k =3D (K); return op_s_rrr_shr(s, a, OP, L, k); } + { StoreRegKind k =3D (K); return op_s_rrr_shr(s, a, OP, L, k); } \ + static bool trans_##NAME##_rri(DisasContext *s, arg_s_rri_rot *a) \ + { StoreRegKind k =3D (K); return op_s_rri_rot(s, a, OP, L, k); } =20 #define DO_ANY2(NAME, OP, L, K) \ static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ { StoreRegKind k =3D (K); return op_s_rxr_shi(s, a, OP, L, k); } \ static bool trans_##NAME##_rxrr(DisasContext *s, arg_s_rrr_shr *a) \ - { StoreRegKind k =3D (K); return op_s_rxr_shr(s, a, OP, L, k); } + { StoreRegKind k =3D (K); return op_s_rxr_shr(s, a, OP, L, k); } \ + static bool trans_##NAME##_rxi(DisasContext *s, arg_s_rri_rot *a) \ + { StoreRegKind k =3D (K); return op_s_rxi_rot(s, a, OP, L, k); } =20 #define DO_CMP2(NAME, OP, L) \ static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } \ static bool trans_##NAME##_xrrr(DisasContext *s, arg_s_rrr_shr *a) \ - { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } + { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } \ + static bool trans_##NAME##_xri(DisasContext *s, arg_s_rri_rot *a) \ + { return op_s_rri_rot(s, a, OP, L, STREG_NONE); } =20 DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) @@ -7905,6 +7981,11 @@ static bool trans_ORN_rrri(DisasContext *s, arg_s_rr= r_shi *a) return op_s_rrr_shi(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); } =20 +static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a) +{ + return op_s_rri_rot(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); +} + #undef DO_ANY3 #undef DO_ANY2 #undef DO_CMP2 @@ -8442,182 +8523,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) } else if (((insn & 0x0e000000) =3D=3D 0 && (insn & 0x00000090) !=3D 0x90) || ((insn & 0x0e000000) =3D=3D (1 << 25))) { - int set_cc, logic_cc, shiftop; - - op1 =3D (insn >> 21) & 0xf; - set_cc =3D (insn >> 20) & 1; - logic_cc =3D table_logic_cc[op1] & set_cc; - - /* data processing instruction */ - if (insn & (1 << 25)) { - /* immediate operand */ - val =3D insn & 0xff; - shift =3D ((insn >> 8) & 0xf) * 2; - val =3D ror32(val, shift); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, val); - if (logic_cc && shift) { - gen_set_CF_bit31(tmp2); - } - } else { - /* register */ - rm =3D (insn) & 0xf; - tmp2 =3D load_reg(s, rm); - shiftop =3D (insn >> 5) & 3; - if (!(insn & (1 << 4))) { - shift =3D (insn >> 7) & 0x1f; - gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); - } else { - rs =3D (insn >> 8) & 0xf; - tmp =3D load_reg(s, rs); - gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc); - } - } - if (op1 !=3D 0x0f && op1 !=3D 0x0d) { - rn =3D (insn >> 16) & 0xf; - tmp =3D load_reg(s, rn); - } else { - tmp =3D NULL; - } - rd =3D (insn >> 12) & 0xf; - switch(op1) { - case 0x00: - tcg_gen_and_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x01: - tcg_gen_xor_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x02: - if (set_cc && rd =3D=3D 15) { - /* SUBS r15, ... is used for exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - gen_sub_CC(tmp, tmp, tmp2); - gen_exception_return(s, tmp); - } else { - if (set_cc) { - gen_sub_CC(tmp, tmp, tmp2); - } else { - tcg_gen_sub_i32(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - } - break; - case 0x03: - if (set_cc) { - gen_sub_CC(tmp, tmp2, tmp); - } else { - tcg_gen_sub_i32(tmp, tmp2, tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x04: - if (set_cc) { - gen_add_CC(tmp, tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x05: - if (set_cc) { - gen_adc_CC(tmp, tmp, tmp2); - } else { - gen_add_carry(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x06: - if (set_cc) { - gen_sbc_CC(tmp, tmp, tmp2); - } else { - gen_sub_carry(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x07: - if (set_cc) { - gen_sbc_CC(tmp, tmp2, tmp); - } else { - gen_sub_carry(tmp, tmp2, tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x08: - if (set_cc) { - tcg_gen_and_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - } - tcg_temp_free_i32(tmp); - break; - case 0x09: - if (set_cc) { - tcg_gen_xor_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - } - tcg_temp_free_i32(tmp); - break; - case 0x0a: - if (set_cc) { - gen_sub_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp); - break; - case 0x0b: - if (set_cc) { - gen_add_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp); - break; - case 0x0c: - tcg_gen_or_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x0d: - if (logic_cc && rd =3D=3D 15) { - /* MOVS r15, ... is used for exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - gen_exception_return(s, tmp2); - } else { - if (logic_cc) { - gen_logic_CC(tmp2); - } - store_reg_bx(s, rd, tmp2); - } - break; - case 0x0e: - tcg_gen_andc_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - default: - case 0x0f: - tcg_gen_not_i32(tmp2, tmp2); - if (logic_cc) { - gen_logic_CC(tmp2); - } - store_reg_bx(s, rd, tmp2); - break; - } - if (op1 !=3D 0x0f && op1 !=3D 0x0d) { - tcg_temp_free_i32(tmp2); - } + /* Data-processing (reg, reg-shift-reg, imm). */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { /* other instructions */ op1 =3D (insn >> 24) & 0xf; @@ -9517,82 +9425,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uin= t32_t pc, uint32_t insn) return true; } =20 -/* Generate code for a Thumb-2 data processing operation. If CONDS is non= zero - then set condition code flags based on the result of the operation. - If SHIFTER_OUT is nonzero then set the carry flag for logical operations - to the high bit of T1. - Returns zero if the opcode is valid. */ - -static int -gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_ou= t, - TCGv_i32 t0, TCGv_i32 t1) -{ - int logic_cc; - - logic_cc =3D 0; - switch (op) { - case 0: /* and */ - tcg_gen_and_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 1: /* bic */ - tcg_gen_andc_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 2: /* orr */ - tcg_gen_or_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 3: /* orn */ - tcg_gen_orc_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 4: /* eor */ - tcg_gen_xor_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 8: /* add */ - if (conds) - gen_add_CC(t0, t0, t1); - else - tcg_gen_add_i32(t0, t0, t1); - break; - case 10: /* adc */ - if (conds) - gen_adc_CC(t0, t0, t1); - else - gen_adc(t0, t1); - break; - case 11: /* sbc */ - if (conds) { - gen_sbc_CC(t0, t0, t1); - } else { - gen_sub_carry(t0, t0, t1); - } - break; - case 13: /* sub */ - if (conds) - gen_sub_CC(t0, t0, t1); - else - tcg_gen_sub_i32(t0, t0, t1); - break; - case 14: /* rsb */ - if (conds) - gen_sub_CC(t0, t1, t0); - else - tcg_gen_sub_i32(t0, t1, t0); - break; - default: /* 5, 6, 7, 9, 12, 15. */ - return 1; - } - if (logic_cc) { - gen_logic_CC(t0); - if (shifter_out) - gen_set_CF_bit31(t1); - } - return 0; -} - /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { @@ -10867,60 +10699,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } } } else { - /* - * 0b1111_0x0x_xxxx_0xxx_xxxx_xxxx - * - Data-processing (modified immediate) - */ - int shifter_out =3D 0; - /* modified 12-bit immediate. */ - shift =3D ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >= > 12); - imm =3D (insn & 0xff); - switch (shift) { - case 0: /* XY */ - /* Nothing to do. */ - break; - case 1: /* 00XY00XY */ - imm |=3D imm << 16; - break; - case 2: /* XY00XY00 */ - imm |=3D imm << 16; - imm <<=3D 8; - break; - case 3: /* XYXYXYXY */ - imm |=3D imm << 16; - imm |=3D imm << 8; - break; - default: /* Rotated constant. */ - shift =3D (shift << 1) | (imm >> 7); - imm |=3D 0x80; - imm =3D imm << (32 - shift); - shifter_out =3D 1; - break; - } - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, imm); - rn =3D (insn >> 16) & 0xf; - if (rn =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp =3D load_reg(s, rn); - } - op =3D (insn >> 21) & 0xf; - if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) !=3D 0, - shifter_out, tmp, tmp2)) - goto illegal_op; - tcg_temp_free_i32(tmp2); - rd =3D (insn >> 8) & 0xf; - if (rd =3D=3D 13 && rn =3D=3D 13 - && (op =3D=3D 8 || op =3D=3D 13)) { - /* ADD(S) SP, SP, imm or SUB(S) SP, SP, imm */ - store_sp_checked(s, tmp); - } else if (rd !=3D 15) { - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } + /* Data-processing (modified immediate) */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } } break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 8e0fb06d05..286adcbf89 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -24,6 +24,7 @@ =20 &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty +&s_rri_rot s rn rd imm rot =20 # Data-processing (register) =20 @@ -76,3 +77,31 @@ ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .= ... @s_rrr_shr MOV_rxrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr MVN_rxrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr + +# Data-processing (immediate) + +%a32extrot 8:4 !function=3Dtimes_2 + +@s_rri_rot ---- ... .... s:1 rn:4 rd:4 .... imm:8 \ + &s_rri_rot rot=3D%a32extrot +@s_rxi_rot ---- ... .... s:1 .... rd:4 .... imm:8 \ + &s_rri_rot rot=3D%a32extrot rn=3D0 +@S_xri_rot ---- ... .... . rn:4 .... .... imm:8 \ + &s_rri_rot rot=3D%a32extrot rd=3D0 s=3D1 + +AND_rri .... 001 0000 . .... .... ............ @s_rri_rot +EOR_rri .... 001 0001 . .... .... ............ @s_rri_rot +SUB_rri .... 001 0010 . .... .... ............ @s_rri_rot +RSB_rri .... 001 0011 . .... .... ............ @s_rri_rot +ADD_rri .... 001 0100 . .... .... ............ @s_rri_rot +ADC_rri .... 001 0101 . .... .... ............ @s_rri_rot +SBC_rri .... 001 0110 . .... .... ............ @s_rri_rot +RSC_rri .... 001 0111 . .... .... ............ @s_rri_rot +TST_xri .... 001 1000 1 .... 0000 ............ @S_xri_rot +TEQ_xri .... 001 1001 1 .... 0000 ............ @S_xri_rot +CMP_xri .... 001 1010 1 .... 0000 ............ @S_xri_rot +CMN_xri .... 001 1011 1 .... 0000 ............ @S_xri_rot +ORR_rri .... 001 1100 . .... .... ............ @s_rri_rot +MOV_rxi .... 001 1101 . 0000 .... ............ @s_rxi_rot +BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot +MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f0a73fa003..50cbe48cc8 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -21,6 +21,7 @@ =20 &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty +&s_rri_rot !extern s rn rd imm rot =20 # Data-processing (register) =20 @@ -67,3 +68,44 @@ RSB_rrri 1110101 1110 . .... 0 ... .... .... ...= . @s_rrr_shi =20 MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ &s_rrr_shr rn=3D0 + +# Data-processing (immediate) + +%t32extrot 26:1 12:3 0:8 !function=3Dt32_expandimm_rot +%t32extimm 26:1 12:3 0:8 !function=3Dt32_expandimm_imm + +@s_rri_rot ....... .... s:1 rn:4 . ... rd:4 ........ \ + &s_rri_rot imm=3D%t32extimm rot=3D%t32extrot +@s_rxi_rot ....... .... s:1 .... . ... rd:4 ........ \ + &s_rri_rot imm=3D%t32extimm rot=3D%t32extrot rn=3D0 +@S_xri_rot ....... .... . rn:4 . ... .... ........ \ + &s_rri_rot imm=3D%t32extimm rot=3D%t32extrot s=3D1 rd=3D0 + +{ + TST_xri 1111 0.0 0000 1 .... 0 ... 1111 ........ @S_xri_rot + AND_rri 1111 0.0 0000 . .... 0 ... .... ........ @s_rri_rot +} +BIC_rri 1111 0.0 0001 . .... 0 ... .... ........ @s_rri_rot +{ + MOV_rxi 1111 0.0 0010 . 1111 0 ... .... ........ @s_rxi_rot + ORR_rri 1111 0.0 0010 . .... 0 ... .... ........ @s_rri_rot +} +{ + MVN_rxi 1111 0.0 0011 . 1111 0 ... .... ........ @s_rxi_rot + ORN_rri 1111 0.0 0011 . .... 0 ... .... ........ @s_rri_rot +} +{ + TEQ_xri 1111 0.0 0100 1 .... 0 ... 1111 ........ @S_xri_rot + EOR_rri 1111 0.0 0100 . .... 0 ... .... ........ @s_rri_rot +} +{ + CMN_xri 1111 0.0 1000 1 .... 0 ... 1111 ........ @S_xri_rot + ADD_rri 1111 0.0 1000 . .... 0 ... .... ........ @s_rri_rot +} +ADC_rri 1111 0.0 1010 . .... 0 ... .... ........ @s_rri_rot +SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot +{ + CMP_xri 1111 0.0 1101 1 .... 0 ... 1111 ........ @S_xri_rot + SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot +} +RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot --=20 2.17.1 From nobody Fri May 3 06:53:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 06/68] target/arm: Convert multiply and multiply accumulate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 248 +++++++++++++++++++++++------------------ target/arm/a32.decode | 17 +++ target/arm/t32.decode | 19 ++++ 3 files changed, 177 insertions(+), 107 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b5af38bf84..94659086c0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7990,6 +7990,125 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rr= i_rot *a) #undef DO_ANY2 #undef DO_CMP2 =20 +/* + * Multiply and multiply accumulate + */ + +static bool op_mla(DisasContext *s, arg_s_rrrr *a, bool add) +{ + TCGv_i32 t1, t2; + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + tcg_gen_mul_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + if (add) { + t2 =3D load_reg(s, a->ra); + tcg_gen_add_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + } + if (a->s) { + gen_logic_CC(t1); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_MUL(DisasContext *s, arg_MUL *a) +{ + return op_mla(s, a, false); +} + +static bool trans_MLA(DisasContext *s, arg_MLA *a) +{ + return op_mla(s, a, true); +} + +static bool trans_MLS(DisasContext *s, arg_MLS *a) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6T2) { + return false; + } + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + tcg_gen_mul_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + t2 =3D load_reg(s, a->ra); + tcg_gen_sub_i32(t1, t2, t1); + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool op_mlal(DisasContext *s, arg_s_rrrr *a, bool uns, bool add) +{ + TCGv_i32 t0, t1, t2, t3; + + t0 =3D load_reg(s, a->rm); + t1 =3D load_reg(s, a->rn); + if (uns) { + tcg_gen_mulu2_i32(t0, t1, t0, t1); + } else { + tcg_gen_muls2_i32(t0, t1, t0, t1); + } + if (add) { + t2 =3D load_reg(s, a->ra); + t3 =3D load_reg(s, a->rd); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + } + if (a->s) { + gen_logicq_cc(t0, t1); + } + store_reg(s, a->ra, t0); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_UMULL(DisasContext *s, arg_UMULL *a) +{ + return op_mlal(s, a, true, false); +} + +static bool trans_SMULL(DisasContext *s, arg_SMULL *a) +{ + return op_mlal(s, a, false, false); +} + +static bool trans_UMLAL(DisasContext *s, arg_UMLAL *a) +{ + return op_mlal(s, a, true, true); +} + +static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a) +{ + return op_mlal(s, a, false, true); +} + +static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 =3D load_reg(s, a->rm); + t1 =3D load_reg(s, a->rn); + t64 =3D gen_mulu_i64_i32(t0, t1); + gen_addq_lo(s, t64, a->ra); + gen_addq_lo(s, t64, a->rd); + gen_storeq_reg(s, a->ra, a->rd, t64); + tcg_temp_free_i64(t64); + return true; +} + /* * Legacy decoder. */ @@ -8536,71 +8655,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) sh =3D (insn >> 5) & 3; if (sh =3D=3D 0) { if (op1 =3D=3D 0x0) { - rd =3D (insn >> 16) & 0xf; - rn =3D (insn >> 12) & 0xf; - rs =3D (insn >> 8) & 0xf; - rm =3D (insn) & 0xf; - op1 =3D (insn >> 20) & 0xf; - switch (op1) { - case 0: case 1: case 2: case 3: case 6: - /* 32 bit mul */ - tmp =3D load_reg(s, rs); - tmp2 =3D load_reg(s, rm); - tcg_gen_mul_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (insn & (1 << 22)) { - /* Subtract (mls) */ - ARCH(6T2); - tmp2 =3D load_reg(s, rn); - tcg_gen_sub_i32(tmp, tmp2, tmp); - tcg_temp_free_i32(tmp2); - } else if (insn & (1 << 21)) { - /* Add */ - tmp2 =3D load_reg(s, rn); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - if (insn & (1 << 20)) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - break; - case 4: - /* 64 bit mul double accumulate (UMAAL) */ - ARCH(6); - tmp =3D load_reg(s, rs); - tmp2 =3D load_reg(s, rm); - tmp64 =3D gen_mulu_i64_i32(tmp, tmp2); - gen_addq_lo(s, tmp64, rn); - gen_addq_lo(s, tmp64, rd); - gen_storeq_reg(s, rn, rd, tmp64); - tcg_temp_free_i64(tmp64); - break; - case 8: case 9: case 10: case 11: - case 12: case 13: case 14: case 15: - /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */ - tmp =3D load_reg(s, rs); - tmp2 =3D load_reg(s, rm); - if (insn & (1 << 22)) { - tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2); - } else { - tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2); - } - if (insn & (1 << 21)) { /* mult accumulate */ - TCGv_i32 al =3D load_reg(s, rn); - TCGv_i32 ah =3D load_reg(s, rd); - tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, al, ah); - tcg_temp_free_i32(al); - tcg_temp_free_i32(ah); - } - if (insn & (1 << 20)) { - gen_logicq_cc(tmp, tmp2); - } - store_reg(s, rn, tmp); - store_reg(s, rd, tmp2); - break; - default: - goto illegal_op; - } + /* Multiply and multiply accumulate. */ + /* All done in decodetree. Reach here for illegal ops= . */ + goto illegal_op; } else { rn =3D (insn >> 16) & 0xf; rd =3D (insn >> 12) & 0xf; @@ -10040,7 +10097,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. = */ switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ + case 0: /* 32 x 32 -> 32, in decodetree */ + goto illegal_op; case 7: /* Unsigned sum of absolute differences. */ break; case 1: /* 16 x 16 -> 32 */ @@ -10057,18 +10115,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tmp =3D load_reg(s, rn); tmp2 =3D load_reg(s, rm); switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ - tcg_gen_mul_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rs !=3D 15) { - tmp2 =3D load_reg(s, rs); - if (op) - tcg_gen_sub_i32(tmp, tmp2, tmp); - else - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 1: /* 16 x 16 -> 32 */ gen_mulxy(tmp, tmp2, op & 2, op & 1); tcg_temp_free_i32(tmp2); @@ -10191,36 +10237,24 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) gen_storeq_reg(s, rs, rd, tmp64); tcg_temp_free_i64(tmp64); } else { - if (op & 0x20) { - /* Unsigned 64-bit multiply */ - tmp64 =3D gen_mulu_i64_i32(tmp, tmp2); - } else { - if (op & 8) { - /* smlalxy */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - gen_mulxy(tmp, tmp2, op & 2, op & 1); - tcg_temp_free_i32(tmp2); - tmp64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - } else { - /* Signed 64-bit multiply */ - tmp64 =3D gen_muls_i64_i32(tmp, tmp2); - } + if ((op & 0x20) || !(op & 8)) { + /* Signed/unsigned 64-bit multiply, in decodetree */ + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + goto illegal_op; } - if (op & 4) { - /* umaal */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i64(tmp64); - goto illegal_op; - } - gen_addq_lo(s, tmp64, rs); - gen_addq_lo(s, tmp64, rd); - } else if (op & 0x40) { + /* smlalxy */ + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + goto illegal_op; + } + gen_mulxy(tmp, tmp2, op & 2, op & 1); + tcg_temp_free_i32(tmp2); + tmp64 =3D tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(tmp64, tmp); + tcg_temp_free_i32(tmp); + if (op & 0x40) { /* 64-bit accumulate. */ gen_addq(s, tmp64, rs, rd); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 286adcbf89..87bbb2eec2 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -25,6 +25,8 @@ &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty &s_rri_rot s rn rd imm rot +&s_rrrr s rd rn rm ra +&rrrr rd rn rm ra =20 # Data-processing (register) =20 @@ -105,3 +107,18 @@ ORR_rri .... 001 1100 . .... .... ...........= . @s_rri_rot MOV_rxi .... 001 1101 . 0000 .... ............ @s_rxi_rot BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot + +# Multiply and multiply accumulate + +@s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr +@s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra= =3D0 +@rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr + +MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn +MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn +UMAAL .... 0000 010 0 .... .... .... 1001 .... @rdamn +MLS .... 0000 011 0 .... .... .... 1001 .... @rdamn +UMULL .... 0000 100 . .... .... .... 1001 .... @s_rdamn +UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn +SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn +SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 50cbe48cc8..40cc69aee3 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -22,6 +22,8 @@ &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot +&s_rrrr !extern s rd rn rm ra +&rrrr !extern rd rn rm ra =20 # Data-processing (register) =20 @@ -109,3 +111,20 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... .....= ... @s_rri_rot SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot } RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot + +# Multiply and multiply accumulate + +@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 +@s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra= =3D0 s=3D0 +@rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr + +{ + MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm + MLA 1111 1011 0000 .... .... .... 0000 .... @s0_rnadm +} +MLS 1111 1011 0000 .... .... .... 0001 .... @rnadm +SMULL 1111 1011 1000 .... .... .... 0000 .... @s0_rnadm +UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm +SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm +UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm +UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm --=20 2.17.1 From nobody Fri May 3 06:53:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YCIk/F5LxR+bAmsRyhfJi8qC+d9H6yIirq1I2qlCLZk=; b=HPosPl9eiczke+k7xDh+6kjHrl5v1F6hnfQ0nrkfjkzhdEOpEUZ4mHsd9wrxvDee47 JrWRXIBNIhc9pJbttavZwxlvcXlP82JAfVCo7cZKEDYY6ld9rOwlJPOd+ASyYq/RZymh Ur+a64Kx1QVeAr3Ixl6IgfHxaqZ5/9U8IIEaNXHVf7Yr2AxHKMwU7URrbBtjHFLxEC5e QSmJ4PX7jeXRBxLXNX3mkyunxZDUMj2tYi824Qq+4OVvMa2ZVeV3DUMMyJUrcc8zaD3+ TcPknfGtpJpxweiUofjme1LeXcBIW1izr8wBCY/yURt6RaoEgk04PZfauJvVkWhtvGi0 nmsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YCIk/F5LxR+bAmsRyhfJi8qC+d9H6yIirq1I2qlCLZk=; b=DBuSBYCu2mjPpchXJQ7u1q++p9MCG278GZxqYMsudV7orQkI6U8mYM5bp62geitYO6 sNINBIKz4I+dDzeaRDhdYbmG2TxsfKikII8ivdgoH2gUTkJWzva8zF70N7fajtsBgq4d 17ZA+p8UFnqAIkQJKh2HAq8oBLb52dO8Q+QmSJ2OzdsFnX6B3p4l/9ThfCEh3/Eu/kLs J8AhWpbpHAJJU4/8geTNji470kB5psIRm+yggHDEsZzhGpwRPDiHpECwlVcuIk0Lbet4 9N4ZjFgmm5NyJ4gRt5gf/pFOU0NBGQG+YLFYTfLdLNoxg7FGr5+ZOqbfWXHfsPcDrunG kR7g== X-Gm-Message-State: APjAAAXdbK1Elf62bUaGtqqSfvQa1rWvdB48l3NyfHbhbeJRPV8Su0sV s6h7Wm7TVQJVL2K5PjNsW1SvTXAoYr0= X-Google-Smtp-Source: APXvYqw+AoDELrnbEdHvdOQnNpH61iX5df2z28Z5p9bhv68Po7LpmE3LDE9BofgYTs6TKjfdELTZXg== X-Received: by 2002:a17:902:6b07:: with SMTP id o7mr24106899plk.180.1566250685895; Mon, 19 Aug 2019 14:38:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:54 -0700 Message-Id: <20190819213755.26175-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 07/68] target/arm: Simplify UMAAL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_mulu2_i32 and tcg_gen_add2_i32. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 34 ++++++++++++---------------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 94659086c0..82bd207799 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7324,21 +7324,6 @@ static void gen_storeq_reg(DisasContext *s, int rlow= , int rhigh, TCGv_i64 val) store_reg(s, rhigh, tmp); } =20 -/* load a 32-bit value from a register and perform a 64-bit accumulate. */ -static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow) -{ - TCGv_i64 tmp; - TCGv_i32 tmp2; - - /* Load value and extend to 64 bits. */ - tmp =3D tcg_temp_new_i64(); - tmp2 =3D load_reg(s, rlow); - tcg_gen_extu_i32_i64(tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_gen_add_i64(val, val, tmp); - tcg_temp_free_i64(tmp); -} - /* load and add a 64-bit value from a register pair. */ static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) { @@ -8090,8 +8075,7 @@ static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a) =20 static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) { - TCGv_i32 t0, t1; - TCGv_i64 t64; + TCGv_i32 t0, t1, t2, zero; =20 if (s->thumb ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) @@ -8101,11 +8085,17 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL = *a) =20 t0 =3D load_reg(s, a->rm); t1 =3D load_reg(s, a->rn); - t64 =3D gen_mulu_i64_i32(t0, t1); - gen_addq_lo(s, t64, a->ra); - gen_addq_lo(s, t64, a->rd); - gen_storeq_reg(s, a->ra, a->rd, t64); - tcg_temp_free_i64(t64); + tcg_gen_mulu2_i32(t0, t1, t0, t1); + zero =3D tcg_const_i32(0); + t2 =3D load_reg(s, a->ra); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); + tcg_temp_free_i32(t2); + t2 =3D load_reg(s, a->rd); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(zero); + store_reg(s, a->ra, t0); + store_reg(s, a->rd, t1); return true; } =20 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566251302; cv=none; d=zoho.com; s=zohoarc; b=A3VesGFI8xdT2FJ3br9C0ZFxY+zutUDBFO2xgXiqPw0v25Yfuw1QGh0ZoLW7xkhQ8aRFnPk0zjd4g/gLWTA9U2SZOwrGJoYvH24AGNvehECDN46c1o3X3+0JCInBGU2pdSROIsA+jt9GfMTjYeRrO/CkFo6+Ybcp2zXTNuNj6A8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566251302; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=4Nawwn1CWQIrW/uHwTKLseXI15oBdHOjRF/v0JlzLb8=; b=WnIxrxlrhX+h+oq29QhSKQIgD/Z6+/PdWg+kC0fRmfquD1uzSNpbAdRIL/500yURZLfLzwPQA+MmvGeEWU7tipCuhRcZGFqktMBr5BLE2Py793JzTwfheM22IGPfifcNZBHC9olo6Cu4FXcm+48NRqpMqtT+eSIJIGTPJDQ/mMU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566251302154798.9959066132889; Mon, 19 Aug 2019 14:48:22 -0700 (PDT) Received: from localhost ([::1]:59060 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpVk-0004kp-Kt for importer@patchew.org; Mon, 19 Aug 2019 17:48:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58606) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpLu-0001MQ-3P for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpLs-00062d-FM for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:09 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:33448) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpLs-00061x-98 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:08 -0400 Received: by mail-pl1-x644.google.com with SMTP id go14so1586048plb.0 for ; Mon, 19 Aug 2019 14:38:08 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4Nawwn1CWQIrW/uHwTKLseXI15oBdHOjRF/v0JlzLb8=; b=oRigrk3owLUYDN0e9JS3SZYVzI3H3b3EZczrFC0wYeRZlcxirqZQhM1nkoGvs4wsQI pD2eH2Ej6Ek7FhRj2I58TTszcKI75RUSnXJw+yIIVbo873ZVhhDG62Oqdsu2gqU/JfBy RKgNjAIFLx10TT4y8nhVaYLL45ej/0j4qE8G0AFNVC35Ldpg1E4pDG1dFTHd/DpUYQ38 0SeiG1bweq+r/H1Vm7DV0ECY9nHDXeZMY4VupVvTOVC8NagFgo9RpgxwtGq4qR8r4ft2 jFoNcz7Y0msWYq2gpwGE6CZ0rUq8ERJhCAcTfEIuoI29BmH3N+EiVo1glVSUdH/0isXO SA2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4Nawwn1CWQIrW/uHwTKLseXI15oBdHOjRF/v0JlzLb8=; b=i9DXRIaetINmvBZWDSOQzwFLazKv2G1tqBesnMw1enXHIU0svuLJrehbjSFUpi4fAR pkydtEcJb4rLMMkZJDmfRJjVdXTTTYawr9vDxT7LlRyG/0bXxbMfFfF9YqDnKgAfLPvi +L7SkaH4H+y0KTXPdP3Oi40t3qDdiUA1XU359Vn8cmaSKVCUiyz44o4uJ3XZ8RGHOdE2 4xYMoebJJbrOw4+b660k9lJCLRpwPuRls32gzqsI5bP2aeNVA8ctydSCp6/XKGc9IIlb 2r4SoRw4ZGQQQtcLLfxwhY7BQAjzDgW2GACIpnNRRJOgn4r32hP16gmT/ZHgHMtgYlxn iY7g== X-Gm-Message-State: APjAAAXeRq1ndy9BZlsI2VFayrlQktTkDK38u8WVw9rLkTMpCX43QkAx 183HnA5ZtSEwchS+YcMZzq/Mitgxvik= X-Google-Smtp-Source: APXvYqxEjmCDx25t25J4uRLEFka37UjRZuEhFOgkzehQfQcX63NMoJrNb6XtvygkDMkDcgQuIBu6UA== X-Received: by 2002:a17:902:2d03:: with SMTP id o3mr18043863plb.96.1566250687019; Mon, 19 Aug 2019 14:38:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:55 -0700 Message-Id: <20190819213755.26175-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 08/68] target/arm: Convert Saturating addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.c | 75 +++++++++++++++++++++++++++--------------- target/arm/a32.decode | 10 ++++++ target/arm/t32.decode | 9 +++++ 3 files changed, 67 insertions(+), 27 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 82bd207799..b731e08fe4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8099,6 +8099,48 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *= a) return true; } =20 +/* + * Saturating addition and subtraction + */ + +static bool op_qaddsub(DisasContext *s, arg_rrr *a, bool add, bool doub) +{ + TCGv_i32 t0, t1; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_5TE) { + return false; + } + + t0 =3D load_reg(s, a->rm); + t1 =3D load_reg(s, a->rn); + if (doub) { + gen_helper_add_saturate(t1, cpu_env, t1, t1); + } + if (add) { + gen_helper_add_saturate(t0, cpu_env, t0, t1); + } else { + gen_helper_sub_saturate(t0, cpu_env, t0, t1); + } + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +#define DO_QADDSUB(NAME, ADD, DOUB) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_qaddsub(s, a, ADD, DOUB); \ +} + +DO_QADDSUB(QADD, true, false) +DO_QADDSUB(QSUB, false, false) +DO_QADDSUB(QDADD, true, true) +DO_QADDSUB(QDSUB, false, true) + +#undef DO_QADDSUB + /* * Legacy decoder. */ @@ -8508,21 +8550,10 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) store_reg(s, rd, tmp); break; } - case 0x5: /* saturating add/subtract */ - ARCH(5TE); - rd =3D (insn >> 12) & 0xf; - rn =3D (insn >> 16) & 0xf; - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rn); - if (op1 & 2) - gen_helper_add_saturate(tmp2, cpu_env, tmp2, tmp2); - if (op1 & 1) - gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2); - else - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + case 0x5: + /* Saturating addition and subtraction. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0x6: /* ERET */ if (op1 !=3D 3) { goto illegal_op; @@ -9989,18 +10020,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) op =3D ((insn >> 17) & 0x38) | ((insn >> 4) & 7); if (op < 4) { /* Saturating add/subtract. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - if (op & 1) - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp); - if (op & 2) - gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp); - else - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { switch (op) { case 0x0a: /* rbit */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 87bbb2eec2..7791be5590 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -27,6 +27,7 @@ &s_rri_rot s rn rd imm rot &s_rrrr s rd rn rm ra &rrrr rd rn rm ra +&rrr rd rn rm =20 # Data-processing (register) =20 @@ -122,3 +123,12 @@ UMULL .... 0000 100 . .... .... .... 1001 .= ... @s_rdamn UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn + +# Saturating addition and subtraction + +@rndm ---- .... .... rn:4 rd:4 .... .... rm:4 &rrr + +QADD .... 0001 0000 .... .... 0000 0101 .... @rndm +QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm +QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm +QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 40cc69aee3..7c6226e0af 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra +&rrr !extern rd rn rm =20 # Data-processing (register) =20 @@ -117,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ......= .. @s_rri_rot @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 @s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra= =3D0 s=3D0 @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr +@rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr =20 { MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm @@ -128,3 +130,10 @@ UMULL 1111 1011 1010 .... .... .... 0000 ..= .. @s0_rnadm SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm + +# Data-processing (two source registers) + +QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm +QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm +QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm +QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566251223; cv=none; d=zoho.com; s=zohoarc; b=EKuSnhDXNlWu5IH/Y1XKBapgWa26N/ONMk/qyN7AlMjHENY/cVNe81wyMSEBVEHvWMCZbkx8fYKkU+apRZkvBO9/cRuY6qYIQeGefyyQ6vodcMVtKW1mqmTURCXjhH3JnjCrxtoTQuAyAELCLJhYI3ufDYUNhoEpbZCjT1b/iU4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566251223; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=FEq/15vwK0NtvonTorhtMB0UzZJdmnn/K7430AdfD8A=; b=LBP49RhizBcG3KyupPTiHiSgfAuU/O1hbIB2DFFxeHd3c6tAnNaUKJ7lJnpVA0RXK4qHrHemjNQao1o+nSrtKjf0nJHmPA1J+Ko9IRzBhtGnz5ouDElbjHDS1wAT2vh48HMt7K9Xv1mU/PWbY/LAtbAARSPPmLkwgJb7O46b9zw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15662512233078.50717537997184; Mon, 19 Aug 2019 14:47:03 -0700 (PDT) Received: from localhost ([::1]:59044 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpUR-0003Il-MQ for importer@patchew.org; Mon, 19 Aug 2019 17:47:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58653) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpLw-0001Pi-0b for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpLu-00063j-0q for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:11 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:34694) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpLt-00063C-Pj for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:09 -0400 Received: by mail-pg1-x541.google.com with SMTP id n9so1937691pgc.1 for ; Mon, 19 Aug 2019 14:38:09 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 09/68] target/arm: Convert Halfword multiply and multiply accumulate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 218 +++++++++++++++++++++++------------------ target/arm/a32.decode | 20 ++++ target/arm/t32.decode | 29 ++++++ 3 files changed, 170 insertions(+), 97 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b731e08fe4..56ae83a7d0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8141,6 +8141,117 @@ DO_QADDSUB(QDSUB, false, true) =20 #undef DO_QADDSUB =20 +/* + * Halfword multiply and multiply accumulate + */ + +static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, + int add_long, bool nt, bool mt) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_5TE) { + return false; + } + + t0 =3D load_reg(s, a->rn); + t1 =3D load_reg(s, a->rm); + gen_mulxy(t0, t1, nt, mt); + tcg_temp_free_i32(t1); + + switch (add_long) { + case 0: + store_reg(s, a->rd, t0); + break; + case 1: + t1 =3D load_reg(s, a->ra); + gen_helper_add_setq(t0, cpu_env, t0, t1); + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + break; + case 2: + t64 =3D tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(t64, t0); + tcg_temp_free_i32(t0); + gen_addq(s, t64, a->ra, a->rd); + gen_storeq_reg(s, a->ra, a->rd, t64); + tcg_temp_free_i64(t64); + break; + default: + g_assert_not_reached(); + } + return true; +} + +#define DO_SMLAX(NAME, add, nt, mt) \ +static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \ +{ \ + return op_smlaxxx(s, a, add, nt, mt); \ +} + +DO_SMLAX(SMULBB, 0, 0, 0) +DO_SMLAX(SMULBT, 0, 0, 1) +DO_SMLAX(SMULTB, 0, 1, 0) +DO_SMLAX(SMULTT, 0, 1, 1) + +DO_SMLAX(SMLABB, 1, 0, 0) +DO_SMLAX(SMLABT, 1, 0, 1) +DO_SMLAX(SMLATB, 1, 1, 0) +DO_SMLAX(SMLATT, 1, 1, 1) + +DO_SMLAX(SMLALBB, 2, 0, 0) +DO_SMLAX(SMLALBT, 2, 0, 1) +DO_SMLAX(SMLALTB, 2, 1, 0) +DO_SMLAX(SMLALTT, 2, 1, 1) + +#undef DO_SMLAX + +static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (!ENABLE_ARCH_5TE) { + return false; + } + + t0 =3D load_reg(s, a->rn); + t1 =3D load_reg(s, a->rm); + if (mt) { + tcg_gen_sari_i32(t1, t1, 16); + } else { + gen_sxth(t1); + } + t64 =3D gen_muls_i64_i32(t0, t1); + tcg_gen_shri_i64(t64, t64, 16); + t1 =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t1, t64); + tcg_temp_free_i64(t64); + if (add) { + t0 =3D load_reg(s, a->ra); + gen_helper_add_setq(t1, cpu_env, t1, t0); + tcg_temp_free_i32(t0); + } + store_reg(s, a->rd, t1); + return true; +} + +#define DO_SMLAWX(NAME, add, mt) \ +static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \ +{ \ + return op_smlawx(s, a, add, mt); \ +} + +DO_SMLAWX(SMULWB, 0, 0) +DO_SMLAWX(SMULWT, 0, 1) +DO_SMLAWX(SMLAWB, 1, 0) +DO_SMLAWX(SMLAWT, 1, 1) + +#undef DO_SMLAWX + /* * Legacy decoder. */ @@ -8607,56 +8718,13 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) } break; } - case 0x8: /* signed multiply */ + case 0x8: case 0xa: case 0xc: case 0xe: - ARCH(5TE); - rs =3D (insn >> 8) & 0xf; - rn =3D (insn >> 12) & 0xf; - rd =3D (insn >> 16) & 0xf; - if (op1 =3D=3D 1) { - /* (32 * 16) >> 16 */ - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - if (sh & 4) - tcg_gen_sari_i32(tmp2, tmp2, 16); - else - gen_sxth(tmp2); - tmp64 =3D gen_muls_i64_i32(tmp, tmp2); - tcg_gen_shri_i64(tmp64, tmp64, 16); - tmp =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); - if ((sh & 2) =3D=3D 0) { - tmp2 =3D load_reg(s, rn); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - } else { - /* 16 * 16 */ - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - gen_mulxy(tmp, tmp2, sh & 2, sh & 4); - tcg_temp_free_i32(tmp2); - if (op1 =3D=3D 2) { - tmp64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - gen_addq(s, tmp64, rn, rd); - gen_storeq_reg(s, rn, rd, tmp64); - tcg_temp_free_i64(tmp64); - } else { - if (op1 =3D=3D 0) { - tmp2 =3D load_reg(s, rn); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - } - } - break; + /* Halfword multiply and multiply accumulate. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; default: goto illegal_op; } @@ -10108,13 +10176,14 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. = */ switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32, in decodetree */ + case 0: /* 32 x 32 -> 32 */ + case 1: /* 16 x 16 -> 32 */ + case 3: /* 32 * 16 -> 32msb */ + /* in decodetree */ goto illegal_op; case 7: /* Unsigned sum of absolute differences. */ break; - case 1: /* 16 x 16 -> 32 */ case 2: /* Dual multiply add. */ - case 3: /* 32 * 16 -> 32msb */ case 4: /* Dual multiply subtract. */ case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { @@ -10126,15 +10195,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tmp =3D load_reg(s, rn); tmp2 =3D load_reg(s, rm); switch ((insn >> 20) & 7) { - case 1: /* 16 x 16 -> 32 */ - gen_mulxy(tmp, tmp2, op & 2, op & 1); - tcg_temp_free_i32(tmp2); - if (rs !=3D 15) { - tmp2 =3D load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 2: /* Dual multiply add. */ case 4: /* Dual multiply subtract. */ if (op) @@ -10158,23 +10218,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tcg_temp_free_i32(tmp2); } break; - case 3: /* 32 * 16 -> 32msb */ - if (op) - tcg_gen_sari_i32(tmp2, tmp2, 16); - else - gen_sxth(tmp2); - tmp64 =3D gen_muls_i64_i32(tmp, tmp2); - tcg_gen_shri_i64(tmp64, tmp64, 16); - tmp =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); - if (rs !=3D 15) - { - tmp2 =3D load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); if (rs !=3D 15) { @@ -10248,29 +10291,10 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) gen_storeq_reg(s, rs, rd, tmp64); tcg_temp_free_i64(tmp64); } else { - if ((op & 0x20) || !(op & 8)) { - /* Signed/unsigned 64-bit multiply, in decodetree */ - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - /* smlalxy */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - gen_mulxy(tmp, tmp2, op & 2, op & 1); + /* Signed/unsigned 64-bit multiply, in decodetree */ tcg_temp_free_i32(tmp2); - tmp64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); tcg_temp_free_i32(tmp); - if (op & 0x40) { - /* 64-bit accumulate. */ - gen_addq(s, tmp64, rs, rd); - } - gen_storeq_reg(s, rs, rd, tmp64); - tcg_temp_free_i64(tmp64); + goto illegal_op; } break; } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 7791be5590..19d12e726b 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -114,6 +114,7 @@ MVN_rxi .... 001 1111 . 0000 .... ............= @s_rxi_rot @s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr @s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra= =3D0 @rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr +@rd0mn ---- .... ... . rd:4 .... rm:4 .... rn:4 &rrrr ra=3D0 =20 MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn @@ -132,3 +133,22 @@ QADD .... 0001 0000 .... .... 0000 0101 ..= .. @rndm QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm + +# Halfword multiply and multiply accumulate + +SMLABB .... 0001 0000 .... .... .... 1000 .... @rdamn +SMLABT .... 0001 0000 .... .... .... 1100 .... @rdamn +SMLATB .... 0001 0000 .... .... .... 1010 .... @rdamn +SMLATT .... 0001 0000 .... .... .... 1110 .... @rdamn +SMLAWB .... 0001 0010 .... .... .... 1000 .... @rdamn +SMULWB .... 0001 0010 .... 0000 .... 1010 .... @rd0mn +SMLAWT .... 0001 0010 .... .... .... 1100 .... @rdamn +SMULWT .... 0001 0010 .... 0000 .... 1110 .... @rd0mn +SMLALBB .... 0001 0100 .... .... .... 1000 .... @rdamn +SMLALBT .... 0001 0100 .... .... .... 1100 .... @rdamn +SMLALTB .... 0001 0100 .... .... .... 1010 .... @rdamn +SMLALTT .... 0001 0100 .... .... .... 1110 .... @rdamn +SMULBB .... 0001 0110 .... 0000 .... 1000 .... @rd0mn +SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn +SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn +SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 7c6226e0af..122a0537ed 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -118,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ......= .. @s_rri_rot @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 @s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra= =3D0 s=3D0 @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr +@rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=3D0 @rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr =20 { @@ -130,6 +131,34 @@ UMULL 1111 1011 1010 .... .... .... 0000 ..= .. @s0_rnadm SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm +{ + SMULWB 1111 1011 0011 .... 1111 .... 0000 .... @rn0dm + SMLAWB 1111 1011 0011 .... .... .... 0000 .... @rnadm +} +{ + SMULWT 1111 1011 0011 .... 1111 .... 0001 .... @rn0dm + SMLAWT 1111 1011 0011 .... .... .... 0001 .... @rnadm +} +{ + SMULBB 1111 1011 0001 .... 1111 .... 0000 .... @rn0dm + SMLABB 1111 1011 0001 .... .... .... 0000 .... @rnadm +} +{ + SMULBT 1111 1011 0001 .... 1111 .... 0001 .... @rn0dm + SMLABT 1111 1011 0001 .... .... .... 0001 .... @rnadm +} +{ + SMULTB 1111 1011 0001 .... 1111 .... 0010 .... @rn0dm + SMLATB 1111 1011 0001 .... .... .... 0010 .... @rnadm +} +{ + SMULTT 1111 1011 0001 .... 1111 .... 0011 .... @rn0dm + SMLATT 1111 1011 0001 .... .... .... 0011 .... @rnadm +} +SMLALBB 1111 1011 1100 .... .... .... 1000 .... @rnadm +SMLALBT 1111 1011 1100 .... .... .... 1001 .... @rnadm +SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm +SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm =20 # Data-processing (two source registers) =20 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UWYlG2k/Brng2tcRnik0JT0fnjwpLVOKsVAvc3Cf6uM=; b=uE9+yCU0T6Ao9JMkI8KrbQfhfd2p5ajqTi+mS0jkyNzaOKbM+TKA8AtOCL4pC6F/Yv /CbiLFEEQlrYbNj5U1s5YbgpvtZ/sTezNqAKO2PPBRgNUzBaZYD+lEybrcTMWGSRW/CF Nft3it02B853GxhnR4bWQ7LtIXYLQjEdkzRWYFWJWx8QK3sYo6TOMgbYyS6P5ROs7Fs1 qnXtAy/D+c1AztrlLgdyBeFHDG08pyGCZ+hQE+TyiYXF7yta4U9WAU33L9p/hhzELN2a DRgFMwT+xQSG/dKxX1X540+PtLcdldj5NPQZ9vVs2l1J+8zEURAZhLxvjHOw0pRnILGo PXTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UWYlG2k/Brng2tcRnik0JT0fnjwpLVOKsVAvc3Cf6uM=; b=bgs35LoFgSqOR9tKKjL2wiLapLd+lDtSgUk92D+6VvRHjhSNuHEWz3OfzrU19CwXZP NqwBDaDmwM0h/YhmekiLK4q1tBf7nxd0GVFy2K+Du1Pf3pE/vaxKzf9Ve6hSVaQtsx/P xVZe6y4ziVu6nx0PRXjDM4nhC4B7hnM22wclN+/HAzZKOV2jX5+ef/N+1YsXuf54aGFY T+d9f1qCsyNdJQ5CApKlpXWUivbbNxxpxYkijTkasf0LT/LxVCWQRwYXvi1RiEnpxrDi cqsnWGqf5/TCAvmgq9kW4RLlr2/vVVlZVNLNrFPzBG3pdTYEna8qaDpP5kElodOnkXbB 4ATg== X-Gm-Message-State: APjAAAWtef8QGbH+u+DvCWEA+TmuBm43BEi5d0q3Z3DaVc0GlPEXQVkq DFbMlSUEwkATnkvL4PJ8NE+nSlswbH4= X-Google-Smtp-Source: APXvYqyzON00wVk0yJxiZEVkc0bKErpX5uOCMiINKu7c6SBBYMNH5j8wPhYJo31NKuCs5KaqgrpPCQ== X-Received: by 2002:a62:584:: with SMTP id 126mr26621954pff.73.1566250689777; Mon, 19 Aug 2019 14:38:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:57 -0700 Message-Id: <20190819213755.26175-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 10/68] target/arm: Simplify op_smlaxxx for SMLAL* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_add2_i32. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 56ae83a7d0..8557ef831f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8148,8 +8148,7 @@ DO_QADDSUB(QDSUB, false, true) static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, int add_long, bool nt, bool mt) { - TCGv_i32 t0, t1; - TCGv_i64 t64; + TCGv_i32 t0, t1, tl, th; =20 if (s->thumb ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) @@ -8173,12 +8172,14 @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, store_reg(s, a->rd, t0); break; case 2: - t64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(t64, t0); + tl =3D load_reg(s, a->ra); + th =3D load_reg(s, a->rd); + t1 =3D tcg_const_i32(0); + tcg_gen_add2_i32(tl, th, tl, th, t0, t1); tcg_temp_free_i32(t0); - gen_addq(s, t64, a->ra, a->rd); - gen_storeq_reg(s, a->ra, a->rd, t64); - tcg_temp_free_i64(t64); + tcg_temp_free_i32(t1); + store_reg(s, a->ra, tl); + store_reg(s, a->rd, th); break; default: g_assert_not_reached(); --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566251339; cv=none; d=zoho.com; s=zohoarc; b=BR562L1rHnozXjVHSx7JPTfa5JCkAol3ybUMPzjoSOCZ8STdv4xRuS+Vp61yZ6bZQ5N9DgIvWhdxWIRP+M4LRJvhr1D1tKTGH/ksOu90zu9fTodyYOK9jGBwdPI57BvtHXf2PBZrX7Fa/JR6bNhHIMl/5MUb+wDUc6Rp+Zf6w/A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566251339; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=z6bTZIJUuD2Rb2udZZO8tN325lpohcam+cQYkXY7q0k=; b=QZPlzILSGPCKJpL1vULWHACDkryTWEOJmYgGtYlubYqZUM2hgk/IrJw1z+S/4agI1b15kT8WgzB033t108JGi1d4lmTSJoVQq5flf6+TiJ4s7at3OstgSX7nO31pMvF4NfAiqFS/ZygNyhQFnP/e9SKwgzhX1HOsF71e3qE8X4E= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566251339265668.6256703753938; Mon, 19 Aug 2019 14:48:59 -0700 (PDT) Received: from localhost ([::1]:59070 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpWJ-0004v9-CD for importer@patchew.org; Mon, 19 Aug 2019 17:48:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58699) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpLx-0001SK-Gi for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpLw-00065V-G1 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:13 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:44256) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpLw-00064r-AQ for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:12 -0400 Received: by mail-pl1-x644.google.com with SMTP id t14so1574161plr.11 for ; Mon, 19 Aug 2019 14:38:12 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=z6bTZIJUuD2Rb2udZZO8tN325lpohcam+cQYkXY7q0k=; b=YZ0YyngK2P7R9z4uAceUFNeutCFwqq8i7vHldiAteQsa2asCHVcg48IqB0ep869q68 WLkmJMH3d9AIM/6t3LdqVsLoNan6DkrZ5bP5w0oWMU9dNJPzn0NceZRiJkn4fA0W7t9O VqGnq6tJFsJS8yAZTutn/9id0o2UvV7gLg5w24eEoXo/Jaw2B3RUlETz/b3mgkiUIkxg Pv5V2nc0CJZfig4FPjVa19zF7nxIaNayil+c2ucKqFf2SsqmklGyNSqj/u31Vw2DtjFt /YBMIXkSMJbhGIqqXP9cCMh7cdqcTG+K4swU2m2hb3JeyKUGvsFG18f0v96DbKCu8d0d DOEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=z6bTZIJUuD2Rb2udZZO8tN325lpohcam+cQYkXY7q0k=; b=pAdooXmFRoVzrJPCPA4k2IPzRX/os6veXer/mlCrVKRe1o0trvFtAZ5Ko3+rq5G1De hpdpfCdGsi7A+7T0oGg3A9LqNcInL8yC87sNIvSgubxgbCz9DaEqprUyKvbZMfzyOAwe rN2hD2uV596eeGCOhZ5EYJRy97sM65BdLGyV7Hl383WeXnRt8UzW2SXQHbkR/pcP4RLO 6EUWxWB3fnMw4NNqhlEa3UHETf3ZWzx9MZaj7Hjtc/HRtIgGrPes9KWB/t7ZVZiIkSYW CgIHY7cgyLwDAvDQ2/6UIR3A3a1p09a/tbWfj8G19uIjI8mO9RGx6DA7gkrxzUiv1IGS ckzA== X-Gm-Message-State: APjAAAVGxeiyUXgQyOcdiqRRQHxh57ivTWK/BRBzNCx7NgbyVh2Q4XzU B6Vj3dttotHbezY4P6W7bp0qAd2Zw/A= X-Google-Smtp-Source: APXvYqyTYPGYlGAlcPRyoPxB0CQOmFFZxh4s4C8Ae2V3wGwXug6GCI5bSU+JZSCR1Ghwu10OTGhz0w== X-Received: by 2002:a17:902:3003:: with SMTP id u3mr10413251plb.161.1566250691131; Mon, 19 Aug 2019 14:38:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:58 -0700 Message-Id: <20190819213755.26175-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 11/68] target/arm: Simplify op_smlawx for SMLAW* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" By shifting the 16-bit input left by 16, we can align the desired portion of the 48-bit product and use tcg_gen_muls2_i32. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 8557ef831f..9a2fb7d3aa 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8213,7 +8213,6 @@ DO_SMLAX(SMLALTT, 2, 1, 1) static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) { TCGv_i32 t0, t1; - TCGv_i64 t64; =20 if (!ENABLE_ARCH_5TE) { return false; @@ -8221,16 +8220,17 @@ static bool op_smlawx(DisasContext *s, arg_rrrr *a,= bool add, bool mt) =20 t0 =3D load_reg(s, a->rn); t1 =3D load_reg(s, a->rm); + /* + * Since the nominal result is product<47:16>, shift the 16-bit + * input up by 16 bits, so that the result is at product<63:32>. + */ if (mt) { - tcg_gen_sari_i32(t1, t1, 16); + tcg_gen_andi_i32(t1, t1, 0xffff0000); } else { - gen_sxth(t1); + tcg_gen_shli_i32(t1, t1, 16); } - t64 =3D gen_muls_i64_i32(t0, t1); - tcg_gen_shri_i64(t64, t64, 16); - t1 =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, t64); - tcg_temp_free_i64(t64); + tcg_gen_muls2_i32(t0, t1, t0, t1); + tcg_temp_free_i32(t0); if (add) { t0 =3D load_reg(s, a->ra); gen_helper_add_setq(t1, cpu_env, t1, t0); --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566251496; cv=none; d=zoho.com; s=zohoarc; b=mK0iOowaSXxcrr2fWcmA09oZflSTNn3AaZKH6UBA7Z/oenkG46eOcKBmKFt7Qe6lm/pIY3mV0QaQOEEYQx1FdnFQZqTpc6zQJSdNMyPizaCRbzAT/9ee68VsKPYPlpkN4+i6Of1orOtyMSfNSS4E8u1mchwYg00fTHFa6Bwk92E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566251496; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=aKVuzxBlVmXAfmZOcitSo8oovzmAL9rVEMNxLaYaWGo=; b=Ge9d1BP5d8+k8vJ5s4GmAGitUer3IWiFGlg/cFPP3PRzpNZekBi9Ncyc3URnQ2khNTMpYl9inPf9UB7xjU/1OGyVYGlFXaoet33C2sWDZHL8M1hHInlUeaY0KVHYTCdhV04ZSW5a2DO94Y5pFX523xV/R6WFRmVLMOGzhjimUR4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566251496481527.8947334079558; Mon, 19 Aug 2019 14:51:36 -0700 (PDT) Received: from localhost ([::1]:59132 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpYt-0000Rj-6J for importer@patchew.org; Mon, 19 Aug 2019 17:51:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58732) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpLy-0001V3-Vj for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpLx-00066e-JT for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:14 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:33050) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpLx-000661-Dn for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:13 -0400 Received: by mail-pf1-x442.google.com with SMTP id g2so1953586pfq.0 for ; Mon, 19 Aug 2019 14:38:13 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aKVuzxBlVmXAfmZOcitSo8oovzmAL9rVEMNxLaYaWGo=; b=bMhxjcUTGfzULpCwWw/NsZAsV+c3dse2Qmuiu19PvgQx89YWEYfU/qMWM/xKZrDGzo 96LIqN3H3R7H2S5rC32b09HHt/9mOZnU2gdV6rS1urIGfpXwYOCIXw06A+2JTCr8P4h4 lB7B/iQWcd7dWNQZcKypIeuMLGCsHwRBYe8q8egbr1T1F4z+R+r6xyWw+iL715IpfkbS asXvLjYSRC1Kt7baZOZZKMDOeytEXpZujKPVdi6w6NwEmzHb/9rXRW7MmgsNlPq8NXbu f6PxO0WMrwr+Ss5hmwvi0d+zoMj9h0/EqBnl4+bOcM8+leGw0yx5BJGFEq7ZdaKxPmMr ZFZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aKVuzxBlVmXAfmZOcitSo8oovzmAL9rVEMNxLaYaWGo=; b=DuTzIEqxtvj56S6vdD9nMgTYaYTPCsJM+N67qMNwW2yhp1ylT8anXDCQ6S84hq41S2 c+2r0NKie64xonQJe6iuMcPJAPJYSmpW7uSpCqbD7MviCjvvecbI3Rhjh0dIW6Jb/pi5 S6ISlNolKtkusfzeLe+kNKx3ZLM3Jcrjhdttba/BMrfsu2WdMKdTh5KzhOKbhzLnbPiQ 81e9+h1HLRmRxpThbaenBVL6vDWKuVfr7CFK+aI3n3ciYopYtnOokickFEDwT1KBm2pr DKI4R1favndChcsoB/DvxAwVxmH6TA90eHTehIoJLKuprZXoS9kdcpqxpNERoZWzens7 qdOg== X-Gm-Message-State: APjAAAWuffP5FnnvTELyRsaHFwNMRf5WfClRSUCW28yRmB0CFtORzq8j oTuc4YQs5toEmrM8ys+PRWnA36+92lY= X-Google-Smtp-Source: APXvYqwpJsGCc1ERNxuV01GVCy+QBGRLAjW+NdTCF7EwOCPW67pNgG7ieHmP//rWRTRx+l9hVeigQA== X-Received: by 2002:aa7:8c57:: with SMTP id e23mr15880674pfd.48.1566250692178; Mon, 19 Aug 2019 14:38:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:59 -0700 Message-Id: <20190819213755.26175-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 12/68] target/arm: Convert MSR (immediate) and hints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 60 +++++++++++++++++++++++++++++------------- target/arm/a32.decode | 25 ++++++++++++++++++ target/arm/t32.decode | 17 ++++++++++++ 3 files changed, 84 insertions(+), 18 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9a2fb7d3aa..ee485b1cbd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8253,6 +8253,44 @@ DO_SMLAWX(SMLAWT, 1, 1) =20 #undef DO_SMLAWX =20 +/* + * MSR (immediate) and hints + */ + +static bool trans_YIELD(DisasContext *s, arg_YIELD *a) +{ + gen_nop_hint(s, 1); + return true; +} + +static bool trans_WFE(DisasContext *s, arg_WFE *a) +{ + gen_nop_hint(s, 2); + return true; +} + +static bool trans_WFI(DisasContext *s, arg_WFI *a) +{ + gen_nop_hint(s, 3); + return true; +} + +static bool trans_NOP(DisasContext *s, arg_NOP *a) +{ + return true; +} + +static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) +{ + uint32_t val =3D ror32(a->imm, a->rot * 2); + uint32_t mask =3D msr_mask(s, a->mask, a->r); + + if (gen_set_psr_im(s, mask, a->r, val)) { + unallocated_encoding(s); + } + return true; +} + /* * Legacy decoder. */ @@ -8526,21 +8564,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) } store_reg(s, rd, tmp); } else { - if (((insn >> 12) & 0xf) !=3D 0xf) - goto illegal_op; - if (((insn >> 16) & 0xf) =3D=3D 0) { - gen_nop_hint(s, insn & 0xff); - } else { - /* CPSR =3D immediate */ - val =3D insn & 0xff; - shift =3D ((insn >> 8) & 0xf) * 2; - val =3D ror32(val, shift); - i =3D ((insn & (1 << 22)) !=3D 0); - if (gen_set_psr_im(s, msr_mask(s, (insn >> 16) & 0xf, i), - i, val)) { - goto illegal_op; - } - } + /* MSR (immediate) and hints */ + /* All done in decodetree. Illegal ops already signalled. */ + g_assert_not_reached(); } } else if ((insn & 0x0f900000) =3D=3D 0x01000000 && (insn & 0x00000090) !=3D 0x00000090) { @@ -10480,9 +10506,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) goto illegal_op; break; case 2: /* cps, nop-hint. */ - if (((insn >> 8) & 7) =3D=3D 0) { - gen_nop_hint(s, insn & 0xff); - } + /* nop hints in decodetree */ /* Implemented as NOP in user mode. */ if (IS_USER(s)) break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 19d12e726b..3d5c5408f9 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -22,6 +22,7 @@ # All insns that have 0xf in insn[31:28] are in a32-uncond.decode. # =20 +&empty &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty &s_rri_rot s rn rd imm rot @@ -152,3 +153,27 @@ SMULBB .... 0001 0110 .... 0000 .... 1000 ..= .. @rd0mn SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn + +# MSR (immediate) and hints + +&msr_i r mask rot imm +@msr_i ---- .... .... mask:4 .... rot:4 imm:8 &msr_i + +{ + { + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + + # The canonical nop ends in 00000000, but the whole of the + # rest of the space executes as nop if otherwise unsupported. + NOP ---- 0011 0010 0000 1111 ---- ---- ---- + } + # Note mask =3D 0 is covered by NOP + MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=3D0 +} +MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=3D1 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 122a0537ed..ccb7cdd4ef 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -19,6 +19,7 @@ # This file is processed by scripts/decodetree.py # =20 +&empty !extern &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot @@ -166,3 +167,19 @@ QADD 1111 1010 1000 .... 1111 .... 1000 ..= .. @rndm QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm + +# Branches and miscellaneous control + +{ + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- +} --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566251649; cv=none; d=zoho.com; s=zohoarc; b=gU2gQ8a9q/F3cP7RNdiLZUIFzCIGbWN2B+XjLmRISOEAT/VqslS78SdOrEqQ7LlAndwBWv/bJiv19zyo4aWHxrtIUjCpGSig9XMXqibV/OhwuISH3asHY0/xKJjg0jT0T1gihcn10nUnUdrP4jMeYxDoGNJ+2NLExeHchA3D/zg= ARC-Message-Signature: i=1; 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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 13/68] target/arm: Convert MRS/MSR (banked, register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The m-profile and a-profile, decodings overlap. Only return false for the case of wrong profile; handle UNDEFINED for permission failure directly. This ensures that we don't accidentally pass an insn that applies to the wrong profile. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 226 ++++++++++++++++++----------------------- target/arm/a32.decode | 14 +++ target/arm/t32.decode | 40 ++++++-- 3 files changed, 142 insertions(+), 138 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ee485b1cbd..026abcaa9c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8291,6 +8291,93 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_i= mm *a) return true; } =20 +/* + * Miscellaneous instructions + */ + +static bool trans_MRS_bank(DisasContext *s, arg_MRS_bank *a) +{ + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_mrs_banked(s, a->r, a->sysm, a->rd); + return true; +} + +static bool trans_MSR_bank(DisasContext *s, arg_MSR_bank *a) +{ + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_msr_banked(s, a->r, a->sysm, a->rn); + return true; +} + +static bool trans_MRS_reg(DisasContext *s, arg_MRS_reg *a) +{ + TCGv_i32 tmp; + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (a->r) { + if (IS_USER(s)) { + unallocated_encoding(s); + return true; + } + tmp =3D load_cpu_field(spsr); + } else { + tmp =3D tcg_temp_new_i32(); + gen_helper_cpsr_read(tmp, cpu_env); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MSR_reg(DisasContext *s, arg_MSR_reg *a) +{ + TCGv_i32 tmp; + uint32_t mask =3D msr_mask(s, a->mask, a->r); + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tmp =3D load_reg(s, a->rn); + if (gen_set_psr(s, mask, a->r, tmp)) { + unallocated_encoding(s); + } + return true; +} + +static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a) +{ + TCGv_i32 tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tmp =3D tcg_const_i32(a->sysm); + gen_helper_v7m_mrs(tmp, cpu_env, tmp); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) +{ + TCGv_i32 addr, reg; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + addr =3D tcg_const_i32((a->mask << 10) | a->sysm); + reg =3D load_reg(s, a->rn); + gen_helper_v7m_msr(cpu_env, addr, reg); + tcg_temp_free_i32(addr); + tcg_temp_free_i32(reg); + gen_lookup_tb(s); + return true; +} + /* * Legacy decoder. */ @@ -8575,46 +8662,10 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) sh =3D (insn >> 4) & 0xf; rm =3D insn & 0xf; switch (sh) { - case 0x0: /* MSR, MRS */ - if (insn & (1 << 9)) { - /* MSR (banked) and MRS (banked) */ - int sysm =3D extract32(insn, 16, 4) | - (extract32(insn, 8, 1) << 4); - int r =3D extract32(insn, 22, 1); - - if (op1 & 1) { - /* MSR (banked) */ - gen_msr_banked(s, r, sysm, rm); - } else { - /* MRS (banked) */ - int rd =3D extract32(insn, 12, 4); - - gen_mrs_banked(s, r, sysm, rd); - } - break; - } - - /* MSR, MRS (for PSRs) */ - if (op1 & 1) { - /* PSR =3D reg */ - tmp =3D load_reg(s, rm); - i =3D ((op1 & 2) !=3D 0); - if (gen_set_psr(s, msr_mask(s, (insn >> 16) & 0xf, i), i, = tmp)) - goto illegal_op; - } else { - /* reg =3D PSR */ - rd =3D (insn >> 12) & 0xf; - if (op1 & 2) { - if (IS_USER(s)) - goto illegal_op; - tmp =3D load_cpu_field(spsr); - } else { - tmp =3D tcg_temp_new_i32(); - gen_helper_cpsr_read(tmp, cpu_env); - } - store_reg(s, rd, tmp); - } - break; + case 0x0: + /* MSR/MRS (banked/register) */ + /* All done in decodetree. Illegal ops already signalled. */ + g_assert_not_reached(); case 0x1: if (op1 =3D=3D 1) { /* branch/exchange thumb (bx). */ @@ -10471,40 +10522,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } else { op =3D (insn >> 20) & 7; switch (op) { - case 0: /* msr cpsr. */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - tmp =3D load_reg(s, rn); - /* the constant is the mask and SYSm fields */ - addr =3D tcg_const_i32(insn & 0xfff); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - tcg_temp_free_i32(tmp); - gen_lookup_tb(s); - break; - } - /* fall through */ - case 1: /* msr spsr. */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - - if (extract32(insn, 5, 1)) { - /* MSR (banked) */ - int sysm =3D extract32(insn, 8, 4) | - (extract32(insn, 4, 1) << 4); - int r =3D op & 1; - - gen_msr_banked(s, r, sysm, rm); - break; - } - - /* MSR (for PSRs) */ - tmp =3D load_reg(s, rn); - if (gen_set_psr(s, - msr_mask(s, (insn >> 8) & 0xf, op =3D=3D 1), - op =3D=3D 1, tmp)) - goto illegal_op; - break; + case 0: /* msr cpsr, in decodetree */ + case 1: /* msr spsr, in decodetree */ + goto illegal_op; case 2: /* cps, nop-hint. */ /* nop hints in decodetree */ /* Implemented as NOP in user mode. */ @@ -10596,61 +10616,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } gen_exception_return(s, tmp); break; - case 6: /* MRS */ - if (extract32(insn, 5, 1) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - /* MRS (banked) */ - int sysm =3D extract32(insn, 16, 4) | - (extract32(insn, 4, 1) << 4); - - gen_mrs_banked(s, 0, sysm, rd); - break; - } - - if (extract32(insn, 16, 4) !=3D 0xf) { - goto illegal_op; - } - if (!arm_dc_feature(s, ARM_FEATURE_M) && - extract32(insn, 0, 8) !=3D 0) { - goto illegal_op; - } - - /* mrs cpsr */ - tmp =3D tcg_temp_new_i32(); - if (arm_dc_feature(s, ARM_FEATURE_M)) { - addr =3D tcg_const_i32(insn & 0xff); - gen_helper_v7m_mrs(tmp, cpu_env, addr); - tcg_temp_free_i32(addr); - } else { - gen_helper_cpsr_read(tmp, cpu_env); - } - store_reg(s, rd, tmp); - break; - case 7: /* MRS */ - if (extract32(insn, 5, 1) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - /* MRS (banked) */ - int sysm =3D extract32(insn, 16, 4) | - (extract32(insn, 4, 1) << 4); - - gen_mrs_banked(s, 1, sysm, rd); - break; - } - - /* mrs spsr. */ - /* Not accessible in user mode. */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)= ) { - goto illegal_op; - } - - if (extract32(insn, 16, 4) !=3D 0xf || - extract32(insn, 0, 8) !=3D 0) { - goto illegal_op; - } - - tmp =3D load_cpu_field(spsr); - store_reg(s, rd, tmp); - break; + case 6: /* MRS, in decodetree */ + case 7: /* MSR, in decodetree */ + goto illegal_op; } } } else { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 3d5c5408f9..6ee12c1140 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,10 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&msr_reg rn r mask +&mrs_reg rd r +&msr_bank rn r sysm +&mrs_bank rd r sysm =20 # Data-processing (register) =20 @@ -177,3 +181,13 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 ..= .. @rd0mn MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=3D0 } MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=3D1 + +# Miscellaneous instructions + +%sysm 8:1 16:4 + +MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %s= ysm +MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %s= ysm + +MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg +MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ccb7cdd4ef..98b682e7ec 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,10 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&msr_reg !extern rn r mask +&mrs_reg !extern rd r +&msr_bank !extern rn r sysm +&mrs_bank !extern rd r sysm =20 # Data-processing (register) =20 @@ -170,16 +174,34 @@ QDSUB 1111 1010 1000 .... 1111 .... 1011 .= ... @rndm =20 # Branches and miscellaneous control =20 +%msr_sysm 4:1 8:4 +%mrs_sysm 4:1 16:4 + { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + { + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 - # The canonical nop ends in 0000 0000, but the whole rest - # of the space is "reserved hint, behaves as nop". - NOP 1111 0011 1010 1111 1000 0000 ---- ---- + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- + } + # Note that the v7m insn overlaps both the normal and banked insn. + { + MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ + &mrs_bank sysm=3D%mrs_sysm + MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg + MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 + } + { + MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ + &msr_bank sysm=3D%msr_sysm + MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg + MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 + } } --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 14/68] target/arm: Convert Cyclic Redundancy Check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 121 +++++++++++++++++++---------------------- target/arm/a32.decode | 9 +++ target/arm/t32.decode | 7 +++ 3 files changed, 72 insertions(+), 65 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 026abcaa9c..f390656ce9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8291,6 +8291,57 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_i= mm *a) return true; } =20 +/* + * Cyclic Redundancy Check + */ + +static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, TCGMemOp sz) +{ + TCGv_i32 t1, t2, t3; + + if (!dc_isar_feature(aa32_crc32, s)) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + switch (sz) { + case MO_8: + gen_uxtb(t2); + break; + case MO_16: + gen_uxth(t2); + break; + case MO_32: + break; + default: + g_assert_not_reached(); + } + t3 =3D tcg_const_i32(1 << sz); + if (c) { + gen_helper_crc32c(t1, t1, t2, t3); + } else { + gen_helper_crc32(t1, t1, t2, t3); + } + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + store_reg(s, a->rd, t1); + return true; +} + +#define DO_CRC32(NAME, c, sz) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ + { return op_crc32(s, a, c, sz); } + +DO_CRC32(CRC32B, false, MO_8) +DO_CRC32(CRC32H, false, MO_16) +DO_CRC32(CRC32W, false, MO_32) +DO_CRC32(CRC32CB, true, MO_8) +DO_CRC32(CRC32CH, true, MO_16) +DO_CRC32(CRC32CW, true, MO_32) + +#undef DO_CRC32 + /* * Miscellaneous instructions */ @@ -8706,39 +8757,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) gen_bx(s, tmp); break; case 0x4: - { - /* crc32/crc32c */ - uint32_t c =3D extract32(insn, 8, 4); - - /* Check this CPU supports ARMv8 CRC instructions. - * op1 =3D=3D 3 is UNPREDICTABLE but handle as UNDEFINED. - * Bits 8, 10 and 11 should be zero. - */ - if (!dc_isar_feature(aa32_crc32, s) || op1 =3D=3D 0x3 || (c & = 0xd) !=3D 0) { - goto illegal_op; - } - - rn =3D extract32(insn, 16, 4); - rd =3D extract32(insn, 12, 4); - - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - if (op1 =3D=3D 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (op1 =3D=3D 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 =3D tcg_const_i32(1 << op1); - if (c & 0x2) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - store_reg(s, rd, tmp); - break; - } + /* crc32 */ + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; case 0x5: /* Saturating addition and subtraction. */ /* All done in decodetree. Reach here for illegal ops. */ @@ -10181,16 +10202,13 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) goto illegal_op; } break; - case 0x20: /* crc32/crc32c */ + case 0x20: /* crc32/crc32c, in decodetree */ case 0x21: case 0x22: case 0x28: case 0x29: case 0x2a: - if (!dc_isar_feature(aa32_crc32, s)) { - goto illegal_op; - } - break; + goto illegal_op; default: goto illegal_op; } @@ -10219,33 +10237,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) case 0x18: /* clz */ tcg_gen_clzi_i32(tmp, tmp, 32); break; - case 0x20: - case 0x21: - case 0x22: - case 0x28: - case 0x29: - case 0x2a: - { - /* crc32/crc32c */ - uint32_t sz =3D op & 0x3; - uint32_t c =3D op & 0x8; - - tmp2 =3D load_reg(s, rm); - if (sz =3D=3D 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (sz =3D=3D 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 =3D tcg_const_i32(1 << sz); - if (c) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - break; - } default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 6ee12c1140..a8ef435b15 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -182,6 +182,15 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 ..= .. @rd0mn } MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=3D1 =20 +# Cyclic Redundancy Check + +CRC32B .... 0001 0000 .... .... 0000 0100 .... @rndm +CRC32H .... 0001 0010 .... .... 0000 0100 .... @rndm +CRC32W .... 0001 0100 .... .... 0000 0100 .... @rndm +CRC32CB .... 0001 0000 .... .... 0010 0100 .... @rndm +CRC32CH .... 0001 0010 .... .... 0010 0100 .... @rndm +CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm + # Miscellaneous instructions =20 %sysm 8:1 16:4 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 98b682e7ec..261db100ff 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -172,6 +172,13 @@ QSUB 1111 1010 1000 .... 1111 .... 1010 ..= .. @rndm QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm =20 +CRC32B 1111 1010 1100 .... 1111 .... 1000 .... @rndm +CRC32H 1111 1010 1100 .... 1111 .... 1001 .... @rndm +CRC32W 1111 1010 1100 .... 1111 .... 1010 .... @rndm +CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm +CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm +CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm + # Branches and miscellaneous control =20 %msr_sysm 4:1 8:4 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F/upwaanfqXSt3Hk/7WIkT0U11Hn2bkl0Zsc2jcodB0=; b=s7d7yvxyrP04hcw4TOgSZXuVe0kp2q777ybiXRZoZ2RxEmdST4Boy/6w3bkuB3R5Wc ljietIQp+kzGWwJu5dR1yABU/E+xqMptzKjG8ujBpuylaoiXSHP/MjLpsf6AEy7wGBBG +BTPCPVAaIW3n5nHX/uFvjgZZwfEITTZaoaZQetl8PRgCKJsLXyH8HO5q/Gatc8f/5Z6 tYxT0OBCjg/O+4TkeI87l+8ju7sXnhDCj/LqqCbRzacB4c94IAH3IodwtcXUjRYwDM+3 CEUkaONwmJmotDMxX/xfpKBAxeRMyoLhxhBt7DYH2S9mIrzD8wOiMheRWDpKQ1DeL9Sv UvAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F/upwaanfqXSt3Hk/7WIkT0U11Hn2bkl0Zsc2jcodB0=; b=itZxwVfp7UxdW/kp4VwIkfTddQoaG+WUBLcsGjDQfA2FdEQymYaJxHHRdK5dB9YjnV Q4f+w+Cin098lkUAXMBgu+UJGH7Vf6IsRSnabfdqSpOQOKJJqBxkbItXr1zboczh4/jF 9EWGKmYJwDBStzDT5TQNlEsXaIp9JzuaD5Aa9HfSQpfCXk2t1FSiv7V7X8D/A63qCrd/ IGez3UEKe9pn1Pm9tDS7XKFvLjWeNQFPD5xK+Mq7MFx/vTc3BaGZ7pCsHRxFt2dYs9UO YvDRDPo6FqtYlaLgDoqvCaCbbqmpcbY6W1mE7aJpUMTERV8813988GRmamyE0jpn1XaF GzTw== X-Gm-Message-State: APjAAAVhM4g56buOP85vJr6R7e5PRlFhQsUSdD9OohQxbnnp04Wu0yKn 3WMNPbv697VcRTGa6+8m0faubn8wwV0= X-Google-Smtp-Source: APXvYqyIwEwuhH74An9HTur0VNW40wAfzfxgfdmHQWbKZop/BKbCLdUu71HtCElQwdnW3uMadWUDyA== X-Received: by 2002:aa7:8189:: with SMTP id g9mr26793797pfi.143.1566250696097; Mon, 19 Aug 2019 14:38:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:02 -0700 Message-Id: <20190819213755.26175-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 78 ++++++++++++++++++++---------------------- target/arm/a32.decode | 7 ++++ target/arm/t32.decode | 2 ++ 3 files changed, 47 insertions(+), 40 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index f390656ce9..ef26ed7b57 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8429,6 +8429,38 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v= 7m *a) return true; } =20 +static bool trans_BX(DisasContext *s, arg_BX *a) +{ + if (!ENABLE_ARCH_4T) { + return false; + } + gen_bx(s, load_reg(s, a->rm)); + return true; +} + +static bool trans_BXJ(DisasContext *s, arg_BXJ *a) +{ + if (!ENABLE_ARCH_5J || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + /* Trivial implementation equivalent to bx. */ + gen_bx(s, load_reg(s, a->rm)); + return true; +} + +static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_5) { + return false; + } + tmp =3D load_reg(s, a->rm); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_bx(s, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8718,12 +8750,7 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) /* All done in decodetree. Illegal ops already signalled. */ g_assert_not_reached(); case 0x1: - if (op1 =3D=3D 1) { - /* branch/exchange thumb (bx). */ - ARCH(4T); - tmp =3D load_reg(s, rm); - gen_bx(s, tmp); - } else if (op1 =3D=3D 3) { + if (op1 =3D=3D 3) { /* clz */ ARCH(5); rd =3D (insn >> 12) & 0xf; @@ -8734,30 +8761,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) goto illegal_op; } break; - case 0x2: - if (op1 =3D=3D 1) { - ARCH(5J); /* bxj */ - /* Trivial implementation equivalent to bx. */ - tmp =3D load_reg(s, rm); - gen_bx(s, tmp); - } else { - goto illegal_op; - } - break; - case 0x3: - if (op1 !=3D 1) - goto illegal_op; - - ARCH(5); - /* branch link/exchange thumb (blx) */ - tmp =3D load_reg(s, rm); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - break; - case 0x4: - /* crc32 */ + case 0x2: /* bxj */ + case 0x3: /* blx */ + case 0x4: /* crc32 */ /* All done in decodetree. Illegal ops reach here. */ goto illegal_op; case 0x5: @@ -10578,16 +10584,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) goto illegal_op; } break; - case 4: /* bxj */ - /* Trivial implementation equivalent to bx. - * This instruction doesn't exist at all for M-pro= file. - */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - tmp =3D load_reg(s, rn); - gen_bx(s, tmp); - break; + case 4: /* bxj, in decodetree */ + goto illegal_op; case 5: /* Exception return. */ if (IS_USER(s)) { goto illegal_op; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index a8ef435b15..6cb9c16e2f 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,7 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&r rm &msr_reg rn r mask &mrs_reg rd r &msr_bank rn r sysm @@ -195,8 +196,14 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 ..= .. @rndm =20 %sysm 8:1 16:4 =20 +@rm ---- .... .... .... .... .... .... rm:4 &r + MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %s= ysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %s= ysm =20 MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg + +BX .... 0001 0010 1111 1111 1111 0001 .... @rm +BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm +BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 261db100ff..337706ebbe 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,7 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&r !extern rm &msr_reg !extern rn r mask &mrs_reg !extern rd r &msr_bank !extern rn r sysm @@ -211,4 +212,5 @@ CRC32CW 1111 1010 1101 .... 1111 .... 1010 ...= . @rndm MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 } + BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r } --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566251885; cv=none; d=zoho.com; s=zohoarc; b=Lz7IZxYBPektPhGC6r+TX9SPb5jhXNbPR+43Bc0h//+HzhuyWtKvqUiCm8eTnpzQoGansYZY+IUBfHmJ49gs5jKW8Nd3m1uDD6B2dbkOESUf6Frigg5MHitIYlppitXZLQ2FRMGS/ZlxRTdsaqgi8xuuhQ18NahsDS4zz6grmdo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566251885; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=zZYWccT7CCrzOlrmxHsfHjAEIVHw6UJ7WILoC7VO3SU=; b=SBmubogtvwZyxnYM7K6+Hmta1tUsyCL2i0y3/3zpwLly3+a0Dqb2iuBtz+Ojmv3GWZK333Mk9wsS9360zD1nOIPhtUMJ3iacID+Ps2erONFx19hSZ3ILzwC1Ptd1J1TZj3IHNyr2M9f/T6bY4tCplsbwnUOvd3bs7+ZIB+NBtY4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566251885153660.9574030782713; Mon, 19 Aug 2019 14:58:05 -0700 (PDT) Received: from localhost ([::1]:59282 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpf9-0001cM-Ny for importer@patchew.org; Mon, 19 Aug 2019 17:58:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58837) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpM4-0001eB-FI for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpM2-0006A0-Sb for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:20 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:41903) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpM2-00069R-Mc for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:18 -0400 Received: by mail-pg1-x541.google.com with SMTP id x15so1926604pgg.8 for ; Mon, 19 Aug 2019 14:38:18 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zZYWccT7CCrzOlrmxHsfHjAEIVHw6UJ7WILoC7VO3SU=; b=PPb1t8l9YP39KVfPVkg+miZTF3Jpd18TujsLmnHArLFTCMt3WmDDzdA6EsoAqoVjBP 9XYQLpHfU9Dtg03+e7F8WObuM9K8a2qXgNojBce1Z1WW/ZzX1fM+drr23SPgMr5L/Lg/ pBHY+l6/RwDzHbfz+YCpWwPW7yyg4eL1AlnDU1zL4XIEuXEYRqaazEB3ysP1ATZPiARm d3/nToby9TXFpQWg+doyEX24e3ugljUBAreYveJSuvwY0EV7OZ38V70yZTrxdG3ihNtm NwAS3XSVFmisUOZJqoA8KAx4gPTDYllXP1sO7uPKaMWbIvZJtKqLKxv+uk+XMEIpRftJ 4Z+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zZYWccT7CCrzOlrmxHsfHjAEIVHw6UJ7WILoC7VO3SU=; b=bJJ1wfDH0849zny+DL2W6qLlFhwmYWkAtvmAmPXOiHcFpxaBCMI9KiOpOtYwUZ74F8 mcyW/JE6nkGw3ZrsYAI/hF8wd9EcsExVaTKFdHAV/BrhNe86mNmMdyFYfA/pjH9OTDa/ BsPultStD8ClOS6fFyhRQarK4OunRZLwViDoYPStcVXw5Hpc9oz5T0/v3/FSrbvINXa6 SFo2rfGICwVj5gQTk1l1xm6MWGRtp+8Ng1oASD5/+PGs4rWqnwg9rplh86SwZYDSrFP5 7qywwx6QbiyY/1Y2U+PFlKwP+dvHIwrNTt1jyW/jof5Cyvza4hRPTuzPZKAGruD1yBwl SSqQ== X-Gm-Message-State: APjAAAWi+Xa8ywQSmdaMWb4ORBo9kMOpvDwtOmIysXdQ62qeoYJnDzf1 sem+T0b2KguSwpKa2s6vrZxm1B1ZA+A= X-Google-Smtp-Source: APXvYqzDroV08IYwhlvi7ngTP+2jkDNYwf9Pzr2ACQjTPqbmJInnqhAi1ZRHYOnXbrcVMzyCnEs3TA== X-Received: by 2002:a63:1f03:: with SMTP id f3mr21523509pgf.249.1566250697329; Mon, 19 Aug 2019 14:38:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:03 -0700 Message-Id: <20190819213755.26175-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 16/68] target/arm: Convert CLZ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Document our choice about the T32 CONSTRAINED UNPREDICTABLE behaviour. This matches the undocumented choice made by the legacy decoder. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 31 +++++++++++++++---------------- target/arm/a32.decode | 4 ++++ target/arm/t32.decode | 5 +++++ 3 files changed, 24 insertions(+), 16 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ef26ed7b57..f0fa5253b6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8461,6 +8461,19 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *= a) return true; } =20 +static bool trans_CLZ(DisasContext *s, arg_CLZ *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_5) { + return false; + } + tmp =3D load_reg(s, a->rm); + tcg_gen_clzi_i32(tmp, tmp, 32); + store_reg(s, a->rd, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8749,18 +8762,7 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) /* MSR/MRS (banked/register) */ /* All done in decodetree. Illegal ops already signalled. */ g_assert_not_reached(); - case 0x1: - if (op1 =3D=3D 3) { - /* clz */ - ARCH(5); - rd =3D (insn >> 12) & 0xf; - tmp =3D load_reg(s, rm); - tcg_gen_clzi_i32(tmp, tmp, 32); - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - break; + case 0x1: /* bx, clz */ case 0x2: /* bxj */ case 0x3: /* blx */ case 0x4: /* crc32 */ @@ -10201,13 +10203,13 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) case 0x08: /* rev */ case 0x09: /* rev16 */ case 0x0b: /* revsh */ - case 0x18: /* clz */ break; case 0x10: /* sel */ if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { goto illegal_op; } break; + case 0x18: /* clz, in decodetree */ case 0x20: /* crc32/crc32c, in decodetree */ case 0x21: case 0x22: @@ -10240,9 +10242,6 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) tcg_temp_free_i32(tmp3); tcg_temp_free_i32(tmp2); break; - case 0x18: /* clz */ - tcg_gen_clzi_i32(tmp, tmp, 32); - break; default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 6cb9c16e2f..182f2b6725 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,7 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&rr rd rm &r rm &msr_reg rn r mask &mrs_reg rd r @@ -197,6 +198,7 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 ...= . @rndm %sysm 8:1 16:4 =20 @rm ---- .... .... .... .... .... .... rm:4 &r +@rdm ---- .... .... .... rd:4 .... .... rm:4 &rr =20 MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %s= ysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %s= ysm @@ -207,3 +209,5 @@ MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 00= 00 rn:4 &msr_reg BX .... 0001 0010 1111 1111 1111 0001 .... @rm BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm + +CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 337706ebbe..67724efe4b 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,7 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&rr !extern rd rm &r !extern rm &msr_reg !extern rn r mask &mrs_reg !extern rd r @@ -126,6 +127,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ......= .. @s_rri_rot @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr @rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=3D0 @rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr +@rdm .... .... .... .... .... rd:4 .... rm:4 &rr =20 { MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm @@ -180,6 +182,9 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 ...= . @rndm CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm =20 +# Note rn !=3D rm is CONSTRAINED UNPREDICTABLE; we choose to ignore rn. +CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm + # Branches and miscellaneous control =20 %msr_sysm 4:1 8:4 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566252056; cv=none; d=zoho.com; s=zohoarc; b=PXiQO2kl2fqyZ9lBv3fHqhJa+jvZURi0LCBv9RKIrHARxjoyRHUnriJC4l7UBQLqZttCwrN5Ek3QoLcyQdCzX4pZyCzWwoUecnBW3jzzIZXZp6KCGaAIKYuzkAuyKliyqGkDheF/z92PR5bvfUeOKNByEs6dgXl8SrKKUf9W2PM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=e+H++wAKyA1U/1YuB/2iGYEbH8KDD+Sy3cPPJBo/ztc=; b=BPkzu9VfHA0Ug4azqB6MlZseOF0rAlCUSH8Px+FcrOi8fOeuOGf48r1VdhRxbQrBac MHNwfmkgnVPfgJ0BBh/vKM9MjGSxmKf+BaHOlZt5gRE9iRGaBM5u1mAIqmPSaHh0+P3Q E4OonWZBWMd1POO7e/n+BI3adVKNLj1Uj+EBVmqzA54TnUMzyMZnMHeIE3lVixtLT0E0 zjfHRvgxAJGf6xBfxtjl4oWNcPQv4uvfp57O/maBfDItlA8sXfezcKPYb0kbvdrnxIOw SWtQcU0K88cNCHhyjxm8YJSFi6bL/0xR23Id5p4ZL3O04/WL5LTfDl+MJ6prBQFtxJgu 7DXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=e+H++wAKyA1U/1YuB/2iGYEbH8KDD+Sy3cPPJBo/ztc=; b=NAdGE4U5MLhB+3kgbLIS404VZR09tIdt/5hpxGnyE/CsFE4WJQsRvi5Zck7+eQq9j/ fdwn5HfOTOy8GNCyDHe+BnlgSMi4U6MHsiAPfKBFEP0Vy1oCp4eyPVLrdKS997GgFkLZ En3EjsR0tynbqtYVbQolgLeVMGWP8OiwwDCCVULdApU8mx64/DKo3EJbTcqjMQ8TRy4Q 9bLe4s8dnuvR8dapaf8e0SKArJ9Vg/gNI1GELVMq60XcepnmwYZlr6aOBzylClY7eye7 duIywZgXjKszwJqSLQGraN9cM1XfIxlm/I1RGMYGDRM6Qu/x0TdyJtyPLuFnjHGbl5VI y8pg== X-Gm-Message-State: APjAAAXv4qT1VpTtwLvOMgGvM9cmlqycFUVimU+PIp2gIW8XvDfD0Hzc WsLJbXr6wckCKdc2NAZ1Z+49iZrWLBQ= X-Google-Smtp-Source: APXvYqxoMwe+U6OcO/POIzp4JGKmrYnUVLKe0+FYnUY4AjVmOtVCdANM+lQeutFyM3c2frgIXKn5Vw== X-Received: by 2002:a65:654d:: with SMTP id a13mr21542136pgw.196.1566250698650; Mon, 19 Aug 2019 14:38:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:04 -0700 Message-Id: <20190819213755.26175-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 17/68] target/arm: Convert ERET X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Pass the T5 encoding of SUBS PC, LR, #IMM through the normal SUBS path to make it clear exactly what's happening -- we hit ALUExceptionReturn along that path. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 58 ++++++++++++++---------------------------- target/arm/a32.decode | 2 ++ target/arm/t32.decode | 8 ++++++ 3 files changed, 29 insertions(+), 39 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index f0fa5253b6..cb7b35489f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8474,6 +8474,23 @@ static bool trans_CLZ(DisasContext *s, arg_CLZ *a) return true; } =20 +static bool trans_ERET(DisasContext *s, arg_ERET *a) +{ + TCGv_i32 tmp; + + if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V7VE)) { + return false; + } + if (s->current_el =3D=3D 2) { + /* ERET from Hyp uses ELR_Hyp, not LR */ + tmp =3D load_cpu_field(elr_el[2]); + } else { + tmp =3D load_reg(s, 14); + } + gen_exception_return(s, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8768,29 +8785,10 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) case 0x4: /* crc32 */ /* All done in decodetree. Illegal ops reach here. */ goto illegal_op; - case 0x5: - /* Saturating addition and subtraction. */ + case 0x5: /* Saturating addition and subtraction. */ + case 0x6: /* ERET */ /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; - case 0x6: /* ERET */ - if (op1 !=3D 3) { - goto illegal_op; - } - if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) { - goto illegal_op; - } - if ((insn & 0x000fff0f) !=3D 0x0000000e) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - - if (s->current_el =3D=3D 2) { - tmp =3D load_cpu_field(elr_el[2]); - } else { - tmp =3D load_reg(s, 14); - } - gen_exception_return(s, tmp); - break; case 7: { int imm16 =3D extract32(insn, 0, 4) | (extract32(insn, 8, 12) = << 4); @@ -10586,24 +10584,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) case 4: /* bxj, in decodetree */ goto illegal_op; case 5: /* Exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - if (rn !=3D 14 || rd !=3D 15) { - goto illegal_op; - } - if (s->current_el =3D=3D 2) { - /* ERET from Hyp uses ELR_Hyp, not LR */ - if (insn & 0xff) { - goto illegal_op; - } - tmp =3D load_cpu_field(elr_el[2]); - } else { - tmp =3D load_reg(s, rn); - tcg_gen_subi_i32(tmp, tmp, insn & 0xff); - } - gen_exception_return(s, tmp); - break; case 6: /* MRS, in decodetree */ case 7: /* MSR, in decodetree */ goto illegal_op; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 182f2b6725..52a66dd1d5 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -211,3 +211,5 @@ BXJ .... 0001 0010 1111 1111 1111 0010 ...= . @rm BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm =20 CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm + +ERET ---- 0001 0110 0000 0000 0000 0110 1110 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 67724efe4b..6236d28b99 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -218,4 +218,12 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ..= .. @rdm MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 } BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r + { + # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as = for + # every other encoding of SUBS. With v7VE, IMM=3D0 is redefined as ER= ET. + # The distinction between the two only matters for Hyp mode. + ERET 1111 0011 1101 1110 1000 1111 0000 0000 + SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ + &s_rri_rot rot=3D0 s=3D1 rd=3D15 rn=3D14 + } } --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566251588; cv=none; d=zoho.com; s=zohoarc; b=PngcNrr8VTs9IhqNpe0XUheIPxfFX5QHPHEbbaDnMDvPdtmRBOHqQwmnWuuFNLgEpSKkWVgifYnswokq2ogboHGh2wIdHEosmGdPcBqzx/hmciFHM/VI+cBxy83dhRqGhpF9oVIi4HIVC52RHvbRPFMOZgK1QMOL3vhIMjfqk80= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566251588; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=meGInlCcNAs08b5g91xBiKJHgrSzZAc6MsZg23QrFBY=; b=n07xYvR0sJh3ZAUTCbXxySzookNiGXikU71ki1Qp7kExr2LrCsy125DuA6XTOFLqwm7akx9MhbMx+lsXDsNbvsZoQilRC6sysoC9Bu8nP0EXagUdXRzUEY3ZvapERbLgjcajEH6SCBwLelcvr4cpBtQuNvQoRRieVGYcoIw8YWM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566251588570236.7766513377817; Mon, 19 Aug 2019 14:53:08 -0700 (PDT) Received: from localhost ([::1]:59172 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpaI-0002nT-NA for importer@patchew.org; Mon, 19 Aug 2019 17:53:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58892) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpM7-0001it-3U for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpM5-0006Bc-Mf for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:22 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:43895) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpM5-0006B5-Fd for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:21 -0400 Received: by mail-pl1-x644.google.com with SMTP id 4so1583889pld.10 for ; Mon, 19 Aug 2019 14:38:21 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=meGInlCcNAs08b5g91xBiKJHgrSzZAc6MsZg23QrFBY=; b=cGOujrt0tiWOvMliBVmVSwC+8Hpw+CNrSgRshPtDFImmTj84oz1ZBmoqDzOBzMjtc2 o6rSnAxOw9xLn3bfeZJZm+857Q9SIE86aUVjxKw/VuVx2lXbDhLQJHDiat3eKWxOqROx g80Csa6aGzZVwTfEA0eMQjfdk2KqpmCzzHXWTOEw5WSXuI3jq++t0WfKzabQNVClk0Wx ntckX+nodPby1IpKAh7M5hVnv8AXCiPV35lfopqf4dcUHyOjJClw7XMIgdkBD1044J8P 1HcZEwO7exniz1u05OtoBRRyGWNnHi43zYPmacV74vYSCq7qMd4hlniADipZuNscf+jj M8eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=meGInlCcNAs08b5g91xBiKJHgrSzZAc6MsZg23QrFBY=; b=EjydBoa9XAnR8ntqs+zlaKMyn2FutarQFCInD6XkPRO0iIkoNpwUvN12cjdWxyVgWG EydCpWD/TtyOJVnPR+mIbPM0dV47WW/AUdjo6x1muF33UmjatBSgwckSvM+NgjQqpWmr umyuN9vnXSKr0g/KiKN9VWRfNJUlF3/oncGWp/Aw7EVBrTXHxnhJ78VNb2BlBkpfQoEt EJ4VXUtf5d5fwAnk79SehtREC7B6ZfLPGEXrzcUwJGFU2Ug5dkUEJBegktBGG3g9vn+7 ARQC+UyqGLO5AdDP3ElXtpUgUUzEIJon8cNwb94Rsq6cmYniIkClhdvXfMyQVKhlnc3Y Ku1g== X-Gm-Message-State: APjAAAU1jjgcThOPcRogsWrvD8fnEpAl5HDQ/fbDAxQgD+Kexb/Wj5sY BSJ79SvvFfwMJG9W7MIiW1qZboI3620= X-Google-Smtp-Source: APXvYqwzyImoDgkVc09aMLc1I8dA9Ph9GW8Zuz4sH4Rn6srb8WiS3qAEMovc9lYhAoKlgeQs+XmZHQ== X-Received: by 2002:a17:902:834c:: with SMTP id z12mr10863794pln.8.1566250700118; Mon, 19 Aug 2019 14:38:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:05 -0700 Message-Id: <20190819213755.26175-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 18/68] target/arm: Convert the rest of A32 Miscelaneous instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This fixes an exiting bug with the T5 encoding of SUBS PC, LR, #IMM, in that it may be executed from user mode as with any other encoding of SUBS, not as ERET. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 119 +++++++++++++---------------------------- target/arm/a32.decode | 8 +++ target/arm/t32.decode | 5 ++ 3 files changed, 50 insertions(+), 82 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index cb7b35489f..cb6296dc12 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8491,6 +8491,39 @@ static bool trans_ERET(DisasContext *s, arg_ERET *a) return true; } =20 +static bool trans_HLT(DisasContext *s, arg_HLT *a) +{ + gen_hlt(s, a->imm); + return true; +} + +static bool trans_BKPT(DisasContext *s, arg_BKPT *a) +{ + if (!ENABLE_ARCH_5) { + return false; + } + gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); + return true; +} + +static bool trans_HVC(DisasContext *s, arg_HVC *a) +{ + if (!ENABLE_ARCH_7 || IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_hvc(s, a->imm); + return true; +} + +static bool trans_SMC(DisasContext *s, arg_SMC *a) +{ + if (!ENABLE_ARCH_6K || IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M))= { + return false; + } + gen_smc(s); + return true; +} + /* * Legacy decoder. */ @@ -8771,68 +8804,8 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) } else if ((insn & 0x0f900000) =3D=3D 0x01000000 && (insn & 0x00000090) !=3D 0x00000090) { /* miscellaneous instructions */ - op1 =3D (insn >> 21) & 3; - sh =3D (insn >> 4) & 0xf; - rm =3D insn & 0xf; - switch (sh) { - case 0x0: - /* MSR/MRS (banked/register) */ - /* All done in decodetree. Illegal ops already signalled. */ - g_assert_not_reached(); - case 0x1: /* bx, clz */ - case 0x2: /* bxj */ - case 0x3: /* blx */ - case 0x4: /* crc32 */ - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - case 0x5: /* Saturating addition and subtraction. */ - case 0x6: /* ERET */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - case 7: - { - int imm16 =3D extract32(insn, 0, 4) | (extract32(insn, 8, 12) = << 4); - switch (op1) { - case 0: - /* HLT */ - gen_hlt(s, imm16); - break; - case 1: - /* bkpt */ - ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false)); - break; - case 2: - /* Hypervisor call (v7) */ - ARCH(7); - if (IS_USER(s)) { - goto illegal_op; - } - gen_hvc(s, imm16); - break; - case 3: - /* Secure monitor call (v6+) */ - ARCH(6K); - if (IS_USER(s)) { - goto illegal_op; - } - gen_smc(s); - break; - default: - g_assert_not_reached(); - } - break; - } - case 0x8: - case 0xa: - case 0xc: - case 0xe: - /* Halfword multiply and multiply accumulate. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - default: - goto illegal_op; - } + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; } else if (((insn & 0x0e000000) =3D=3D 0 && (insn & 0x00000090) !=3D 0x90) || ((insn & 0x0e000000) =3D=3D (1 << 25))) { @@ -10493,26 +10466,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) goto illegal_op; =20 if (insn & (1 << 26)) { - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - if (!(insn & (1 << 20))) { - /* Hypervisor call (v7) */ - int imm16 =3D extract32(insn, 16, 4) << 12 - | extract32(insn, 0, 12); - ARCH(7); - if (IS_USER(s)) { - goto illegal_op; - } - gen_hvc(s, imm16); - } else { - /* Secure monitor call (v6+) */ - ARCH(6K); - if (IS_USER(s)) { - goto illegal_op; - } - gen_smc(s); - } + /* hvc, smc, in decodetree */ + goto illegal_op; } else { op =3D (insn >> 20) & 7; switch (op) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 52a66dd1d5..c7f156be6d 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -31,6 +31,7 @@ &rrr rd rn rm &rr rd rm &r rm +&i imm &msr_reg rn r mask &mrs_reg rd r &msr_bank rn r sysm @@ -196,9 +197,11 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 ..= .. @rndm # Miscellaneous instructions =20 %sysm 8:1 16:4 +%imm16_8_0 8:12 0:4 =20 @rm ---- .... .... .... .... .... .... rm:4 &r @rdm ---- .... .... .... rd:4 .... .... rm:4 &rr +@i16 ---- .... .... .... .... .... .... .... &i imm=3D%im= m16_8_0 =20 MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %s= ysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %s= ysm @@ -213,3 +216,8 @@ BLX_r .... 0001 0010 1111 1111 1111 0011 ...= . @rm CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm =20 ERET ---- 0001 0110 0000 0000 0000 0110 1110 + +HLT .... 0001 0000 .... .... .... 0111 .... @i16 +BKPT .... 0001 0010 .... .... .... 0111 .... @i16 +HVC .... 0001 0100 .... .... .... 0111 .... @i16 +SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 6236d28b99..5116c6165a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -28,6 +28,7 @@ &rrr !extern rd rn rm &rr !extern rd rm &r !extern rm +&i !extern imm &msr_reg !extern rn r mask &mrs_reg !extern rd r &msr_bank !extern rn r sysm @@ -189,6 +190,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ...= . @rdm =20 %msr_sysm 4:1 8:4 %mrs_sysm 4:1 16:4 +%imm16_16_0 16:4 0:12 =20 { { @@ -226,4 +228,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ...= . @rdm SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ &s_rri_rot rot=3D0 s=3D1 rd=3D15 rn=3D14 } + SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i + HVC 1111 0111 1110 .... 1000 .... .... .... \ + &i imm=3D%imm16_16_0 } --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lmni/76O+knM0gbFh8KJGT9HS18kVAz/Vke5rjDhrnk=; b=hCX45omn7zmvTg4bYLt5wK3G4l7dfL2jPcgj+kXHf97Kyb9DpZ27nhjvkAhBGgOwPI vYc3HvxNaMhHHLRGBANezEMGtlPfTEibk2+VpxP7C5dmxkXWYty7v95a+CicdSgYTg9y Gm3X1bJ1Em/YpbwVjWpRsbdsQua/dK5LRXl3qLbHwvtdn8ebEizXiRemV71jt+6L0jm/ vmNDL+/Fk00mc7kqoY1FBVHv9NJEzR37Fq7LyFC1qcNDUQWKvcmXq35iSnxacRJWoCCX dU+Iu0PiK7oCegktiMExarNnSkS0Cda+wCGEpG4tgyxgKFR0VRAi2kwqYWBVSAL7+H2l HdGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lmni/76O+knM0gbFh8KJGT9HS18kVAz/Vke5rjDhrnk=; b=qZa3JHgk9PauIcDrM/+4tKZoft0RXChJhig5YYO9m2AVoe9lQqTQeWOe2b7wTVFdrL ldL8Le1Opa5Dxg2bIbm+3bmUbtEovvw72NQM89AYnXo62QTfR8YqJaOs5AGsGapLMB+G /+W9d/EevN5DXJ4vrJ65t6VntpLcecNUzfGcBd2oPrQBNe4BEbEmjrPfnPlB0E+1hBHr B7riFiMcLhETuPRp40AOZYlXr64HYhzyfYEzXB0h39lkt3n8h0RG+lcxK0D0nrrYpz+c hUxXWSRtmNqRXx8Vmd0pTTDdH1Oa6qwkJoR19P6vOaXtgz00HIIhpB857vSvFAEWXjGW ekJA== X-Gm-Message-State: APjAAAVTgtWazY/uODgKg3FMDzSfZcWKuRfUo0so5vvX5+Dvwvf8Nff8 CSzxYJsZSnZvwOxupoPwRGc84Eu0rPg= X-Google-Smtp-Source: APXvYqw9km7sGN/s6NKIjv2ZO6bCIC75wjGZg4hnLbngU3sltuy0myisS9LtL9od2YTjUk4L5g80HQ== X-Received: by 2002:a63:b64:: with SMTP id a36mr22296590pgl.215.1566250701387; Mon, 19 Aug 2019 14:38:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:06 -0700 Message-Id: <20190819213755.26175-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 19/68] target/arm: Convert T32 ADDW/SUBW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 24 +++++++++++++----------- target/arm/a32.decode | 1 + target/arm/t32.decode | 19 +++++++++++++++++++ 3 files changed, 33 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index cb6296dc12..0e51289928 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7626,6 +7626,11 @@ static void arm_skip_unless(DisasContext *s, uint32_= t cond) * Constant expanders for the decoders. */ =20 +static int negate(DisasContext *s, int x) +{ + return -x; +} + static int times_2(DisasContext *s, int x) { return x * 2; @@ -7975,6 +7980,12 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rri= _rot *a) #undef DO_ANY2 #undef DO_CMP2 =20 +static bool trans_ADR(DisasContext *s, arg_ri *a) +{ + store_reg_bx(s, a->rd, add_reg_for_lit(s, 15, a->imm)); + return true; +} + /* * Multiply and multiply accumulate */ @@ -10670,17 +10681,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } store_reg(s, rd, tmp); } else { - /* Add/sub 12-bit immediate. */ - if (insn & (1 << 23)) { - imm =3D -imm; - } - tmp =3D add_reg_for_lit(s, rn, imm); - if (rn =3D=3D 13 && rd =3D=3D 13) { - /* ADD SP, SP, imm or SUB SP, SP, imm */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } + /* Add/sub 12-bit immediate, in decodetree */ + goto illegal_op; } } } else { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index c7f156be6d..aac991664d 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -30,6 +30,7 @@ &rrrr rd rn rm ra &rrr rd rn rm &rr rd rm +&ri rd imm &r rm &i imm &msr_reg rn r mask diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 5116c6165a..be4e5f087c 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -27,6 +27,7 @@ &rrrr !extern rd rn rm ra &rrr !extern rd rn rm &rr !extern rd rm +&ri !extern rd imm &r !extern rm &i !extern imm &msr_reg !extern rn r mask @@ -121,6 +122,24 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... .....= ... @s_rri_rot } RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot =20 +# Data processing (plain binary immediate) + +%imm12_26_12_0 26:1 12:3 0:8 +%neg12_26_12_0 26:1 12:3 0:8 !function=3Dnegate +@s0_rri_12 .... ... .... . rn:4 . ... rd:4 ........ \ + &s_rri_rot imm=3D%imm12_26_12_0 rot=3D0 s=3D0 + +{ + ADR 1111 0.1 0000 0 1111 0 ... rd:4 ........ \ + &ri imm=3D%imm12_26_12_0 + ADD_rri 1111 0.1 0000 0 .... 0 ... .... ........ @s0_rri_12 +} +{ + ADR 1111 0.1 0101 0 1111 0 ... rd:4 ........ \ + &ri imm=3D%neg12_26_12_0 + SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 +} + # Multiply and multiply accumulate =20 @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ItuDBnfuLwArEWzLn7WSrEMHT0kiRIq2FCIlqwgPOVw=; b=tmr0XUomXySEarMa0Gf/5BgiBgJ8PAvVA2if3IedgEIRy8HzSk8AMq626XzQt69JE9 35nWwyOefZi/pgh4mWlyU38YDvB0eXyRk8/RRsGBM2vJqAUSPDk1Zoz+ep3h+S/+czsZ HuLAdrJPHVSW0UcVi4s4GScxiOkfXTMAZ4ylq7uwIbtT/IB0gemPzTsu72oXQmIpb8rS 1qqdibKiMw4mJzRBlMd/LPkIiwCs8GA1/17/fxNtT4skLcDpKkkZVwgxUFKQbtjf6WvK H9/R+pB6uvCRzvf0wsEH36rpjL/W2p+n55wKEKyXwEeVSmfBuSIxqD61eFkeLetnCDvr aJjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ItuDBnfuLwArEWzLn7WSrEMHT0kiRIq2FCIlqwgPOVw=; b=qNSrc5VoVAy4LLe6yaqSoZdRkMJfI8FfgYXH2DldgmzorxOlOsrBaLnoGmblpNfV/0 jUZgGDN3FyvhUrrTmJNfo4WOh/BtMi6ohPKw33Rivttrl6bCQkvY0e+2kYQw/8wpmnYg FB9122PgMCWdJhI5xCVCRQO/8u+Ickv/md2VjvSS1ZyHtInXfMZA0+3DlTYLPPpFk1KM N0Yo5ve9eewD6m5pRP9srT+gzJrscwhLDqlEBu/9Jk35ixEZNECqLPEgwGwDxMq7fvRU ioNJY3P8vqVGyJTxxaduXnEfnGiVTfVes5DEl/ZRfbScq8/OfvhcFVMRqDHUPHNIGtzW vqlg== X-Gm-Message-State: APjAAAX69SpgXwnn9qPrvke+ORF/vYjUPiHekIMA2uMnZWOr7rorIbbS 9bfPpHn7OE7BKLR67/aRmCDI1j6z5uk= X-Google-Smtp-Source: APXvYqw8t6jnYAJ4dkwXCRTTl7agS/ZI3GUuYzuhDs6gjT5CoesaFXSsR4i9kM1yMJcVviyTVZe+eA== X-Received: by 2002:a17:902:7c12:: with SMTP id x18mr25108602pll.123.1566250702667; Mon, 19 Aug 2019 14:38:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:07 -0700 Message-Id: <20190819213755.26175-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 20/68] target/arm: Convert load/store (register, immediate, literal) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 797 ++++++++++++++++++----------------------- target/arm/a32.decode | 120 +++++++ target/arm/t32.decode | 141 ++++++++ 3 files changed, 615 insertions(+), 443 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0e51289928..f7c4db872c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1246,62 +1246,6 @@ static inline void gen_hlt(DisasContext *s, int imm) unallocated_encoding(s); } =20 -static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, - TCGv_i32 var) -{ - int val, rm, shift, shiftop; - TCGv_i32 offset; - - if (!(insn & (1 << 25))) { - /* immediate */ - val =3D insn & 0xfff; - if (!(insn & (1 << 23))) - val =3D -val; - if (val !=3D 0) - tcg_gen_addi_i32(var, var, val); - } else { - /* shift/register */ - rm =3D (insn) & 0xf; - shift =3D (insn >> 7) & 0x1f; - shiftop =3D (insn >> 5) & 3; - offset =3D load_reg(s, rm); - gen_arm_shift_im(offset, shiftop, shift, 0); - if (!(insn & (1 << 23))) - tcg_gen_sub_i32(var, var, offset); - else - tcg_gen_add_i32(var, var, offset); - tcg_temp_free_i32(offset); - } -} - -static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn, - int extra, TCGv_i32 var) -{ - int val, rm; - TCGv_i32 offset; - - if (insn & (1 << 22)) { - /* immediate */ - val =3D (insn & 0xf) | ((insn >> 4) & 0xf0); - if (!(insn & (1 << 23))) - val =3D -val; - val +=3D extra; - if (val !=3D 0) - tcg_gen_addi_i32(var, var, val); - } else { - /* register */ - if (extra) - tcg_gen_addi_i32(var, var, extra); - rm =3D (insn) & 0xf; - offset =3D load_reg(s, rm); - if (!(insn & (1 << 23))) - tcg_gen_sub_i32(var, var, offset); - else - tcg_gen_add_i32(var, var, offset); - tcg_temp_free_i32(offset); - } -} - static TCGv_ptr get_fpstatus_ptr(int neon) { TCGv_ptr statusptr =3D tcg_temp_new_ptr(); @@ -7636,6 +7580,11 @@ static int times_2(DisasContext *s, int x) return x * 2; } =20 +static int times_4(DisasContext *s, int x) +{ + return x * 4; +} + /* Return only the rotation part of T32ExpandImm. */ static int t32_expandimm_rot(DisasContext *s, int x) { @@ -8535,6 +8484,345 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a) return true; } =20 +/* + * Load/store register index + */ + +static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w) +{ + ISSInfo ret; + + /* ISS not valid if writeback */ + if (p && !w) { + ret =3D rd; + } else { + ret =3D ISSInvalid; + } + return ret; +} + +static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a) +{ + TCGv_i32 addr =3D load_reg(s, a->rn); + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + if (a->p) { + TCGv_i32 ofs =3D load_reg(s, a->rm); + gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); + if (a->u) { + tcg_gen_add_i32(addr, addr, ofs); + } else { + tcg_gen_sub_i32(addr, addr, ofs); + } + tcg_temp_free_i32(ofs); + } + return addr; +} + +static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a, + TCGv_i32 addr, int address_offset) +{ + if (!a->p) { + TCGv_i32 ofs =3D load_reg(s, a->rm); + gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); + if (a->u) { + tcg_gen_add_i32(addr, addr, ofs); + } else { + tcg_gen_sub_i32(addr, addr, ofs); + } + tcg_temp_free_i32(ofs); + } else if (!a->w) { + tcg_temp_free_i32(addr); + return; + } + tcg_gen_addi_i32(addr, addr, address_offset); + store_reg(s, a->rn, addr); +} + +static bool op_load_rr(DisasContext *s, arg_ldst_rr *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo =3D make_issinfo(s, a->rt, a->p, a->w); + TCGv_i32 addr, tmp; + + addr =3D op_addr_rr_pre(s, a); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + + /* + * Perform base writeback before the loaded value to + * ensure correct behavior with overlapping index registers. + */ + op_addr_rr_post(s, a, addr, 0); + store_reg_from_load(s, a->rt, tmp); + return true; +} + +static bool op_store_rr(DisasContext *s, arg_ldst_rr *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo =3D make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; + TCGv_i32 addr, tmp; + + addr =3D op_addr_rr_pre(s, a); + + tmp =3D load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + tcg_temp_free_i32(tmp); + + op_addr_rr_post(s, a, addr, 0); + return true; +} + +static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) +{ + int mem_idx =3D get_mem_index(s); + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + addr =3D op_addr_rr_pre(s, a); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt, tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt + 1, tmp); + + /* LDRD w/ base writeback is undefined if the registers overlap. */ + op_addr_rr_post(s, a, addr, -4); + return true; +} + +static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) +{ + int mem_idx =3D get_mem_index(s); + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + addr =3D op_addr_rr_pre(s, a); + + tmp =3D load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp =3D load_reg(s, a->rt + 1); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + op_addr_rr_post(s, a, addr, -4); + return true; +} + +/* + * Load/store immediate index + */ + +static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a) +{ + int ofs =3D a->imm; + + if (!a->u) { + ofs =3D -ofs; + } + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + /* + * Stackcheck. Here we know 'addr' is the current SP; + * U is set if we're moving SP up, else down. It is + * UNKNOWN whether the limit check triggers when SP starts + * below the limit and ends up above it; we chose to do so. + */ + if (!a->u) { + TCGv_i32 newsp =3D tcg_temp_new_i32(); + tcg_gen_addi_i32(newsp, cpu_R[13], ofs); + gen_helper_v8m_stackcheck(cpu_env, newsp); + tcg_temp_free_i32(newsp); + } else { + gen_helper_v8m_stackcheck(cpu_env, cpu_R[13]); + } + } + + return add_reg_for_lit(s, a->rn, a->p ? ofs : 0); +} + +static void op_addr_ri_post(DisasContext *s, arg_ldst_ri *a, + TCGv_i32 addr, int address_offset) +{ + if (!a->p) { + if (a->u) { + address_offset +=3D a->imm; + } else { + address_offset -=3D a->imm; + } + } else if (!a->w) { + tcg_temp_free_i32(addr); + return; + } + tcg_gen_addi_i32(addr, addr, address_offset); + store_reg(s, a->rn, addr); +} + +static bool op_load_ri(DisasContext *s, arg_ldst_ri *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo =3D make_issinfo(s, a->rt, a->p, a->w); + TCGv_i32 addr, tmp; + + addr =3D op_addr_ri_pre(s, a); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + + /* + * Perform base writeback before the loaded value to + * ensure correct behavior with overlapping index registers. + */ + op_addr_ri_post(s, a, addr, 0); + store_reg_from_load(s, a->rt, tmp); + return true; +} + +static bool op_store_ri(DisasContext *s, arg_ldst_ri *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo =3D make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; + TCGv_i32 addr, tmp; + + addr =3D op_addr_ri_pre(s, a); + + tmp =3D load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + tcg_temp_free_i32(tmp); + + op_addr_ri_post(s, a, addr, 0); + return true; +} + +static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) +{ + int mem_idx =3D get_mem_index(s); + TCGv_i32 addr, tmp; + + addr =3D op_addr_ri_pre(s, a); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt, tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, rt2, tmp); + + /* LDRD w/ base writeback is undefined if the registers overlap. */ + op_addr_ri_post(s, a, addr, -4); + return true; +} + +static bool trans_LDRD_ri_a32(DisasContext *s, arg_ldst_ri *a) +{ + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + return op_ldrd_ri(s, a, a->rt + 1); +} + +static bool trans_LDRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) +{ + arg_ldst_ri b =3D { + .u =3D a->u, .w =3D a->w, .p =3D a->p, + .rn =3D a->rn, .rt =3D a->rt, .imm =3D a->imm + }; + return op_ldrd_ri(s, &b, a->rt2); +} + +static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) +{ + int mem_idx =3D get_mem_index(s); + TCGv_i32 addr, tmp; + + addr =3D op_addr_ri_pre(s, a); + + tmp =3D load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp =3D load_reg(s, rt2); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + op_addr_ri_post(s, a, addr, -4); + return true; +} + +static bool trans_STRD_ri_a32(DisasContext *s, arg_ldst_ri *a) +{ + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + return op_strd_ri(s, a, a->rt + 1); +} + +static bool trans_STRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) +{ + arg_ldst_ri b =3D { + .u =3D a->u, .w =3D a->w, .p =3D a->p, + .rn =3D a->rn, .rt =3D a->rt, .imm =3D a->imm + }; + return op_strd_ri(s, &b, a->rt2); +} + +#define DO_LDST(NAME, WHICH, MEMOP) \ +static bool trans_##NAME##_ri(DisasContext *s, arg_ldst_ri *a) \ +{ \ + return op_##WHICH##_ri(s, a, MEMOP, get_mem_index(s)); \ +} \ +static bool trans_##NAME##T_ri(DisasContext *s, arg_ldst_ri *a) \ +{ \ + return op_##WHICH##_ri(s, a, MEMOP, get_a32_user_mem_index(s)); \ +} \ +static bool trans_##NAME##_rr(DisasContext *s, arg_ldst_rr *a) \ +{ \ + return op_##WHICH##_rr(s, a, MEMOP, get_mem_index(s)); \ +} \ +static bool trans_##NAME##T_rr(DisasContext *s, arg_ldst_rr *a) \ +{ \ + return op_##WHICH##_rr(s, a, MEMOP, get_a32_user_mem_index(s)); \ +} + +DO_LDST(LDR, load, MO_UL) +DO_LDST(LDRB, load, MO_UB) +DO_LDST(LDRH, load, MO_UW) +DO_LDST(LDRSB, load, MO_SB) +DO_LDST(LDRSH, load, MO_SW) + +DO_LDST(STR, store, MO_UL) +DO_LDST(STRB, store, MO_UB) +DO_LDST(STRH, store, MO_UW) + +#undef DO_LDST + /* * Legacy decoder. */ @@ -8992,100 +9280,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) } } } else { - int address_offset; - bool load =3D insn & (1 << 20); - bool wbit =3D insn & (1 << 21); - bool pbit =3D insn & (1 << 24); - bool doubleword =3D false; - ISSInfo issinfo; - - /* Misc load/store */ - rn =3D (insn >> 16) & 0xf; - rd =3D (insn >> 12) & 0xf; - - /* ISS not valid if writeback */ - issinfo =3D (pbit & !wbit) ? rd : ISSInvalid; - - if (!load && (sh & 2)) { - /* doubleword */ - ARCH(5TE); - if (rd & 1) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - load =3D (sh & 1) =3D=3D 0; - doubleword =3D true; - } - - addr =3D load_reg(s, rn); - if (pbit) { - gen_add_datah_offset(s, insn, 0, addr); - } - address_offset =3D 0; - - if (doubleword) { - if (!load) { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp =3D load_reg(s, rd + 1); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } else { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - rd++; - } - address_offset =3D -4; - } else if (load) { - /* load */ - tmp =3D tcg_temp_new_i32(); - switch (sh) { - case 1: - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - case 2: - gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - default: - case 3: - gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - } - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issi= nfo); - tcg_temp_free_i32(tmp); - } - /* Perform base writeback before the loaded value to - ensure correct behavior with overlapping index register= s. - ldrd with base writeback is undefined if the - destination and index registers overlap. */ - if (!pbit) { - gen_add_datah_offset(s, insn, address_offset, addr); - store_reg(s, rn, addr); - } else if (wbit) { - if (address_offset) - tcg_gen_addi_i32(addr, addr, address_offset); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - if (load) { - /* Complete the load. */ - store_reg(s, rd, tmp); - } + /* Extra load/store (register) instructions */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } break; case 0x4: @@ -9393,58 +9590,8 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) break; } do_ldst: - /* Check for undefined extension instructions - * per the ARM Bible IE: - * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx - */ - sh =3D (0xf << 20) | (0xf << 4); - if (op1 =3D=3D 0x7 && ((insn & sh) =3D=3D sh)) - { - goto illegal_op; - } - /* load/store byte/word */ - rn =3D (insn >> 16) & 0xf; - rd =3D (insn >> 12) & 0xf; - tmp2 =3D load_reg(s, rn); - if ((insn & 0x01200000) =3D=3D 0x00200000) { - /* ldrt/strt */ - i =3D get_a32_user_mem_index(s); - } else { - i =3D get_mem_index(s); - } - if (insn & (1 << 24)) - gen_add_data_offset(s, insn, tmp2); - if (insn & (1 << 20)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - if (insn & (1 << 22)) { - gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd); - } else { - gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd); - } - } else { - /* store */ - tmp =3D load_reg(s, rd); - if (insn & (1 << 22)) { - gen_aa32_st8_iss(s, tmp, tmp2, i, rd); - } else { - gen_aa32_st32_iss(s, tmp, tmp2, i, rd); - } - tcg_temp_free_i32(tmp); - } - if (!(insn & (1 << 24))) { - gen_add_data_offset(s, insn, tmp2); - store_reg(s, rn, tmp2); - } else if (insn & (1 << 21)) { - store_reg(s, rn, tmp2); - } else { - tcg_temp_free_i32(tmp2); - } - if (insn & (1 << 20)) { - /* Complete the load. */ - store_reg_from_load(s, rd, tmp); - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0x08: case 0x09: { @@ -9748,75 +9895,8 @@ static void disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) s->condexec_mask =3D 0; } } else if (insn & 0x01200000) { - /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (post-indexed) - * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (literal and immediate) - * 0b1111_1001_x11x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (pre-indexed) - */ - bool wback =3D extract32(insn, 21, 1); - - if (rn =3D=3D 15 && (insn & (1 << 21))) { - /* UNPREDICTABLE */ - goto illegal_op; - } - - addr =3D add_reg_for_lit(s, rn, 0); - offset =3D (insn & 0xff) * 4; - if ((insn & (1 << 23)) =3D=3D 0) { - offset =3D -offset; - } - - if (s->v8m_stackcheck && rn =3D=3D 13 && wback) { - /* - * Here 'addr' is the current SP; if offset is +ve we'= re - * moving SP up, else down. It is UNKNOWN whether the = limit - * check triggers when SP starts below the limit and e= nds - * up above it; check whichever of the current and fin= al - * SP is lower, so QEMU will trigger in that situation. - */ - if ((int32_t)offset < 0) { - TCGv_i32 newsp =3D tcg_temp_new_i32(); - - tcg_gen_addi_i32(newsp, addr, offset); - gen_helper_v8m_stackcheck(cpu_env, newsp); - tcg_temp_free_i32(newsp); - } else { - gen_helper_v8m_stackcheck(cpu_env, addr); - } - } - - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, offset); - offset =3D 0; - } - if (insn & (1 << 20)) { - /* ldrd */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rs, tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - } else { - /* strd */ - tmp =3D load_reg(s, rs); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp =3D load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - if (wback) { - /* Base writeback. */ - tcg_gen_addi_i32(addr, addr, offset - 4); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } + /* load/store dual, in decodetree */ + goto illegal_op; } else if ((insn & (1 << 23)) =3D=3D 0) { /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx * - load/store exclusive word @@ -10692,184 +10772,15 @@ static void disas_thumb2_insn(DisasContext *s, u= int32_t insn) } } break; - case 12: /* Load/store single data item. */ - { - int postinc =3D 0; - int writeback =3D 0; - int memidx; - ISSInfo issinfo; - + case 12: if ((insn & 0x01100000) =3D=3D 0x01000000) { if (disas_neon_ls_insn(s, insn)) { goto illegal_op; } break; } - op =3D ((insn >> 21) & 3) | ((insn >> 22) & 4); - if (rs =3D=3D 15) { - if (!(insn & (1 << 20))) { - goto illegal_op; - } - if (op !=3D 2) { - /* Byte or halfword load space with dest =3D=3D r15 : memo= ry hints. - * Catch them early so we don't emit pointless addressing = code. - * This space is a mix of: - * PLD/PLDW/PLI, which we implement as NOPs (note that u= nlike - * the ARM encodings, PLDW space doesn't UNDEF for non= -v7MP - * cores) - * unallocated hints, which must be treated as NOPs - * UNPREDICTABLE space, which we NOP or UNDEF depending on - * which is easiest for the decoding logic - * Some space which must UNDEF - */ - int op1 =3D (insn >> 23) & 3; - int op2 =3D (insn >> 6) & 0x3f; - if (op & 2) { - goto illegal_op; - } - if (rn =3D=3D 15) { - /* UNPREDICTABLE, unallocated hint or - * PLD/PLDW/PLI (literal) - */ - return; - } - if (op1 & 1) { - return; /* PLD/PLDW/PLI or unallocated hint */ - } - if ((op2 =3D=3D 0) || ((op2 & 0x3c) =3D=3D 0x30)) { - return; /* PLD/PLDW/PLI or unallocated hint */ - } - /* UNDEF space, or an UNPREDICTABLE */ - goto illegal_op; - } - } - memidx =3D get_mem_index(s); - imm =3D insn & 0xfff; - if (insn & (1 << 23)) { - /* PC relative or Positive offset. */ - addr =3D add_reg_for_lit(s, rn, imm); - } else if (rn =3D=3D 15) { - /* PC relative with negative offset. */ - addr =3D add_reg_for_lit(s, rn, -imm); - } else { - addr =3D load_reg(s, rn); - imm =3D insn & 0xff; - switch ((insn >> 8) & 0xf) { - case 0x0: /* Shifted Register. */ - shift =3D (insn >> 4) & 0xf; - if (shift > 3) { - tcg_temp_free_i32(addr); - goto illegal_op; - } - tmp =3D load_reg(s, rm); - tcg_gen_shli_i32(tmp, tmp, shift); - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - break; - case 0xc: /* Negative offset. */ - tcg_gen_addi_i32(addr, addr, -imm); - break; - case 0xe: /* User privilege. */ - tcg_gen_addi_i32(addr, addr, imm); - memidx =3D get_a32_user_mem_index(s); - break; - case 0x9: /* Post-decrement. */ - imm =3D -imm; - /* Fall through. */ - case 0xb: /* Post-increment. */ - postinc =3D 1; - writeback =3D 1; - break; - case 0xd: /* Pre-decrement. */ - imm =3D -imm; - /* Fall through. */ - case 0xf: /* Pre-increment. */ - writeback =3D 1; - break; - default: - tcg_temp_free_i32(addr); - goto illegal_op; - } - } - - issinfo =3D writeback ? ISSInvalid : rs; - - if (s->v8m_stackcheck && rn =3D=3D 13 && writeback) { - /* - * Stackcheck. Here we know 'addr' is the current SP; - * if imm is +ve we're moving SP up, else down. It is - * UNKNOWN whether the limit check triggers when SP starts - * below the limit and ends up above it; we chose to do so. - */ - if ((int32_t)imm < 0) { - TCGv_i32 newsp =3D tcg_temp_new_i32(); - - tcg_gen_addi_i32(newsp, addr, imm); - gen_helper_v8m_stackcheck(cpu_env, newsp); - tcg_temp_free_i32(newsp); - } else { - gen_helper_v8m_stackcheck(cpu_env, addr); - } - } - - if (writeback && !postinc) { - tcg_gen_addi_i32(addr, addr, imm); - } - - if (insn & (1 << 20)) { - /* Load. */ - tmp =3D tcg_temp_new_i32(); - switch (op) { - case 0: - gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo); - break; - case 4: - gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo); - break; - case 1: - gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo); - break; - case 5: - gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo); - break; - case 2: - gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo); - break; - default: - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - goto illegal_op; - } - store_reg_from_load(s, rs, tmp); - } else { - /* Store. */ - tmp =3D load_reg(s, rs); - switch (op) { - case 0: - gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo); - break; - case 1: - gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo); - break; - case 2: - gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo); - break; - default: - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - goto illegal_op; - } - tcg_temp_free_i32(tmp); - } - if (postinc) - tcg_gen_addi_i32(addr, addr, imm); - if (writeback) { - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - } - break; + /* Load/store single data item, in decodetree */ + goto illegal_op; default: goto illegal_op; } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index aac991664d..f7742deaee 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -37,6 +37,8 @@ &mrs_reg rd r &msr_bank rn r sysm &mrs_bank rd r sysm +&ldst_rr p w u rn rt rm shimm shtype +&ldst_ri p w u rn rt imm =20 # Data-processing (register) =20 @@ -222,3 +224,121 @@ HLT .... 0001 0000 .... .... .... 0111 .= ... @i16 BKPT .... 0001 0010 .... .... .... 0111 .... @i16 HVC .... 0001 0100 .... .... .... 0111 .... @i16 SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i + +# Load/Store Dual, Half, Signed Byte (register) + +@ldst_rr_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=3D1 shimm=3D0 shtype=3D0 +@ldst_rr_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=3D0 w=3D0 shimm=3D0 shtype=3D0 + +STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_pw0 +STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p1w + +LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_pw0 +LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_p1w + +STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_pw0 +STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_p1w + +LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_pw0 +LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p1w + +LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_pw0 +LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p1w + +LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_pw0 +LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p1w + +# Note the unpriv load/stores use the previously invalid P=3D0, W=3D1 enco= ding, +# and act as normal post-indexed (P=3D0, W=3D0). +@ldst_rr_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=3D0 w=3D0 shimm=3D0 shtype=3D0 + +STRHT_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p0w1 +LDRHT_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p0w1 +LDRSBT_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p0w1 +LDRSHT_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p0w1 + +# Load/Store word and unsigned byte (register) + +@ldst_rs_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=3D1 +@ldst_rs_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=3D0 w=3D0 + +STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_pw0 +STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p1w +STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_pw0 +STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p1w + +LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_pw0 +LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p1w +LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_pw0 +LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p1w + +@ldst_rs_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=3D0 w=3D0 + +STRT_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p0w1 +STRBT_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p0w1 +LDRT_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p0w1 +LDRBT_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p0w1 + +# Load/Store Dual, Half, Signed Byte (immediate) + +%imm8s_8_0 8:4 0:4 +@ldst_ri8_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=3D%imm8s_8_0 p=3D1 +@ldst_ri8_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=3D%imm8s_8_0 p=3D0 w=3D0 + +STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_pw0 +STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p1w + +LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_pw0 +LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_p1w + +STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_pw0 +STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_p1w + +LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_pw0 +LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p1w + +LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_pw0 +LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p1w + +LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_pw0 +LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p1w + +# Note the unpriv load/stores use the previously invalid P=3D0, W=3D1 enco= ding, +# and act as normal post-indexed (P=3D0, W=3D0). +@ldst_ri8_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=3D%imm8s_8_0 p=3D0 w=3D0 + +STRHT_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p0= w1 +LDRHT_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p0= w1 +LDRSBT_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p0= w1 +LDRSHT_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p0= w1 + +# Load/Store word and unsigned byte (immediate) + +@ldst_ri12_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 imm:12 &ldst_ri p= =3D1 +@ldst_ri12_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 imm:12 &ldst_ri p= =3D0 w=3D0 + +STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p= 1w +STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p= w0 +STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p= 1w +STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p= w0 + +LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p= 1w +LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p= w0 +LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p= 1w +LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p= w0 + +@ldst_ri12_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 imm:12 &ldst_ri p= =3D0 w=3D0 + +STRT_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p= 0w1 +STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p= 0w1 +LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p= 0w1 +LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p= 0w1 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index be4e5f087c..a86597562b 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -34,6 +34,8 @@ &mrs_reg !extern rd r &msr_bank !extern rn r sysm &mrs_bank !extern rd r sysm +&ldst_rr !extern p w u rn rt rm shimm shtype +&ldst_ri !extern p w u rn rt imm =20 # Data-processing (register) =20 @@ -251,3 +253,142 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .= ... @rdm HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=3D%imm16_16_0 } + +# Load/store (register, immediate, literal) + +@ldst_rr .... .... .... rn:4 rt:4 ...... shimm:2 rm:4 \ + &ldst_rr p=3D1 w=3D0 u=3D1 shtype=3D0 +@ldst_ri_idx .... .... .... rn:4 rt:4 . p:1 u:1 . imm:8 \ + &ldst_ri w=3D1 +@ldst_ri_neg .... .... .... rn:4 rt:4 .... imm:8 \ + &ldst_ri p=3D1 w=3D0 u=3D0 +@ldst_ri_unp .... .... .... rn:4 rt:4 .... imm:8 \ + &ldst_ri p=3D1 w=3D0 u=3D1 +@ldst_ri_pos .... .... .... rn:4 rt:4 imm:12 \ + &ldst_ri p=3D1 w=3D0 u=3D1 +@ldst_ri_lit .... .... u:1 ... .... rt:4 imm:12 \ + &ldst_ri p=3D1 w=3D0 rn=3D15 + +STRB_rr 1111 1000 0000 .... .... 000000 .. .... @ldst_rr +STRB_ri 1111 1000 0000 .... .... 1..1 ........ @ldst_ri_idx +STRB_ri 1111 1000 0000 .... .... 1100 ........ @ldst_ri_neg +STRBT_ri 1111 1000 0000 .... .... 1110 ........ @ldst_ri_unp +STRB_ri 1111 1000 1000 .... .... ............ @ldst_ri_pos + +STRH_rr 1111 1000 0010 .... .... 000000 .. .... @ldst_rr +STRH_ri 1111 1000 0010 .... .... 1..1 ........ @ldst_ri_idx +STRH_ri 1111 1000 0010 .... .... 1100 ........ @ldst_ri_neg +STRHT_ri 1111 1000 0010 .... .... 1110 ........ @ldst_ri_unp +STRH_ri 1111 1000 1010 .... .... ............ @ldst_ri_pos + +STR_rr 1111 1000 0100 .... .... 000000 .. .... @ldst_rr +STR_ri 1111 1000 0100 .... .... 1..1 ........ @ldst_ri_idx +STR_ri 1111 1000 0100 .... .... 1100 ........ @ldst_ri_neg +STRT_ri 1111 1000 0100 .... .... 1110 ........ @ldst_ri_unp +STR_ri 1111 1000 1100 .... .... ............ @ldst_ri_pos + +# Note that Load, unsigned (literal) overlaps all other load encodings. +{ + { + NOP 1111 1000 -001 1111 1111 ------------ # PLD + LDRB_ri 1111 1000 .001 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1000 1001 ---- 1111 ------------ # PLD + LDRB_ri 1111 1000 1001 .... .... ............ @ldst_ri_pos + } + LDRB_ri 1111 1000 0001 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1000 0001 ---- 1111 1100 -------- # PLD + LDRB_ri 1111 1000 0001 .... .... 1100 ........ @ldst_ri_neg + } + LDRBT_ri 1111 1000 0001 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1000 0001 ---- 1111 000000 -- ---- # PLD + LDRB_rr 1111 1000 0001 .... .... 000000 .. .... @ldst_rr + } +} +{ + { + NOP 1111 1000 -011 1111 1111 ------------ # PLD + LDRH_ri 1111 1000 .011 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1000 1011 ---- 1111 ------------ # PLDW + LDRH_ri 1111 1000 1011 .... .... ............ @ldst_ri_pos + } + LDRH_ri 1111 1000 0011 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1000 0011 ---- 1111 1100 -------- # PLDW + LDRH_ri 1111 1000 0011 .... .... 1100 ........ @ldst_ri_neg + } + LDRHT_ri 1111 1000 0011 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1000 0011 ---- 1111 000000 -- ---- # PLDW + LDRH_rr 1111 1000 0011 .... .... 000000 .. .... @ldst_rr + } +} +{ + LDR_ri 1111 1000 .101 1111 .... ............ @ldst_ri_lit + LDR_ri 1111 1000 1101 .... .... ............ @ldst_ri_pos + LDR_ri 1111 1000 0101 .... .... 1..1 ........ @ldst_ri_idx + LDR_ri 1111 1000 0101 .... .... 1100 ........ @ldst_ri_neg + LDRT_ri 1111 1000 0101 .... .... 1110 ........ @ldst_ri_unp + LDR_rr 1111 1000 0101 .... .... 000000 .. .... @ldst_rr +} +# NOPs here are PLI. +{ + { + NOP 1111 1001 -001 1111 1111 ------------ + LDRSB_ri 1111 1001 .001 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1001 1001 ---- 1111 ------------ + LDRSB_ri 1111 1001 1001 .... .... ............ @ldst_ri_pos + } + LDRSB_ri 1111 1001 0001 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1001 0001 ---- 1111 1100 -------- + LDRSB_ri 1111 1001 0001 .... .... 1100 ........ @ldst_ri_neg + } + LDRSBT_ri 1111 1001 0001 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1001 0001 ---- 1111 000000 -- ---- + LDRSB_rr 1111 1001 0001 .... .... 000000 .. .... @ldst_rr + } +} +# NOPs here are unallocated memory hints, treated as NOP. +{ + { + NOP 1111 1001 -011 1111 1111 ------------ + LDRSH_ri 1111 1001 .011 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1001 1011 ---- 1111 ------------ + LDRSH_ri 1111 1001 1011 .... .... ............ @ldst_ri_pos + } + LDRSH_ri 1111 1001 0011 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1001 0011 ---- 1111 1100 -------- + LDRSH_ri 1111 1001 0011 .... .... 1100 ........ @ldst_ri_neg + } + LDRSHT_ri 1111 1001 0011 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1001 0011 ---- 1111 000000 -- ---- + LDRSH_rr 1111 1001 0011 .... .... 000000 .. .... @ldst_rr + } +} + +%imm8x4 0:8 !function=3Dtimes_4 +&ldst_ri2 p w u rn rt rt2 imm +@ldstd_ri8 .... .... u:1 ... rn:4 rt:4 rt2:4 ........ \ + &ldst_ri2 imm=3D%imm8x4 + +STRD_ri_t32 1110 1000 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D0 +LDRD_ri_t32 1110 1000 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D0 + +STRD_ri_t32 1110 1001 .100 .... .... .... ........ @ldstd_ri8 w=3D= 0 p=3D1 +LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=3D= 0 p=3D1 + +STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 +LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 --=20 2.17.1 From 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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 21/68] target/arm: Convert Synchronization primitives X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 560 ++++++++++++++++++++++------------------- target/arm/a32.decode | 48 ++++ target/arm/t32.decode | 46 ++++ 3 files changed, 396 insertions(+), 258 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index f7c4db872c..3b0998444d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8823,6 +8823,302 @@ DO_LDST(STRH, store, MO_UW) =20 #undef DO_LDST =20 +/* + * Synchronization primitives + */ + +static bool op_swp(DisasContext *s, arg_SWP *a, TCGMemOp opc) +{ + TCGv_i32 addr, tmp; + TCGv taddr; + + opc |=3D s->be_data; + addr =3D load_reg(s, a->rn); + taddr =3D gen_aa32_addr(s, addr, opc); + tcg_temp_free_i32(addr); + + tmp =3D load_reg(s, a->rt2); + tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, get_mem_index(s), opc); + tcg_temp_free(taddr); + + store_reg(s, a->rt, tmp); + return true; +} + +static bool trans_SWP(DisasContext *s, arg_SWP *a) +{ + return op_swp(s, a, MO_UL | MO_ALIGN); +} + +static bool trans_SWPB(DisasContext *s, arg_SWP *a) +{ + return op_swp(s, a, MO_UB); +} + +/* + * Load/Store Exclusive and Load-Acquire/Store-Release + */ + +static bool op_strex(DisasContext *s, arg_STREX *a, TCGMemOp mop, bool rel) +{ + TCGv_i32 addr; + + if (rel) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + + addr =3D tcg_temp_local_new_i32(); + load_reg_var(s, addr, a->rn); + tcg_gen_addi_i32(addr, addr, a->imm); + + gen_store_exclusive(s, a->rd, a->rt, a->rt2, addr, mop); + tcg_temp_free_i32(addr); + return true; +} + +static bool trans_STREX(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_strex(s, a, MO_32, false); +} + +static bool trans_STREXD_a32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6K || (a->rt & 1)) { + return false; + } + a->rt2 =3D a->rt + 1; + return op_strex(s, a, MO_64, false); +} + +static bool trans_STREXD_t32(DisasContext *s, arg_STREX *a) +{ + return op_strex(s, a, MO_64, false); +} + +static bool trans_STREXB(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + return op_strex(s, a, MO_8, false); +} + +static bool trans_STREXH(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + return op_strex(s, a, MO_16, false); +} + +static bool trans_STLEX(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_32, true); +} + +static bool trans_STLEXD_a32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8 || (a->rt & 1)) { + return false; + } + a->rt2 =3D a->rt + 1; + return op_strex(s, a, MO_64, true); +} + +static bool trans_STLEXD_t32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_64, true); +} + +static bool trans_STLEXB(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_8, true); +} + +static bool trans_STLEXH(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_16, true); +} + +static bool op_stl(DisasContext *s, arg_STL *a, TCGMemOp mop) +{ + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_8) { + return false; + } + addr =3D load_reg(s, a->rn); + + tmp =3D load_reg(s, a->rt); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(addr); + return true; +} + +static bool trans_STL(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UL); +} + +static bool trans_STLB(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UB); +} + +static bool trans_STLH(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UW); +} + +static bool op_ldrex(DisasContext *s, arg_LDREX *a, TCGMemOp mop, bool acq) +{ + TCGv_i32 addr; + + addr =3D tcg_temp_local_new_i32(); + load_reg_var(s, addr, a->rn); + tcg_gen_addi_i32(addr, addr, a->imm); + + gen_load_exclusive(s, a->rt, a->rt2, addr, mop); + tcg_temp_free_i32(addr); + + if (acq) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + return true; +} + +static bool trans_LDREX(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_ldrex(s, a, MO_32, false); +} + +static bool trans_LDREXD_a32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6K || (a->rt & 1)) { + return false; + } + a->rt2 =3D a->rt + 1; + return op_ldrex(s, a, MO_64, false); +} + +static bool trans_LDREXD_t32(DisasContext *s, arg_LDREX *a) +{ + return op_ldrex(s, a, MO_64, false); +} + +static bool trans_LDREXB(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + return op_ldrex(s, a, MO_8, false); +} + +static bool trans_LDREXH(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + return op_ldrex(s, a, MO_16, false); +} + +static bool trans_LDAEX(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_32, true); +} + +static bool trans_LDAEXD_a32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8 || (a->rt & 1)) { + return false; + } + a->rt2 =3D a->rt + 1; + return op_ldrex(s, a, MO_64, true); +} + +static bool trans_LDAEXD_t32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_64, true); +} + +static bool trans_LDAEXB(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_8, true); +} + +static bool trans_LDAEXH(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_16, true); +} + +static bool op_lda(DisasContext *s, arg_LDA *a, TCGMemOp mop) +{ + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_8) { + return false; + } + addr =3D load_reg(s, a->rn); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); + tcg_temp_free_i32(addr); + + store_reg(s, a->rt, tmp); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + return true; +} + +static bool trans_LDA(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UL); +} + +static bool trans_LDAB(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UB); +} + +static bool trans_LDAH(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UW); +} + /* * Legacy decoder. */ @@ -9118,172 +9414,8 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) case 0x0: case 0x1: /* multiplies, extra load/stores */ - sh =3D (insn >> 5) & 3; - if (sh =3D=3D 0) { - if (op1 =3D=3D 0x0) { - /* Multiply and multiply accumulate. */ - /* All done in decodetree. Reach here for illegal ops= . */ - goto illegal_op; - } else { - rn =3D (insn >> 16) & 0xf; - rd =3D (insn >> 12) & 0xf; - if (insn & (1 << 23)) { - /* load/store exclusive */ - bool is_ld =3D extract32(insn, 20, 1); - bool is_lasr =3D !extract32(insn, 8, 1); - int op2 =3D (insn >> 8) & 3; - op1 =3D (insn >> 21) & 0x3; - - switch (op2) { - case 0: /* lda/stl */ - if (op1 =3D=3D 1) { - goto illegal_op; - } - ARCH(8); - break; - case 1: /* reserved */ - goto illegal_op; - case 2: /* ldaex/stlex */ - ARCH(8); - break; - case 3: /* ldrex/strex */ - if (op1) { - ARCH(6K); - } else { - ARCH(6); - } - break; - } - - addr =3D tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - - if (is_lasr && !is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - - if (op2 =3D=3D 0) { - if (is_ld) { - tmp =3D tcg_temp_new_i32(); - switch (op1) { - case 0: /* lda */ - gen_aa32_ld32u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - case 2: /* ldab */ - gen_aa32_ld8u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - case 3: /* ldah */ - gen_aa32_ld16u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - default: - abort(); - } - store_reg(s, rd, tmp); - } else { - rm =3D insn & 0xf; - tmp =3D load_reg(s, rm); - switch (op1) { - case 0: /* stl */ - gen_aa32_st32_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - case 2: /* stlb */ - gen_aa32_st8_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - case 3: /* stlh */ - gen_aa32_st16_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - default: - abort(); - } - tcg_temp_free_i32(tmp); - } - } else if (is_ld) { - switch (op1) { - case 0: /* ldrex */ - gen_load_exclusive(s, rd, 15, addr, 2); - break; - case 1: /* ldrexd */ - gen_load_exclusive(s, rd, rd + 1, addr, 3); - break; - case 2: /* ldrexb */ - gen_load_exclusive(s, rd, 15, addr, 0); - break; - case 3: /* ldrexh */ - gen_load_exclusive(s, rd, 15, addr, 1); - break; - default: - abort(); - } - } else { - rm =3D insn & 0xf; - switch (op1) { - case 0: /* strex */ - gen_store_exclusive(s, rd, rm, 15, addr, 2= ); - break; - case 1: /* strexd */ - gen_store_exclusive(s, rd, rm, rm + 1, add= r, 3); - break; - case 2: /* strexb */ - gen_store_exclusive(s, rd, rm, 15, addr, 0= ); - break; - case 3: /* strexh */ - gen_store_exclusive(s, rd, rm, 15, addr, 1= ); - break; - default: - abort(); - } - } - tcg_temp_free_i32(addr); - - if (is_lasr && is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } - } else if ((insn & 0x00300f00) =3D=3D 0) { - /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx - * - SWP, SWPB - */ - - TCGv taddr; - TCGMemOp opc =3D s->be_data; - - rm =3D (insn) & 0xf; - - if (insn & (1 << 22)) { - opc |=3D MO_UB; - } else { - opc |=3D MO_UL | MO_ALIGN; - } - - addr =3D load_reg(s, rn); - taddr =3D gen_aa32_addr(s, addr, opc); - tcg_temp_free_i32(addr); - - tmp =3D load_reg(s, rm); - tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, - get_mem_index(s), opc); - tcg_temp_free(taddr); - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - } - } else { - /* Extra load/store (register) instructions */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; break; case 0x4: case 0x5: @@ -9932,15 +10064,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) } goto illegal_op; } - addr =3D tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2); - if (insn & (1 << 20)) { - gen_load_exclusive(s, rs, 15, addr, 2); - } else { - gen_store_exclusive(s, rd, rs, 15, addr, 2); - } - tcg_temp_free_i32(addr); + /* Load/store exclusive, in decodetree */ + goto illegal_op; } else if ((insn & (7 << 5)) =3D=3D 0) { /* Table Branch. */ addr =3D load_reg(s, rn); @@ -9962,89 +10087,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) tcg_gen_addi_i32(tmp, tmp, read_pc(s)); store_reg(s, 15, tmp); } else { - bool is_lasr =3D false; - bool is_ld =3D extract32(insn, 20, 1); - int op2 =3D (insn >> 6) & 0x3; - op =3D (insn >> 4) & 0x3; - switch (op2) { - case 0: - goto illegal_op; - case 1: - /* Load/store exclusive byte/halfword/doubleword */ - if (op =3D=3D 2) { - goto illegal_op; - } - ARCH(7); - break; - case 2: - /* Load-acquire/store-release */ - if (op =3D=3D 3) { - goto illegal_op; - } - /* Fall through */ - case 3: - /* Load-acquire/store-release exclusive */ - ARCH(8); - is_lasr =3D true; - break; - } - - if (is_lasr && !is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - - addr =3D tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - if (!(op2 & 1)) { - if (is_ld) { - tmp =3D tcg_temp_new_i32(); - switch (op) { - case 0: /* ldab */ - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(= s), - rs | ISSIsAcqRel); - break; - case 1: /* ldah */ - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index= (s), - rs | ISSIsAcqRel); - break; - case 2: /* lda */ - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index= (s), - rs | ISSIsAcqRel); - break; - default: - abort(); - } - store_reg(s, rs, tmp); - } else { - tmp =3D load_reg(s, rs); - switch (op) { - case 0: /* stlb */ - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s= ), - rs | ISSIsAcqRel); - break; - case 1: /* stlh */ - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(= s), - rs | ISSIsAcqRel); - break; - case 2: /* stl */ - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(= s), - rs | ISSIsAcqRel); - break; - default: - abort(); - } - tcg_temp_free_i32(tmp); - } - } else if (is_ld) { - gen_load_exclusive(s, rs, rd, addr, op); - } else { - gen_store_exclusive(s, rm, rs, rd, addr, op); - } - tcg_temp_free_i32(addr); - - if (is_lasr && is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } + /* Load/store exclusive, load-acq/store-rel, in decodetree= */ + goto illegal_op; } } else { /* Load/store multiple, RFE, SRS. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index f7742deaee..c76cbad569 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -39,6 +39,8 @@ &mrs_bank rd r sysm &ldst_rr p w u rn rt rm shimm shtype &ldst_ri p w u rn rt imm +&strex rn rd rt rt2 imm +&ldrex rn rt rt2 imm =20 # Data-processing (register) =20 @@ -342,3 +344,49 @@ STRT_ri .... 010. .0.0 .... .... ............= @ldst_ri12_p0w1 STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p= 0w1 LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p= 0w1 LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p= 0w1 + +# Synchronization primitives + +@swp ---- .... .... rn:4 rt:4 .... .... rt2:4 + +SWP .... 0001 0000 .... .... 0000 1001 .... @swp +SWPB .... 0001 0100 .... .... 0000 1001 .... @swp + +# Load/Store Exclusive and Load-Acquire/Store-Release +# +# Note rt2 for STREXD/LDREXD is set by the helper after checking rt is eve= n. + +@strex ---- .... .... rn:4 rd:4 .... .... rt:4 \ + &strex imm=3D0 rt2=3D15 +@ldrex ---- .... .... rn:4 rt:4 .... .... .... \ + &ldrex imm=3D0 rt2=3D15 +@stl ---- .... .... rn:4 .... .... .... rt:4 \ + &ldrex imm=3D0 rt2=3D15 + +STREX .... 0001 1000 .... .... 1111 1001 .... @strex +STREXD_a32 .... 0001 1010 .... .... 1111 1001 .... @strex +STREXB .... 0001 1100 .... .... 1111 1001 .... @strex +STREXH .... 0001 1110 .... .... 1111 1001 .... @strex + +STLEX .... 0001 1000 .... .... 1110 1001 .... @strex +STLEXD_a32 .... 0001 1010 .... .... 1110 1001 .... @strex +STLEXB .... 0001 1100 .... .... 1110 1001 .... @strex +STLEXH .... 0001 1110 .... .... 1110 1001 .... @strex + +STL .... 0001 1000 .... 1111 1100 1001 .... @stl +STLB .... 0001 1100 .... 1111 1100 1001 .... @stl +STLH .... 0001 1110 .... 1111 1100 1001 .... @stl + +LDREX .... 0001 1001 .... .... 1111 1001 1111 @ldrex +LDREXD_a32 .... 0001 1011 .... .... 1111 1001 1111 @ldrex +LDREXB .... 0001 1101 .... .... 1111 1001 1111 @ldrex +LDREXH .... 0001 1111 .... .... 1111 1001 1111 @ldrex + +LDAEX .... 0001 1001 .... .... 1110 1001 1111 @ldrex +LDAEXD_a32 .... 0001 1011 .... .... 1110 1001 1111 @ldrex +LDAEXB .... 0001 1101 .... .... 1110 1001 1111 @ldrex +LDAEXH .... 0001 1111 .... .... 1110 1001 1111 @ldrex + +LDA .... 0001 1001 .... .... 1100 1001 1111 @ldrex +LDAB .... 0001 1101 .... .... 1100 1001 1111 @ldrex +LDAH .... 0001 1111 .... .... 1100 1001 1111 @ldrex diff --git a/target/arm/t32.decode b/target/arm/t32.decode index a86597562b..70cf8039d7 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -36,6 +36,8 @@ &mrs_bank !extern rd r sysm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&strex !extern rn rd rt rt2 imm +&ldrex !extern rn rt rt2 imm =20 # Data-processing (register) =20 @@ -392,3 +394,47 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... .......= . @ldstd_ri8 w=3D0 p=3D1 =20 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 + +# Load/Store Exclusive and Load-Acquire/Store-Release + +@strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \ + &strex rt2=3D15 imm=3D%imm8x4 +@strex_0 .... .... .... rn:4 rt:4 .... .... rd:4 \ + &strex rt2=3D15 imm=3D0 +@strex_d .... .... .... rn:4 rt:4 rt2:4 .... rd:4 \ + &strex imm=3D0 + +@ldrex_i .... .... .... rn:4 rt:4 .... .... .... \ + &ldrex rt2=3D15 imm=3D%imm8x4 +@ldrex_0 .... .... .... rn:4 rt:4 .... .... .... \ + &ldrex rt2=3D15 imm=3D0 +@ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \ + &ldrex imm=3D0 + +STREX 1110 1000 0100 .... .... .... .... .... @strex_i +STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0 +STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0 +STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d + +STLEX 1110 1000 1100 .... .... 1111 1110 .... @strex_0 +STLEXB 1110 1000 1100 .... .... 1111 1100 .... @strex_0 +STLEXH 1110 1000 1100 .... .... 1111 1101 .... @strex_0 +STLEXD_t32 1110 1000 1100 .... .... .... 1111 .... @strex_d + +STL 1110 1000 1100 .... .... 1111 1010 1111 @ldrex_0 +STLB 1110 1000 1100 .... .... 1111 1000 1111 @ldrex_0 +STLH 1110 1000 1100 .... .... 1111 1001 1111 @ldrex_0 + +LDREX 1110 1000 0101 .... .... 1111 .... .... @ldrex_i +LDREXB 1110 1000 1101 .... .... 1111 0100 1111 @ldrex_0 +LDREXH 1110 1000 1101 .... .... 1111 0101 1111 @ldrex_0 +LDREXD_t32 1110 1000 1101 .... .... .... 0111 1111 @ldrex_d + +LDAEX 1110 1000 1101 .... .... 1111 1110 1111 @ldrex_0 +LDAEXB 1110 1000 1101 .... .... 1111 1100 1111 @ldrex_0 +LDAEXH 1110 1000 1101 .... .... 1111 1101 1111 @ldrex_0 +LDAEXD_t32 1110 1000 1101 .... .... .... 1111 1111 @ldrex_d + +LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 +LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 +LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566251674; cv=none; d=zoho.com; s=zohoarc; b=ltSpi2SnTEfLm9k9EzYygo2qZ1+K9unXXenU1Bk1tjYn1xwYDWYD0oA66VvP/2bp/oA0n67T5JSW4wuNLpk07QGnmZBghXXe0lEXT1MIt6CWngnccVuNzMlytGxh1GW65Lrx8HaMTPxMDzk0M2CiwD/KjTgAOnBJ9ttrx/5p/U0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566251674; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=0nkhvFNWh9JA2E6GDxXbIzz/FtBFCfF30Q7P+QipECs=; b=JuRtb0xR9M7fXl3ziBI1UfaKxBtAxDnIDsObSRLVdIAsSU5Qb/Qp4UaNNLbt8onC6VniAq4O9Wh92ICZyobBDRZjUlGqtTvdiRXs/ShnqVuwLfxyAltCJUcKmjyzUcGJzlc5mNSKpiq6kz3gmcZvgCEdwREaTCi3XWH+pCpFMn0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156625167455996.35928340189525; Mon, 19 Aug 2019 14:54:34 -0700 (PDT) Received: from localhost ([::1]:59223 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpbk-0005Ch-VR for importer@patchew.org; Mon, 19 Aug 2019 17:54:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59001) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMC-0001tg-Nq for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMA-0006Fo-OQ for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:28 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:33449) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMA-0006F4-H2 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:26 -0400 Received: by mail-pl1-x643.google.com with SMTP id go14so1586410plb.0 for ; Mon, 19 Aug 2019 14:38:26 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 22/68] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 200 +++++++++++++++++++++-------------------- target/arm/a32.decode | 20 +++++ target/arm/t32.decode | 19 ++++ 3 files changed, 143 insertions(+), 96 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 3b0998444d..2764a1a637 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9119,6 +9119,103 @@ static bool trans_LDAH(DisasContext *s, arg_LDA *a) return op_lda(s, a, MO_UW); } =20 +/* + * Media instructions + */ + +static bool trans_USADA8(DisasContext *s, arg_USADA8 *a) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + gen_helper_usad8(t1, t1, t2); + tcg_temp_free_i32(t2); + if (a->ra !=3D 15) { + t2 =3D load_reg(s, a->ra); + tcg_gen_add_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool op_bfx(DisasContext *s, arg_UBFX *a, bool u) +{ + TCGv_i32 tmp; + int width =3D a->widthm1 + 1; + int shift =3D a->lsb; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp =3D load_reg(s, a->rn); + if (shift + width > 32) { + return false; + } else if (width < 32) { + if (u) { + tcg_gen_extract_i32(tmp, tmp, shift, width); + } else { + tcg_gen_sextract_i32(tmp, tmp, shift, width); + } + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SBFX(DisasContext *s, arg_SBFX *a) +{ + return op_bfx(s, a, false); +} + +static bool trans_UBFX(DisasContext *s, arg_UBFX *a) +{ + return op_bfx(s, a, true); +} + +static bool trans_BFCI(DisasContext *s, arg_BFCI *a) +{ + TCGv_i32 tmp; + int msb =3D a->msb, lsb =3D a->lsb; + int width; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + if (msb < lsb) { + /* UNPREDICTABLE; we choose to UNDEF */ + return false; + } + + width =3D msb + 1 - lsb; + if (a->rn =3D=3D 15) { + /* BFC */ + tmp =3D tcg_const_i32(0); + } else { + /* BFI */ + tmp =3D load_reg(s, a->rn); + } + if (width !=3D 32) { + TCGv_i32 tmp2 =3D load_reg(s, a->rd); + tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width); + tcg_temp_free_i32(tmp2); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_UDF(DisasContext *s, arg_UDF *a) +{ + unallocated_encoding(s); + return true; +} + /* * Legacy decoder. */ @@ -9659,65 +9756,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) } break; case 3: - op1 =3D ((insn >> 17) & 0x38) | ((insn >> 5) & 7); - switch (op1) { - case 0: /* Unsigned sum of absolute differences. */ - ARCH(6); - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - gen_helper_usad8(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rd !=3D 15) { - tmp2 =3D load_reg(s, rd); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rn, tmp); - break; - case 0x20: case 0x24: case 0x28: case 0x2c: - /* Bitfield insert/clear. */ - ARCH(6T2); - shift =3D (insn >> 7) & 0x1f; - i =3D (insn >> 16) & 0x1f; - if (i < shift) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - i =3D i + 1 - shift; - if (rm =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp =3D load_reg(s, rm); - } - if (i !=3D 32) { - tmp2 =3D load_reg(s, rd); - tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, i); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - break; - case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */ - case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */ - ARCH(6T2); - tmp =3D load_reg(s, rm); - shift =3D (insn >> 7) & 0x1f; - i =3D ((insn >> 16) & 0x1f) + 1; - if (shift + i > 32) - goto illegal_op; - if (i < 32) { - if (op1 & 0x20) { - tcg_gen_extract_i32(tmp, tmp, shift, i); - } else { - tcg_gen_sextract_i32(tmp, tmp, shift, i); - } - } - store_reg(s, rd, tmp); - break; - default: - goto illegal_op; - } - break; + /* USAD, BFI, BFC, SBFX, UBFX */ + /* Done by decodetree */ + goto illegal_op; } break; } @@ -10359,10 +10400,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) case 0: /* 32 x 32 -> 32 */ case 1: /* 16 x 16 -> 32 */ case 3: /* 32 * 16 -> 32msb */ + case 7: /* Unsigned sum of absolute differences. */ /* in decodetree */ goto illegal_op; - case 7: /* Unsigned sum of absolute differences. */ - break; case 2: /* Dual multiply add. */ case 4: /* Dual multiply subtract. */ case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ @@ -10420,15 +10460,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } tcg_temp_free_i32(tmp2); break; - case 7: /* Unsigned sum of absolute differences. */ - gen_helper_usad8(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rs !=3D 15) { - tmp2 =3D load_reg(s, rs); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; } store_reg(s, rd, tmp); break; @@ -10723,32 +10754,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tmp =3D load_reg(s, rn); } switch (op) { - case 2: /* Signed bitfield extract. */ - imm++; - if (shift + imm > 32) - goto illegal_op; - if (imm < 32) { - tcg_gen_sextract_i32(tmp, tmp, shift, imm); - } - break; - case 6: /* Unsigned bitfield extract. */ - imm++; - if (shift + imm > 32) - goto illegal_op; - if (imm < 32) { - tcg_gen_extract_i32(tmp, tmp, shift, imm); - } - break; - case 3: /* Bitfield insert/clear. */ - if (imm < shift) - goto illegal_op; - imm =3D imm + 1 - shift; - if (imm !=3D 32) { - tmp2 =3D load_reg(s, rd); - tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, imm= ); - tcg_temp_free_i32(tmp2); - } - break; + case 2: /* Signed bitfield extract, in decodetree */ + case 6: /* Unsigned bitfield extract, in decodetree */ + case 3: /* Bitfield insert/clear, in decodetree */ case 7: goto illegal_op; default: /* Saturate. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index c76cbad569..285c08ca22 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -41,6 +41,8 @@ &ldst_ri p w u rn rt imm &strex rn rd rt rt2 imm &ldrex rn rt rt2 imm +&bfx rd rn lsb widthm1 +&bfi rd rn lsb msb =20 # Data-processing (register) =20 @@ -390,3 +392,21 @@ LDAEXH .... 0001 1111 .... .... 1110 1001 11= 11 @ldrex LDA .... 0001 1001 .... .... 1100 1001 1111 @ldrex LDAB .... 0001 1101 .... .... 1100 1001 1111 @ldrex LDAH .... 0001 1111 .... .... 1100 1001 1111 @ldrex + +# Media instructions + +# usad8 is usada8 w/ ra=3D15 +USADA8 ---- 0111 1000 rd:4 ra:4 rm:4 0001 rn:4 + +# ubfx and sbfx +@bfx ---- .... ... widthm1:5 rd:4 lsb:5 ... rn:4 &bfx + +SBFX .... 0111 101 ..... .... ..... 101 .... @bfx +UBFX .... 0111 111 ..... .... ..... 101 .... @bfx + +# bfc is bfi w/ rn=3D15 +BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn:4 &bfi + +# While we could get UDEF by not including this, add the pattern for +# documentation and to conflict with any other typos in this file. +UDF 1110 0111 1111 ---- ---- ---- 1111 ---- diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 70cf8039d7..682fc5c2c4 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -38,6 +38,8 @@ &ldst_ri !extern p w u rn rt imm &strex !extern rn rd rt rt2 imm &ldrex !extern rn rt rt2 imm +&bfx !extern rd rn lsb widthm1 +&bfi !extern rd rn lsb msb =20 # Data-processing (register) =20 @@ -144,6 +146,19 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... .....= ... @s_rri_rot SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 } =20 +# Saturate, bitfield + +@bfx .... .... ... . rn:4 . ... rd:4 .. . widthm1:5 \ + &bfx lsb=3D%imm5_12_6 +@bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \ + &bfi lsb=3D%imm5_12_6 + +SBFX 1111 0011 010 0 .... 0 ... .... ..0..... @bfx +UBFX 1111 0011 110 0 .... 0 ... .... ..0..... @bfx + +# bfc is bfi w/ rn=3D15 +BFCI 1111 0011 011 0 .... 0 ... .... ..0..... @bfi + # Multiply and multiply accumulate =20 @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 @@ -192,6 +207,9 @@ SMLALBT 1111 1011 1100 .... .... .... 1001 ...= . @rnadm SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm =20 +# usad8 is usada8 w/ ra=3D15 +USADA8 1111 1011 0111 .... .... .... 0000 .... @rnadm + # Data-processing (two source registers) =20 QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm @@ -254,6 +272,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ...= . @rdm SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=3D%imm16_16_0 + UDF 1111 0111 1111 ---- 1010 ---- ---- ---- } =20 # Load/store (register, immediate, literal) --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 23/68] target/arm: Convert Parallel addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 229 ++++++++++++++++++++--------------------- target/arm/a32.decode | 44 ++++++++ target/arm/t32.decode | 44 ++++++++ 3 files changed, 200 insertions(+), 117 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 2764a1a637..cf03527afc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -648,99 +648,6 @@ static inline void gen_arm_shift_reg(TCGv_i32 var, int= shiftop, tcg_temp_free_i32(shift); } =20 -#define PAS_OP(pfx) \ - switch (op2) { \ - case 0: gen_pas_helper(glue(pfx,add16)); break; \ - case 1: gen_pas_helper(glue(pfx,addsubx)); break; \ - case 2: gen_pas_helper(glue(pfx,subaddx)); break; \ - case 3: gen_pas_helper(glue(pfx,sub16)); break; \ - case 4: gen_pas_helper(glue(pfx,add8)); break; \ - case 7: gen_pas_helper(glue(pfx,sub8)); break; \ - } -static void gen_arm_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32= b) -{ - TCGv_ptr tmp; - - switch (op1) { -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) - case 1: - tmp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(s) - tcg_temp_free_ptr(tmp); - break; - case 5: - tmp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(u) - tcg_temp_free_ptr(tmp); - break; -#undef gen_pas_helper -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) - case 2: - PAS_OP(q); - break; - case 3: - PAS_OP(sh); - break; - case 6: - PAS_OP(uq); - break; - case 7: - PAS_OP(uh); - break; -#undef gen_pas_helper - } -} -#undef PAS_OP - -/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings= . */ -#define PAS_OP(pfx) \ - switch (op1) { \ - case 0: gen_pas_helper(glue(pfx,add8)); break; \ - case 1: gen_pas_helper(glue(pfx,add16)); break; \ - case 2: gen_pas_helper(glue(pfx,addsubx)); break; \ - case 4: gen_pas_helper(glue(pfx,sub8)); break; \ - case 5: gen_pas_helper(glue(pfx,sub16)); break; \ - case 6: gen_pas_helper(glue(pfx,subaddx)); break; \ - } -static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_= i32 b) -{ - TCGv_ptr tmp; - - switch (op2) { -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) - case 0: - tmp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(s) - tcg_temp_free_ptr(tmp); - break; - case 4: - tmp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(u) - tcg_temp_free_ptr(tmp); - break; -#undef gen_pas_helper -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) - case 1: - PAS_OP(q); - break; - case 2: - PAS_OP(sh); - break; - case 5: - PAS_OP(uq); - break; - case 6: - PAS_OP(uh); - break; -#undef gen_pas_helper - } -} -#undef PAS_OP - /* * Generate a conditional based on ARM condition code cc. * This is common between ARM and Aarch64 targets. @@ -9216,6 +9123,114 @@ static bool trans_UDF(DisasContext *s, arg_UDF *a) return true; } =20 +/* + * Parallel addition and subtraction + */ + +static bool op_par_addsub(DisasContext *s, arg_rrr *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 t0, t1; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 =3D load_reg(s, a->rn); + t1 =3D load_reg(s, a->rm); + + gen(t0, t0, t1); + + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +static bool op_par_addsub_ge(DisasContext *s, arg_rrr *a, + void (*gen)(TCGv_i32, TCGv_i32, + TCGv_i32, TCGv_ptr)) +{ + TCGv_i32 t0, t1; + TCGv_ptr ge; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 =3D load_reg(s, a->rn); + t1 =3D load_reg(s, a->rm); + + ge =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ge, cpu_env, offsetof(CPUARMState, GE)); + gen(t0, t0, t1, ge); + + tcg_temp_free_ptr(ge); + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +#define DO_PAR_ADDSUB(NAME, helper) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_par_addsub(s, a, helper); \ +} + +#define DO_PAR_ADDSUB_GE(NAME, helper) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_par_addsub_ge(s, a, helper); \ +} + +DO_PAR_ADDSUB_GE(SADD16, gen_helper_sadd16) +DO_PAR_ADDSUB_GE(SASX, gen_helper_saddsubx) +DO_PAR_ADDSUB_GE(SSAX, gen_helper_ssubaddx) +DO_PAR_ADDSUB_GE(SSUB16, gen_helper_ssub16) +DO_PAR_ADDSUB_GE(SADD8, gen_helper_sadd8) +DO_PAR_ADDSUB_GE(SSUB8, gen_helper_ssub8) + +DO_PAR_ADDSUB_GE(UADD16, gen_helper_uadd16) +DO_PAR_ADDSUB_GE(UASX, gen_helper_uaddsubx) +DO_PAR_ADDSUB_GE(USAX, gen_helper_usubaddx) +DO_PAR_ADDSUB_GE(USUB16, gen_helper_usub16) +DO_PAR_ADDSUB_GE(UADD8, gen_helper_uadd8) +DO_PAR_ADDSUB_GE(USUB8, gen_helper_usub8) + +DO_PAR_ADDSUB(QADD16, gen_helper_qadd16) +DO_PAR_ADDSUB(QASX, gen_helper_qaddsubx) +DO_PAR_ADDSUB(QSAX, gen_helper_qsubaddx) +DO_PAR_ADDSUB(QSUB16, gen_helper_qsub16) +DO_PAR_ADDSUB(QADD8, gen_helper_qadd8) +DO_PAR_ADDSUB(QSUB8, gen_helper_qsub8) + +DO_PAR_ADDSUB(UQADD16, gen_helper_uqadd16) +DO_PAR_ADDSUB(UQASX, gen_helper_uqaddsubx) +DO_PAR_ADDSUB(UQSAX, gen_helper_uqsubaddx) +DO_PAR_ADDSUB(UQSUB16, gen_helper_uqsub16) +DO_PAR_ADDSUB(UQADD8, gen_helper_uqadd8) +DO_PAR_ADDSUB(UQSUB8, gen_helper_uqsub8) + +DO_PAR_ADDSUB(SHADD16, gen_helper_shadd16) +DO_PAR_ADDSUB(SHASX, gen_helper_shaddsubx) +DO_PAR_ADDSUB(SHSAX, gen_helper_shsubaddx) +DO_PAR_ADDSUB(SHSUB16, gen_helper_shsub16) +DO_PAR_ADDSUB(SHADD8, gen_helper_shadd8) +DO_PAR_ADDSUB(SHSUB8, gen_helper_shsub8) + +DO_PAR_ADDSUB(UHADD16, gen_helper_uhadd16) +DO_PAR_ADDSUB(UHASX, gen_helper_uhaddsubx) +DO_PAR_ADDSUB(UHSAX, gen_helper_uhsubaddx) +DO_PAR_ADDSUB(UHSUB16, gen_helper_uhsub16) +DO_PAR_ADDSUB(UHADD8, gen_helper_uhadd8) +DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8) + +#undef DO_PAR_ADDSUB +#undef DO_PAR_ADDSUB_GE + /* * Legacy decoder. */ @@ -9528,16 +9543,8 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) rs =3D (insn >> 8) & 0xf; switch ((insn >> 23) & 3) { case 0: /* Parallel add/subtract. */ - op1 =3D (insn >> 20) & 7; - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - sh =3D (insn >> 5) & 7; - if ((op1 & 3) =3D=3D 0 || sh =3D=3D 5 || sh =3D=3D 6) - goto illegal_op; - gen_arm_parallel_addsub(op1, sh, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + /* Done by decodetree */ + goto illegal_op; case 1: if ((insn & 0x00700020) =3D=3D 0) { /* Halfword pack. */ @@ -10324,20 +10331,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } store_reg(s, rd, tmp); break; - case 2: /* SIMD add/subtract. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - op =3D (insn >> 20) & 7; - shift =3D (insn >> 4) & 7; - if ((op & 3) =3D=3D 3 || (shift & 3) =3D=3D 3) - goto illegal_op; - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - gen_thumb2_parallel_addsub(op, shift, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + case 2: /* SIMD add/subtract, in decodetree */ + goto illegal_op; case 3: /* Other data processing. */ op =3D ((insn >> 17) & 0x38) | ((insn >> 4) & 7); if (op < 4) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 285c08ca22..4dfd8133f7 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -410,3 +410,47 @@ BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn= :4 &bfi # While we could get UDEF by not including this, add the pattern for # documentation and to conflict with any other typos in this file. UDF 1110 0111 1111 ---- ---- ---- 1111 ---- + +# Parallel addition and subtraction + +SADD16 .... 0110 0001 .... .... 1111 0001 .... @rndm +SASX .... 0110 0001 .... .... 1111 0011 .... @rndm +SSAX .... 0110 0001 .... .... 1111 0101 .... @rndm +SSUB16 .... 0110 0001 .... .... 1111 0111 .... @rndm +SADD8 .... 0110 0001 .... .... 1111 1001 .... @rndm +SSUB8 .... 0110 0001 .... .... 1111 1111 .... @rndm + +QADD16 .... 0110 0010 .... .... 1111 0001 .... @rndm +QASX .... 0110 0010 .... .... 1111 0011 .... @rndm +QSAX .... 0110 0010 .... .... 1111 0101 .... @rndm +QSUB16 .... 0110 0010 .... .... 1111 0111 .... @rndm +QADD8 .... 0110 0010 .... .... 1111 1001 .... @rndm +QSUB8 .... 0110 0010 .... .... 1111 1111 .... @rndm + +SHADD16 .... 0110 0011 .... .... 1111 0001 .... @rndm +SHASX .... 0110 0011 .... .... 1111 0011 .... @rndm +SHSAX .... 0110 0011 .... .... 1111 0101 .... @rndm +SHSUB16 .... 0110 0011 .... .... 1111 0111 .... @rndm +SHADD8 .... 0110 0011 .... .... 1111 1001 .... @rndm +SHSUB8 .... 0110 0011 .... .... 1111 1111 .... @rndm + +UADD16 .... 0110 0101 .... .... 1111 0001 .... @rndm +UASX .... 0110 0101 .... .... 1111 0011 .... @rndm +USAX .... 0110 0101 .... .... 1111 0101 .... @rndm +USUB16 .... 0110 0101 .... .... 1111 0111 .... @rndm +UADD8 .... 0110 0101 .... .... 1111 1001 .... @rndm +USUB8 .... 0110 0101 .... .... 1111 1111 .... @rndm + +UQADD16 .... 0110 0110 .... .... 1111 0001 .... @rndm +UQASX .... 0110 0110 .... .... 1111 0011 .... @rndm +UQSAX .... 0110 0110 .... .... 1111 0101 .... @rndm +UQSUB16 .... 0110 0110 .... .... 1111 0111 .... @rndm +UQADD8 .... 0110 0110 .... .... 1111 1001 .... @rndm +UQSUB8 .... 0110 0110 .... .... 1111 1111 .... @rndm + +UHADD16 .... 0110 0111 .... .... 1111 0001 .... @rndm +UHASX .... 0110 0111 .... .... 1111 0011 .... @rndm +UHSAX .... 0110 0111 .... .... 1111 0101 .... @rndm +UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm +UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm +UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 682fc5c2c4..c899c56766 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -457,3 +457,47 @@ LDAEXD_t32 1110 1000 1101 .... .... .... 1111 11= 11 @ldrex_d LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 + +# Parallel addition and subtraction + +SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm +QADD8 1111 1010 1000 .... 1111 .... 0001 .... @rndm +SHADD8 1111 1010 1000 .... 1111 .... 0010 .... @rndm +UADD8 1111 1010 1000 .... 1111 .... 0100 .... @rndm +UQADD8 1111 1010 1000 .... 1111 .... 0101 .... @rndm +UHADD8 1111 1010 1000 .... 1111 .... 0110 .... @rndm + +SADD16 1111 1010 1001 .... 1111 .... 0000 .... @rndm +QADD16 1111 1010 1001 .... 1111 .... 0001 .... @rndm +SHADD16 1111 1010 1001 .... 1111 .... 0010 .... @rndm +UADD16 1111 1010 1001 .... 1111 .... 0100 .... @rndm +UQADD16 1111 1010 1001 .... 1111 .... 0101 .... @rndm +UHADD16 1111 1010 1001 .... 1111 .... 0110 .... @rndm + +SASX 1111 1010 1010 .... 1111 .... 0000 .... @rndm +QASX 1111 1010 1010 .... 1111 .... 0001 .... @rndm +SHASX 1111 1010 1010 .... 1111 .... 0010 .... @rndm +UASX 1111 1010 1010 .... 1111 .... 0100 .... @rndm +UQASX 1111 1010 1010 .... 1111 .... 0101 .... @rndm +UHASX 1111 1010 1010 .... 1111 .... 0110 .... @rndm + +SSUB8 1111 1010 1100 .... 1111 .... 0000 .... @rndm +QSUB8 1111 1010 1100 .... 1111 .... 0001 .... @rndm +SHSUB8 1111 1010 1100 .... 1111 .... 0010 .... @rndm +USUB8 1111 1010 1100 .... 1111 .... 0100 .... @rndm +UQSUB8 1111 1010 1100 .... 1111 .... 0101 .... @rndm +UHSUB8 1111 1010 1100 .... 1111 .... 0110 .... @rndm + +SSUB16 1111 1010 1101 .... 1111 .... 0000 .... @rndm +QSUB16 1111 1010 1101 .... 1111 .... 0001 .... @rndm +SHSUB16 1111 1010 1101 .... 1111 .... 0010 .... @rndm +USUB16 1111 1010 1101 .... 1111 .... 0100 .... @rndm +UQSUB16 1111 1010 1101 .... 1111 .... 0101 .... @rndm +UHSUB16 1111 1010 1101 .... 1111 .... 0110 .... @rndm + +SSAX 1111 1010 1110 .... 1111 .... 0000 .... @rndm +QSAX 1111 1010 1110 .... 1111 .... 0001 .... @rndm +SHSAX 1111 1010 1110 .... 1111 .... 0010 .... @rndm +USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm +UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm +UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JeupHb+SK2H6RvZmssVMi7mElAvZ/xp7OPh0k/6CdzA=; b=pzWGH2J+mfpK3Vzd2pjLZTMXhxOYeZMHC0Ff3kji+Ox7iuPLJ1Ndo1I+fD+GV+6UHy 1VZEixevEX41iXF6uGMF0G0bFUFNwuE4zaXB58S8lLIA5DujmM/DUShGGO9ZMXl7h7i/ SXea7d2RRuG9ZZj+B0woyWIqf8G7TNA0Xqjee+8LbSWShnu9IDOLR1UEUYLUsveIbtBF 5AgacEc/FLHRKG9uKsm9HWzwA+Ic14pgPtPP173nCzl1MibXW5KNqkbiXdKqBygucujA zV0MBE9Ky3MOxs5Y+e+BmyrHUXfpYsiMv9ErR+1oZ3TtN4nSTBiY15uMfbnZ05pyofyu cFIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JeupHb+SK2H6RvZmssVMi7mElAvZ/xp7OPh0k/6CdzA=; b=laK6EhS3ARE9Tsvrhw3X98tLXzhNpLYFQv0ArDgJP4qaWvFVwJLWaD85TLeJ1zM+Lr VE9R6ffDHbxrWhujNUinNhJtmzyI+u12rBhyXBgA8/zd2EKVHS4kb54hZL8hrmO3x0Ly OlYecipCo0qSgrzVrGj6pUNPZs9y+NBvqZSHfOq+ICXbwTwxDdyc+MWzs2cx4D1WBOvT 670VM6GF6pAjGctQTUMRA/KnDyYzbUsQN1nusJtksKpBdQ6t/GeegxHPgTNioEdwRuRY 9RrwwA/VaZMrdSzJbimZFlG7EQUcHrDkN3mkefCIfyZhcsndRAYnsIXNR+S9asNTFHLl 7wlA== X-Gm-Message-State: APjAAAUn278Oh6p4ByIAUdF+b57PXWNvTNrdPOahH+AgTq6MDPjBT/0j 2hyaAt/C+EjtvCIMcWe40aUHdN+zMsQ= X-Google-Smtp-Source: APXvYqxTwAPZkE88yEVgnb+MVBn6gp94zCy5ROF0Eb2h+HavHoh8GXYYKnKpkY2Acddl76Lc3Jh5SA== X-Received: by 2002:a17:90a:b30e:: with SMTP id d14mr21806186pjr.26.1566250707873; Mon, 19 Aug 2019 14:38:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:11 -0700 Message-Id: <20190819213755.26175-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 24/68] target/arm: Convert Packing, unpacking, saturation, and reversal X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 541 ++++++++++++++++++----------------------- target/arm/a32.decode | 32 +++ target/arm/t32.decode | 37 ++- 3 files changed, 300 insertions(+), 310 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index cf03527afc..d31e89f308 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -355,7 +355,7 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) } =20 /* Byteswap each halfword. */ -static void gen_rev16(TCGv_i32 var) +static void gen_rev16(TCGv_i32 dest, TCGv_i32 var) { TCGv_i32 tmp =3D tcg_temp_new_i32(); TCGv_i32 mask =3D tcg_const_i32(0x00ff00ff); @@ -363,17 +363,17 @@ static void gen_rev16(TCGv_i32 var) tcg_gen_and_i32(tmp, tmp, mask); tcg_gen_and_i32(var, var, mask); tcg_gen_shli_i32(var, var, 8); - tcg_gen_or_i32(var, var, tmp); + tcg_gen_or_i32(dest, var, tmp); tcg_temp_free_i32(mask); tcg_temp_free_i32(tmp); } =20 /* Byteswap low halfword and sign extend. */ -static void gen_revsh(TCGv_i32 var) +static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) { tcg_gen_ext16u_i32(var, var); tcg_gen_bswap16_i32(var, var); - tcg_gen_ext16s_i32(var, var); + tcg_gen_ext16s_i32(dest, var); } =20 /* 32x32->64 multiply. Marks inputs as dead. */ @@ -426,7 +426,7 @@ static void gen_swap_half(TCGv_i32 var) t0 =3D (t0 + t1) ^ tmp; */ =20 -static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) +static void gen_add16(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) { TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_xor_i32(tmp, t0, t1); @@ -434,9 +434,8 @@ static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) tcg_gen_andi_i32(t0, t0, ~0x8000); tcg_gen_andi_i32(t1, t1, ~0x8000); tcg_gen_add_i32(t0, t0, t1); - tcg_gen_xor_i32(t0, t0, tmp); + tcg_gen_xor_i32(dest, t0, tmp); tcg_temp_free_i32(tmp); - tcg_temp_free_i32(t1); } =20 /* Set N and Z flags from var. */ @@ -6340,7 +6339,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } break; case NEON_2RM_VREV16: - gen_rev16(tmp); + gen_rev16(tmp, tmp); break; case NEON_2RM_VCLS: switch (size) { @@ -9231,13 +9230,225 @@ DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8) #undef DO_PAR_ADDSUB #undef DO_PAR_ADDSUB_GE =20 +/* + * Packing, unpacking, saturation, and reversal + */ + +static bool trans_PKH(DisasContext *s, arg_PKH *a) +{ + TCGv_i32 tn, tm; + int shift =3D a->imm; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + tn =3D load_reg(s, a->rn); + tm =3D load_reg(s, a->rm); + if (a->tb) { + /* PKHTB */ + if (shift =3D=3D 0) { + shift =3D 31; + } + tcg_gen_sari_i32(tm, tm, shift); + tcg_gen_deposit_i32(tn, tn, tm, 0, 16); + } else { + /* PKHBT */ + tcg_gen_shli_i32(tm, tm, shift); + tcg_gen_deposit_i32(tn, tm, tn, 0, 16); + } + tcg_temp_free_i32(tm); + store_reg(s, a->rd, tn); + return true; +} + +static bool op_sat(DisasContext *s, arg_sat *a, + void (*gen)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp, satimm; + int shift =3D a->imm; + + if (!ENABLE_ARCH_6) { + return false; + } + + tmp =3D load_reg(s, a->rn); + if (a->sh) { + tcg_gen_sari_i32(tmp, tmp, shift ? shift : 31); + } else { + tcg_gen_shli_i32(tmp, tmp, shift); + } + + satimm =3D tcg_const_i32(a->satimm); + gen(tmp, cpu_env, tmp, satimm); + tcg_temp_free_i32(satimm); + + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SSAT(DisasContext *s, arg_sat *a) +{ + return op_sat(s, a, gen_helper_ssat); +} + +static bool trans_USAT(DisasContext *s, arg_sat *a) +{ + return op_sat(s, a, gen_helper_usat); +} + +static bool trans_SSAT16(DisasContext *s, arg_sat *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_sat(s, a, gen_helper_ssat16); +} + +static bool trans_USAT16(DisasContext *s, arg_sat *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_sat(s, a, gen_helper_usat16); +} + +static bool op_xta(DisasContext *s, arg_rrr_rot *a, + void (*gen_extract)(TCGv_i32, TCGv_i32), + void (*gen_add)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6) { + return false; + } + + tmp =3D load_reg(s, a->rm); + /* + * TODO: In many cases we could do a shift instead of a rotate. + * Combined with a simple extend, that becomes an extract. + */ + tcg_gen_rotri_i32(tmp, tmp, a->rot * 8); + gen_extract(tmp, tmp); + + if (a->rn !=3D 15) { + TCGv_i32 tmp2 =3D load_reg(s, a->rn); + gen_add(tmp, tmp, tmp2); + tcg_temp_free_i32(tmp2); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SXTAB(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext8s_i32, tcg_gen_add_i32); +} + +static bool trans_SXTAH(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext16s_i32, tcg_gen_add_i32); +} + +static bool trans_SXTAB16(DisasContext *s, arg_rrr_rot *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_xta(s, a, gen_helper_sxtb16, gen_add16); +} + +static bool trans_UXTAB(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext8u_i32, tcg_gen_add_i32); +} + +static bool trans_UXTAH(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext16u_i32, tcg_gen_add_i32); +} + +static bool trans_UXTAB16(DisasContext *s, arg_rrr_rot *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_xta(s, a, gen_helper_uxtb16, gen_add16); +} + +static bool trans_SEL(DisasContext *s, arg_rrr *a) +{ + TCGv_i32 t1, t2, t3; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + t3 =3D tcg_temp_new_i32(); + tcg_gen_ld_i32(t3, cpu_env, offsetof(CPUARMState, GE)); + gen_helper_sel_flags(t1, t3, t1, t2); + tcg_temp_free_i32(t3); + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool op_rr(DisasContext *s, arg_rr *a, + void (*gen)(TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp; + + tmp =3D load_reg(s, a->rm); + gen(tmp, tmp); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_REV(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, tcg_gen_bswap32_i32); +} + +static bool trans_REV16(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, gen_rev16); +} + +static bool trans_REVSH(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, gen_revsh); +} + +static bool trans_RBIT(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6T2) { + return false; + } + return op_rr(s, a, gen_helper_rbit); +} + /* * Legacy decoder. */ =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; + unsigned int cond, val, op1, i, rm, rs, rn, rd; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 tmp3; @@ -9546,112 +9757,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) /* Done by decodetree */ goto illegal_op; case 1: - if ((insn & 0x00700020) =3D=3D 0) { - /* Halfword pack. */ - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - shift =3D (insn >> 7) & 0x1f; - if (insn & (1 << 6)) { - /* pkhtb */ - if (shift =3D=3D 0) { - shift =3D 31; - } - tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16); - } else { - /* pkhbt */ - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00200020) =3D=3D 0x00200000) { - /* [us]sat */ - tmp =3D load_reg(s, rm); - shift =3D (insn >> 7) & 0x1f; - if (insn & (1 << 6)) { - if (shift =3D=3D 0) - shift =3D 31; - tcg_gen_sari_i32(tmp, tmp, shift); - } else { - tcg_gen_shli_i32(tmp, tmp, shift); - } - sh =3D (insn >> 16) & 0x1f; - tmp2 =3D tcg_const_i32(sh); - if (insn & (1 << 22)) - gen_helper_usat(tmp, cpu_env, tmp, tmp2); - else - gen_helper_ssat(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00300fe0) =3D=3D 0x00200f20) { - /* [us]sat16 */ - tmp =3D load_reg(s, rm); - sh =3D (insn >> 16) & 0x1f; - tmp2 =3D tcg_const_i32(sh); - if (insn & (1 << 22)) - gen_helper_usat16(tmp, cpu_env, tmp, tmp2); - else - gen_helper_ssat16(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00700fe0) =3D=3D 0x00000fa0) { - /* Select bytes. */ - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - tmp3 =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState= , GE)); - gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); - tcg_temp_free_i32(tmp3); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x000003e0) =3D=3D 0x00000060) { - tmp =3D load_reg(s, rm); - shift =3D (insn >> 10) & 3; - /* ??? In many cases it's not necessary to do a - rotate, a shift is sufficient. */ - tcg_gen_rotri_i32(tmp, tmp, shift * 8); - op1 =3D (insn >> 20) & 7; - switch (op1) { - case 0: gen_sxtb16(tmp); break; - case 2: gen_sxtb(tmp); break; - case 3: gen_sxth(tmp); break; - case 4: gen_uxtb16(tmp); break; - case 6: gen_uxtb(tmp); break; - case 7: gen_uxth(tmp); break; - default: goto illegal_op; - } - if (rn !=3D 15) { - tmp2 =3D load_reg(s, rn); - if ((op1 & 3) =3D=3D 0) { - gen_add16(tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - } - store_reg(s, rd, tmp); - } else if ((insn & 0x003f0f60) =3D=3D 0x003f0f20) { - /* rev */ - tmp =3D load_reg(s, rm); - if (insn & (1 << 22)) { - if (insn & (1 << 7)) { - gen_revsh(tmp); - } else { - ARCH(6T2); - gen_helper_rbit(tmp, tmp); - } - } else { - if (insn & (1 << 7)) - gen_rev16(tmp); - else - tcg_gen_bswap32_i32(tmp, tmp); - } - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - break; + /* Halfword pack, [US]SAT, [US]SAT16, SEL, REV et al */ + /* Done by decodetree */ + goto illegal_op; case 2: /* Multiplies (Type 3). */ switch ((insn >> 20) & 0x7) { case 5: @@ -9990,7 +10098,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uin= t32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t imm, shift, offset; + uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10245,151 +10353,18 @@ static void disas_thumb2_insn(DisasContext *s, u= int32_t insn) } break; case 5: - - op =3D (insn >> 21) & 0xf; - if (op =3D=3D 6) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - /* Halfword pack. */ - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - shift =3D ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3); - if (insn & (1 << 5)) { - /* pkhtb */ - if (shift =3D=3D 0) { - shift =3D 31; - } - tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16); - } else { - /* pkhbt */ - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else { - /* Data processing register constant shift. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } - break; + /* All in decodetree */ + goto illegal_op; case 13: /* Misc data processing. */ op =3D ((insn >> 22) & 6) | ((insn >> 7) & 1); if (op < 4 && (insn & 0xf000) !=3D 0xf000) goto illegal_op; switch (op) { case 0: /* Register controlled shift, in decodetree */ - goto illegal_op; - case 1: /* Sign/zero extend. */ - op =3D (insn >> 20) & 7; - switch (op) { - case 0: /* SXTAH, SXTH */ - case 1: /* UXTAH, UXTH */ - case 4: /* SXTAB, SXTB */ - case 5: /* UXTAB, UXTB */ - break; - case 2: /* SXTAB16, SXTB16 */ - case 3: /* UXTAB16, UXTB16 */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - default: - goto illegal_op; - } - if (rn !=3D 15) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - } - tmp =3D load_reg(s, rm); - shift =3D (insn >> 4) & 3; - /* ??? In many cases it's not necessary to do a - rotate, a shift is sufficient. */ - tcg_gen_rotri_i32(tmp, tmp, shift * 8); - op =3D (insn >> 20) & 7; - switch (op) { - case 0: gen_sxth(tmp); break; - case 1: gen_uxth(tmp); break; - case 2: gen_sxtb16(tmp); break; - case 3: gen_uxtb16(tmp); break; - case 4: gen_sxtb(tmp); break; - case 5: gen_uxtb(tmp); break; - default: - g_assert_not_reached(); - } - if (rn !=3D 15) { - tmp2 =3D load_reg(s, rn); - if ((op >> 1) =3D=3D 1) { - gen_add16(tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - } - store_reg(s, rd, tmp); - break; + case 1: /* Sign/zero extend, in decodetree */ case 2: /* SIMD add/subtract, in decodetree */ + case 3: /* Other data processing, in decodetree */ goto illegal_op; - case 3: /* Other data processing. */ - op =3D ((insn >> 17) & 0x38) | ((insn >> 4) & 7); - if (op < 4) { - /* Saturating add/subtract. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - switch (op) { - case 0x0a: /* rbit */ - case 0x08: /* rev */ - case 0x09: /* rev16 */ - case 0x0b: /* revsh */ - break; - case 0x10: /* sel */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - case 0x18: /* clz, in decodetree */ - case 0x20: /* crc32/crc32c, in decodetree */ - case 0x21: - case 0x22: - case 0x28: - case 0x29: - case 0x2a: - goto illegal_op; - default: - goto illegal_op; - } - tmp =3D load_reg(s, rn); - switch (op) { - case 0x0a: /* rbit */ - gen_helper_rbit(tmp, tmp); - break; - case 0x08: /* rev */ - tcg_gen_bswap32_i32(tmp, tmp); - break; - case 0x09: /* rev16 */ - gen_rev16(tmp); - break; - case 0x0b: /* revsh */ - gen_revsh(tmp); - break; - case 0x10: /* sel */ - tmp2 =3D load_reg(s, rm); - tmp3 =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE= )); - gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); - tcg_temp_free_i32(tmp3); - tcg_temp_free_i32(tmp2); - break; - default: - g_assert_not_reached(); - } - } - store_reg(s, rd, tmp); - break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. = */ switch ((insn >> 20) & 7) { case 0: /* 32 x 32 -> 32 */ @@ -10736,60 +10711,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) * - Data-processing (plain binary immediate) */ if (insn & (1 << 24)) { - if (insn & (1 << 20)) - goto illegal_op; - /* Bitfield/Saturate. */ - op =3D (insn >> 21) & 7; - imm =3D insn & 0x1f; - shift =3D ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); - if (rn =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp =3D load_reg(s, rn); - } - switch (op) { - case 2: /* Signed bitfield extract, in decodetree */ - case 6: /* Unsigned bitfield extract, in decodetree */ - case 3: /* Bitfield insert/clear, in decodetree */ - case 7: - goto illegal_op; - default: /* Saturate. */ - if (op & 1) { - tcg_gen_sari_i32(tmp, tmp, shift); - } else { - tcg_gen_shli_i32(tmp, tmp, shift); - } - tmp2 =3D tcg_const_i32(imm); - if (op & 4) { - /* Unsigned. */ - if ((op & 1) && shift =3D=3D 0) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_D= SP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - gen_helper_usat16(tmp, cpu_env, tmp, tmp2); - } else { - gen_helper_usat(tmp, cpu_env, tmp, tmp2); - } - } else { - /* Signed. */ - if ((op & 1) && shift =3D=3D 0) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_D= SP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - gen_helper_ssat16(tmp, cpu_env, tmp, tmp2); - } else { - gen_helper_ssat(tmp, cpu_env, tmp, tmp2); - } - } - tcg_temp_free_i32(tmp2); - break; - } - store_reg(s, rd, tmp); + /* Bitfield/Saturate, in decodetree */ + goto illegal_op; } else { imm =3D ((insn & 0x04000000) >> 15) | ((insn & 0x7000) >> 4) | (insn & 0xff); @@ -11481,8 +11404,8 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) tmp =3D load_reg(s, rn); switch (op1) { case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_rev16(tmp); break; - case 3: gen_revsh(tmp); break; + case 1: gen_rev16(tmp, tmp); break; + case 3: gen_revsh(tmp, tmp); break; default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 4dfd8133f7..4990eb3839 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -28,6 +28,7 @@ &s_rri_rot s rn rd imm rot &s_rrrr s rd rn rm ra &rrrr rd rn rm ra +&rrr_rot rd rn rm rot &rrr rd rn rm &rr rd rm &ri rd imm @@ -43,6 +44,8 @@ &ldrex rn rt rt2 imm &bfx rd rn lsb widthm1 &bfi rd rn lsb msb +&sat rd rn satimm imm sh +&pkh rd rn rm imm tb =20 # Data-processing (register) =20 @@ -454,3 +457,32 @@ UHSAX .... 0110 0111 .... .... 1111 0101 ..= .. @rndm UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm + +# Packing, unpacking, saturation, and reversal + +PKH ---- 0110 1000 rn:4 rd:4 imm:5 tb:1 01 rm:4 &pkh + +@sat ---- .... ... satimm:5 rd:4 imm:5 sh:1 .. rn:4 &sat +@sat16 ---- .... .... satimm:4 rd:4 .... .... rn:4 \ + &sat imm=3D0 sh=3D0 + +SSAT .... 0110 101. .... .... .... ..01 .... @sat +USAT .... 0110 111. .... .... .... ..01 .... @sat + +SSAT16 .... 0110 1010 .... .... 1111 0011 .... @sat16 +USAT16 .... 0110 1110 .... .... 1111 0011 .... @sat16 + +@rrr_rot ---- .... .... rn:4 rd:4 rot:2 ...... rm:4 &rrr_rot + +SXTAB16 .... 0110 1000 .... .... ..00 0111 .... @rrr_rot +SXTAB .... 0110 1010 .... .... ..00 0111 .... @rrr_rot +SXTAH .... 0110 1011 .... .... ..00 0111 .... @rrr_rot +UXTAB16 .... 0110 1100 .... .... ..00 0111 .... @rrr_rot +UXTAB .... 0110 1110 .... .... ..00 0111 .... @rrr_rot +UXTAH .... 0110 1111 .... .... ..00 0111 .... @rrr_rot + +SEL .... 0110 1000 .... .... 1111 1011 .... @rndm +REV .... 0110 1011 1111 .... 1111 0011 .... @rdm +REV16 .... 0110 1011 1111 .... 1111 1011 .... @rdm +REVSH .... 0110 1111 1111 .... 1111 1011 .... @rdm +RBIT .... 0110 1111 1111 .... 1111 0011 .... @rdm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c899c56766..71f6d728f2 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -25,6 +25,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra +&rrr_rot !extern rd rn rm rot &rrr !extern rd rn rm &rr !extern rd rm &ri !extern rd imm @@ -40,6 +41,8 @@ &ldrex !extern rn rt rt2 imm &bfx !extern rd rn lsb widthm1 &bfi !extern rd rn lsb msb +&sat !extern rd rn satimm imm sh +&pkh !extern rd rn rm imm tb =20 # Data-processing (register) =20 @@ -69,7 +72,8 @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... ....= @s_rrr_shi TEQ_xrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi } -# PKHBT, PKHTB at opc1 =3D 0110 +PKH 1110101 0110 0 rn:4 0 ... rd:4 .. tb:1 0 rm:4 \ + &pkh imm=3D%imm5_12_6 { CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi @@ -148,6 +152,20 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... .....= ... @s_rri_rot =20 # Saturate, bitfield =20 +@sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \ + &sat imm=3D%imm5_12_6 +@sat16 .... .... .. . . rn:4 . ... rd:4 .. . satimm:5 \ + &sat sh=3D0 imm=3D0 + +{ + SSAT16 1111 0011 001 0 .... 0 000 .... 00 0 ..... @sat16 + SSAT 1111 0011 00. 0 .... 0 ... .... .. 0 ..... @sat +} +{ + USAT16 1111 0011 101 0 .... 0 000 .... 00 0 ..... @sat16 + USAT 1111 0011 10. 0 .... 0 ... .... .. 0 ..... @sat +} + @bfx .... .... ... . rn:4 . ... rd:4 .. . widthm1:5 \ &bfx lsb=3D%imm5_12_6 @bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \ @@ -224,7 +242,13 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 ..= .. @rndm CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm =20 +SEL 1111 1010 1010 .... 1111 .... 1000 .... @rndm + # Note rn !=3D rm is CONSTRAINED UNPREDICTABLE; we choose to ignore rn. +REV 1111 1010 1001 ---- 1111 .... 1000 .... @rdm +REV16 1111 1010 1001 ---- 1111 .... 1001 .... @rdm +RBIT 1111 1010 1001 ---- 1111 .... 1010 .... @rdm +REVSH 1111 1010 1001 ---- 1111 .... 1011 .... @rdm CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm =20 # Branches and miscellaneous control @@ -501,3 +525,14 @@ SHSAX 1111 1010 1110 .... 1111 .... 0010 ..= .. @rndm USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm + +# Register extends + +@rrr_rot .... .... .... rn:4 .... rd:4 .. rot:2 rm:4 &rrr_rot + +SXTAH 1111 1010 0000 .... 1111 .... 10.. .... @rrr_rot +UXTAH 1111 1010 0001 .... 1111 .... 10.. .... @rrr_rot +SXTAB16 1111 1010 0010 .... 1111 .... 10.. .... @rrr_rot +UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot +SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot +UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 25/68] target/arm: Convert Signed multiply, signed and unsigned divide X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 463 ++++++++++++++++++----------------------- target/arm/a32.decode | 22 ++ target/arm/t32.decode | 18 ++ 3 files changed, 247 insertions(+), 256 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d31e89f308..7962ac49e6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9442,18 +9442,217 @@ static bool trans_RBIT(DisasContext *s, arg_rr *a) return op_rr(s, a, gen_helper_rbit); } =20 +/* + * Signed multiply, signed and unsigned divide + */ + +static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + if (m_swap) { + gen_swap_half(t2); + } + gen_smul_dual(t1, t2); + + if (sub) { + /* This subtraction cannot overflow. */ + tcg_gen_sub_i32(t1, t1, t2); + } else { + /* + * This addition cannot overflow 32 bits; however it may + * overflow considered as a signed operation, in which case + * we must set the Q flag. + */ + gen_helper_add_setq(t1, cpu_env, t1, t2); + } + tcg_temp_free_i32(t2); + + if (a->ra !=3D 15) { + t2 =3D load_reg(s, a->ra); + gen_helper_add_setq(t1, cpu_env, t1, t2); + tcg_temp_free_i32(t2); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SMLAD(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, false, false); +} + +static bool trans_SMLADX(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, true, false); +} + +static bool trans_SMLSD(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, false, true); +} + +static bool trans_SMLSDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, true, true); +} + +static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) +{ + TCGv_i32 t1, t2; + TCGv_i64 l1, l2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + if (m_swap) { + gen_swap_half(t2); + } + gen_smul_dual(t1, t2); + + l1 =3D tcg_temp_new_i64(); + l2 =3D tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(l1, t1); + tcg_gen_ext_i32_i64(l2, t2); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); + + if (sub) { + tcg_gen_sub_i64(l1, l1, l2); + } else { + tcg_gen_add_i64(l1, l1, l2); + } + tcg_temp_free_i64(l2); + + gen_addq(s, l1, a->ra, a->rd); + gen_storeq_reg(s, a->ra, a->rd, l1); + tcg_temp_free_i64(l1); + return true; +} + +static bool trans_SMLALD(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, false, false); +} + +static bool trans_SMLALDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, true, false); +} + +static bool trans_SMLSLD(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, false, true); +} + +static bool trans_SMLSLDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, true, true); +} + +static bool op_smmla(DisasContext *s, arg_rrrr *a, bool round, bool sub) +{ + TCGv_i32 t1, t2; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + tcg_gen_muls2_i32(t2, t1, t1, t2); + + if (a->ra !=3D 15) { + TCGv_i32 t3 =3D load_reg(s, a->ra); + if (sub) { + tcg_gen_sub_i32(t1, t1, t3); + } else { + tcg_gen_add_i32(t1, t1, t3); + } + tcg_temp_free_i32(t3); + } + if (round) { + tcg_gen_shri_i32(t2, t2, 31); + tcg_gen_add_i32(t1, t1, t2); + } + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SMMLA(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, false, false); +} + +static bool trans_SMMLAR(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, true, false); +} + +static bool trans_SMMLS(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, false, true); +} + +static bool trans_SMMLSR(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, true, true); +} + +static bool op_div(DisasContext *s, arg_rrr *a, bool u) +{ + TCGv_i32 t1, t2; + + if (s->thumb + ? !dc_isar_feature(thumb_div, s) + : !dc_isar_feature(arm_div, s)) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + if (u) { + gen_helper_udiv(t1, t1, t2); + } else { + gen_helper_sdiv(t1, t1, t2); + } + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SDIV(DisasContext *s, arg_rrr *a) +{ + return op_div(s, a, false); +} + +static bool trans_UDIV(DisasContext *s, arg_rrr *a) +{ + return op_div(s, a, true); +} + /* * Legacy decoder. */ =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rm, rs, rn, rd; + unsigned int cond, val, op1, i, rn, rd; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 tmp3; TCGv_i32 addr; - TCGv_i64 tmp64; =20 /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -9736,148 +9935,10 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) switch(op1) { case 0x0: case 0x1: - /* multiplies, extra load/stores */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - break; case 0x4: case 0x5: - goto do_ldst; case 0x6: case 0x7: - if (insn & (1 << 4)) { - ARCH(6); - /* Armv6 Media instructions. */ - rm =3D insn & 0xf; - rn =3D (insn >> 16) & 0xf; - rd =3D (insn >> 12) & 0xf; - rs =3D (insn >> 8) & 0xf; - switch ((insn >> 23) & 3) { - case 0: /* Parallel add/subtract. */ - /* Done by decodetree */ - goto illegal_op; - case 1: - /* Halfword pack, [US]SAT, [US]SAT16, SEL, REV et al */ - /* Done by decodetree */ - goto illegal_op; - case 2: /* Multiplies (Type 3). */ - switch ((insn >> 20) & 0x7) { - case 5: - if (((insn >> 6) ^ (insn >> 7)) & 1) { - /* op2 not 00x or 11x : UNDEF */ - goto illegal_op; - } - /* Signed multiply most significant [accumulate]. - (SMMUL, SMMLA, SMMLS) */ - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); - - if (rd !=3D 15) { - tmp3 =3D load_reg(s, rd); - if (insn & (1 << 6)) { - tcg_gen_sub_i32(tmp, tmp, tmp3); - } else { - tcg_gen_add_i32(tmp, tmp, tmp3); - } - tcg_temp_free_i32(tmp3); - } - if (insn & (1 << 5)) { - /* - * Adding 0x80000000 to the 64-bit quantity - * means that we have carry in to the high - * word when the low word has the high bit set. - */ - tcg_gen_shri_i32(tmp2, tmp2, 31); - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rn, tmp); - break; - case 0: - case 4: - /* SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD */ - if (insn & (1 << 7)) { - goto illegal_op; - } - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - if (insn & (1 << 5)) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (insn & (1 << 22)) { - /* smlald, smlsld */ - TCGv_i64 tmp64_2; - - tmp64 =3D tcg_temp_new_i64(); - tmp64_2 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_gen_ext_i32_i64(tmp64_2, tmp2); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - if (insn & (1 << 6)) { - tcg_gen_sub_i64(tmp64, tmp64, tmp64_2); - } else { - tcg_gen_add_i64(tmp64, tmp64, tmp64_2); - } - tcg_temp_free_i64(tmp64_2); - gen_addq(s, tmp64, rd, rn); - gen_storeq_reg(s, rd, rn, tmp64); - tcg_temp_free_i64(tmp64); - } else { - /* smuad, smusd, smlad, smlsd */ - if (insn & (1 << 6)) { - /* This subtraction cannot overflow. */ - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - /* This addition cannot overflow 32 bits; - * however it may overflow considered as a - * signed operation, in which case we must= set - * the Q flag. - */ - gen_helper_add_setq(tmp, cpu_env, tmp, tmp= 2); - } - tcg_temp_free_i32(tmp2); - if (rd !=3D 15) - { - tmp2 =3D load_reg(s, rd); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp= 2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rn, tmp); - } - break; - case 1: - case 3: - /* SDIV, UDIV */ - if (!dc_isar_feature(arm_div, s)) { - goto illegal_op; - } - if (((insn >> 5) & 7) || (rd !=3D 15)) { - goto illegal_op; - } - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - if (insn & (1 << 21)) { - gen_helper_udiv(tmp, tmp, tmp2); - } else { - gen_helper_sdiv(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rn, tmp); - break; - default: - goto illegal_op; - } - break; - case 3: - /* USAD, BFI, BFC, SBFX, UBFX */ - /* Done by decodetree */ - goto illegal_op; - } - break; - } - do_ldst: /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; case 0x08: @@ -10102,9 +10163,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 tmp3; TCGv_i32 addr; - TCGv_i64 tmp64; int op; =20 /* @@ -10365,119 +10424,11 @@ static void disas_thumb2_insn(DisasContext *s, u= int32_t insn) case 2: /* SIMD add/subtract, in decodetree */ case 3: /* Other data processing, in decodetree */ goto illegal_op; - case 4: case 5: /* 32-bit multiply. Sum of absolute differences. = */ - switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ - case 1: /* 16 x 16 -> 32 */ - case 3: /* 32 * 16 -> 32msb */ - case 7: /* Unsigned sum of absolute differences. */ - /* in decodetree */ - goto illegal_op; - case 2: /* Dual multiply add. */ - case 4: /* Dual multiply subtract. */ - case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - } - op =3D (insn >> 4) & 0xf; - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - switch ((insn >> 20) & 7) { - case 2: /* Dual multiply add. */ - case 4: /* Dual multiply subtract. */ - if (op) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (insn & (1 << 22)) { - /* This subtraction cannot overflow. */ - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - /* This addition cannot overflow 32 bits; - * however it may overflow considered as a signed - * operation, in which case we must set the Q flag. - */ - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - if (rs !=3D 15) - { - tmp2 =3D load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; - case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ - tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); - if (rs !=3D 15) { - tmp3 =3D load_reg(s, rs); - if (insn & (1 << 20)) { - tcg_gen_add_i32(tmp, tmp, tmp3); - } else { - tcg_gen_sub_i32(tmp, tmp, tmp3); - } - tcg_temp_free_i32(tmp3); - } - if (insn & (1 << 4)) { - /* - * Adding 0x80000000 to the 64-bit quantity - * means that we have carry in to the high - * word when the low word has the high bit set. - */ - tcg_gen_shri_i32(tmp2, tmp2, 31); - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - break; - } - store_reg(s, rd, tmp); - break; - case 6: case 7: /* 64-bit multiply, Divide. */ - op =3D ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70); - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - if ((op & 0x50) =3D=3D 0x10) { - /* sdiv, udiv */ - if (!dc_isar_feature(thumb_div, s)) { - goto illegal_op; - } - if (op & 0x20) - gen_helper_udiv(tmp, tmp, tmp2); - else - gen_helper_sdiv(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((op & 0xe) =3D=3D 0xc) { - /* Dual multiply accumulate long. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - if (op & 1) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (op & 0x10) { - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - /* BUGFIX */ - tmp64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - gen_addq(s, tmp64, rs, rd); - gen_storeq_reg(s, rs, rd, tmp64); - tcg_temp_free_i64(tmp64); - } else { - /* Signed/unsigned 64-bit multiply, in decodetree */ - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - break; + case 4: case 5: + /* 32-bit multiply. Sum of absolute differences, in decodetre= e */ + goto illegal_op; + case 6: case 7: /* 64-bit multiply, Divide, in decodetree */ + goto illegal_op; } break; case 6: case 7: case 14: case 15: diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 4990eb3839..d7a333b90b 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -486,3 +486,25 @@ REV .... 0110 1011 1111 .... 1111 0011 ..= .. @rdm REV16 .... 0110 1011 1111 .... 1111 1011 .... @rdm REVSH .... 0110 1111 1111 .... 1111 1011 .... @rdm RBIT .... 0110 1111 1111 .... 1111 0011 .... @rdm + +# Signed multiply, signed and unsigned divide + +@rdmn ---- .... .... rd:4 .... rm:4 .... rn:4 &rrr + +SMLAD .... 0111 0000 .... .... .... 0001 .... @rdamn +SMLADX .... 0111 0000 .... .... .... 0011 .... @rdamn +SMLSD .... 0111 0000 .... .... .... 0101 .... @rdamn +SMLSDX .... 0111 0000 .... .... .... 0111 .... @rdamn + +SDIV .... 0111 0001 .... 1111 .... 0001 .... @rdmn +UDIV .... 0111 0011 .... 1111 .... 0001 .... @rdmn + +SMLALD .... 0111 0100 .... .... .... 0001 .... @rdamn +SMLALDX .... 0111 0100 .... .... .... 0011 .... @rdamn +SMLSLD .... 0111 0100 .... .... .... 0101 .... @rdamn +SMLSLDX .... 0111 0100 .... .... .... 0111 .... @rdamn + +SMMLA .... 0111 0101 .... .... .... 0001 .... @rdamn +SMMLAR .... 0111 0101 .... .... .... 0011 .... @rdamn +SMMLS .... 0111 0101 .... .... .... 1101 .... @rdamn +SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 71f6d728f2..677acb698d 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -228,6 +228,24 @@ SMLALTT 1111 1011 1100 .... .... .... 1011 ..= .. @rnadm # usad8 is usada8 w/ ra=3D15 USADA8 1111 1011 0111 .... .... .... 0000 .... @rnadm =20 +SMLAD 1111 1011 0010 .... .... .... 0000 .... @rnadm +SMLADX 1111 1011 0010 .... .... .... 0001 .... @rnadm +SMLSD 1111 1011 0100 .... .... .... 0000 .... @rnadm +SMLSDX 1111 1011 0100 .... .... .... 0001 .... @rnadm + +SMLALD 1111 1011 1100 .... .... .... 1100 .... @rnadm +SMLALDX 1111 1011 1100 .... .... .... 1101 .... @rnadm +SMLSLD 1111 1011 1101 .... .... .... 1100 .... @rnadm +SMLSLDX 1111 1011 1101 .... .... .... 1101 .... @rnadm + +SMMLA 1111 1011 0101 .... .... .... 0000 .... @rnadm +SMMLAR 1111 1011 0101 .... .... .... 0001 .... @rnadm +SMMLS 1111 1011 0110 .... .... .... 0000 .... @rnadm +SMMLSR 1111 1011 0110 .... .... .... 0001 .... @rnadm + +SDIV 1111 1011 1001 .... 1111 .... 1111 .... @rndm +UDIV 1111 1011 1011 .... 1111 .... 1111 .... @rndm + # Data-processing (two source registers) =20 QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VezSzLCtFs9kY3Fe5wLKu5xLpiNSXhDdz7VdFtZV8bc=; b=ulv9UWqoykjQuoORkZKHART9F1UQJ5YF4smszkfmZD96jkaFF6AzK63EezyXvAV5mT ZrJcDoz0PwXVM3sWokk/i825/SRehg/pVS8jd0rahdv7BdbVIIeZYlxmJZS90oyrgodd VZ2biauI+FxWaMdq+3SvaUvpfVWhu/3akhXY5ptKHzoa+Vo2GcrJf0W1uxIk4hNWOhfF 5C8QrBMNHKXs/nBTab5ajRwqXlOMhtPv4hJupD/0MOYDYqH/DGLgZlsx08m7JoXXjYkx kMQTf8IPWwNNMSCJsKOWpWrX8TVzqUzie0oc+NT+kWyh71n43GtZrX1dW3BP9F74+2lr tioQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VezSzLCtFs9kY3Fe5wLKu5xLpiNSXhDdz7VdFtZV8bc=; b=OWNssDYYBTR3lR/fHGb3waBUBjd5SKWpARYPIRpDv3gYWFHe4Bu8ZDU/ORGhJWRIgq BImglHdO/ppfwIH/5ljJP89l8DFaIjaMb1rc7ll/HMpkmKTglOHqMajcDGWhm3QoY1Yq xP/C+cGvolQFGF3Ct9Hb8RfKA4OqXO3lqyNnP3QogfehHhA3PvDDmjIyQL9ern2cfr2P 7tIV9zqlpOcvvA3ju5zUunNZlc64xZUTyp+OxxP0KlFP1W6DE0K9OhFf+xtS2UmcPHo9 IL7tesLXDmXPpEDbR/upbrRRGOCVcQk1PADQhnaEk2lj1U9PSj1oKYS3q0HaMwU74vb6 K+FQ== X-Gm-Message-State: APjAAAX0WcMCnKxOMpq2aGtC5C0pE/y1rP0iZgVWEeR2POX8o2O2emzm rg0Lg/OLNvaO9LCJd4Cz27L25STorIY= X-Google-Smtp-Source: APXvYqxpuLhojcnlaRKl5Zrc2InKU6heGumh9JRDNXn3cQjeg4B8kg1n9Yz3rmJEr1xxu2P33pU7RA== X-Received: by 2002:a17:902:223:: with SMTP id 32mr25241732plc.220.1566250709791; Mon, 19 Aug 2019 14:38:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:13 -0700 Message-Id: <20190819213755.26175-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 26/68] target/arm: Convert MOVW, MOVT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 89 ++++++++++++++++-------------------------- target/arm/a32.decode | 6 +++ target/arm/t32.decode | 9 +++++ 3 files changed, 48 insertions(+), 56 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 7962ac49e6..81eae286e8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7841,6 +7841,34 @@ static bool trans_ADR(DisasContext *s, arg_ri *a) return true; } =20 +static bool trans_MOVW(DisasContext *s, arg_MOVW *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp =3D tcg_const_i32(a->imm); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MOVT(DisasContext *s, arg_MOVW *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp =3D load_reg(s, a->rd); + tcg_gen_ext16u_i32(tmp, tmp); + tcg_gen_ori_i32(tmp, tmp, a->imm << 16); + store_reg(s, a->rd, tmp); + return true; +} + /* * Multiply and multiply accumulate */ @@ -9649,7 +9677,7 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a) =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rn, rd; + unsigned int cond, val, op1, i, rn; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -9898,26 +9926,8 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) /* fall back to legacy decoder */ =20 if ((insn & 0x0f900000) =3D=3D 0x03000000) { - if ((insn & (1 << 21)) =3D=3D 0) { - ARCH(6T2); - rd =3D (insn >> 12) & 0xf; - val =3D ((insn >> 4) & 0xf000) | (insn & 0xfff); - if ((insn & (1 << 22)) =3D=3D 0) { - /* MOVW */ - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, val); - } else { - /* MOVT */ - tmp =3D load_reg(s, rd); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_ori_i32(tmp, tmp, val << 16); - } - store_reg(s, rd, tmp); - } else { - /* MSR (immediate) and hints */ - /* All done in decodetree. Illegal ops already signalled. */ - g_assert_not_reached(); - } + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; } else if ((insn & 0x0f900000) =3D=3D 0x01000000 && (insn & 0x00000090) !=3D 0x00000090) { /* miscellaneous instructions */ @@ -10655,42 +10665,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) /* * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx * - Data-processing (modified immediate, plain binary immedi= ate) + * All in decodetree. */ - if (insn & (1 << 25)) { - /* - * 0b1111_0x1x_xxxx_0xxx_xxxx_xxxx - * - Data-processing (plain binary immediate) - */ - if (insn & (1 << 24)) { - /* Bitfield/Saturate, in decodetree */ - goto illegal_op; - } else { - imm =3D ((insn & 0x04000000) >> 15) - | ((insn & 0x7000) >> 4) | (insn & 0xff); - if (insn & (1 << 22)) { - /* 16-bit immediate. */ - imm |=3D (insn >> 4) & 0xf000; - if (insn & (1 << 23)) { - /* movt */ - tmp =3D load_reg(s, rd); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_ori_i32(tmp, tmp, imm << 16); - } else { - /* movw */ - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, imm); - } - store_reg(s, rd, tmp); - } else { - /* Add/sub 12-bit immediate, in decodetree */ - goto illegal_op; - } - } - } else { - /* Data-processing (modified immediate) */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } + goto illegal_op; } break; case 12: diff --git a/target/arm/a32.decode b/target/arm/a32.decode index d7a333b90b..341882e637 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -73,6 +73,12 @@ MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 ..= .. @s_rxr_shi BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi =20 +%imm16 16:4 0:12 +@mov16 ---- .... .... .... rd:4 ............ &ri imm=3D%i= mm16 + +MOVW .... 0011 0000 .... .... ............ @mov16 +MOVT .... 0011 0100 .... .... ............ @mov16 + # Data-processing (register-shifted register) =20 @s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \ diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 677acb698d..f315fde0f4 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -150,6 +150,15 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... .....= ... @s_rri_rot SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 } =20 +# Move Wide + +%imm16_26_16_12_0 16:4 26:1 12:3 0:8 +@mov16 .... .... .... .... .... rd:4 .... .... \ + &ri imm=3D%imm16_26_16_12_0 + +MOVW 1111 0.10 0100 .... 0 ... .... ........ @mov16 +MOVT 1111 0.10 1100 .... 0 ... .... ........ @mov16 + # Saturate, bitfield =20 @sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \ --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566251956; cv=none; d=zoho.com; s=zohoarc; b=BXULyell9uASP+GpB2dcdD70fLPt+QXRu8X5wJgJlXuYijBBiLcQns/CIFMceLtXdSmodXf0LT4w9ViwW4xoa3l09mltbPyicNKf4+Mm8PolXPn/l2zutCWkD+LwbWSRKEJEf+6YymuN+1OGDpyosJuTEBnMxJA6qt8gK6dUpdk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566251956; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=E5jCqhd4j782M1OXjBueNYjMszsPuCY448GdoglEKE4=; b=OGFBE5TSnXEh9liLNTDa8zfznZm9/wyAL6XfQZBiIiGiSLVS3BY0D4zfQMX1os/36Iob15L/CMSq+PISMuZTRgi7Js8BVjdvgd+jJTSB/utDawh1hq25fmG6IRX6Yx2+mtmqT2kEQrZF1gQNa6ifWEsUBEW4PTwyUkvQ5uANXs8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566251956073426.713174424208; Mon, 19 Aug 2019 14:59:16 -0700 (PDT) Received: from localhost ([::1]:59326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpgG-0003Oa-73 for importer@patchew.org; Mon, 19 Aug 2019 17:59:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59151) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMJ-00023t-67 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMG-0006LR-ML for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:34 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:35396) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMG-0006Kk-E8 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:32 -0400 Received: by mail-pg1-x544.google.com with SMTP id n4so1936197pgv.2 for ; Mon, 19 Aug 2019 14:38:32 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=E5jCqhd4j782M1OXjBueNYjMszsPuCY448GdoglEKE4=; b=SrpWT4l3bKxHSBB33gh3xRkrSURvlXj3ZVyZLImMhl86D4Jh1Y7sLf2ftdW5e5qSpA F3M3UMUYWtM4rQebyBbP8HAFRXvjazeV7lH1YBqI9jAcAuyQZQwyytuI9IXAL6XaoFTJ cVKr7qg1WSmXtciVPMRuZs6b9MB5YTd0IrczNBta7QivMwiPCgdZvzLluIfl1vBtkcbR Y9WXdzYq7eF/NSLAQkXWWptdNamPdSTrqZwcUh/oLdoMGYgkyzh0nyy3jFTYxO5VFHIn C+3NpgJgojprqLCWqPTzqyz7TDnC0Pn3ADiQdUMwqPfljeZvk/1qRUYL8SSOkkyKjv4g oReA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=E5jCqhd4j782M1OXjBueNYjMszsPuCY448GdoglEKE4=; b=MT1GKygjmkGfJLuxwzIwoRqsWLngWraasGYoHzSzRbsraPcPZipQzdXksnyaArCbMV yWPthzHZHgzgVzjpmEs3Pilkc0u+spmQK0dD590XcDhz5TARe0w/imTMhpy6atxrmuzo +3cg/NnnJiK342PFynjEs2RTdgZHq/Vf+SCZ/Zjvz5MX7T8knBCKwgO/pzkj7EEc7bDl +C50yBUQFOGyE3mW1hjQP1oqbXItLi5hb/5dRbofnEUn+fesSHxALa7JeyaQtc4gLR+L RcZeb6yX2M2zvFRgy+y/Cbb+I6H5MJjv0q18zY9aysAU3fhPSTditrgsNimDlySSvP/w tTPg== X-Gm-Message-State: APjAAAUIouKN+iyxVVwUj5ISXQbzJEt5QY54fiPzdeRnvG49JKz2nyGH fIYkV5tjVJ/gBR6Ft9VUCOs8uOcu2SE= X-Google-Smtp-Source: APXvYqxxNPe4TBF/k960pfQjtAPzLdco3jVNdH+SXtW7JOdqV5LDe0O/ou4kNn1MzWNrbFEfaDxoGA== X-Received: by 2002:a17:90b:949:: with SMTP id dw9mr23134183pjb.49.1566250710980; Mon, 19 Aug 2019 14:38:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:14 -0700 Message-Id: <20190819213755.26175-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v2 27/68] target/arm: Convert LDM, STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This includes a minor bug fix to LDM (user), which requires bit 21 to be 0, which means no writeback. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 426 ++++++++++++++++++++++------------------- target/arm/a32.decode | 6 + target/arm/t32.decode | 10 + 3 files changed, 241 insertions(+), 201 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 81eae286e8..4451adbb97 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9671,6 +9671,227 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a) return op_div(s, a, true); } =20 +/* + * Block data transfer + */ + +static TCGv_i32 op_addr_block_pre(DisasContext *s, arg_ldst_block *a, int = n) +{ + TCGv_i32 addr =3D load_reg(s, a->rn); + + if (a->b) { + if (a->i) { + /* pre increment */ + tcg_gen_addi_i32(addr, addr, 4); + } else { + /* pre decrement */ + tcg_gen_addi_i32(addr, addr, -(n * 4)); + } + } else if (!a->i && n !=3D 1) { + /* post decrement */ + tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); + } + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + /* + * If the writeback is incrementing SP rather than + * decrementing it, and the initial SP is below the + * stack limit but the final written-back SP would + * be above, then then we must not perform any memory + * accesses, but it is IMPDEF whether we generate + * an exception. We choose to do so in this case. + * At this point 'addr' is the lowest address, so + * either the original SP (if incrementing) or our + * final SP (if decrementing), so that's what we check. + */ + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + return addr; +} + +static void op_addr_block_post(DisasContext *s, arg_ldst_block *a, + TCGv_i32 addr, int n) +{ + if (a->w) { + /* write back */ + if (!a->b) { + if (a->i) { + /* post increment */ + tcg_gen_addi_i32(addr, addr, 4); + } else { + /* post decrement */ + tcg_gen_addi_i32(addr, addr, -(n * 4)); + } + } else if (!a->i && n !=3D 1) { + /* pre decrement */ + tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } +} + +static bool op_stm(DisasContext *s, arg_ldst_block *a) +{ + int i, j, n, list, mem_idx; + bool user =3D a->u; + TCGv_i32 addr, tmp, tmp2; + + if (user) { + /* STM (user) */ + if (IS_USER(s)) { + /* Only usable in supervisor mode. */ + return false; + } + } + + list =3D a->list; + n =3D ctpop16(list); + /* TODO: test invalid n =3D=3D 0 case */ + + addr =3D op_addr_block_pre(s, a, n); + mem_idx =3D get_mem_index(s); + + for (i =3D j =3D 0; i < 16; i++) { + if (!(list & (1 << i))) { + continue; + } + + if (user && i !=3D 15) { + tmp =3D tcg_temp_new_i32(); + tmp2 =3D tcg_const_i32(i); + gen_helper_get_user_reg(tmp, cpu_env, tmp2); + tcg_temp_free_i32(tmp2); + } else { + tmp =3D load_reg(s, i); + } + gen_aa32_st32(s, tmp, addr, mem_idx); + tcg_temp_free_i32(tmp); + + /* No need to add after the last transfer. */ + if (++j !=3D n) { + tcg_gen_addi_i32(addr, addr, 4); + } + } + + op_addr_block_post(s, a, addr, n); + return true; +} + +static bool trans_STM(DisasContext *s, arg_ldst_block *a) +{ + return op_stm(s, a); +} + +static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback register in register list is UNPREDICATABLE for T32. */ + if (a->w && (a->list & (1 << a->rn))) { + return false; + } + return op_stm(s, a); +} + +static bool do_ldm(DisasContext *s, arg_ldst_block *a) +{ + int i, j, n, list, mem_idx; + bool loaded_base; + bool user =3D a->u; + bool exc_return =3D false; + TCGv_i32 addr, tmp, tmp2, loaded_var; + + if (user) { + /* LDM (user), LDM (exception return) */ + if (IS_USER(s)) { + /* Only usable in supervisor mode. */ + return false; + } + if (extract32(a->list, 15, 1)) { + exc_return =3D true; + user =3D false; + } else { + /* LDM (user) does not allow writeback. */ + if (a->w) { + return false; + } + } + } + + list =3D a->list; + n =3D ctpop16(list); + /* TODO: test invalid n =3D=3D 0 case */ + + addr =3D op_addr_block_pre(s, a, n); + mem_idx =3D get_mem_index(s); + loaded_base =3D false; + loaded_var =3D NULL; + + for (i =3D j =3D 0; i < 16; i++) { + if (!(list & (1 << i))) { + continue; + } + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld32u(s, tmp, addr, mem_idx); + if (user) { + tmp2 =3D tcg_const_i32(i); + gen_helper_set_user_reg(cpu_env, tmp2, tmp); + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + } else if (i =3D=3D a->rn) { + loaded_var =3D tmp; + loaded_base =3D true; + } else if (i =3D=3D 15 && exc_return) { + store_pc_exc_ret(s, tmp); + } else { + store_reg_from_load(s, i, tmp); + } + + /* No need to add after the last transfer. */ + if (++j !=3D n) { + tcg_gen_addi_i32(addr, addr, 4); + } + } + + op_addr_block_post(s, a, addr, n); + + if (loaded_base) { + store_reg(s, a->rn, loaded_var); + } + + if (exc_return) { + /* Restore CPSR from SPSR. */ + tmp =3D load_cpu_field(spsr); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_cpsr_write_eret(cpu_env, tmp); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } + tcg_temp_free_i32(tmp); + /* Must exit loop to check un-masked IRQs */ + s->base.is_jmp =3D DISAS_EXIT; + } + return true; +} + +static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) +{ + return do_ldm(s, a); +} + +static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback register in register list is UNPREDICATABLE for T32. */ + if (a->w && (a->list & (1 << a->rn))) { + return false; + } + return do_ldm(s, a); +} + /* * Legacy decoder. */ @@ -9949,142 +10170,10 @@ static void disas_arm_insn(DisasContext *s, unsig= ned int insn) case 0x5: case 0x6: case 0x7: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; case 0x08: case 0x09: - { - int j, n, loaded_base; - bool exc_return =3D false; - bool is_load =3D extract32(insn, 20, 1); - bool user =3D false; - TCGv_i32 loaded_var; - /* load/store multiple words */ - /* XXX: store correct base if write back */ - if (insn & (1 << 22)) { - /* LDM (user), LDM (exception return) and STM (user) */ - if (IS_USER(s)) - goto illegal_op; /* only usable in supervisor mode= */ - - if (is_load && extract32(insn, 15, 1)) { - exc_return =3D true; - } else { - user =3D true; - } - } - rn =3D (insn >> 16) & 0xf; - addr =3D load_reg(s, rn); - - /* compute total size */ - loaded_base =3D 0; - loaded_var =3D NULL; - n =3D 0; - for (i =3D 0; i < 16; i++) { - if (insn & (1 << i)) - n++; - } - /* XXX: test invalid n =3D=3D 0 case ? */ - if (insn & (1 << 23)) { - if (insn & (1 << 24)) { - /* pre increment */ - tcg_gen_addi_i32(addr, addr, 4); - } else { - /* post increment */ - } - } else { - if (insn & (1 << 24)) { - /* pre decrement */ - tcg_gen_addi_i32(addr, addr, -(n * 4)); - } else { - /* post decrement */ - if (n !=3D 1) - tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); - } - } - j =3D 0; - for (i =3D 0; i < 16; i++) { - if (insn & (1 << i)) { - if (is_load) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (user) { - tmp2 =3D tcg_const_i32(i); - gen_helper_set_user_reg(cpu_env, tmp2, tmp= ); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - } else if (i =3D=3D rn) { - loaded_var =3D tmp; - loaded_base =3D 1; - } else if (i =3D=3D 15 && exc_return) { - store_pc_exc_ret(s, tmp); - } else { - store_reg_from_load(s, i, tmp); - } - } else { - /* store */ - if (i =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, read_pc(s)); - } else if (user) { - tmp =3D tcg_temp_new_i32(); - tmp2 =3D tcg_const_i32(i); - gen_helper_get_user_reg(tmp, cpu_env, tmp2= ); - tcg_temp_free_i32(tmp2); - } else { - tmp =3D load_reg(s, i); - } - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - j++; - /* no need to add after the last transfer */ - if (j !=3D n) - tcg_gen_addi_i32(addr, addr, 4); - } - } - if (insn & (1 << 21)) { - /* write back */ - if (insn & (1 << 23)) { - if (insn & (1 << 24)) { - /* pre increment */ - } else { - /* post increment */ - tcg_gen_addi_i32(addr, addr, 4); - } - } else { - if (insn & (1 << 24)) { - /* pre decrement */ - if (n !=3D 1) - tcg_gen_addi_i32(addr, addr, -((n - 1) * 4= )); - } else { - /* post decrement */ - tcg_gen_addi_i32(addr, addr, -(n * 4)); - } - } - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - if (loaded_base) { - store_reg(s, rn, loaded_var); - } - if (exc_return) { - /* Restore CPSR from SPSR. */ - tmp =3D load_cpu_field(spsr); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_cpsr_write_eret(cpu_env, tmp); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); - } - tcg_temp_free_i32(tmp); - /* Must exit loop to check un-masked IRQs */ - s->base.is_jmp =3D DISAS_EXIT; - } - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0xa: case 0xb: { @@ -10351,73 +10440,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) insn & (1 << 21)); } } else { - int i, loaded_base =3D 0; - TCGv_i32 loaded_var; - bool wback =3D extract32(insn, 21, 1); - /* Load/store multiple. */ - addr =3D load_reg(s, rn); - offset =3D 0; - for (i =3D 0; i < 16; i++) { - if (insn & (1 << i)) - offset +=3D 4; - } - - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, -offset); - } - - if (s->v8m_stackcheck && rn =3D=3D 13 && wback) { - /* - * If the writeback is incrementing SP rather than - * decrementing it, and the initial SP is below the - * stack limit but the final written-back SP would - * be above, then then we must not perform any memory - * accesses, but it is IMPDEF whether we generate - * an exception. We choose to do so in this case. - * At this point 'addr' is the lowest address, so - * either the original SP (if incrementing) or our - * final SP (if decrementing), so that's what we check. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - loaded_var =3D NULL; - for (i =3D 0; i < 16; i++) { - if ((insn & (1 << i)) =3D=3D 0) - continue; - if (insn & (1 << 20)) { - /* Load. */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i =3D=3D rn) { - loaded_var =3D tmp; - loaded_base =3D 1; - } else { - store_reg_from_load(s, i, tmp); - } - } else { - /* Store. */ - tmp =3D load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_gen_addi_i32(addr, addr, 4); - } - if (loaded_base) { - store_reg(s, rn, loaded_var); - } - if (wback) { - /* Base register writeback. */ - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, -offset); - } - /* Fault if writeback register is in register list. */ - if (insn & (1 << rn)) - goto illegal_op; - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } + /* Load/store multiple, in decodetree */ + goto illegal_op; } } break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 341882e637..1267a689e2 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -40,6 +40,7 @@ &mrs_bank rd r sysm &ldst_rr p w u rn rt rm shimm shtype &ldst_ri p w u rn rt imm +&ldst_block rn i b u w list &strex rn rd rt rt2 imm &ldrex rn rt rt2 imm &bfx rd rn lsb widthm1 @@ -514,3 +515,8 @@ SMMLA .... 0111 0101 .... .... .... 0001 ...= . @rdamn SMMLAR .... 0111 0101 .... .... .... 0011 .... @rdamn SMMLS .... 0111 0101 .... .... .... 1101 .... @rdamn SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn + +# Block data transfer + +STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block +LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f315fde0f4..f1e2b934f8 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -37,6 +37,7 @@ &mrs_bank !extern rd r sysm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&ldst_block !extern rn i b u w list &strex !extern rn rd rt rt2 imm &ldrex !extern rn rt rt2 imm &bfx !extern rd rn lsb widthm1 @@ -563,3 +564,12 @@ SXTAB16 1111 1010 0010 .... 1111 .... 10.. ..= .. @rrr_rot UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot + +# Load/store multiple + +@ldstm .... .... .. w:1 . rn:4 list:16 &ldst_block = u=3D0 + +STM_t32 1110 1000 10.0 .... ................ @ldstm i=3D1= b=3D0 +STM_t32 1110 1001 00.0 .... ................ @ldstm i=3D0= b=3D1 +LDM_t32 1110 1000 10.1 .... ................ @ldstm i=3D1= b=3D0 +LDM_t32 1110 1001 00.1 .... ................ @ldstm i=3D0= b=3D1 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cT5iUCtc/TpahCb9mQHDGpDMCKYLz7wFvW1IJP8R1rM=; b=Lt6jyPRXPkhYjZoDRfVNn+cQMWd2wYuXE5YkYeaJGJs2Ch45FXr200uR+MKGQR7bob R8NDvUDCFDCznJ49LSZ2RMNuoO8t7fgNy2C1k8rQvCgXdcuhEVfnwO7PHucoKQEZgaum n4ZOX1dbw1td4u9DkI43VzPI6NWtAlta2Ozboa18zo/6h+F1Tv4Nc2NMxMcjOkjwZMMK mE/zKVVKx4Jrv8l0bnVEwGxDPKULjBtvWxAnT6cXtvK1XPLs5/GFODlhATZURdarx2Gs Dj93p7LFEYhaq4hyu8eHK8GOYc7odqX2gViuVp1+2dy/im8rcTEFefrM/GAh6X/rBbOv ubnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cT5iUCtc/TpahCb9mQHDGpDMCKYLz7wFvW1IJP8R1rM=; b=mPmIkNcBpge74rIYzCGy/X+s4aavjG9AG6KXXEIxIt47VclaRXQieMmOT3LznahmVa d4NEDJSxktM43LQ7oXHJGdz+MXUfMofkWPzHI8bTUOOBdMD1ZpMBuyncsQfpdKGTgD5e 2L+z/Z4xYIvkCTo3h4y8R6XKdpnsxW2uHIcOc16EBafLv3pf6EbwPRCfnIrj/dwQ7Krf +mecA8vhVe9rDDtizjKXn3Rw0/qGrmgdNW94bDwq6Hcta+qTlukLsqB0QXHdhDz71EP1 NHDimJ9AqdLGJYO3nElQ3fovGD1NjRj/t0M60Ju5CJWvqvJjy/lUhtYzmLU3wpntPNIB dGNA== X-Gm-Message-State: APjAAAU6KIOPR1U7D6mneMsc6klvML1Qfi73qHCUN8psORNB4ySHIQ40 yZWRc+28/o3BzoBrsGXtLMvxoduDy6k= X-Google-Smtp-Source: APXvYqzNx/G53Ww2bd4M4Kelw+Tb7DFpP8ZKBQuQccfTQt41YgvxxZKIMcYY8Eg3QMEVYMmexjvT3Q== X-Received: by 2002:aa7:97aa:: with SMTP id d10mr26529772pfq.176.1566250712299; Mon, 19 Aug 2019 14:38:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:15 -0700 Message-Id: <20190819213755.26175-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v2 28/68] target/arm: Diagnose writeback register in list for LDM for v7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Prior to v7, for the A32 encoding, this operation wrote an UNKNOWN value back to the base register. Starting in v7 this is UNPREDICTABLE. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4451adbb97..29e2eae441 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9880,6 +9880,14 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *= a) =20 static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) { + /* + * Writeback register in register list is UNPREDICATABLE + * for ArchVersion() >=3D 7. Prior to v7, A32 would write + * an UNKNOWN value to the base register. + */ + if (ENABLE_ARCH_7 && a->w && (a->list & (1 << a->rn))) { + return false; + } return do_ldm(s, a); } =20 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566251797; cv=none; d=zoho.com; s=zohoarc; b=Wb/qiKnpIxS/ujl+UTD10HajajWGmCBI/X6b6SIzzw2vUNvJsN+7ADKKcXG2J/nw3OEOu8R/dfyYoHg/4KIJqWIeo5734wwbxsQ57SES2QQT99l3C52Ue8bXd27J5EjKqQq00KDlekRzvNrbnbxKpUzRaCJoEGpcTb4lav9G044= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566251797; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=PE2YkC2uYnkrGF/f+RQwnN2RH8jlq2MEkPtJdHa8VHQ=; b=C0233m7nY8Rp2qHSp5X6heZ4LXk5mcIzJtT+UODoNSAOjqwflKTvjGcTHKi5cf13SrD0ifj9KrkR4OeU1ReQtehFZiby6nU6dNb4JgHUo7uGOSb2I4SiTOWnkjFW7uklgaHYFg6WV/nI/9ZotFQodxjYrLFBgZdZSw62GcURD0Q= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566251797494212.8304742727007; Mon, 19 Aug 2019 14:56:37 -0700 (PDT) Received: from localhost ([::1]:59258 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpdf-0007g1-1h for importer@patchew.org; Mon, 19 Aug 2019 17:56:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59189) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMK-000265-G6 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMJ-0006Nu-0i for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:36 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:43141) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMI-0006N6-O6 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:34 -0400 Received: by mail-pg1-x544.google.com with SMTP id k3so1921599pgb.10 for ; Mon, 19 Aug 2019 14:38:34 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PE2YkC2uYnkrGF/f+RQwnN2RH8jlq2MEkPtJdHa8VHQ=; b=t8oNyn9ZZ3RCoFQiIKX4jSToehRsZPBSpTvpY9Z9O0ijBgjNpKVTXyQQZIj+0WQ1I9 vNssbEbg6nKXjvsygAhI5ZFYDHFXOe/jw8E/zmSjoiCT3D6DbkmJ4SI65C+i5glaquEj exzjnem76xrCYZdKpZsexjc6bFARf8cGzp0Ys+IWQ4ZDKMUoDuTLzxjLI8XxjQg7Dn42 yKjbV5ycXhFT1NOZUC1RmQa75ErVhGNizoUDdc0h4aJVW9h/kehjv0qgQYEsVChuRj/P e1hZc6hrr8YwFEFpq5wuuDR3YzMk2wA64D2E/2ta6lMlYUWOosLaFXvWmKHn/LUU9cbw 3R8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PE2YkC2uYnkrGF/f+RQwnN2RH8jlq2MEkPtJdHa8VHQ=; b=Mntx5l6WZZJc3V55U2SjLpD4yf9VtVXzSRn0cXCc5bty1YgreuVXxwuPJmUe8i2Xuz rfI0Jgw5TXDxhAoSWs1XU0Ms13/6tNOfnhDz341fGJGp+ToV5cNCyIn3SU8Qvmtg4c1E KpIkLkBoMbsLdl11Fc22uMIzbbDag0oSYC8fZu1H8QEyOMG9Uuj2afN8EGV7J0fjVeAH KYupepGBc/KtvZKsR/BPkF1YWhADDNUFT1YfDjA3hzibQdqVbhjaoUI8MZ/Vm7UjDber ffVPrEfS3fRXJycFWdqPRAnvDL/VEv4lQKY6e/6hHdA14qr9BFc+mLS3IAq3pGeqdFlk inrw== X-Gm-Message-State: APjAAAVukD9mKDTPKCsh8DZmgd8AAmvkTy3tyeZIYxV6cZJm/mJwLiXH pyCIyZzvNbTNzjKU8BhE4AbrY6nqEXw= X-Google-Smtp-Source: APXvYqxgALNgiwL5LxxNgNOjY3hpHYZNCkpg62IU22V2zRzmwICq2jve7P0gWxDoK0UpD2P8UXDpPQ== X-Received: by 2002:a62:1703:: with SMTP id 3mr22426920pfx.118.1566250713399; Mon, 19 Aug 2019 14:38:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:16 -0700 Message-Id: <20190819213755.26175-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v2 29/68] target/arm: Diagnose too few registers in list for LDM/STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This has been a TODO item for quite a while. The minimum bit count for A32 and T16 is 1, and for T32 is 2. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 29e2eae441..1792bb7abd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9733,7 +9733,7 @@ static void op_addr_block_post(DisasContext *s, arg_l= dst_block *a, } } =20 -static bool op_stm(DisasContext *s, arg_ldst_block *a) +static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) { int i, j, n, list, mem_idx; bool user =3D a->u; @@ -9749,7 +9749,9 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a) =20 list =3D a->list; n =3D ctpop16(list); - /* TODO: test invalid n =3D=3D 0 case */ + if (n < min_n) { + return false; + } =20 addr =3D op_addr_block_pre(s, a, n); mem_idx =3D get_mem_index(s); @@ -9782,7 +9784,8 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a) =20 static bool trans_STM(DisasContext *s, arg_ldst_block *a) { - return op_stm(s, a); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return op_stm(s, a, 1); } =20 static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) @@ -9791,10 +9794,11 @@ static bool trans_STM_t32(DisasContext *s, arg_ldst= _block *a) if (a->w && (a->list & (1 << a->rn))) { return false; } - return op_stm(s, a); + /* BitCount(list) < 2 is UNPREDICTABLE */ + return op_stm(s, a, 2); } =20 -static bool do_ldm(DisasContext *s, arg_ldst_block *a) +static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) { int i, j, n, list, mem_idx; bool loaded_base; @@ -9821,7 +9825,9 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a) =20 list =3D a->list; n =3D ctpop16(list); - /* TODO: test invalid n =3D=3D 0 case */ + if (n < min_n) { + return false; + } =20 addr =3D op_addr_block_pre(s, a, n); mem_idx =3D get_mem_index(s); @@ -9888,7 +9894,8 @@ static bool trans_LDM_a32(DisasContext *s, arg_ldst_b= lock *a) if (ENABLE_ARCH_7 && a->w && (a->list & (1 << a->rn))) { return false; } - return do_ldm(s, a); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return do_ldm(s, a, 1); } =20 static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) @@ -9897,7 +9904,8 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_b= lock *a) if (a->w && (a->list & (1 << a->rn))) { return false; } - return do_ldm(s, a); + /* BitCount(list) < 2 is UNPREDICTABLE */ + return do_ldm(s, a, 2); } =20 /* --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566252050; cv=none; d=zoho.com; s=zohoarc; b=LC8TxqeTSe/v3YvhWla1LNYccpQmzYVjWKhCZX1aF5f8ABXpxEpN3PxeHMs+NNbEPqf8QOObhDbILgeBAtCg7BWaBQZkourCxqElkse7Ac6Xi2McfSAEJHmJr5FpL/9FaK+eFS6hNclHUwda+PiX6dj2F0BpFHumTGZ4p/8i/X4= ARC-Message-Signature: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VR7o5gOGgy8kJ+DLCf8SWN2RwI2Evgg2aslGYIJEmas=; b=zoOabdENlkr74t3j2JqIBVCkTd4o5R1yV3FaVqj5B+UUBq08a51joHpguxhx3XF+d2 uBn4pMJaw5sK0ld89+p3X06rkGQ2pUrygIPunWnxj7mSIgIMahct+/XPHgxe9i3V1D+u pFx0Gca3QVBQkZK7uitn5/pRClrgpFmdle/DvR4zwFHn53DQsxus+sV+IEO6lZpceCMS ubgUKj0xmSISIyzONFPSr2QToSLL0+TlZcu1WBsBqGzMb0M/EAAEb/tE3kYldi6BY0/b gHrMkjyyPMMcpTwOPmr+Sw0asz2ufxhq31Ss5fHXT2Opmzl6ebP3NajTzTfPMpCChHTm s1kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VR7o5gOGgy8kJ+DLCf8SWN2RwI2Evgg2aslGYIJEmas=; b=W9W4/gxRPJEI4cL2FJIi82H0b9htGs4Zu4xRuXgPMh3m8g191U7uSQ9ODiZTwqgxXy 9espYPq6c8kMtzaQLGF6o+oaq0Io5Xkdae/LDzTbFo+jnHjtXi3ZYOGT3vnxEJqeQwp+ wvXaL64vlxJzeMlOxy3hTsk8Cic74dVPMyuV9ZD2p6+HykBnfYQ4SyIqbisPYP4Q0GeZ um6mmxUz2A/J16/vEvcPs7j9GQjP/pv7NXRZgjMJTS+tockbUk9G2zGo+0t2+FNuD/4y FZCrZ6Wofo0qtAyK1/j9CM5WQTQHc8v1DsR1Xz+Hap9mYCbqSv0Wd/nekVm74a0o8p0Z ElVg== X-Gm-Message-State: APjAAAWx6eyBRPkvDuFE/I7aU3LiCs422+VVwOG2lUs5lsBiaodng6YS HiJQp/sGerku3uZvLU3MbWWa//AN9tA= X-Google-Smtp-Source: APXvYqyLYYa3cU5GkFgBDQRqSHJUl9/HOK6L1QiIkbxnRqMkaFjtDtN29r1KV1aUbJZPTEQH0exhDw== X-Received: by 2002:a17:90a:d592:: with SMTP id v18mr22935517pju.135.1566250714831; Mon, 19 Aug 2019 14:38:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:17 -0700 Message-Id: <20190819213755.26175-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v2 30/68] target/arm: Diagnose base == pc for LDM/STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We have been using store_reg and not store_reg_for_load when writing back a loaded value into the base register. At first glance this is incorrect when base =3D=3D pc, however that case is UNPREDICTABLE. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 1792bb7abd..09636aab4e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9752,6 +9752,10 @@ static bool op_stm(DisasContext *s, arg_ldst_block *= a, int min_n) if (n < min_n) { return false; } + /* Using PC as the base register is UNPREDICTABLE. */ + if (a->rn =3D=3D 15) { + return false; + } =20 addr =3D op_addr_block_pre(s, a, n); mem_idx =3D get_mem_index(s); @@ -9828,6 +9832,10 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *= a, int min_n) if (n < min_n) { return false; } + /* Using PC as the base register is UNPREDICTABLE. */ + if (a->rn =3D=3D 15) { + return false; + } =20 addr =3D op_addr_block_pre(s, a, n); mem_idx =3D get_mem_index(s); @@ -9864,6 +9872,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) op_addr_block_post(s, a, addr, n); =20 if (loaded_base) { + /* Note that we reject base =3D=3D pc above. */ store_reg(s, a->rn, loaded_var); } =20 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566252029; cv=none; d=zoho.com; s=zohoarc; b=N729Yj/eVwFBpPlHY6pJQc6w8PjB6BFAs6MF9QxInb+q6NCLLtszWmwq/AmwdVqVBmnJc8jamQ9COHlDJeY+BiuLdQOwapFbxpSqkcQKCgm0jl5pXvNVEevMpEmmAWrRwbuN9bMyYkbZ+I1bnoea77Xiq2hcoKufxXSUw+eOU6k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566252029; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=v9AR5e2vTyYPnkVwbheCeAc1mDx0MtVRV+9wSe0MQcA=; b=RW+9itF0sytAjBOx+fvnxYh2FRKCPhCVZOBxLogDuYBG3QZb5AAYOAl0NK3iguKQWX5qOzYzQLGrHZB22TGutK248zv9ayYzDiybWkK0vmUhU4IFzfJ4sYWK+WzuWI6MoYsNzP+ri9UhNiExax70oAEfWWmN981DdOxG44Tj8yk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566252029733119.51847072013538; Mon, 19 Aug 2019 15:00:29 -0700 (PDT) Received: from localhost ([::1]:59348 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzphT-0004wZ-Vc for importer@patchew.org; Mon, 19 Aug 2019 18:00:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59277) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMO-0002Bt-0j for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpML-0006PX-RE for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:39 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:44076) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpML-0006P1-Jh for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:37 -0400 Received: by mail-pg1-x531.google.com with SMTP id i18so1918362pgl.11 for ; Mon, 19 Aug 2019 14:38:37 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=v9AR5e2vTyYPnkVwbheCeAc1mDx0MtVRV+9wSe0MQcA=; b=wV4Onl44EKekCd9FaaKJMCo1vE4fdDbrqc2iDsjvigz6jF4KNk5jjjpbFUEgSWsfYn cMvFLsfgjGmS3gJ0PbsjrVEkGlnbqTNb5m2Hi68lWz/0CRKTr8cJ8m0/KWewBywxeW0E mf8qmGZkkt3OZa2BZbZxFXbV2r6zdWN2sBsWryDaqhIx71oraD4VrYY9JwoC5HO7yF5y HpoghHt75dQWeTAjvuDDlnDQ1CNvIjLO7naBiGBvd0yZh7E94ctGRdh+TJyylEDr44BO jV3ERhB1fugFkZmLTpUYOvhjgWIcQZSsA6H0pK3IpNVhLrL+P2nzDsD1ehSDpLfz0qvd WyMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v9AR5e2vTyYPnkVwbheCeAc1mDx0MtVRV+9wSe0MQcA=; b=jF95GAfzXXV4pVBhmolZNbjnfGS3IcaBo2sFl3/T92Q1582VW1PGOHRCqu7VkUzfGI rXsnIvVgVLHgQg4xbk3yagyIzYhN6u5y41447NurYB1FcolqL1haIz+WBJ4WyU7UKXC/ PsdqqYXq9K4VKx7F+w79UxBqMdKYfokNs/mRHaR22SqbpA8L/ghlRKounc+9EMYANlVK ClQ98I+XsTId/knZf3lb/zC2r6PH+0ZQKrIv4O1/SUNyas8pa+xffE4GvtBzO/DgtI5q 77l5E8ZE+8o1tvZfJCQmxqW5Y1lE3z2Sp3GZL/BrK+Vq+E0tylHrLCo9utMRhL3GrXRh 2T3Q== X-Gm-Message-State: APjAAAWBiP5oTflWxKtRiB+z7Rq6VVAxcw3dv5hglQXBsTamooypAE+k I33kMxm3ZY6YKWlhe7YSbmyYPTYI4/Y= X-Google-Smtp-Source: APXvYqz8EyxmQUGzacBCvd7RvkMsncsnWF7EMViwR8Kh/QIZfDefJt51KrsrUwBq87Pd7MGq4LvsvA== X-Received: by 2002:a17:90a:feb:: with SMTP id 98mr21704602pjz.55.1566250716060; Mon, 19 Aug 2019 14:38:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:18 -0700 Message-Id: <20190819213755.26175-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::531 Subject: [Qemu-devel] [PATCH v2 31/68] target/arm: Convert B, BL, BLX (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 133 +++++++++++++++-------------------- target/arm/a32-uncond.decode | 8 +++ target/arm/a32.decode | 8 +++ target/arm/t32.decode | 81 ++++++++++++--------- 4 files changed, 123 insertions(+), 107 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 09636aab4e..6b7b3df685 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7523,6 +7523,14 @@ static int t32_expandimm_imm(DisasContext *s, int x) return imm; } =20 +static int t32_branch24(DisasContext *s, int x) +{ + /* Convert J1:J2 at x[22:21] to I2:I1, which involves I=3DJ^~S. */ + x ^=3D !(x < 0) * (3 << 21); + /* Append the final zero. */ + return x << 1; +} + /* * Include the generated decoders. */ @@ -9917,13 +9925,56 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst= _block *a) return do_ldm(s, a, 2); } =20 +/* + * Branch, branch with link + */ + +static bool trans_B(DisasContext *s, arg_i *a) +{ + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a) +{ + /* This has cond from encoding, required to be outside IT block. */ + if (a->cond >=3D 0xe) { + return false; + } + if (s->condexec_mask) { + unallocated_encoding(s); + return true; + } + arm_skip_unless(s, a->cond); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_BL(DisasContext *s, arg_i *a) +{ + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) +{ + /* For A32, ARCH(5) is checked near the start of the uncond block. */ + if (s->thumb && (a->imm & 2)) { + return false; + } + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_bx_im(s, (read_pc(s) & ~3) + a->imm + !s->thumb); + return true; +} + /* * Legacy decoder. */ =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rn; + unsigned int cond, op1, i, rn; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10091,21 +10142,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) } gen_rfe(s, tmp, tmp2); return; - } else if ((insn & 0x0e000000) =3D=3D 0x0a000000) { - /* branch link and change to thumb (blx ) */ - int32_t offset; - - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, s->base.pc_next); - store_reg(s, 14, tmp); - /* Sign-extend the 24-bit offset */ - offset =3D (((int32_t)insn) << 8) >> 8; - val =3D read_pc(s); - /* offset * 4 + bit24 * 2 + (thumb bit) */ - val +=3D (offset << 2) | ((insn >> 23) & 2) | 1; - /* protected by ARCH(5); above, near the start of uncond block= */ - gen_bx_im(s, val); - return; } else if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10197,23 +10233,10 @@ static void disas_arm_insn(DisasContext *s, unsig= ned int insn) case 0x7: case 0x08: case 0x09: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; case 0xa: case 0xb: - { - int32_t offset; - - /* branch (and link) */ - if (insn & (1 << 24)) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, s->base.pc_next); - store_reg(s, 14, tmp); - } - offset =3D sextract32(insn << 2, 0, 26); - gen_jmp(s, read_pc(s) + offset); - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0xc: case 0xd: case 0xe: @@ -10580,32 +10603,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) if (insn & (1 << 15)) { /* Branches, misc control. */ if (insn & 0x5000) { - /* Unconditional branch. */ - /* signextend(hw1[10:0]) -> offset[:12]. */ - offset =3D ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff; - /* hw1[10:0] -> offset[11:1]. */ - offset |=3D (insn & 0x7ff) << 1; - /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22] - offset[24:22] already have the same value because of the - sign extension above. */ - offset ^=3D ((~insn) & (1 << 13)) << 10; - offset ^=3D ((~insn) & (1 << 11)) << 11; - - if (insn & (1 << 14)) { - /* Branch and link. */ - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); - } - - offset +=3D read_pc(s); - if (insn & (1 << 12)) { - /* b/bl */ - gen_jmp(s, offset); - } else { - /* blx */ - offset &=3D ~(uint32_t)2; - /* thumb2 bx, no need to check */ - gen_bx_im(s, offset); - } + /* Unconditional branch, in decodetree */ + goto illegal_op; } else if (((insn >> 23) & 7) =3D=3D 7) { /* Misc control */ if (insn & (1 << 13)) @@ -10691,24 +10690,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } } } else { - /* Conditional branch. */ - op =3D (insn >> 22) & 0xf; - /* Generate a conditional jump to next instruction. */ - arm_skip_unless(s, op); - - /* offset[11:1] =3D insn[10:0] */ - offset =3D (insn & 0x7ff) << 1; - /* offset[17:12] =3D insn[21:16]. */ - offset |=3D (insn & 0x003f0000) >> 4; - /* offset[31:20] =3D insn[26]. */ - offset |=3D ((int32_t)((insn << 5) & 0x80000000)) >> 11; - /* offset[18] =3D insn[13]. */ - offset |=3D (insn & (1 << 13)) << 5; - /* offset[19] =3D insn[11]. */ - offset |=3D (insn & (1 << 11)) << 8; - - /* jump to the offset */ - gen_jmp(s, read_pc(s) + offset); + /* Conditional branch, in decodetree */ + goto illegal_op; } } else { /* diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 8dee26d3b6..573ac2cf8e 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -21,3 +21,11 @@ # All insns that have 0xf in insn[31:28] are decoded here. # All of those that have a COND field in insn[31:28] are in a32.decode # + +&i !extern imm + +# Branch with Link and Exchange + +%imm24h 0:s24 24:1 !function=3Dtimes_2 + +BLX_i 1111 101 . ........................ &i imm=3D%im= m24h diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 1267a689e2..62c6f8562e 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -520,3 +520,11 @@ SMMLSR .... 0111 0101 .... .... .... 1111 ..= .. @rdamn =20 STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block + +# Branch, branch with link + +%imm26 0:s24 !function=3Dtimes_4 +@branch ---- .... ........................ &i imm=3D%im= m26 + +B .... 1010 ........................ @branch +BL .... 1011 ........................ @branch diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f1e2b934f8..ebc92f2c28 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -284,47 +284,55 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .= ... @rdm %msr_sysm 4:1 8:4 %mrs_sysm 4:1 16:4 %imm16_16_0 16:4 0:12 +%imm21 26:s1 11:1 13:1 16:6 0:11 !function=3Dtimes_2 +&ci cond imm =20 { + # Group insn[25:23] =3D 111, which is cond=3D111x for the branch below, + # or unconditional, which would be illegal for the branch. { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + # Hints + { + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 - # The canonical nop ends in 0000 0000, but the whole rest - # of the space is "reserved hint, behaves as nop". - NOP 1111 0011 1010 1111 1000 0000 ---- ---- - } - # Note that the v7m insn overlaps both the normal and banked insn. - { - MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- + } + # Note that the v7m insn overlaps both the normal and banked insn. + { + MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ &mrs_bank sysm=3D%mrs_sysm - MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg - MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 - } - { - MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ + MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg + MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 + } + { + MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ &msr_bank sysm=3D%msr_sysm - MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg - MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 - } - BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r - { - # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as = for - # every other encoding of SUBS. With v7VE, IMM=3D0 is redefined as ER= ET. - # The distinction between the two only matters for Hyp mode. - ERET 1111 0011 1101 1110 1000 1111 0000 0000 - SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ + MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg + MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 + } + BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r + { + # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works a= s for + # every other encoding of SUBS. With v7VE, IMM=3D0 is redefined as = ERET. + # The distinction between the two only matters for Hyp mode. + ERET 1111 0011 1101 1110 1000 1111 0000 0000 + SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ &s_rri_rot rot=3D0 s=3D1 rd=3D15 rn=3D14 - } - SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i - HVC 1111 0111 1110 .... 1000 .... .... .... \ + } + SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i + HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=3D%imm16_16_0 - UDF 1111 0111 1111 ---- 1010 ---- ---- ---- + UDF 1111 0111 1111 ---- 1010 ---- ---- ---- + } + B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=3D%i= mm21 } =20 # Load/store (register, immediate, literal) @@ -573,3 +581,12 @@ STM_t32 1110 1000 10.0 .... ................ = @ldstm i=3D1 b=3D0 STM_t32 1110 1001 00.0 .... ................ @ldstm i=3D0= b=3D1 LDM_t32 1110 1000 10.1 .... ................ @ldstm i=3D1= b=3D0 LDM_t32 1110 1001 00.1 .... ................ @ldstm i=3D0= b=3D1 + +# Branches + +%imm24 26:s1 13:1 11:1 16:10 0:11 !function=3Dt32_branch24 +@branch24 ................................ &i imm=3D%im= m24 + +B 1111 0. .......... 10.1 ............ @branch24 +BL 1111 0. .......... 11.1 ............ @branch24 +BLX_i 1111 0. .......... 11.0 ............ @branch24 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566252324; cv=none; d=zoho.com; s=zohoarc; b=nRVXW+CNBaCcJszg+8gCu78DoV0rVHa+UyJBJk4sPntbWOKiqJuR2BI3V463kh0hmesk/O6DUlEeiUtFxuZtzNkIz6v/ghh9hsuxEGYSTJllM4JBcnj6/CKFYSxQ3ZoY7gB8YsWCB6n0vE/YC3DrDZKXPacVodHeqyXf235vdxU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566252324; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=PQ+LqO+lz8aRvDtiE1Qc+qi0l6DF2tSTKskus1LdpN4=; b=OxgzvxZzQb2USERe95mqyIK3HHsgI8JhMbRPsfsADFirsxRxVcXT2VXY/WZ0QKHscH/OtHrVgccenmsZtp/e6vYZQo9NWQiLD+sHrXe0/cs+TOZNYfUvoaC//zvA3y3paVUB+RiBRC39hLyQKlsqaXCWbHMMQ8ALNj2Hi7d71pU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566252324117276.4792119453904; Mon, 19 Aug 2019 15:05:24 -0700 (PDT) Received: from localhost ([::1]:59458 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpmE-0002ro-In for importer@patchew.org; Mon, 19 Aug 2019 18:05:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59264) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMN-0002At-AK for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMM-0006Pw-92 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:39 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:44547) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMM-0006PR-49 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:38 -0400 Received: by mail-pf1-x444.google.com with SMTP id c81so1936604pfc.11 for ; Mon, 19 Aug 2019 14:38:38 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PQ+LqO+lz8aRvDtiE1Qc+qi0l6DF2tSTKskus1LdpN4=; b=yJtSnyCnzFgS8dO+gi9fsUmsemw5RartDZNEsx/CN9M9gFxSZQ8iCboaDsqo9BgcP9 VJ/8frTOBPA+8HbkZjVnWcEXc6NpkWmXIPMDDmZs08/YYHslBtRn0OTfk28/aWqrXgiE QYavLQyrS38/iX8xsNsvGxsHKUOpg3leK08WVsFof2PoET7tmmU1EpDSIBdfmUIjwydf sUGBw/ZDM+irk9IgZmsoZGKHan0CYmFzqmKs0YrQPsiNA5V16BrpX+yIDtCHcy6lC3MD rrzhXllmvOdl4vo44T41AMF88Rjs5K7ibHMVeKQmcHTNfSYt3YUTE6cPx+hYt7GZOSdl CPWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PQ+LqO+lz8aRvDtiE1Qc+qi0l6DF2tSTKskus1LdpN4=; b=l/GFF4/aipSS3pJmJMFUt4qER80q/Y3upb5K5f0so0T+IMnQO+KbpWfP0rFps1JaeM iWACBi6JdqrjogYYSkwc9gRR70xn8La0miqY6nA2FEYVq/uDgS/a81GdDzIEAcwOFBlc BcON38jnUdNHTNDjMsGIoCWAKcUPvWb1RPPuxiioBxJxDyZ2suj5GYGls9N4T+sRRXeL sEqszov3mh48eaUNBhEEj8XIkdScOA7k6hnYobpgX9LWUcOEWqnJnCpTJxCWo6ItXroE UDrrPjiWsaSOaeTQ7d2YMRCHgeOXb640q0beFfj6i76+IYrXJL6eS4KMBeuJFJyPcN38 INew== X-Gm-Message-State: APjAAAVDto9q23ozBkmSfCWIAji4Nqrw5XmGKXskJSO24xEK3J+RXSlg 4Cs137Jov3n/5umprHT2traPasoPob4= X-Google-Smtp-Source: APXvYqwRJeYrQsnSE9U4nHrRpTKk0mLzwlMNxxtTHtzv6iOAvmq6/+VtKSbu9lsJyKIFSOeXz4hnDQ== X-Received: by 2002:aa7:925a:: with SMTP id 26mr26490232pfp.198.1566250716944; Mon, 19 Aug 2019 14:38:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:19 -0700 Message-Id: <20190819213755.26175-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 32/68] target/arm: Convert SVC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.c | 19 +++++++++++++------ target/arm/a32.decode | 4 ++++ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 6b7b3df685..b6d8b7be8c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9968,6 +9968,18 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *= a) return true; } =20 +/* + * Supervisor call + */ + +static bool trans_SVC(DisasContext *s, arg_SVC *a) +{ + gen_set_pc_im(s, s->base.pc_next); + s->svc_imm =3D a->imm; + s->base.is_jmp =3D DISAS_SWI; + return true; +} + /* * Legacy decoder. */ @@ -10235,6 +10247,7 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) case 0x09: case 0xa: case 0xb: + case 0xf: /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; case 0xc: @@ -10250,12 +10263,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) goto illegal_op; } break; - case 0xf: - /* swi */ - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm =3D extract32(insn, 0, 24); - s->base.is_jmp =3D DISAS_SWI; - break; default: illegal_op: unallocated_encoding(s); diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 62c6f8562e..0bd952c069 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -528,3 +528,7 @@ LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:1= 6 &ldst_block =20 B .... 1010 ........................ @branch BL .... 1011 ........................ @branch + +# Supervisor call + +SVC ---- 1111 imm:24 &i --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566252466; cv=none; d=zoho.com; s=zohoarc; b=c5Aq8x4hymADO0nN22HrRSravthzMG8VvqOwT3hhbFGJBdcPWgOqpGvUJs+6UIkFUJPLJn2GowqOr8e+EmRNC7d7hqnuZG11Xk6GxLldXT7FXUgEUIE5xDala0yOrZ7ZmvrEtnFZPU3k31+2DdnU/n7QCYMAY+ggqo/5pd3bzM4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566252466; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=sBLN1mbpyRVW7i8qjZto4S2aiB09EK81j9lCJDX6kUc=; b=R5Lzk+rIyTWE7X9cFd1qTz76GgWtPSykWAkvgR5D7V/Oxcx+ry1IzW7vSYu9MCX8cmqugBQZ6UXceSQV1Ugdt7YrgDkOn0NB8pXF3lcs6JPYTE2RvAA3HcPjBoZo3hA4ERFCwWvDLbgm6Ycquxvd58br9RGJ5d/yo9tHRLU5xl0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566252466181656.0864388737706; Mon, 19 Aug 2019 15:07:46 -0700 (PDT) Received: from localhost ([::1]:59526 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpoU-0006cV-Ii for importer@patchew.org; Mon, 19 Aug 2019 18:07:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59300) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMP-0002Dp-2k for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMN-0006Qt-FU for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:40 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:46331) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMN-0006QF-86 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:39 -0400 Received: by mail-pf1-x444.google.com with SMTP id q139so1933420pfc.13 for ; Mon, 19 Aug 2019 14:38:39 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sBLN1mbpyRVW7i8qjZto4S2aiB09EK81j9lCJDX6kUc=; b=upuuasOxPwmX5Z9V/qsNqZt4dSjKDvH759oLf3ykUI7uFCy/MkiVXYg9E/mVKTapOk jnbhbSyDMcTW/TBhJ2GteVJ8bebwHgH/0zKD09++qJuvOV8bMp71/FX1E9swPy/PLOiq ni5+NI8ms+jDAkySFeHi5xl23x/betoQDX9AaL2AuzgZ0GHbPSlRkHIckwt11H94PhV3 wRbjh8ClILaN0YmjH8ZGV1Rmiyq3V8INIS7/oNa0xJ6wxd6wIHEvD5+Pe33hTbNkClwf 2hZZiT/PoMoqoEOWpZAxxiqcXeFu1UGgoOOBE7u/6zFcfMKCaMn1tAB/CZkldHF953qc YPFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sBLN1mbpyRVW7i8qjZto4S2aiB09EK81j9lCJDX6kUc=; b=iPFxo8835oU6yx26HEMlsLKBfF86A/KC8JxpyA5wr3Gz9r41yqK2Wt9bLxc3buyP0W AaqfUMNFpwMB+3sULf8j2kmwiOdcIIAu3P+8KHncQ0JK9R9/iGUFecLGpxK0QI23Tq0j Um/6pu/b+IgMfJFM2nVxcM9Pzynz0SefaCdxikAbXOfP/OwrQiUAXU0faidgUyPUEp31 GsNufIzRydyIE/ITnaSTb5w5EuVwFEQ31He+oFnaCxY9Tom4Pnd7Rw/Dcm7lA3j1HeNI 8SHdgbXnw31DujQMLhNV7oi0nVEiYASFveJAewoS/P/XQnW2+HdSehcwYJL+KcFYO1/r kaPA== X-Gm-Message-State: APjAAAUumDTttJEvh45fAMWO1z2hOdzVwlk4n7kFyGrEvph5yYkZCHBu NohNFN0qbiK6hWCBf4dO84CYlsmAxD0= X-Google-Smtp-Source: APXvYqzP5I3yOMpsWC64pQe1uFM1YFCYGZEOlBd6vDY7kGia90QJokltwt14ZjZs0IKZNIcx6Oyh2A== X-Received: by 2002:a62:8246:: with SMTP id w67mr27082046pfd.226.1566250717983; Mon, 19 Aug 2019 14:38:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:20 -0700 Message-Id: <20190819213755.26175-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 33/68] target/arm: Convert RFE and SRS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 150 ++++++++++++++--------------------- target/arm/a32-uncond.decode | 8 ++ target/arm/t32.decode | 12 +++ 3 files changed, 81 insertions(+), 89 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b6d8b7be8c..e268c5168d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9980,16 +9980,71 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) return true; } =20 +/* + * Unconditional system instructions + */ + +static bool trans_RFE(DisasContext *s, arg_RFE *a) +{ + int32_t offset; + TCGv_i32 addr, t1, t2; + + if (IS_USER(s) || !ENABLE_ARCH_6) { + return false; + } + + addr =3D load_reg(s, a->rn); + + switch (a->pu) { + case 0: offset =3D -4; break; /* DA */ + case 1: offset =3D 0; break; /* IA */ + case 2: offset =3D -8; break; /* DB */ + case 3: offset =3D 4; break; /* IB */ + default: + g_assert_not_reached(); + } + tcg_gen_addi_i32(addr, addr, offset); + + /* Load PC into tmp and CPSR into tmp2. */ + t1 =3D tcg_temp_new_i32(); + gen_aa32_ld32u(s, t1, addr, get_mem_index(s)); + tcg_gen_addi_i32(addr, addr, 4); + t2 =3D tcg_temp_new_i32(); + gen_aa32_ld32u(s, t2, addr, get_mem_index(s)); + + if (a->w) { + /* Base writeback. */ + switch (a->pu) { + case 0: offset =3D -8; break; + case 1: offset =3D 4; break; + case 2: offset =3D -4; break; + case 3: offset =3D 0; break; + } + tcg_gen_addi_i32(addr, addr, offset); + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } + gen_rfe(s, t1, t2); + return true; +} + +static bool trans_SRS(DisasContext *s, arg_SRS *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + gen_srs(s, a->mode, a->pu, a->w); + return true; +} + /* * Legacy decoder. */ =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, op1, i, rn; - TCGv_i32 tmp; - TCGv_i32 tmp2; - TCGv_i32 addr; + unsigned int cond, op1; =20 /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -10108,52 +10163,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) default: goto illegal_op; } - } else if ((insn & 0x0e5fffe0) =3D=3D 0x084d0500) { - /* srs */ - ARCH(6); - gen_srs(s, (insn & 0x1f), (insn >> 23) & 3, insn & (1 << 21)); - return; - } else if ((insn & 0x0e50ffe0) =3D=3D 0x08100a00) { - /* rfe */ - int32_t offset; - if (IS_USER(s)) - goto illegal_op; - ARCH(6); - rn =3D (insn >> 16) & 0xf; - addr =3D load_reg(s, rn); - i =3D (insn >> 23) & 3; - switch (i) { - case 0: offset =3D -4; break; /* DA */ - case 1: offset =3D 0; break; /* IA */ - case 2: offset =3D -8; break; /* DB */ - case 3: offset =3D 4; break; /* IB */ - default: abort(); - } - if (offset) - tcg_gen_addi_i32(addr, addr, offset); - /* Load PC into tmp and CPSR into tmp2. */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - tcg_gen_addi_i32(addr, addr, 4); - tmp2 =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - if (insn & (1 << 21)) { - /* Base writeback. */ - switch (i) { - case 0: offset =3D -8; break; - case 1: offset =3D 4; break; - case 2: offset =3D -4; break; - case 3: offset =3D 0; break; - default: abort(); - } - if (offset) - tcg_gen_addi_i32(addr, addr, offset); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - gen_rfe(s, tmp, tmp2); - return; } else if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10316,7 +10325,6 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; - TCGv_i32 tmp2; TCGv_i32 addr; int op; =20 @@ -10460,44 +10468,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) goto illegal_op; } } else { - /* Load/store multiple, RFE, SRS. */ - if (((insn >> 23) & 1) =3D=3D ((insn >> 24) & 1)) { - /* RFE, SRS: not available in user mode or on M profile */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - if (insn & (1 << 20)) { - /* rfe */ - addr =3D load_reg(s, rn); - if ((insn & (1 << 24)) =3D=3D 0) - tcg_gen_addi_i32(addr, addr, -8); - /* Load PC into tmp and CPSR into tmp2. */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - tcg_gen_addi_i32(addr, addr, 4); - tmp2 =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - if (insn & (1 << 21)) { - /* Base writeback. */ - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, 4); - } else { - tcg_gen_addi_i32(addr, addr, -4); - } - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - gen_rfe(s, tmp, tmp2); - } else { - /* srs */ - gen_srs(s, (insn & 0x1f), (insn & (1 << 24)) ? 1 : 2, - insn & (1 << 21)); - } - } else { - /* Load/store multiple, in decodetree */ - goto illegal_op; - } + /* Load/store multiple, RFE, SRS, in decodetree */ + goto illegal_op; } break; case 5: diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 573ac2cf8e..3b961233e5 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -29,3 +29,11 @@ %imm24h 0:s24 24:1 !function=3Dtimes_2 =20 BLX_i 1111 101 . ........................ &i imm=3D%im= m24h + +# System Instructions + +&rfe rn w pu +&srs mode w pu + +RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe +SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ebc92f2c28..c8a8aeceee 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -582,6 +582,18 @@ STM_t32 1110 1001 00.0 .... ................ = @ldstm i=3D0 b=3D1 LDM_t32 1110 1000 10.1 .... ................ @ldstm i=3D1= b=3D0 LDM_t32 1110 1001 00.1 .... ................ @ldstm i=3D0= b=3D1 =20 +&rfe !extern rn w pu +@rfe .... .... .. w:1 . rn:4 ................ &rfe + +RFE 1110 1000 00.1 .... 1100000000000000 @rfe pu=3D2 +RFE 1110 1001 10.1 .... 1100000000000000 @rfe pu=3D1 + +&srs !extern mode w pu +@srs .... .... .. w:1 . .... ........... mode:5 &srs + +SRS 1110 1000 00.0 1101 1100 0000 000. .... @srs pu=3D2 +SRS 1110 1001 10.0 1101 1100 0000 000. .... @srs pu=3D1 + # Branches =20 %imm24 26:s1 13:1 11:1 16:10 0:11 !function=3Dt32_branch24 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MYM8dYqYPl4eqxjsUKYjeBmOOKaa2+t2xb+fej5q23g=; b=uubnh2nnslDD4Dn/VjckXQhvv20xcu4vVoTR0Rl15Vf1QQPPLibQOk5/FCa4PFZ5lI AXoHtsVsKRtjaQ3816MGgTBIgPc9sispVcSN4LL2k+dY8hJ8iE2IYzLuJN+Cvxl9cXW7 hbQxWW63KjDfbZTvZhCxCVoaHoZa82nFClbtbIVFwzk+zALie1YIdKOMvGdwTUSdpD7y +L8Pk9VV/9r9bwNeA95XzK5K8zHVf1TXmN221+j0xEoB8+H7tH/vtrfkbI3VrsU3SIYS OquS4eY7tMCSVbIOhWeb/XbHBo65DovhA2D3iYIagJnET0Kf/Xg42h5ycZFS4XCTOxmr qz8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MYM8dYqYPl4eqxjsUKYjeBmOOKaa2+t2xb+fej5q23g=; b=CfQF3CRXCGHdUkj7WT0jV+Bd0b83/1Rcqv/+FRKWUSrTORyWUBYva0UiWWnmK6fzWQ qfw3hkNqzW9l2/WBPyqGZdr+9V+5RhZzM9jOYkJIE+4uX0oYcFWI8Hx/Z4x8QBQ4exWK t2Rx8oYLfb6bPqk5wmUss5yi4Mig6Kx1vKI4yp1339OEh1CBcImPRRjBE4I7fnC2JLvr YajsnwKsGslHAtLQ9oOnKqmV4SJDY+wLegmaoZa+T5UsFT2Ftxa7t3hOkpVrpyDSnX8B FrddNttgkkBeJ3K8zgbLh6IUgktjNKZJftNEIT7WaGvxfcLGO1z1wRKVwrnjeXRxls1o YHZg== X-Gm-Message-State: APjAAAUnN1dv0ipu/Nno2oYTyW4cGGZgd6ez6uoSQGubG44YGKMNq3eA oDu/Nt4aFkgUBV5dHE95w51PXmHsQNA= X-Google-Smtp-Source: APXvYqzcWvdSC5XaTyyNDuZbVCilCF7CeTd5a5C12GZutOrv57i4e+P3k7AWqXfluReQ058ufTvrhQ== X-Received: by 2002:a62:4ed1:: with SMTP id c200mr26227581pfb.218.1566250719254; Mon, 19 Aug 2019 14:38:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:21 -0700 Message-Id: <20190819213755.26175-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v2 34/68] target/arm: Convert Clear-Exclusive, Barriers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 122 +++++++++++++++-------------------- target/arm/a32-uncond.decode | 10 +++ target/arm/t32.decode | 10 +++ 3 files changed, 73 insertions(+), 69 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index e268c5168d..6489bbc09c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10038,6 +10038,58 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a) return true; } =20 +/* + * Clear-Exclusive, Barriers + */ + +static bool trans_CLREX(DisasContext *s, arg_CLREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + gen_clrex(s); + return true; +} + +static bool trans_DSB(DisasContext *s, arg_DSB *a) +{ + if (!s->thumb && !ENABLE_ARCH_7) { + return false; + } + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + return true; +} + +static bool trans_DMB(DisasContext *s, arg_DMB *a) +{ + return trans_DSB(s, NULL); +} + +static bool trans_ISB(DisasContext *s, arg_ISB *a) +{ + /* + * We need to break the TB after this insn to execute + * self-modifying code correctly and also to take + * any pending interrupts immediately. + */ + gen_goto_tb(s, 0, s->base.pc_next); + return true; +} + +static bool trans_SB(DisasContext *s, arg_SB *a) +{ + if (!dc_isar_feature(aa32_sb, s)) { + return false; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->base.pc_next); + return true; +} + /* * Legacy decoder. */ @@ -10131,38 +10183,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) s->base.is_jmp =3D DISAS_UPDATE; } return; - } else if ((insn & 0x0fffff00) =3D=3D 0x057ff000) { - switch ((insn >> 4) & 0xf) { - case 1: /* clrex */ - ARCH(6K); - gen_clrex(s); - return; - case 4: /* dsb */ - case 5: /* dmb */ - ARCH(7); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - return; - case 6: /* isb */ - /* We need to break the TB after this insn to execute - * self-modifying code correctly and also to take - * any pending interrupts immediately. - */ - gen_goto_tb(s, 0, s->base.pc_next); - return; - case 7: /* sb */ - if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { - goto illegal_op; - } - /* - * TODO: There is no speculation barrier opcode - * for TCG; MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); - return; - default: - goto illegal_op; - } } else if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10623,43 +10643,7 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) gen_set_psr_im(s, offset, 0, imm); } break; - case 3: /* Special control operations. */ - if (!arm_dc_feature(s, ARM_FEATURE_V7) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - op =3D (insn >> 4) & 0xf; - switch (op) { - case 2: /* clrex */ - gen_clrex(s); - break; - case 4: /* dsb */ - case 5: /* dmb */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - break; - case 6: /* isb */ - /* We need to break the TB after this insn - * to execute self-modifying code correctly - * and also to take any pending interrupts - * immediately. - */ - gen_goto_tb(s, 0, s->base.pc_next); - break; - case 7: /* sb */ - if ((insn & 0xf) || !dc_isar_feature(aa32_sb, = s)) { - goto illegal_op; - } - /* - * TODO: There is no speculation barrier opcode - * for TCG; MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); - break; - default: - goto illegal_op; - } - break; + case 3: /* Special control operations, in decodetree */ case 4: /* bxj, in decodetree */ goto illegal_op; case 5: /* Exception return. */ diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 3b961233e5..b077958cec 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -22,6 +22,7 @@ # All of those that have a COND field in insn[31:28] are in a32.decode # =20 +&empty !extern &i !extern imm =20 # Branch with Link and Exchange @@ -37,3 +38,12 @@ BLX_i 1111 101 . ........................ = &i imm=3D%imm24h =20 RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs + +# Clear-Exclusive, Barriers + +# QEMU does not require the option field for the barriers. +CLREX 1111 0101 0111 1111 1111 0000 0001 1111 +DSB 1111 0101 0111 1111 1111 0000 0100 ---- +DMB 1111 0101 0111 1111 1111 0000 0101 ---- +ISB 1111 0101 0111 1111 1111 0000 0110 ---- +SB 1111 0101 0111 1111 1111 0000 0111 0000 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c8a8aeceee..18c268e712 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -305,6 +305,16 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ..= .. @rdm # of the space is "reserved hint, behaves as nop". NOP 1111 0011 1010 1111 1000 0000 ---- ---- } + + # Miscelaneous control + { + CLREX 1111 0011 1011 1111 1000 1111 0010 1111 + DSB 1111 0011 1011 1111 1000 1111 0100 ---- + DMB 1111 0011 1011 1111 1000 1111 0101 ---- + ISB 1111 0011 1011 1111 1000 1111 0110 ---- + SB 1111 0011 1011 1111 1000 1111 0111 0000 + } + # Note that the v7m insn overlaps both the normal and banked insn. { MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566252607; cv=none; d=zoho.com; s=zohoarc; b=ENvwMXa4JKi2nLFrIY1bObcO7TGfYrs8p2bpVeMKZrM/3NMN4TxIgBZjv+Ex87DZADeR/DjUxnkKeLq7E6vDD8XIhDXUOBDctetTST095C3VG5pHtMozw8AP730UscbLMNb88rhkLJxyPMqljyt39mXP1sNG772fPgMB+B+WfE0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566252607; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=hd9oAYsJN/ILLc4tSsxONdbYI/SdPS1ZDtg8ggp1IIQ=; b=ENq0z4ghhYQnxhXQq3eSWfZdjFomsgiTzzeegyRP9tfkzmIdp6gGnFOTVi8u4jN/T6/df+f86p5v+NdQieuhgDGHMlmpmdJIBJryQyNmDSkxfsSNcu4lnvW5+x+l3QAPhzrWBLlsrS31PaqkpYtzu9C6S1XpOuQv8QWV4MMsty4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566252607450931.6184426233546; Mon, 19 Aug 2019 15:10:07 -0700 (PDT) Received: from localhost ([::1]:59582 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpqm-0001mp-4i for importer@patchew.org; Mon, 19 Aug 2019 18:10:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59356) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMR-0002Hp-3D for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMP-0006SW-PR for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:42 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:45689) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMP-0006S0-Je for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:41 -0400 Received: by mail-pl1-x641.google.com with SMTP id y8so1579591plr.12 for ; Mon, 19 Aug 2019 14:38:41 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hd9oAYsJN/ILLc4tSsxONdbYI/SdPS1ZDtg8ggp1IIQ=; b=rs+aVxyaYjn4n4buKJ3z0ywGpFYSnZgAxFwRAeGetgTAPEHnQ5d+udqVtXclrIRPru NeOKcEWs+SFX6oaejTAs8KfnWuDNtq09fp7+ao2MXbMjmjJgILMW1H3MkwX+aBl8hyt6 YC34YHTOpbO8OfD15JT6dxfbaCWHKzj+p5D9DNIPayibyrmHmAhmIbx6TxAYy0VWL2Ds FBd6VrdGWc3NA65LgF6umRlsnLzrEtqLV01Ezy4pnwlL1d8WajenZhorz5xHzrFgMIOQ iGGCh4UOOHAvIVPA1XDi2GKWruBa6WTBgrNXWS+S1yYK3Y0Oqdiru0GdCxn8sLx+8wWD lobw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hd9oAYsJN/ILLc4tSsxONdbYI/SdPS1ZDtg8ggp1IIQ=; b=rG5iv2qb1r2oL9Dq9EWTXqJa0EzT4zQqcBimn+vYmOlBy7o4NxtzNKuaXaRtwbn9nP C6mn8NWW7uXcbMZV46RSXzgZzSCWB1ETeuGv25k56yzwxdzknsfEWP0LHV6pFLbKgBcl 77oxIvEIeoSGy0tHxaFtrkXuTuLSZccpFvgmqZY7g6H8a0oEBPy5UkcxBw/2RiIyYOOB xDJD6EQ23Q6IGLNSA2bDE7rkYVWopPvOSwxf2VojRKAEhASAC1tCQCcC0C0qSbmuQ++J Y+to9GApfvMg9PjkRWAM3ojaRRtt+fxwVpCC9pBa1a41c6Kn3gPF4W69yda+hLKpc6bX DkTw== X-Gm-Message-State: APjAAAWTDZTxtUUFl5B4iOW4daA0PrpeqqKC3jBsxeQrcb4RL9lMkzOd ZxfCKrLgZmHAEB0tHpJxjrav020fKNw= X-Google-Smtp-Source: APXvYqxC2PIxG7qr3vjVIOvBbR0EGdK8nkEWB/V1gLI0WeuX8XTE5bMKkYxSzGC614VyDeanpGRVwQ== X-Received: by 2002:a17:902:2bcb:: with SMTP id l69mr22578442plb.282.1566250720368; Mon, 19 Aug 2019 14:38:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:22 -0700 Message-Id: <20190819213755.26175-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 35/68] target/arm: Convert CPS (privileged) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 87 +++++++++++++++--------------------- target/arm/a32-uncond.decode | 3 ++ target/arm/t32.decode | 3 ++ 3 files changed, 42 insertions(+), 51 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 6489bbc09c..928205d993 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10038,6 +10038,40 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a) return true; } =20 +static bool trans_CPS(DisasContext *s, arg_CPS *a) +{ + uint32_t mask, val; + + if (IS_USER(s)) { + /* Implemented as NOP in user mode. */ + return true; + } + + mask =3D val =3D 0; + if (a->imod & 2) { + if (a->A) { + mask |=3D CPSR_A; + } + if (a->I) { + mask |=3D CPSR_I; + } + if (a->F) { + mask |=3D CPSR_F; + } + if (a->imod & 1) { + val |=3D mask; + } + } + if (a->M) { + mask |=3D CPSR_M; + val |=3D a->mode; + } + if (mask) { + gen_set_psr_im(s, mask, 0, val); + } + return true; +} + /* * Clear-Exclusive, Barriers */ @@ -10209,31 +10243,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) ARCH(5TE); } else if ((insn & 0x0f000010) =3D=3D 0x0e000010) { /* Additional coprocessor register transfer. */ - } else if ((insn & 0x0ff10020) =3D=3D 0x01000000) { - uint32_t mask; - uint32_t val; - /* cps (privileged) */ - if (IS_USER(s)) - return; - mask =3D val =3D 0; - if (insn & (1 << 19)) { - if (insn & (1 << 8)) - mask |=3D CPSR_A; - if (insn & (1 << 7)) - mask |=3D CPSR_I; - if (insn & (1 << 6)) - mask |=3D CPSR_F; - if (insn & (1 << 18)) - val |=3D mask; - } - if (insn & (1 << 17)) { - mask |=3D CPSR_M; - val |=3D (insn & 0x1f); - } - if (mask) { - gen_set_psr_im(s, mask, 0, val); - } - return; } goto illegal_op; } @@ -10342,7 +10351,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, ui= nt32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 addr; @@ -10618,31 +10626,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) case 0: /* msr cpsr, in decodetree */ case 1: /* msr spsr, in decodetree */ goto illegal_op; - case 2: /* cps, nop-hint. */ - /* nop hints in decodetree */ - /* Implemented as NOP in user mode. */ - if (IS_USER(s)) - break; - offset =3D 0; - imm =3D 0; - if (insn & (1 << 10)) { - if (insn & (1 << 7)) - offset |=3D CPSR_A; - if (insn & (1 << 6)) - offset |=3D CPSR_I; - if (insn & (1 << 5)) - offset |=3D CPSR_F; - if (insn & (1 << 9)) - imm =3D CPSR_A | CPSR_I | CPSR_F; - } - if (insn & (1 << 8)) { - offset |=3D 0x1f; - imm |=3D (insn & 0x1f); - } - if (offset) { - gen_set_psr_im(s, offset, 0, imm); - } - break; + case 2: /* cps, nop-hint, in decodetree */ + goto illegal_op; case 3: /* Special control operations, in decodetree */ case 4: /* bxj, in decodetree */ goto illegal_op; diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index b077958cec..eb1c55b330 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -35,9 +35,12 @@ BLX_i 1111 101 . ........................ = &i imm=3D%imm24h =20 &rfe rn w pu &srs mode w pu +&cps mode imod M A I F =20 RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs +CPS 1111 0001 0000 imod:2 M:1 0 0000 000 A:1 I:1 F:1 0 mode:5= \ + &cps =20 # Clear-Exclusive, Barriers =20 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 18c268e712..354ad77fe6 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -44,6 +44,7 @@ &bfi !extern rd rn lsb msb &sat !extern rd rn satimm imm sh &pkh !extern rd rn rm imm tb +&cps !extern mode imod M A I F =20 # Data-processing (register) =20 @@ -340,6 +341,8 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ...= . @rdm SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=3D%imm16_16_0 + CPS 1111 0011 1010 1111 1000 0 imod:2 M:1 A:1 I:1 F:1 mode:5 \ + &cps UDF 1111 0111 1111 ---- 1010 ---- ---- ---- } B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=3D%i= mm21 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 36/68] target/arm: Convert SETEND X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.c | 22 +++++++++++++--------- target/arm/a32-uncond.decode | 4 ++++ 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 928205d993..46e88d1d17 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10124,6 +10124,18 @@ static bool trans_SB(DisasContext *s, arg_SB *a) return true; } =20 +static bool trans_SETEND(DisasContext *s, arg_SETEND *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + if (a->E !=3D (s->be_data =3D=3D MO_BE)) { + gen_helper_setend(cpu_env); + s->base.is_jmp =3D DISAS_UPDATE; + } + return true; +} + /* * Legacy decoder. */ @@ -10209,15 +10221,7 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) return; /* v7MP: Unallocated memory hint: must NOP */ } =20 - if ((insn & 0x0ffffdff) =3D=3D 0x01010000) { - ARCH(6); - /* setend */ - if (((insn >> 9) & 1) !=3D !!(s->be_data =3D=3D MO_BE)) { - gen_helper_setend(cpu_env); - s->base.is_jmp =3D DISAS_UPDATE; - } - return; - } else if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { + if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ if (extract32(s->c15_cpar, 1, 1)) { diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index eb1c55b330..d5ed48f0fd 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -24,6 +24,7 @@ =20 &empty !extern &i !extern imm +&setend E =20 # Branch with Link and Exchange =20 @@ -50,3 +51,6 @@ DSB 1111 0101 0111 1111 1111 0000 0100 ---- DMB 1111 0101 0111 1111 1111 0000 0101 ---- ISB 1111 0101 0111 1111 1111 0000 0110 ---- SB 1111 0101 0111 1111 1111 0000 0111 0000 + +# Set Endianness +SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 37/68] target/arm: Convert PLI, PLD, PLDW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.c | 37 +++++++++++++++++++----------------- target/arm/a32-uncond.decode | 10 ++++++++++ 2 files changed, 30 insertions(+), 17 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 46e88d1d17..a30a9bb4e0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10136,6 +10136,26 @@ static bool trans_SETEND(DisasContext *s, arg_SETE= ND *a) return true; } =20 +/* + * Preload instructions + * All are nops, contingent on the appropriate arch level. + */ + +static bool trans_PLD(DisasContext *s, arg_PLD *a) +{ + return ENABLE_ARCH_5TE; +} + +static bool trans_PLDW(DisasContext *s, arg_PLD *a) +{ + return arm_dc_feature(s, ARM_FEATURE_V7MP); +} + +static bool trans_PLI(DisasContext *s, arg_PLD *a) +{ + return ENABLE_ARCH_7; +} + /* * Legacy decoder. */ @@ -10196,23 +10216,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) } return; } - if (((insn & 0x0f30f000) =3D=3D 0x0510f000) || - ((insn & 0x0f30f010) =3D=3D 0x0710f000)) { - if ((insn & (1 << 22)) =3D=3D 0) { - /* PLDW; v7MP */ - if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { - goto illegal_op; - } - } - /* Otherwise PLD; v5TE+ */ - ARCH(5TE); - return; - } - if (((insn & 0x0f70f000) =3D=3D 0x0450f000) || - ((insn & 0x0f70f010) =3D=3D 0x0650f000)) { - ARCH(7); - return; /* PLI; V7 */ - } if (((insn & 0x0f700000) =3D=3D 0x04100000) || ((insn & 0x0f700010) =3D=3D 0x06100000)) { if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index d5ed48f0fd..aed381cb8e 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -54,3 +54,13 @@ SB 1111 0101 0111 1111 1111 0000 0111 0000 =20 # Set Endianness SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend + +# Preload instructions + +PLD 1111 0101 -101 ---- 1111 ---- ---- ---- # (imm, lit) 5= te +PLDW 1111 0101 -001 ---- 1111 ---- ---- ---- # (imm, lit) 7= mp +PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7 + +PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5= te +PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7= mp +PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 38/68] target/arm: Convert Unallocated memory hint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.c | 8 -------- target/arm/a32-uncond.decode | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index a30a9bb4e0..9ec6b25c03 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10216,14 +10216,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) } return; } - if (((insn & 0x0f700000) =3D=3D 0x04100000) || - ((insn & 0x0f700010) =3D=3D 0x06100000)) { - if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { - goto illegal_op; - } - return; /* v7MP: Unallocated memory hint: must NOP */ - } - if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index aed381cb8e..afa95bf7aa 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -64,3 +64,11 @@ PLI 1111 0100 -101 ---- 1111 ---- ---- ----= # (imm, lit) 7 PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5= te PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7= mp PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7 + +# Unallocated memory hints +# +# Since these are v7MP nops, and PLDW is v7MP and implemented as nop, +# (ab)use the PLDW helper. + +PLDW 1111 0100 -001 ---- ---- ---- ---- ---- +PLDW 1111 0110 -001 ---- ---- ---- ---0 ---- --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566252280; cv=none; d=zoho.com; s=zohoarc; b=dTF4lTN0wgzNkdeMh6XSVQyNw3mGffjCOThPQGKf7hyAsjhNUqV6ZlY0HNxeDc/zcuyfKc46T0mKgK7BQiHOuKaxXBbmLag0l5SNDYs4A/a5FQQ5eNm/7ElTkW7Crq5y76qy/5TXEQ2sx3flT5X5SNplliWGvG5xA+qHVbn37II= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566252280; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=4oWyeRO7VGSUxbfq5SQ/Ttd5DuqgQfk+9PyV2J/44KI=; b=CC3LT1u/GZUHXd4niW+dMJ9mmvk/4yqGwKAHns6o/SccFjAOz/x8Z103xuoOAEpZz5yIAsyHnNlIbA9JFWCykTilLQBrtECZb9cG3oOPOQyjpXWGJp8WZ1awVA2b/qfsFCBqmF/Ph14FlTdWsj50W2you6FCv+5dEY9I+7PlIVk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566252280197689.3924109586152; Mon, 19 Aug 2019 15:04:40 -0700 (PDT) Received: from localhost ([::1]:59450 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzplW-0001eR-TU for importer@patchew.org; Mon, 19 Aug 2019 18:04:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59474) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMX-0002Nn-AD for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMU-0006Vw-UP for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:49 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:37319) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMU-0006V9-Ok for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:46 -0400 Received: by mail-pl1-x62c.google.com with SMTP id bj8so1586758plb.4 for ; Mon, 19 Aug 2019 14:38:46 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::62c Subject: [Qemu-devel] [PATCH v2 39/68] target/arm: Convert Table Branch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 57 +++++++++++++++++++++++++----------------- target/arm/t32.decode | 8 +++++- 2 files changed, 41 insertions(+), 24 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9ec6b25c03..7c05e7006e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9968,6 +9968,37 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *= a) return true; } =20 +static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) +{ + TCGv_i32 addr, tmp; + + tmp =3D load_reg(s, a->rm); + if (half) { + tcg_gen_add_i32(tmp, tmp, tmp); + } + addr =3D load_reg(s, a->rn); + tcg_gen_add_i32(addr, addr, tmp); + + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), + half ? MO_UW | s->be_data : MO_UB); + tcg_temp_free_i32(addr); + + tcg_gen_add_i32(tmp, tmp, tmp); + tcg_gen_addi_i32(tmp, tmp, read_pc(s)); + store_reg(s, 15, tmp); + return true; +} + +static bool trans_TBB(DisasContext *s, arg_tbranch *a) +{ + return op_tbranch(s, a, false); +} + +static bool trans_TBH(DisasContext *s, arg_tbranch *a) +{ + return op_tbranch(s, a, true); +} + /* * Supervisor call */ @@ -10350,9 +10381,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, ui= nt32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rm, rs; - TCGv_i32 tmp; - TCGv_i32 addr; + uint32_t rd, rn, rs; int op; =20 /* @@ -10398,7 +10427,6 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) rn =3D (insn >> 16) & 0xf; rs =3D (insn >> 12) & 0xf; rd =3D (insn >> 8) & 0xf; - rm =3D insn & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ @@ -10471,25 +10499,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) /* Load/store exclusive, in decodetree */ goto illegal_op; } else if ((insn & (7 << 5)) =3D=3D 0) { - /* Table Branch. */ - addr =3D load_reg(s, rn); - tmp =3D load_reg(s, rm); - tcg_gen_add_i32(addr, addr, tmp); - if (insn & (1 << 4)) { - /* tbh */ - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); - } else { /* tbb */ - tcg_temp_free_i32(tmp); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); - } - tcg_temp_free_i32(addr); - tcg_gen_shli_i32(tmp, tmp, 1); - tcg_gen_addi_i32(tmp, tmp, read_pc(s)); - store_reg(s, 15, tmp); + /* Table Branch, in decodetree */ + goto illegal_op; } else { /* Load/store exclusive, load-acq/store-rel, in decodetree= */ goto illegal_op; diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 354ad77fe6..0cc0808c05 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -487,7 +487,7 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... ........= @ldstd_ri8 w=3D0 p=3D1 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 =20 -# Load/Store Exclusive and Load-Acquire/Store-Release +# Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch =20 @strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \ &strex rt2=3D15 imm=3D%imm8x4 @@ -531,6 +531,12 @@ LDA 1110 1000 1101 .... .... 1111 1010 11= 11 @ldrex_0 LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 =20 +&tbranch rn rm +@tbranch .... .... .... rn:4 .... .... .... rm:4 &tbranch + +TBB 1110 1000 1101 .... 1111 0000 0000 .... @tbranch +TBH 1110 1000 1101 .... 1111 0000 0001 .... @tbranch + # Parallel addition and subtraction =20 SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566252362; cv=none; d=zoho.com; s=zohoarc; b=J916adSgnXN91E9S9xnj9QDI6nwAR2c65UHXL0PZtelGB4kamofFj5wwr243QpK6NdimDph+92tOmsNxjR3fMeytQcVdTJg52WiBLauywqNc5WN7I/7ZzI9punMIfl7D00WlYmT1oXULYU314tj3ob6ZyaV7Axnr84Fx9qwKQxI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566252362; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=wLniY7IH5XOVstT1ZURU/Pqp4JvYW6tk9V3WWoNomaw=; b=gMS1njAL10D4OeT9dE0uo5MaEDzevUFGz+WaR9zYoA+3VMrYrDxwrCibCUBTimWtQNJwkUXlxfNiNMSBnQTjpgLfZv2LEPeni09rO80AR1LDPm6cYqTnKlEjAVaTC4+7D1UYAaHVoLQX3lAwMAoJ3WvkrWUmvxAOTnUaVajiMTc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566252362774621.3123316534214; Mon, 19 Aug 2019 15:06:02 -0700 (PDT) Received: from localhost ([::1]:59480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpmo-0003ua-4l for importer@patchew.org; Mon, 19 Aug 2019 18:05:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59513) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMb-0002Px-9w for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMX-0006Yu-F3 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:53 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:46332) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMX-0006W0-7m for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:49 -0400 Received: by mail-pf1-x443.google.com with SMTP id q139so1933662pfc.13 for ; Mon, 19 Aug 2019 14:38:47 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wLniY7IH5XOVstT1ZURU/Pqp4JvYW6tk9V3WWoNomaw=; b=Fzr8/0vmfS6tSszW7ZllixzfRjddneCkY3yTW+m9YASnALE0+/I7xJV/rXV2NlepPR l7fvYZFPWDJL4lkV5FoRQLS2oyKNOCjBasxe7Hy6SFdbHARbFNwLcaGGdqyyz0tPi3a8 cG5BPLHtvUaf9yk6KZgXd7IWYlPTbyuXchEl0ZaMsxJpDU6rjB1cKu79L0ZCv49UG5dt MhasRf1cTv4f3KH2ZUvuF6HuvbZHRgrKqfTxu9533K1jNkvSMtnqF7jO6Ky2mWlkh8o/ eTdvgsbPzhgo2hX1QvhOE5VDz0vzv/HbIczzBC90C4q1HZyhPqLphzwnEqY82AgH015a rTrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wLniY7IH5XOVstT1ZURU/Pqp4JvYW6tk9V3WWoNomaw=; b=LZxl+3tunOJvda6koIuZWd33iR/h48GSAIgf+o/ej5Wgd2G2o6JDLyaevqIacBeoad SJI2y7aZi4IceKzI8tSfNAjhoZwraMglHLm2+KqjFcOgJbC0D+3IeXds7OycB4a1Maqo vkK7LfQfyAgl6q21mJtFALF790D1WHQoT7T0tQqqQjIkmBk5vHfbEe9qtobVLT2RzESx 0kh0DDnhLavXul7m8f2LiX9rur8motXcax7/DavOmCYTiFZrKJlH6QOHEjuQhY4e6Y3W DkfPUX9sBDtCIFG3b+ORx/hz3fxvqM0NggsYhASNQCB4/GUsC9rbSlTs7BXq6TjlJ+gu cGpQ== X-Gm-Message-State: APjAAAUz0Ips9zw0Ecjh+HYzRPQMS/eYKmXZdlJFhEeQTwZHkTtQ9Y3N 4yZ9dd5OqfbnsGz+1hEBxUWxlKMDbOc= X-Google-Smtp-Source: APXvYqx8KCW+nrN2cD+a0gmjz2UlXqpJ5QkZDzVHodaw9BoHuge5eQPGsicGc4GCCsuoXHw1Og74nQ== X-Received: by 2002:a62:2603:: with SMTP id m3mr27356125pfm.163.1566250726092; Mon, 19 Aug 2019 14:38:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:27 -0700 Message-Id: <20190819213755.26175-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v2 40/68] target/arm: Convert SG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 51 ++++++++++++++++++++++++------------------ target/arm/t32.decode | 5 ++++- 2 files changed, 33 insertions(+), 23 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 7c05e7006e..9a8864e8ff 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8426,6 +8426,34 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a) return true; } =20 +static bool trans_SG(DisasContext *s, arg_SG *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + /* + * SG (v8M only) + * The bulk of the behaviour for this instruction is implemented + * in v7m_handle_execute_nsc(), which deals with the insn when + * it is executed by a CPU in non-secure state from memory + * which is Secure & NonSecure-Callable. + * Here we only need to handle the remaining cases: + * * in NS memory (including the "security extension not + * implemented" case) : NOP + * * in S memory but CPU already secure (clear IT bits) + * We know that the attribute for the memory this insn is + * in must match the current CPU state, because otherwise + * get_phys_addr_pmsav8 would have generated an exception. + */ + if (s->v8m_secure) { + /* Like the IT insn, we don't need to generate any code */ + s->condexec_cond =3D 0; + s->condexec_mask =3D 0; + } + return true; +} + /* * Load/store register index */ @@ -10437,28 +10465,7 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) * - load/store doubleword, load/store exclusive, ldacq/strel, * table branch, TT. */ - if (insn =3D=3D 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M)= && - arm_dc_feature(s, ARM_FEATURE_V8)) { - /* 0b1110_1001_0111_1111_1110_1001_0111_111 - * - SG (v8M only) - * The bulk of the behaviour for this instruction is imple= mented - * in v7m_handle_execute_nsc(), which deals with the insn = when - * it is executed by a CPU in non-secure state from memory - * which is Secure & NonSecure-Callable. - * Here we only need to handle the remaining cases: - * * in NS memory (including the "security extension not - * implemented" case) : NOP - * * in S memory but CPU already secure (clear IT bits) - * We know that the attribute for the memory this insn is - * in must match the current CPU state, because otherwise - * get_phys_addr_pmsav8 would have generated an exception. - */ - if (s->v8m_secure) { - /* Like the IT insn, we don't need to generate any cod= e */ - s->condexec_cond =3D 0; - s->condexec_mask =3D 0; - } - } else if (insn & 0x01200000) { + if (insn & 0x01200000) { /* load/store dual, in decodetree */ goto illegal_op; } else if ((insn & (1 << 23)) =3D=3D 0) { diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 0cc0808c05..ce46650446 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -485,7 +485,10 @@ STRD_ri_t32 1110 1001 .100 .... .... .... .......= . @ldstd_ri8 w=3D0 p=3D1 LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=3D= 0 p=3D1 =20 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 -LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 +{ + SG 1110 1001 0111 1111 1110 1001 01111111 + LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 +} =20 # Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch =20 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ac3UBjPihyDkOeX0vZxfIb3puwN3GecMDaJ1xyBUXaw=; b=VRiUNrzCYdV2Fjxa9QpObGV22NV5RPDM6YKfqC4R20btrDTQT8tH2oFbUdq0MujkiR Ar7IApPhQp9siEY3cQ4oMIqajBbJSIJnTguFuyETeCWbJudkZv3d1a4NvTrqH+T1+7ti tmM/p9YsIVcaJD73f4veRXN80sWJI418zM7CPyToiKXXm5sNLwHwonFjukw3eDzsF8nA eoVp3KQ9ygS6g7ikDHI/qDWCT99hsBRCJPIhWREG5fB71UF2JA608xjS7BbznGPrpjr7 +rOaq0j2JISMe0HktD7nS3ceRRmiA4Ac7Q556zguAO8PJABdXOJINGYKm53YOjTe1wY8 O4cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ac3UBjPihyDkOeX0vZxfIb3puwN3GecMDaJ1xyBUXaw=; b=isLiqaxi+20xOL8QyyMkuPjNQW/02RFcZMtpY8zmjEGdGTbOGJ8DEN8oeXfeTGfCSP 3jTQwd3f+ssqf4U1okDwKluzec/v8Aqd8V+Chc4xIqD36YNa1ZRA4WGJdxnc6R8duZjy WzkwrL5x7khdwDkc/jF96v8E6rpbuc1I0y/qdaZlWKTdcPCNS7m8DV0FHMjJaCK3ZR96 CTHQdO2+4/5UBjYQXm9y1uKhhrA1lF9qPchTK9dmZBj+WggqEUSNM2zNJxXBfRI+t3zK t5xtfvSxcdDfsHOUG6oRxf24rSfaKB8KwP7EIXj1R48z1NFgRDqncfqzlQb5TmtCYUwq sXQA== X-Gm-Message-State: APjAAAURifEgTwbb1HnIXvM/AfkC/88v15cPs0Q2ITQ9QAq3BaYFDDuy XYg3qic0BJE0ahMuJ0rTiyunkDG00zU= X-Google-Smtp-Source: APXvYqx4LamgaJDw1LT9cmAMavLrBNJ6adbVGQ37v05DG++uJiE2J3bkryRjBmrLH9Pat3vO0hUX8Q== X-Received: by 2002:a17:902:2bc5:: with SMTP id l63mr22378145plb.239.1566250727323; Mon, 19 Aug 2019 14:38:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:28 -0700 Message-Id: <20190819213755.26175-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 41/68] target/arm: Convert TT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 87 +++++++++++++----------------------------- target/arm/t32.decode | 5 ++- 2 files changed, 31 insertions(+), 61 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9a8864e8ff..d1078ca1ec 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8454,6 +8454,30 @@ static bool trans_SG(DisasContext *s, arg_SG *a) return true; } =20 +static bool trans_TT(DisasContext *s, arg_TT *a) +{ + TCGv_i32 addr, tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + if (a->rd =3D=3D 13 || a->rd =3D=3D 15 || a->rn =3D=3D 15) { + /* We UNDEF for these UNPREDICTABLE cases */ + return false; + } + if (a->A && !s->v8m_secure) { + return false; + } + + addr =3D load_reg(s, a->rn); + tmp =3D tcg_const_i32((a->A << 1) | a->T); + gen_helper_v7m_tt(tmp, cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + store_reg(s, a->rd, tmp); + return true; +} + /* * Load/store register index */ @@ -10409,7 +10433,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, ui= nt32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rs; + uint32_t rn; int op; =20 /* @@ -10453,70 +10477,13 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) /* fall back to legacy decoder */ =20 rn =3D (insn >> 16) & 0xf; - rs =3D (insn >> 12) & 0xf; - rd =3D (insn >> 8) & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ abort(); case 4: - if (insn & (1 << 22)) { - /* 0b1110_100x_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store doubleword, load/store exclusive, ldacq/strel, - * table branch, TT. - */ - if (insn & 0x01200000) { - /* load/store dual, in decodetree */ - goto illegal_op; - } else if ((insn & (1 << 23)) =3D=3D 0) { - /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store exclusive word - * - TT (v8M only) - */ - if (rs =3D=3D 15) { - if (!(insn & (1 << 20)) && - arm_dc_feature(s, ARM_FEATURE_M) && - arm_dc_feature(s, ARM_FEATURE_V8)) { - /* 0b1110_1000_0100_xxxx_1111_xxxx_xxxx_xxxx - * - TT (v8M only) - */ - bool alt =3D insn & (1 << 7); - TCGv_i32 addr, op, ttresp; - - if ((insn & 0x3f) || rd =3D=3D 13 || rd =3D=3D 15 = || rn =3D=3D 15) { - /* we UNDEF for these UNPREDICTABLE cases */ - goto illegal_op; - } - - if (alt && !s->v8m_secure) { - goto illegal_op; - } - - addr =3D load_reg(s, rn); - op =3D tcg_const_i32(extract32(insn, 6, 2)); - ttresp =3D tcg_temp_new_i32(); - gen_helper_v7m_tt(ttresp, cpu_env, addr, op); - tcg_temp_free_i32(addr); - tcg_temp_free_i32(op); - store_reg(s, rd, ttresp); - break; - } - goto illegal_op; - } - /* Load/store exclusive, in decodetree */ - goto illegal_op; - } else if ((insn & (7 << 5)) =3D=3D 0) { - /* Table Branch, in decodetree */ - goto illegal_op; - } else { - /* Load/store exclusive, load-acq/store-rel, in decodetree= */ - goto illegal_op; - } - } else { - /* Load/store multiple, RFE, SRS, in decodetree */ - goto illegal_op; - } - break; + /* All in decodetree */ + goto illegal_op; case 5: /* All in decodetree */ goto illegal_op; diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ce46650446..bb875f77b0 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -506,7 +506,10 @@ STRD_ri_t32 1110 1001 .110 .... .... .... .......= . @ldstd_ri8 w=3D1 p=3D1 @ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \ &ldrex imm=3D0 =20 -STREX 1110 1000 0100 .... .... .... .... .... @strex_i +{ + TT 1110 1000 0100 rn:4 1111 rd:4 A:1 T:1 000000 + STREX 1110 1000 0100 .... .... .... .... .... @strex_i +} STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0 STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0 STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566253289; cv=none; d=zoho.com; s=zohoarc; b=JZO5Ep1S0d21yEYVYMSbAyOJOVCvEnm8AT0RkNgvYZxnEkLBZX8eShUFvKGGTH54PBypVNSV9qOaTWvyAVGSnSXuL8uZpQit5wIj5HYB3SkZRDcxBuN947ozEwoV9O7J7xAFwzCXnBnbuUb4IcAIj9fUIxXRkhgSqdpLPZZSLuA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566253289; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ya11/VX/aRn7vG6mAkOVxrie0vDf0+2x0xJimT8Kw/s=; b=aHlzDIOr6gXjBYhpYyg+Wb53YUyx6H3182h+HTnCt9gV3N7dW0Z1HIVfFM6eRQUEi7JSXB+ny58nKqcTxCGeBwYf3ojvG+bu9XiGdz0PuNmvNtFxe6I0wVBcEUbyqNmnNTko8E7NKZ5ZPaUQCYmJE6wspu4mxJ+ZUnvvRSzxZ8Y= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566253289127739.6860382854038; Mon, 19 Aug 2019 15:21:29 -0700 (PDT) Received: from localhost ([::1]:59838 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzq1n-000122-Cm for importer@patchew.org; Mon, 19 Aug 2019 18:21:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59590) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMf-0002S4-BG for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMd-0006d1-A6 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:57 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:43897) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMb-0006Ya-92 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:55 -0400 Received: by mail-pl1-x644.google.com with SMTP id 4so1584506pld.10 for ; Mon, 19 Aug 2019 14:38:49 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ya11/VX/aRn7vG6mAkOVxrie0vDf0+2x0xJimT8Kw/s=; b=I3cLjXuSdVRvaHttEFWO9xBVqNs1NkIOgvZVedtNuoVMPL71J3umdP1DUTEkzHkCSJ KMDZSOE4l1CDRRan+IG4AprZMjriFaLecR9fv2URZ7NjbDPZAAYvx5huDgW1/sw1euGZ bEHpTWn89HiwJ2N+yqUrAqeSsT9YG1ILdHpjkIsk07CyPj6NLkTZYMiep26znN9lzY+Z nBNDMoSI/7K49b/f5I+r/PAb7D8VcXB32Kpw0cKPHl3VN34eOJ9BBucSubGXNqK5RYuE yoWDnwrcBiWg44E/ffk4oua5oTGg14oCYsyaGYayIkaSj12MxODfOiGUC5t5e0lBUIrE nPhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ya11/VX/aRn7vG6mAkOVxrie0vDf0+2x0xJimT8Kw/s=; b=lv3q8VXjGdikn6WmqoNRAH4uzflF5LLt9G808ahSXaqnCF2hR/jCWHkDDGDXm4iWk0 zJDKk94nva4e5MW6W6lPw03jCATw6YelC8EcJkXa8esq+aHsCqPnAPSnkofIZ/FnsLk5 hwSh1HDMO3Ca6Qi2v4lnoWkNLzntdqMFdosNQ7QSaHmf6Ns7zxcqoP+aEUejW61Vid8W lRr7ScQHUG6JzEcwy5Ih1ys75Zi94VR4IXsgxnmWdC24DfY1aualRnr+xpWxxWMeCrTC TkcU4viYY3KCL88m+cBW09GJEVI+kSrLoH4j543WRS1JDq3rjJOgWT+Ac0/q2wqvDc97 2rLA== X-Gm-Message-State: APjAAAX6w5ciEinNVgL/pRxObL2+MTBwnFCV1Si2R4CTz0wjEh46EnCp Qk9I4Rb5hTY6LsdLVljKF42zWoQyScA= X-Google-Smtp-Source: APXvYqzlo+d5k+D+qQ6WqPxHhAgweq6oUyBsw/d97NTJlpfUxwz5l70LANos5TgZDTx28i5gm0bMJA== X-Received: by 2002:a17:902:6b07:: with SMTP id o7mr24108861plk.180.1566250728492; Mon, 19 Aug 2019 14:38:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:29 -0700 Message-Id: <20190819213755.26175-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 42/68] target/arm: Simplify disas_thumb2_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fold away all of the cases that now just goto illegal_op, because all of their internal bits are now in decodetree. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 79 ++---------------------------------------- 1 file changed, 3 insertions(+), 76 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d1078ca1ec..25c74206c2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10433,9 +10433,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, ui= nt32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rn; - int op; - /* * ARMv6-M supports a limited subset of Thumb2 instructions. * Other Thumb1 architectures allow only 32-bit @@ -10476,34 +10473,10 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) } /* fall back to legacy decoder */ =20 - rn =3D (insn >> 16) & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ abort(); - case 4: - /* All in decodetree */ - goto illegal_op; - case 5: - /* All in decodetree */ - goto illegal_op; - case 13: /* Misc data processing. */ - op =3D ((insn >> 22) & 6) | ((insn >> 7) & 1); - if (op < 4 && (insn & 0xf000) !=3D 0xf000) - goto illegal_op; - switch (op) { - case 0: /* Register controlled shift, in decodetree */ - case 1: /* Sign/zero extend, in decodetree */ - case 2: /* SIMD add/subtract, in decodetree */ - case 3: /* Other data processing, in decodetree */ - goto illegal_op; - case 4: case 5: - /* 32-bit multiply. Sum of absolute differences, in decodetre= e */ - goto illegal_op; - case 6: case 7: /* 64-bit multiply, Divide, in decodetree */ - goto illegal_op; - } - break; case 6: case 7: case 14: case 15: /* Coprocessor. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { @@ -10532,6 +10505,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) } =20 if (arm_dc_feature(s, ARM_FEATURE_VFP)) { + uint32_t rn =3D (insn >> 16) & 0xf; TCGv_i32 fptr =3D load_reg(s, rn); =20 if (extract32(insn, 20, 1)) { @@ -10590,50 +10564,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } } break; - case 8: case 9: case 10: case 11: - if (insn & (1 << 15)) { - /* Branches, misc control. */ - if (insn & 0x5000) { - /* Unconditional branch, in decodetree */ - goto illegal_op; - } else if (((insn >> 23) & 7) =3D=3D 7) { - /* Misc control */ - if (insn & (1 << 13)) - goto illegal_op; - - if (insn & (1 << 26)) { - /* hvc, smc, in decodetree */ - goto illegal_op; - } else { - op =3D (insn >> 20) & 7; - switch (op) { - case 0: /* msr cpsr, in decodetree */ - case 1: /* msr spsr, in decodetree */ - goto illegal_op; - case 2: /* cps, nop-hint, in decodetree */ - goto illegal_op; - case 3: /* Special control operations, in decodetree */ - case 4: /* bxj, in decodetree */ - goto illegal_op; - case 5: /* Exception return. */ - case 6: /* MRS, in decodetree */ - case 7: /* MSR, in decodetree */ - goto illegal_op; - } - } - } else { - /* Conditional branch, in decodetree */ - goto illegal_op; - } - } else { - /* - * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx - * - Data-processing (modified immediate, plain binary immedi= ate) - * All in decodetree. - */ - goto illegal_op; - } - break; case 12: if ((insn & 0x01100000) =3D=3D 0x01000000) { if (disas_neon_ls_insn(s, insn)) { @@ -10641,14 +10571,11 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) } break; } - /* Load/store single data item, in decodetree */ goto illegal_op; default: - goto illegal_op; + illegal_op: + unallocated_encoding(s); } - return; -illegal_op: - unallocated_encoding(s); } =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566253156; cv=none; d=zoho.com; s=zohoarc; b=k24p5FDpeesn9ZOapddztTBaA3uNClk/59+uooD27S7VWdi/1GwG6zM2vteiotQqJOZtSkYW+AwFdwmivPzuTwAaeb8RNqPrpXFs418vaKSWpyaJ8b6p3ePSMAWwpwlz2utU3S0fyAs8NphdW3lYbbvyOSW9eU86yRGBmECPkdE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566253156; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=c57Ge3veQfkyW7vksKvqnmVUD20AJ8LyQ3MkWHHu68w=; b=AObuOWUAW4owowQ7uWoAkQqJ3VdYZ6zUrng7QcLAMB5DN3QtijZLkrIN+0sofJ4RaGtbQIStVGIqF4OuuIjDAZIr2W2YJ2IwhGlSkQcA1b508Qomu9UX2OpafnS3IjOXHHtBkezlsA9xZ6R7ASAhyfdJmr/CRnd7TueSq64x1uk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566253156917416.95980968544177; Mon, 19 Aug 2019 15:19:16 -0700 (PDT) Received: from localhost ([::1]:59790 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpzf-00068A-7u for importer@patchew.org; Mon, 19 Aug 2019 18:19:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59592) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMf-0002S8-Bt for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMd-0006ci-8y for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:57 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:41490) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMb-0006ZH-8T for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:54 -0400 Received: by mail-pl1-x641.google.com with SMTP id m9so1578429pls.8 for ; Mon, 19 Aug 2019 14:38:50 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=c57Ge3veQfkyW7vksKvqnmVUD20AJ8LyQ3MkWHHu68w=; b=DCwIxhDjQ+vIrTflFcWht7h6SrT3HijQEDrF5uGuRMnbgQOyuOcrOKlpTCutUHMmuJ HAh2+h4AHBPd19EdTEL1xc7uY4xoEEu8177qgEDabglk7DaGwaD7UiSHzlC0064M9WbC JYfeK/IwyV6eKqmM0K35aSn1SG7EOSYg7aXa3Nw3AEC1M9vh8URAk9Iq5RPK88/I2VqS 8x0wCL+rHUgMQbsIjgglapkD2a/N5HVUEXNawSNd65/Mf2GhIY3pv5aivlg/QydC0guF ZRV754R0xllZtGSptpPtFh6gyBAim+exDg4tfLExGwmQZrdE9f5Pc0CC0uZ6FTE82m6u ozrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=c57Ge3veQfkyW7vksKvqnmVUD20AJ8LyQ3MkWHHu68w=; b=UU4ok+YOFT33nfmrugHF+mPFFv8P1VolHA1gKbinhMeBR1pN2/wj7tPLp3GVd8e/i3 zsMHCaGtt8kvtEzqDRFvGFtqUYSTG2xcOxpU1Kr7uddY5hD0mfD90/9eQhKQMHagfRez ULuF9UyMHJMCM1J7jDkpiNUdh2unhlcBAX71qm7W2v/ZhKkevgIRTmGanyazs7h3ZTfE GdtHNEKzOyag46schsfAJUYx6hfmaY6mozUyQA4E24q+bBZsGC3iRDvS8m8N5hhAkwCS j6zK80m4TGvf6BMW8P8P48/GQSwlvxukTYjxmHqjm7cKqdpmjibhHX7rFDxCtJoqimPZ 63FA== X-Gm-Message-State: APjAAAXzplIZ3PU1rX/9ADCkN/hKZuLDJLnr+sNPDf2QIRI0T7TA27bC FKniH0R9dx7TSVtUczzn0Cy287BFNk8= X-Google-Smtp-Source: APXvYqwHa9n174E1tI4HKGvVnsAuZ4KKYQlwiqhmYq0pB7QhgU17V/pIkKHJM9rVxNEmPGZWMWQIiA== X-Received: by 2002:a17:902:e48d:: with SMTP id cj13mr2127884plb.177.1566250729553; Mon, 19 Aug 2019 14:38:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:30 -0700 Message-Id: <20190819213755.26175-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 43/68] target/arm: Simplify disas_arm_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fold away all of the cases that now just goto illegal_op, because all of their internal bits are now in decodetree. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 69 ++++++++++-------------------------------- 1 file changed, 16 insertions(+), 53 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 25c74206c2..49bab7d863 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10245,7 +10245,7 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a) =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, op1; + unsigned int cond =3D insn >> 28; =20 /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -10255,7 +10255,6 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) default_exception_el(s)); return; } - cond =3D insn >> 28; =20 if (cond =3D=3D 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we @@ -10320,11 +10319,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) goto illegal_op; } return; - } else if ((insn & 0x0fe00000) =3D=3D 0x0c400000) { - /* Coprocessor double register transfer. */ - ARCH(5TE); - } else if ((insn & 0x0f000010) =3D=3D 0x0e000010) { - /* Additional coprocessor register transfer. */ } goto illegal_op; } @@ -10339,55 +10333,24 @@ static void disas_arm_insn(DisasContext *s, unsig= ned int insn) } /* fall back to legacy decoder */ =20 - if ((insn & 0x0f900000) =3D=3D 0x03000000) { - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - } else if ((insn & 0x0f900000) =3D=3D 0x01000000 - && (insn & 0x00000090) !=3D 0x00000090) { - /* miscellaneous instructions */ - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - } else if (((insn & 0x0e000000) =3D=3D 0 && - (insn & 0x00000090) !=3D 0x90) || - ((insn & 0x0e000000) =3D=3D (1 << 25))) { - /* Data-processing (reg, reg-shift-reg, imm). */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - /* other instructions */ - op1 =3D (insn >> 24) & 0xf; - switch(op1) { - case 0x0: - case 0x1: - case 0x4: - case 0x5: - case 0x6: - case 0x7: - case 0x08: - case 0x09: - case 0xa: - case 0xb: - case 0xf: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - case 0xc: - case 0xd: - case 0xe: - if (((insn >> 8) & 0xe) =3D=3D 10) { - /* VFP. */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - } else if (disas_coproc_insn(s, insn)) { - /* Coprocessor. */ + switch ((insn >> 24) & 0xf) { + case 0xc: + case 0xd: + case 0xe: + if (((insn >> 8) & 0xe) =3D=3D 10) { + /* VFP. */ + if (disas_vfp_insn(s, insn)) { goto illegal_op; } - break; - default: - illegal_op: - unallocated_encoding(s); - break; + } else if (disas_coproc_insn(s, insn)) { + /* Coprocessor. */ + goto illegal_op; } + break; + default: + illegal_op: + unallocated_encoding(s); + break; } } =20 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566253002; cv=none; d=zoho.com; s=zohoarc; b=DPgqk1CFpQUnETlMjdRwIZtYh52+iKSPTVHHYAIPbHjoymOjTjSB/UeoXZxQKeUsSZthLWT+GJO5WTsWCNFLFghOODSgsrOsF/nwS4nGnmM/S/DtBfK6LWAD0IAMUz/A5oRetgV16wymvwp/JbHuWepEwIEGLIyX77WmNSfbuUE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566253002; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=BfxhiN9KVAYzZaSCSHTjQwUy5qzA5PRPe+BsdkgEMbc=; b=lphzFdHZIrA7fFVxlXw3rbTX+sLfj8REvBYBt8xZY/fuTi2bbsKsgLc/ttU9yiBUag9LWHcuNptDzarrm+pid993hS9l4KZo8HDU2WJ7eBqiDiBojpIi6NynFD2VS+c7jUykpIrsouaJLTPm3Cxjoa2QIhR8/05WSunErXSSMh8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566253002211183.08802494365727; Mon, 19 Aug 2019 15:16:42 -0700 (PDT) Received: from localhost ([::1]:59734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpxA-0001vT-Pe for importer@patchew.org; Mon, 19 Aug 2019 18:16:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59594) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMf-0002SB-DG for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMd-0006dE-BY for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:57 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:35170) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMb-0006Zb-8t for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:55 -0400 Received: by mail-pl1-x643.google.com with SMTP id gn20so1589900plb.2 for ; Mon, 19 Aug 2019 14:38:51 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BfxhiN9KVAYzZaSCSHTjQwUy5qzA5PRPe+BsdkgEMbc=; b=YbWqlQ1FUre1zS50UU5iFqvHcfv/hidgQU2q+eCjx+H5GQoVPigDyYNImUtMo7qeiP hMs+geXRTiCY+ia4a+J+BylzQXYdF/OU3VJgUKxdqQd1UO+xK0O8aVh6bl6iFGnjHERG Za7xa5ltWcUupTh/YLjw7TpMgO8ifjM4p8cR52gyxKa//FSlTQLdFN3DQGeZvjM9hkUP 8uDw6emDiSiKK/SA/39lwgXKegAgzhefeShGmMNabU+12NBCUIY3xBuWT8JeL6QXexGl pTVIZQeexKcTeaUw5jiYeykQiJcrE8IOm4FPYch8ZxydXQTpH0b9t+lvxuJIOr4vVmtc ZYlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BfxhiN9KVAYzZaSCSHTjQwUy5qzA5PRPe+BsdkgEMbc=; b=PF1bZpYacAgpiFywGLi/K9JmYjtMr4+Cb2aWRqd+lY6mxKJB6EIo4h+eRkK1JWHnfE M2TIpOki6UzeFn3LXLvAH2irjOgs/0+LLuarqKd7hM+oAZKv2VevrchT1GFQMNBd+2zJ bAFYfVIHO5kIv/ixJhH/hZZEJeWvK8n5+pohsQ5evZCGkig+cLWeiBb/PVIcTE/nxjEt jX9E27rqSc20wuke0RsozuVzHYKrbcJvW66UeIXqqYFsCxw04kNVC0tCIUbcn63IHHz3 HKOtk+RD3ZZhSoaoSBxD9AbjoNa7Ww7yVsDPDkb2Y7RhwrsIFWZ8a2wP0FO1zdpYFfeH 9JZw== X-Gm-Message-State: APjAAAWTYAmv+pxnyBkNgsy6SaMKVTuptzGfkRBQnVgWNzrIlskBdy93 Pi289Xj5Y+OI+3BTX+g0bcbidGXGekQ= X-Google-Smtp-Source: APXvYqzOMPpw2ICebjUfqMZ2W9I2ozG+hTftPhaEv0s8IRN9p0aN33/+20XkkMY0+Sk536/km1FOZg== X-Received: by 2002:a17:902:6bc7:: with SMTP id m7mr25197711plt.60.1566250730808; Mon, 19 Aug 2019 14:38:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:31 -0700 Message-Id: <20190819213755.26175-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 44/68] target/arm: Add skeleton for T16 decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.c | 6 ++++++ target/arm/Makefile.objs | 6 ++++++ target/arm/t16.decode | 20 ++++++++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 target/arm/t16.decode diff --git a/target/arm/translate.c b/target/arm/translate.c index 49bab7d863..90d608a2d2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7538,6 +7538,7 @@ static int t32_branch24(DisasContext *s, int x) #include "decode-a32.inc.c" #include "decode-a32-uncond.inc.c" #include "decode-t32.inc.c" +#include "decode-t16.inc.c" =20 /* Helpers to swap operands for reverse-subtract. */ static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) @@ -10550,6 +10551,11 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) TCGv_i32 tmp2; TCGv_i32 addr; =20 + if (disas_t16(s, insn)) { + return; + } + /* fall back to legacy decoder */ + switch (insn >> 12) { case 0: case 1: =20 diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 7806b4dac0..cf26c16f5f 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -43,12 +43,18 @@ target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32= .decode $(DECODETREE) $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ "GEN", $(TARGET_DIR)$@) =20 +target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETRE= E) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c target/arm/translate.o: target/arm/decode-a32.inc.c target/arm/translate.o: target/arm/decode-a32-uncond.inc.c target/arm/translate.o: target/arm/decode-t32.inc.c +target/arm/translate.o: target/arm/decode-t16.inc.c =20 obj-y +=3D tlb_helper.o debug_helper.o obj-y +=3D translate.o op_helper.o diff --git a/target/arm/t16.decode b/target/arm/t16.decode new file mode 100644 index 0000000000..e954f61fe4 --- /dev/null +++ b/target/arm/t16.decode @@ -0,0 +1,20 @@ +# Thumb1 instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566252471; cv=none; d=zoho.com; s=zohoarc; b=RIN7eCksXv6XSHvgmRpuavSGqGKHqeEy6Iz097qkYUTLTmIscqd6yU4N/rh5+fOLXqcAyNUMkRJMaeI4f8XSvUcYq0KzgaklfWNyfNPKdGZzbOrOJSjjSkbbBAFmOfVQn0GmT21N5k40ipXx1/5jVNCto6eF2KEnl5Usg44JCG8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566252471; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=NNqewFxAhp3TmNZYeBy2lNscR/CrnSrYWBFvc4ZcTG4=; b=QcBbYmW5pu41/J2lTHYTAxpCD7SQPcMmMcqFPcEHrHTSRXQLMyuZLlWGWPLMPgF7p8B6kDcFKUrb/U68vkjGvjcI+FC6RsRONm9XhD9u3hsnyoJKqSV3JMMHLRczBxa2aQY9VADDbcbT8XorO0maUhAz4STlq9zHQV9BZQ8Gj2w= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566252471868981.5374166195032; Mon, 19 Aug 2019 15:07:51 -0700 (PDT) Received: from localhost ([::1]:59534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpoa-0006j3-FG for importer@patchew.org; Mon, 19 Aug 2019 18:07:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59641) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMh-0002T1-Dh for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMf-0006fi-BG for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:59 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:40808) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMd-0006au-8N for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:57 -0400 Received: by mail-pg1-x542.google.com with SMTP id w10so1927984pgj.7 for ; Mon, 19 Aug 2019 14:38:53 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NNqewFxAhp3TmNZYeBy2lNscR/CrnSrYWBFvc4ZcTG4=; b=r5EwM5I9gX9aNCrTZZpwXCMnyDdCNN39XSzG2ENvcklVcaQyXaXf7lRSVQHiOC1LmQ 3I9B4rrVKiUIj/7GcjJIZp26p62c+vX/nX//UaYVPfwDjpGHIhB8ZhLNghzXx/ZovKS/ TBvwPtCZLdCE1vutYzKIBLtqV+GN/M4IH2Us70Ii7p6yT/uwPZoNODqJhl8jNi/HSYAD /TcOQSE/vgrrPRPnOQP9wCV4mNZ+SO6RgCzCtZt149sVHk/T1KP+0S3AzncJBaZFsiIb KjVWV9j/33ALUV0dcRRSbygHfSrv/hr+/ob5xOovvkTmYulLmvqg9zRlGg1ufVzzPl7O UZlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NNqewFxAhp3TmNZYeBy2lNscR/CrnSrYWBFvc4ZcTG4=; b=i36EMrcIUydJLvSXABknFaw2mEEz91kG0as2L6Hn07qSSFpMl4KoBVpDKB4QtHQOBW IFB0WrctmGrPmoUizpmWImfQJEgDWa49HTZGTYnf0gnmIOZAy4cRQsWliaoW7LKgloub dE4z2AArwjU4g26e/aXf9uMAxENW3hYVyXMZZlhDxW9esspLNTXsmFyiMZSlEWl7om8N nZBCBHyHpsHK+RVD1C5r2BpISD6eHleSbxAn9NY63qAA7G6vq/3XOP2zv2qda15e+rB/ IOrGF6CUKh/qqZbrh2Popot+Ni+0DSTD7niKDL0nTVfsE7OHQMetcmkZ/FyZdHEqevk2 3+wg== X-Gm-Message-State: APjAAAXolXgQVUupYpdbscf0IkgcvNNUb8ts+wYYjw5W55jBMt9fybL+ UunMv3lpkM0mtQCa2sWS93tyTRwySN4= X-Google-Smtp-Source: APXvYqxPGPlXMQFy58wgjTBpjK2+zyOs4RziZCUJUqHiigmQNUFYJMp3iSTdhB+90ZOmISK234AeIg== X-Received: by 2002:a63:5f09:: with SMTP id t9mr22017442pgb.351.1566250732046; Mon, 19 Aug 2019 14:38:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:32 -0700 Message-Id: <20190819213755.26175-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 45/68] target/arm: Convert T16 data-processing (two low regs) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 152 ++--------------------------------------- target/arm/t16.decode | 36 ++++++++++ 2 files changed, 43 insertions(+), 145 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 90d608a2d2..7c5769bd42 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -445,13 +445,6 @@ static inline void gen_logic_CC(TCGv_i32 var) tcg_gen_mov_i32(cpu_ZF, var); } =20 -/* T0 +=3D T1 + CF. */ -static void gen_adc(TCGv_i32 t0, TCGv_i32 t1) -{ - tcg_gen_add_i32(t0, t0, t1); - tcg_gen_add_i32(t0, t0, cpu_CF); -} - /* dest =3D T0 + T1 + CF. */ static void gen_add_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) { @@ -7531,6 +7524,11 @@ static int t32_branch24(DisasContext *s, int x) return x << 1; } =20 +static int t16_setflags(DisasContext *s) +{ + return s->condexec_mask =3D=3D 0; +} + /* * Include the generated decoders. */ @@ -10742,145 +10740,9 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) =20 /* * 0b0100_00xx_xxxx_xxxx - * - Data-processing (two low registers) + * - Data-processing (two low registers), in decodetree */ - rd =3D insn & 7; - rm =3D (insn >> 3) & 7; - op =3D (insn >> 6) & 0xf; - if (op =3D=3D 2 || op =3D=3D 3 || op =3D=3D 4 || op =3D=3D 7) { - /* the shift/rotate ops want the operands backwards */ - val =3D rm; - rm =3D rd; - rd =3D val; - val =3D 1; - } else { - val =3D 0; - } - - if (op =3D=3D 9) { /* neg */ - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else if (op !=3D 0xf) { /* mvn doesn't read its first operand */ - tmp =3D load_reg(s, rd); - } else { - tmp =3D NULL; - } - - tmp2 =3D load_reg(s, rm); - switch (op) { - case 0x0: /* and */ - tcg_gen_and_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0x1: /* eor */ - tcg_gen_xor_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0x2: /* lsl */ - if (s->condexec_mask) { - gen_shl(tmp2, tmp2, tmp); - } else { - gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x3: /* lsr */ - if (s->condexec_mask) { - gen_shr(tmp2, tmp2, tmp); - } else { - gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x4: /* asr */ - if (s->condexec_mask) { - gen_sar(tmp2, tmp2, tmp); - } else { - gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x5: /* adc */ - if (s->condexec_mask) { - gen_adc(tmp, tmp2); - } else { - gen_adc_CC(tmp, tmp, tmp2); - } - break; - case 0x6: /* sbc */ - if (s->condexec_mask) { - gen_sub_carry(tmp, tmp, tmp2); - } else { - gen_sbc_CC(tmp, tmp, tmp2); - } - break; - case 0x7: /* ror */ - if (s->condexec_mask) { - tcg_gen_andi_i32(tmp, tmp, 0x1f); - tcg_gen_rotr_i32(tmp2, tmp2, tmp); - } else { - gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x8: /* tst */ - tcg_gen_and_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - rd =3D 16; - break; - case 0x9: /* neg */ - if (s->condexec_mask) - tcg_gen_neg_i32(tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - break; - case 0xa: /* cmp */ - gen_sub_CC(tmp, tmp, tmp2); - rd =3D 16; - break; - case 0xb: /* cmn */ - gen_add_CC(tmp, tmp, tmp2); - rd =3D 16; - break; - case 0xc: /* orr */ - tcg_gen_or_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xd: /* mul */ - tcg_gen_mul_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xe: /* bic */ - tcg_gen_andc_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xf: /* mvn */ - tcg_gen_not_i32(tmp2, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp2); - val =3D 1; - rm =3D rd; - break; - } - if (rd !=3D 16) { - if (val) { - store_reg(s, rm, tmp2); - if (op !=3D 0xf) - tcg_temp_free_i32(tmp); - } else { - store_reg(s, rd, tmp); - tcg_temp_free_i32(tmp2); - } - } else { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - } - break; + goto illegal_op; =20 case 5: /* load/store register offset. */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index e954f61fe4..44e7250c55 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -18,3 +18,39 @@ # # This file is processed by scripts/decodetree.py # + +&s_rrr_shi !extern s rd rn rm shim shty +&s_rrr_shr !extern s rn rd rm rs shty +&s_rri_rot !extern s rn rd imm rot +&s_rrrr !extern s rd rn rm ra + +# Set S if the instruction is outside of an IT block. +%s !function=3Dt16_setflags + +# Data-processing (two low registers) + +%reg_0 0:3 + +@lll_noshr ...... .... rm:3 rd:3 \ + &s_rrr_shi %s rn=3D%reg_0 shim=3D0 shty=3D0 +@xll_noshr ...... .... rm:3 rn:3 \ + &s_rrr_shi s=3D1 rd=3D0 shim=3D0 shty=3D0 +@lxl_shr ...... .... rs:3 rd:3 \ + &s_rrr_shr %s rm=3D%reg_0 rn=3D0 + +AND_rrri 010000 0000 ... ... @lll_noshr +EOR_rrri 010000 0001 ... ... @lll_noshr +MOV_rxrr 010000 0010 ... ... @lxl_shr shty=3D0 # LSL +MOV_rxrr 010000 0011 ... ... @lxl_shr shty=3D1 # LSR +MOV_rxrr 010000 0100 ... ... @lxl_shr shty=3D2 # ASR +ADC_rrri 010000 0101 ... ... @lll_noshr +SBC_rrri 010000 0110 ... ... @lll_noshr +MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3D3 # ROR +TST_xrri 010000 1000 ... ... @xll_noshr +RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=3D0 rot= =3D0 +CMP_xrri 010000 1010 ... ... @xll_noshr +CMN_xrri 010000 1011 ... ... @xll_noshr +ORR_rrri 010000 1100 ... ... @lll_noshr +MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=3D%reg_0 ra= =3D0 +BIC_rrri 010000 1110 ... ... @lll_noshr +MVN_rxri 010000 1111 ... ... @lll_noshr --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UChj47Tk8bdejdFnV6vdPORz5eDZg2iYcmHyUtBCb38=; b=RsDh0VI+3TDvB/NdPYoknfGk7dHH7mMgWZnrlQx6TlORcBl3SNwSFk9BBsiMp3M2GY Om2LJwKbLJt6cGvBZqChMgSAkn4kgKJHXGCerSPLw+Ml9quHO85AQtNyN0+s8TMaO0q/ OHYq6FCGbgU/VsejmXBUQn9gzzTEdQp8A1rlbVNV1W9k1VwKI8X7CImNe3L4KKgh8Gnb 2W4hRZMli+w2g/u0Fh9hn9JqFdaQ+/J2LZeYVDish/5S8POpFBotfRnp60YxnTfjSuSH SBH1Jr615WL2ZnfToOhjoiGoDURu71TsHPT/M4NPcV78fXXxb7n8JJOnDaUCjtKuAdhJ 80dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UChj47Tk8bdejdFnV6vdPORz5eDZg2iYcmHyUtBCb38=; b=mqaWX0Y+jhDODGMFnJGj3mMekzWThSEQQtostw4+QPNBUgSCjzVXXZfIFc0V0mYllF TSDmY+V/tn79IElMV2A4t5IPXyYnKNsD4HFCLJ4DWthiFHTG2MpREOXYFLxJLaqTCDgp cAwiVvbAY03uM26eGNhyFhH63OoXC2wQIFvMt1OAfiOVoKSVMvWDQpZ19afhrcx+gIEj 3riLa5CEkhlSAwkOVg8LQcwhtdRV5kF/2mViy4QrNn6X8fmynEqlvebwEQz6XfNghMNI BSzFk0AXv37QTuMvDbDRJwszYIUKFz5S1G0AfwWCdJ3thxYVf2Azt5qNQ88JCWzkHkVC CVtA== X-Gm-Message-State: APjAAAWMh4XAHqMBUOq46HruWw74iTld/8H86QV+oylS6DCWj1QVpSNb 7Y1oTCqVJNefJGYwU+Rdd4hWcS6rbNo= X-Google-Smtp-Source: APXvYqwAAxbLt4Hjv4vRMSvL07mQ4M1xXXF7xYkc3bpCImti4Lg1S3AMdAOPngh+hgFNWpAtvgShuA== X-Received: by 2002:a62:5250:: with SMTP id g77mr26780026pfb.158.1566250733306; Mon, 19 Aug 2019 14:38:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:33 -0700 Message-Id: <20190819213755.26175-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 46/68] target/arm: Convert T16 load/store (register offset) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 51 ++---------------------------------------- target/arm/t16.decode | 15 +++++++++++++ 2 files changed, 17 insertions(+), 49 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 7c5769bd42..e19961fb6c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10745,55 +10745,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) goto illegal_op; =20 case 5: - /* load/store register offset. */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - rm =3D (insn >> 6) & 7; - op =3D (insn >> 9) & 7; - addr =3D load_reg(s, rn); - tmp =3D load_reg(s, rm); - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - - if (op < 3) { /* store */ - tmp =3D load_reg(s, rd); - } else { - tmp =3D tcg_temp_new_i32(); - } - - switch (op) { - case 0: /* str */ - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - break; - case 1: /* strh */ - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - break; - case 2: /* strb */ - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16B= it); - break; - case 3: /* ldrsb */ - gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - break; - case 4: /* ldr */ - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - break; - case 5: /* ldrh */ - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - break; - case 6: /* ldrb */ - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - break; - case 7: /* ldrsh */ - gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - break; - } - if (op >=3D 3) { /* load */ - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; + /* load/store register offset, in decodetree */ + goto illegal_op; =20 case 6: /* load/store word immediate offset */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 44e7250c55..83fe4363c7 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&ldst_rr !extern p w u rn rt rm shimm shtype =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -54,3 +55,17 @@ ORR_rrri 010000 1100 ... ... @lll_nos= hr MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=3D%reg_0 ra= =3D0 BIC_rrri 010000 1110 ... ... @lll_noshr MVN_rxri 010000 1111 ... ... @lll_noshr + +# Load/store (register offset) + +@ldst_rr ....... rm:3 rn:3 rt:3 \ + &ldst_rr p=3D1 w=3D0 u=3D1 shimm=3D0 shtype=3D0 + +STR_rr 0101 000 ... ... ... @ldst_rr +STRH_rr 0101 001 ... ... ... @ldst_rr +STRB_rr 0101 010 ... ... ... @ldst_rr +LDRSB_rr 0101 011 ... ... ... @ldst_rr +LDR_rr 0101 100 ... ... ... @ldst_rr +LDRH_rr 0101 101 ... ... ... @ldst_rr +LDRB_rr 0101 110 ... ... ... @ldst_rr +LDRSH_rr 0101 111 ... ... ... @ldst_rr --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VFBU7xB1tZeQF9Ur7x5GUr3vG1VIlCf7jhvfNaK9tC0=; b=l6E8rkRCcCq9NjGdgmdCaOfUp1hUCk8OnzveXy+ovospNVBusw/ZuE+U6GsDHVqN6/ OLvheKhhduzX8D9Vc7rE05wC5yDgFDmtW/prE85Kt+Ol8YWCuMlweacUfbk93gmdARES k/fiVLxdDn6zqswtTVtrEzfo7A/TgiOyD9Qj4zGdGLSIbnrBnGImCbkpShNEehNpmyYO x6+fU07BTW2Azevcoo6ufxAhxEdEdNcMrCbFY/0PxGHW+jaNPq6hZJuRmLcT5HWWhN/Z b4KNKJDjg4CuawJjv6ANQLaWuIWhQ5FGa2997h8R4iBwgwI3k2mLx1e/l6ni+iOh8v63 PyrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VFBU7xB1tZeQF9Ur7x5GUr3vG1VIlCf7jhvfNaK9tC0=; b=dQW30+9m8UrHLvH6Dk8zABntFHGqcjXs2TixqNK/CecQdvKX3qRkOSSXHg1ngx+0xf uF3KPEGD0CHDKammU7ZBwOKOcmts5qK1mJ7k4xgfb3Cr/R7KNgsmpzdyQIMWuyBoVdxC FRGLu3jouBRzwhlZkwcK/sf7610CD93YC9IE3WIWniSN4YSddjzxdPVa6yKJkYBQd8IO pkhCGFWHpTU0Pd2hRJt15jKgI3KoMv+C2toFKEV176ieQEhwWqS01VM0yYX26tcqTK/i f0jiqdd7vs97CJ146Ycnuks3lcudR5MVbbOkpYl4yTbbSYOOxOXgpuFSdrm1AyNLPyd7 5Hnw== X-Gm-Message-State: APjAAAVHalKhwSfb6vW8PoBXuL8c6UrpH4pV2tXRWS5hdIqWM3IqmFM8 HhYBBylammoe2FUcJ0V1uLK0aQwGbcg= X-Google-Smtp-Source: APXvYqzBFkjYhsJ3+06HVnFoKbDVQh/Y+XC98FdQcjajdgM+7Hyf1QRez2vD2lI31hWt4rs8vEWmpQ== X-Received: by 2002:a62:584:: with SMTP id 126mr26624406pff.73.1566250734445; Mon, 19 Aug 2019 14:38:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:34 -0700 Message-Id: <20190819213755.26175-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v2 47/68] target/arm: Convert T16 load/store (immediate offset) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 94 +++--------------------------------------- target/arm/t16.decode | 33 +++++++++++++++ 2 files changed, 38 insertions(+), 89 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index e19961fb6c..24537fc107 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10744,97 +10744,13 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) */ goto illegal_op; =20 - case 5: - /* load/store register offset, in decodetree */ + case 5: /* load/store register offset, in decodetree */ + case 6: /* load/store word immediate offset, in decodetree */ + case 7: /* load/store byte immediate offset, in decodetree */ + case 8: /* load/store halfword immediate offset, in decodetree */ + case 9: /* load/store from stack, in decodetree */ goto illegal_op; =20 - case 6: - /* load/store word immediate offset */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - addr =3D load_reg(s, rn); - val =3D (insn >> 4) & 0x7c; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 7: - /* load/store byte immediate offset */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - addr =3D load_reg(s, rn); - val =3D (insn >> 6) & 0x1f; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16B= it); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 8: - /* load/store halfword immediate offset */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - addr =3D load_reg(s, rn); - val =3D (insn >> 5) & 0x3e; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 9: - /* load/store from stack */ - rd =3D (insn >> 8) & 7; - addr =3D load_reg(s, 13); - val =3D (insn & 0xff) * 4; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - case 10: /* * 0b1010_xxxx_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 83fe4363c7..1cf79789ac 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ldst_rr !extern p w u rn rt rm shimm shtype +&ldst_ri !extern p w u rn rt imm =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -69,3 +70,35 @@ LDR_rr 0101 100 ... ... ... @ldst_rr LDRH_rr 0101 101 ... ... ... @ldst_rr LDRB_rr 0101 110 ... ... ... @ldst_rr LDRSH_rr 0101 111 ... ... ... @ldst_rr + +# Load/store word/byte (immediate offset) + +%imm5_6x4 6:5 !function=3Dtimes_4 + +@ldst_ri_1 ..... imm:5 rn:3 rt:3 \ + &ldst_ri p=3D1 w=3D0 u=3D1 +@ldst_ri_4 ..... ..... rn:3 rt:3 \ + &ldst_ri p=3D1 w=3D0 u=3D1 imm=3D%imm5_6x4 + +STR_ri 01100 ..... ... ... @ldst_ri_4 +LDR_ri 01101 ..... ... ... @ldst_ri_4 +STRB_ri 01110 ..... ... ... @ldst_ri_1 +LDRB_ri 01111 ..... ... ... @ldst_ri_1 + +# Load/store halfword (immediate offset) + +%imm5_6x2 6:5 !function=3Dtimes_2 +@ldst_ri_2 ..... ..... rn:3 rt:3 \ + &ldst_ri p=3D1 w=3D0 u=3D1 imm=3D%imm5_6x2 + +STRH_ri 10000 ..... ... ... @ldst_ri_2 +LDRH_ri 10001 ..... ... ... @ldst_ri_2 + +# Load/store (SP-relative) + +%imm8_0x4 0:8 !function=3Dtimes_4 +@ldst_spec_i ..... rt:3 ........ \ + &ldst_ri p=3D1 w=3D0 u=3D1 imm=3D%imm8_0x4 + +STR_ri 10010 ... ........ @ldst_spec_i rn=3D13 +LDR_ri 10011 ... ........ @ldst_spec_i rn=3D13 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fWWvdDru9knlRm6IuiK5xbgxCPFGSOj1TibiqgY2wt8=; b=grW2OU+wjg/5blRzRrGgbm6QX4+AxMXafojAUOXf/h/bJW41xxALJFqKvkV9qG5ix8 +IVCedUWBAVE+xyVpar6Xcw/VcYj3Jf+sSFlvgr654a/rGMqjAM4eY17yJat4Jw8lUve QNQZLPHKWSgT4asBLpPLIwiezLISqCO5o2n2mHQKmU83ivFwZcVw7UAkTgXA2YBHHklg NNURNx8hYC9IlelKGc/iknMcOjBPiOBqHhf3jrKlHgeXDe1ByyNmElFnhJGCNsubmCe0 fKaIVulbcK0mvnet4b4+gzg5Jcg1/kEP5fwZTV3k1ckIGv8jGTgn9N25QcGOhctWD8na lu6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fWWvdDru9knlRm6IuiK5xbgxCPFGSOj1TibiqgY2wt8=; b=UqMW/8anZtrrvwHNiX2Cpxx/Bm+s6tV4sDiQVMa5/neZYWPowaZMcw35D0zRLlutf1 1emUGbPzBzPNL0ibVamgBxiJIW10YMjvClOJSHeWxaIKoLTJYS1kAEvGLbBeUTNdq5qw lkc/FsWoTcjOckrlzuJUtddS9gZxjjqJHs02s91mLTvoC4/psU3PPrVBtANHA1lp0wEX FA7R4CIyYJOKZPIA7TRtSu7t9iXgqdA6o5e3w3M7sYGmFIvBAuJLt2kN/Ka14gxK9O8a MKgtfgeDoKPMMX7MASiNp6Haani37K/LPjjHOyms5qbcOkWxN4SWLkJR5OAF7x8561Ma t2vg== X-Gm-Message-State: APjAAAUJT0kwobb+pCKvIpcSmKSfgGrmaZZyAI8e8wUoQ8VCS9MeeY6D NVGF8MVFGINzntKRTHSy7Y9qMCSnijc= X-Google-Smtp-Source: APXvYqw3kP0fBOMR2QxGwg4rTdOZzZjotyZ60YLKajzAjZQ3nrk7zY8fOTmDpHBTtxyZ55s9jgrbbg== X-Received: by 2002:aa7:8c57:: with SMTP id e23mr15883178pfd.48.1566250735751; Mon, 19 Aug 2019 14:38:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:35 -0700 Message-Id: <20190819213755.26175-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42f Subject: [Qemu-devel] [PATCH v2 48/68] target/arm: Convert T16 add pc/sp (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 12 +----------- target/arm/t16.decode | 7 +++++++ 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 24537fc107..2640f50fcf 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10749,19 +10749,9 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) case 7: /* load/store byte immediate offset, in decodetree */ case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ + case 10: /* add PC/SP (immediate), in decodetree */ goto illegal_op; =20 - case 10: - /* - * 0b1010_xxxx_xxxx_xxxx - * - Add PC/SP (immediate) - */ - rd =3D (insn >> 8) & 7; - val =3D (insn & 0xff) * 4; - tmp =3D add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val); - store_reg(s, rd, tmp); - break; - case 11: /* misc */ op =3D (insn >> 8) & 0xf; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 1cf79789ac..71b3e8f02e 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&ri !extern rd imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm =20 @@ -102,3 +103,9 @@ LDRH_ri 10001 ..... ... ... @ldst_r= i_2 =20 STR_ri 10010 ... ........ @ldst_spec_i rn=3D13 LDR_ri 10011 ... ........ @ldst_spec_i rn=3D13 + +# Add PC/SP (immediate) + +ADR 10100 rd:3 ........ imm=3D%imm8_0x4 +ADD_rri 10101 rd:3 ........ \ + &s_rri_rot rn=3D13 s=3D0 rot=3D0 imm=3D%imm8_0x4 # SP --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566252628; cv=none; d=zoho.com; s=zohoarc; b=boWydYvKj7bvdm7P53ykL39fNT3WdN1JlAtIXTIaaOhq0BMx2Jf2IMmjovmPc6t12gKpyBsxrrvNLQO4CVjllW3uWP1U2ySbj3nt35/h46ifymkN0ok0WW1vO7ZzWo2Hq2sP1bPqJi3LSVjHwu3Y/0kBtWVucm7GjNvcwfiBnXA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566252628; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ciKrEcP+T8tnigUgJH1zluGMRq2FWUolUVP3r6kA9kc=; b=JXKVYwLbyi24MlNLnO7heXLEWkRee0DSRmFXjCTxSTzawvK5id1CLOVV8I2K4gnum42BqvAQTWYwgk1HsVkEf95GSBRVV9o7d3uqO4rRtVqLWxRbt8h74yIG26SfwpEp8TVMUysOk2EeLVg/S4FMjDe0PobV/SxmqCLyj19Nl84= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566252628010375.6238828197072; Mon, 19 Aug 2019 15:10:28 -0700 (PDT) Received: from localhost ([::1]:59590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpr3-0002GV-Mb for importer@patchew.org; Mon, 19 Aug 2019 18:10:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59724) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMj-0002WC-5x for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMh-0006hW-JV for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:01 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:37306) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMh-0006g1-C5 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:59 -0400 Received: by mail-pf1-x441.google.com with SMTP id 129so1947366pfa.4 for ; Mon, 19 Aug 2019 14:38:57 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v2 49/68] target/arm: Convert T16 load/store multiple X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 48 ++++++++---------------------------------- target/arm/t16.decode | 8 +++++++ 2 files changed, 17 insertions(+), 39 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 2640f50fcf..d417958b23 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9976,6 +9976,14 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_= block *a) return do_ldm(s, a, 2); } =20 +static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback is conditional on the base register not being loaded. */ + a->w =3D !(a->list & (1 << a->rn)); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return do_ldm(s, a, 1); +} + /* * Branch, branch with link */ @@ -10750,6 +10758,7 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ case 10: /* add PC/SP (immediate), in decodetree */ + case 12: /* load/store multiple, in decodetree */ goto illegal_op; =20 case 11: @@ -10973,45 +10982,6 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) } break; =20 - case 12: - { - /* load/store multiple */ - TCGv_i32 loaded_var =3D NULL; - rn =3D (insn >> 8) & 0x7; - addr =3D load_reg(s, rn); - for (i =3D 0; i < 8; i++) { - if (insn & (1 << i)) { - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i =3D=3D rn) { - loaded_var =3D tmp; - } else { - store_reg(s, i, tmp); - } - } else { - /* store */ - tmp =3D load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - /* advance to the next address */ - tcg_gen_addi_i32(addr, addr, 4); - } - } - if ((insn & (1 << rn)) =3D=3D 0) { - /* base reg not in list: base register writeback */ - store_reg(s, rn, addr); - } else { - /* base reg in list: if load, complete it now */ - if (insn & (1 << 11)) { - store_reg(s, rn, loaded_var); - } - tcg_temp_free_i32(addr); - } - break; - } case 13: /* conditional branch or swi */ cond =3D (insn >> 8) & 0xf; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 71b3e8f02e..a7a437f930 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -26,6 +26,7 @@ &ri !extern rd imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&ldst_block !extern rn i b u w list =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -109,3 +110,10 @@ LDR_ri 10011 ... ........ @ldst_= spec_i rn=3D13 ADR 10100 rd:3 ........ imm=3D%imm8_0x4 ADD_rri 10101 rd:3 ........ \ &s_rri_rot rn=3D13 s=3D0 rot=3D0 imm=3D%imm8_0x4 # SP + +# Load/store multiple + +@ldstm ..... rn:3 list:8 &ldst_block i=3D1 b=3D0 u= =3D0 w=3D1 + +STM 11000 ... ........ @ldstm +LDM_t16 11001 ... ........ @ldstm --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 50/68] target/arm: Convert T16 add/sub (3 low, 2 low and imm) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 26 ++------------------------ target/arm/t16.decode | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 24 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d417958b23..6f30415371 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10572,31 +10572,9 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) * 0b0001_1xxx_xxxx_xxxx * - Add, subtract (three low registers) * - Add, subtract (two low registers and immediate) + * In decodetree. */ - rn =3D (insn >> 3) & 7; - tmp =3D load_reg(s, rn); - if (insn & (1 << 10)) { - /* immediate */ - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, (insn >> 6) & 7); - } else { - /* reg */ - rm =3D (insn >> 6) & 7; - tmp2 =3D load_reg(s, rm); - } - if (insn & (1 << 9)) { - if (s->condexec_mask) - tcg_gen_sub_i32(tmp, tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - } else { - if (s->condexec_mask) - tcg_gen_add_i32(tmp, tmp, tmp2); - else - gen_add_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); + goto illegal_op; } else { /* shift immediate */ rm =3D (insn >> 3) & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index a7a437f930..2b5f368d31 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -117,3 +117,19 @@ ADD_rri 10101 rd:3 ........ \ =20 STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm + +# Add/subtract (three low registers) + +@addsub_3 ....... rm:3 rn:3 rd:3 \ + &s_rrr_shi %s shim=3D0 shty=3D0 + +ADD_rrri 0001100 ... ... ... @addsub_3 +SUB_rrri 0001101 ... ... ... @addsub_3 + +# Add/subtract (two low registers and immediate) + +@addsub_2i ....... imm:3 rn:3 rd:3 \ + &s_rri_rot %s rot=3D0 + +ADD_rri 0001 110 ... ... ... @addsub_2i +SUB_rri 0001 111 ... ... ... @addsub_2i --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 51/68] target/arm: Convert T16 one low register and immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 44 ++---------------------------------------- target/arm/t16.decode | 11 +++++++++++ 2 files changed, 13 insertions(+), 42 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 6f30415371..3a3b113822 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10586,48 +10586,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) store_reg(s, rd, tmp); } break; - case 2: case 3: - /* - * 0b001x_xxxx_xxxx_xxxx - * - Add, subtract, compare, move (one low register and immediate) - */ - op =3D (insn >> 11) & 3; - rd =3D (insn >> 8) & 0x7; - if (op =3D=3D 0) { /* mov */ - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, insn & 0xff); - if (!s->condexec_mask) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - } else { - tmp =3D load_reg(s, rd); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, insn & 0xff); - switch (op) { - case 1: /* cmp */ - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - break; - case 2: /* add */ - if (s->condexec_mask) - tcg_gen_add_i32(tmp, tmp, tmp2); - else - gen_add_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; - case 3: /* sub */ - if (s->condexec_mask) - tcg_gen_sub_i32(tmp, tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; - } - } - break; + case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ + goto illegal_op; case 4: if (insn & (1 << 11)) { rd =3D (insn >> 8) & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 2b5f368d31..0654275e68 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -133,3 +133,14 @@ SUB_rrri 0001101 ... ... ... @addsu= b_3 =20 ADD_rri 0001 110 ... ... ... @addsub_2i SUB_rri 0001 111 ... ... ... @addsub_2i + +# Add, subtract, compare, move (one low register and immediate) + +%reg_8 8:3 +@arith_1i ..... rd:3 imm:8 \ + &s_rri_rot rot=3D0 rn=3D%reg_8 + +MOV_rxi 00100 ... ........ @arith_1i %s +CMP_xri 00101 ... ........ @arith_1i s=3D1 +ADD_rri 00110 ... ........ @arith_1i %s +SUB_rri 00111 ... ........ @arith_1i %s --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v2 52/68] target/arm: Convert T16 branch and exchange X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 64 +++++++++++++++--------------------------- target/arm/t16.decode | 10 +++++++ 2 files changed, 33 insertions(+), 41 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 3a3b113822..60bfc943a3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8335,7 +8335,7 @@ static bool trans_BX(DisasContext *s, arg_BX *a) if (!ENABLE_ARCH_4T) { return false; } - gen_bx(s, load_reg(s, a->rm)); + gen_bx_excret(s, load_reg(s, a->rm)); return true; } =20 @@ -8362,6 +8362,26 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *= a) return true; } =20 +static bool trans_BXNS(DisasContext *s, arg_BXNS *a) +{ + if (!s->v8m_secure || IS_USER_ONLY) { + unallocated_encoding(s); + } else { + gen_bxns(s, a->rm); + } + return true; +} + +static bool trans_BLXNS(DisasContext *s, arg_BLXNS *a) +{ + if (!s->v8m_secure || IS_USER_ONLY) { + unallocated_encoding(s); + } else { + gen_blxns(s, a->rm); + } + return true; +} + static bool trans_CLZ(DisasContext *s, arg_CLZ *a) { TCGv_i32 tmp; @@ -10637,49 +10657,11 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) } break; case 3: - { /* 0b0100_0111_xxxx_xxxx * - branch [and link] exchange thumb register + * In decodetree */ - bool link =3D insn & (1 << 7); - - if (insn & 3) { - goto undef; - } - if (link) { - ARCH(5); - } - if ((insn & 4)) { - /* BXNS/BLXNS: only exists for v8M with the - * security extensions, and always UNDEF if NonSecure. - * We don't implement these in the user-only mode - * either (in theory you can use them from Secure User - * mode but they are too tied in to system emulation.) - */ - if (!s->v8m_secure || IS_USER_ONLY) { - goto undef; - } - if (link) { - gen_blxns(s, rm); - } else { - gen_bxns(s, rm); - } - break; - } - /* BLX/BX */ - tmp =3D load_reg(s, rm); - if (link) { - val =3D (uint32_t)s->base.pc_next | 1; - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, val); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - } else { - /* Only BX works as exception-return, not BLX */ - gen_bx_excret(s, tmp); - } - break; - } + goto illegal_op; } break; } diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 0654275e68..edddbfb9b8 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ri !extern rd imm +&r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list @@ -144,3 +145,12 @@ MOV_rxi 00100 ... ........ @arith= _1i %s CMP_xri 00101 ... ........ @arith_1i s=3D1 ADD_rri 00110 ... ........ @arith_1i %s SUB_rri 00111 ... ........ @arith_1i %s + +# Branch and exchange + +@branchr .... .... . rm:4 ... &r + +BX 0100 0111 0 .... 000 @branchr +BLX_r 0100 0111 1 .... 000 @branchr +BXNS 0100 0111 0 .... 100 @branchr +BLXNS 0100 0111 1 .... 100 @branchr --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 53/68] target/arm: Convert T16 add, compare, move (two high registers) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 49 ++---------------------------------------- target/arm/t16.decode | 10 +++++++++ 2 files changed, 12 insertions(+), 47 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 60bfc943a3..e639059a5a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10620,55 +10620,10 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) store_reg(s, rd, tmp); break; } - if (insn & (1 << 10)) { - /* 0b0100_01xx_xxxx_xxxx - * - data processing extended, branch and exchange - */ - rd =3D (insn & 7) | ((insn >> 4) & 8); - rm =3D (insn >> 3) & 0xf; - op =3D (insn >> 8) & 3; - switch (op) { - case 0: /* add */ - tmp =3D load_reg(s, rd); - tmp2 =3D load_reg(s, rm); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rd =3D=3D 13) { - /* ADD SP, SP, reg */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } - break; - case 1: /* cmp */ - tmp =3D load_reg(s, rd); - tmp2 =3D load_reg(s, rm); - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - break; - case 2: /* mov/cpy */ - tmp =3D load_reg(s, rm); - if (rd =3D=3D 13) { - /* MOV SP, reg */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } - break; - case 3: - /* 0b0100_0111_xxxx_xxxx - * - branch [and link] exchange thumb register - * In decodetree - */ - goto illegal_op; - } - break; - } =20 /* - * 0b0100_00xx_xxxx_xxxx - * - Data-processing (two low registers), in decodetree + * - Data-processing (two low registers), in decodetree + * - data processing extended, branch and exchange, in decodetree */ goto illegal_op; =20 diff --git a/target/arm/t16.decode b/target/arm/t16.decode index edddbfb9b8..5a570484e3 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -146,6 +146,16 @@ CMP_xri 00101 ... ........ @arith= _1i s=3D1 ADD_rri 00110 ... ........ @arith_1i %s SUB_rri 00111 ... ........ @arith_1i %s =20 +# Add, compare, move (two high registers) + +%reg_0_7 7:1 0:3 +@addsub_2h .... .... . rm:4 ... \ + &s_rrr_shi rd=3D%reg_0_7 rn=3D%reg_0_7 shim=3D0 shty=3D0 + +ADD_rrri 0100 0100 . .... ... @addsub_2h s=3D0 +CMP_xrri 0100 0101 . .... ... @addsub_2h s=3D1 +MOV_rxri 0100 0110 . .... ... @addsub_2h s=3D0 + # Branch and exchange =20 @branchr .... .... . rm:4 ... &r --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 54/68] target/arm: Convert T16 adjust sp (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 15 ++------------- target/arm/t16.decode | 9 +++++++++ 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index e639059a5a..cac3893386 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10640,19 +10640,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) /* misc */ op =3D (insn >> 8) & 0xf; switch (op) { - case 0: - /* - * 0b1011_0000_xxxx_xxxx - * - ADD (SP plus immediate) - * - SUB (SP minus immediate) - */ - tmp =3D load_reg(s, 13); - val =3D (insn & 0x7f) * 4; - if (insn & (1 << 7)) - val =3D -(int32_t)val; - tcg_gen_addi_i32(tmp, tmp, val); - store_sp_checked(s, tmp); - break; + case 0: /* add/sub (sp, immediate), in decodetree */ + goto illegal_op; =20 case 2: /* sign/zero extend. */ ARCH(6); diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 5a570484e3..b425b86795 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -156,6 +156,15 @@ ADD_rrri 0100 0100 . .... ... @addsu= b_2h s=3D0 CMP_xrri 0100 0101 . .... ... @addsub_2h s=3D1 MOV_rxri 0100 0110 . .... ... @addsub_2h s=3D0 =20 +# Adjust SP (immediate) + +%imm7_0x4 0:7 !function=3Dtimes_4 +@addsub_sp_i .... .... . ....... \ + &s_rri_rot s=3D0 rd=3D13 rn=3D13 rot=3D0 imm=3D%imm7_0x4 + +ADD_rri 1011 0000 0 ....... @addsub_sp_i +SUB_rri 1011 0000 1 ....... @addsub_sp_i + # Branch and exchange =20 @branchr .... .... . rm:4 ... &r --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566252863; cv=none; d=zoho.com; s=zohoarc; b=BjPA1H+v8Ew8zGYPQEaEZLG7aNxcVd0h4kLHKhvLB95Em1YsI/5Gd6nDSzbe/4BJ61/MoYhaVheShjVYv8X78HVz6PPHnf98/+WJmgWGg+AMG/BkXNtehZwjNBTVHQPmyo6qjsLMXGLR/pdhyhErXgHktYB8kLrtR2nv9vmKwjk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566252863; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=IoEU+NRa2JWhajyfKqrmJYRYOBCu04dzJDGI4c2fGqA=; b=iQWcRvChP6oOPQteOA6+rF2CNpygLXqVZBaI7jU+AmZ+WmTnSU8Pcn7lrUIkWH1uyj2Oz1S29Er0LwXu1vvuUOf2/r+beaxogTN8bRtwtOLC+MHMOTGPog68nbGMmqlIOzn8lX54IEwlK9U04PGcZd+BB1fJpnpHaLNsmXWtXU4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566252863973321.99099807847927; Mon, 19 Aug 2019 15:14:23 -0700 (PDT) Received: from localhost ([::1]:59684 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpuw-0007Rw-Io for importer@patchew.org; Mon, 19 Aug 2019 18:14:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59881) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMp-0002ie-FY for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMo-0006oa-5V for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:07 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:46335) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMn-0006nf-WA for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:06 -0400 Received: by mail-pf1-x444.google.com with SMTP id q139so1934188pfc.13 for ; Mon, 19 Aug 2019 14:39:05 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 55/68] target/arm: Convert T16, extract X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 14 +------------- target/arm/t16.decode | 10 ++++++++++ 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index cac3893386..414c562fb3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10641,21 +10641,9 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) op =3D (insn >> 8) & 0xf; switch (op) { case 0: /* add/sub (sp, immediate), in decodetree */ + case 2: /* sign/zero extend, in decodetree */ goto illegal_op; =20 - case 2: /* sign/zero extend. */ - ARCH(6); - rd =3D insn & 7; - rm =3D (insn >> 3) & 7; - tmp =3D load_reg(s, rm); - switch ((insn >> 6) & 3) { - case 0: gen_sxth(tmp); break; - case 1: gen_sxtb(tmp); break; - case 2: gen_uxth(tmp); break; - case 3: gen_uxtb(tmp); break; - } - store_reg(s, rd, tmp); - break; case 4: case 5: case 0xc: case 0xd: /* * 0b1011_x10x_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index b425b86795..b5b5086e8a 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&rrr_rot !extern rd rn rm rot &ri !extern rd imm &r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype @@ -173,3 +174,12 @@ BX 0100 0111 0 .... 000 @branc= hr BLX_r 0100 0111 1 .... 000 @branchr BXNS 0100 0111 0 .... 100 @branchr BLXNS 0100 0111 1 .... 100 @branchr + +# Extend + +@extend .... .... .. rm:3 rd:3 &rrr_rot rn=3D15 rot=3D0 + +SXTAH 1011 0010 00 ... ... @extend +SXTAB 1011 0010 01 ... ... @extend +UXTAH 1011 0010 10 ... ... @extend +UXTAB 1011 0010 11 ... ... @extend --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v2 56/68] target/arm: Convert T16, Change processor state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 85 ++++++++++++++++++++---------------------- target/arm/t16.decode | 12 ++++++ 2 files changed, 52 insertions(+), 45 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 414c562fb3..368f0ab147 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7474,6 +7474,11 @@ static int negate(DisasContext *s, int x) return -x; } =20 +static int plus_2(DisasContext *s, int x) +{ + return x + 2; +} + static int times_2(DisasContext *s, int x) { return x * 2; @@ -10152,6 +10157,9 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) { uint32_t mask, val; =20 + if (ENABLE_ARCH_6 && arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } if (IS_USER(s)) { /* Implemented as NOP in user mode. */ return true; @@ -10182,6 +10190,36 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) return true; } =20 +static bool trans_CPS_v6m(DisasContext *s, arg_CPS_v6m *a) +{ + TCGv_i32 tmp, addr; + + if (!(ENABLE_ARCH_6 && arm_dc_feature(s, ARM_FEATURE_M))) { + return false; + } + if (IS_USER(s)) { + /* Implemented as NOP in user mode. */ + return true; + } + + tmp =3D tcg_const_i32(a->im); + /* FAULTMASK */ + if (a->F) { + addr =3D tcg_const_i32(19); + gen_helper_v7m_msr(cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + } + /* PRIMASK */ + if (a->I) { + addr =3D tcg_const_i32(16); + gen_helper_v7m_msr(cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + } + tcg_temp_free_i32(tmp); + gen_lookup_tb(s); + return true; +} + /* * Clear-Exclusive, Barriers */ @@ -10783,51 +10821,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) break; } =20 - case 6: - switch ((insn >> 5) & 7) { - case 2: - /* setend */ - ARCH(6); - if (((insn >> 3) & 1) !=3D !!(s->be_data =3D=3D MO_BE)) { - gen_helper_setend(cpu_env); - s->base.is_jmp =3D DISAS_UPDATE; - } - break; - case 3: - /* cps */ - ARCH(6); - if (IS_USER(s)) { - break; - } - if (arm_dc_feature(s, ARM_FEATURE_M)) { - tmp =3D tcg_const_i32((insn & (1 << 4)) !=3D 0); - /* FAULTMASK */ - if (insn & 1) { - addr =3D tcg_const_i32(19); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - } - /* PRIMASK */ - if (insn & 2) { - addr =3D tcg_const_i32(16); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - } - tcg_temp_free_i32(tmp); - gen_lookup_tb(s); - } else { - if (insn & (1 << 4)) { - shift =3D CPSR_A | CPSR_I | CPSR_F; - } else { - shift =3D 0; - } - gen_set_psr_im(s, ((insn & 7) << 6), 0, shift); - } - break; - default: - goto undef; - } - break; + case 6: /* setend, cps; in decodetree */ + goto illegal_op; =20 default: goto undef; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index b5b5086e8a..3bf1a31731 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -29,6 +29,8 @@ &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list +&setend !extern E +&cps !extern mode imod M A I F =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -183,3 +185,13 @@ SXTAH 1011 0010 00 ... ... @extend SXTAB 1011 0010 01 ... ... @extend UXTAH 1011 0010 10 ... ... @extend UXTAB 1011 0010 11 ... ... @extend + +# Change processor state + +%imod 4:1 !function=3Dplus_2 + +SETEND 1011 0110 010 1 E:1 000 &setend +{ + CPS_v6m 1011 0110 011 im:1 00 I:1 F:1 + CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=3D0 M=3D0 %imod +} --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::52f Subject: [Qemu-devel] [PATCH v2 57/68] target/arm: Convert T16, Reverse bytes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 18 +++--------------- target/arm/t16.decode | 9 +++++++++ 2 files changed, 12 insertions(+), 15 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 368f0ab147..176cba2992 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10608,7 +10608,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rn, rd, shift, cond; + uint32_t val, op, rm, rd, shift, cond; int32_t offset; int i; TCGv_i32 tmp; @@ -10805,20 +10805,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) break; } =20 - /* Otherwise this is rev */ - ARCH(6); - rn =3D (insn >> 3) & 0x7; - rd =3D insn & 0x7; - tmp =3D load_reg(s, rn); - switch (op1) { - case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_rev16(tmp, tmp); break; - case 3: gen_revsh(tmp, tmp); break; - default: - g_assert_not_reached(); - } - store_reg(s, rd, tmp); - break; + /* Otherwise this is rev, in decodetree */ + goto illegal_op; } =20 case 6: /* setend, cps; in decodetree */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 3bf1a31731..ec21be7ef0 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrr_rot !extern rd rn rm rot +&rr !extern rd rm &ri !extern rd imm &r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype @@ -195,3 +196,11 @@ SETEND 1011 0110 010 1 E:1 000 &setend CPS_v6m 1011 0110 011 im:1 00 I:1 F:1 CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=3D0 M=3D0 %imod } + +# Reverse bytes + +@rdm .... .... .. rm:3 rd:3 &rr + +REV 1011 1010 00 ... ... @rdm +REV16 1011 1010 01 ... ... @rdm +REVSH 1011 1010 11 ... ... @rdm --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v2 58/68] target/arm: Convert T16, nop hints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 3 +-- target/arm/t16.decode | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 176cba2992..67f0202d29 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10769,8 +10769,7 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) =20 case 15: /* IT, nop-hint. */ if ((insn & 0xf) =3D=3D 0) { - gen_nop_hint(s, (insn >> 4) & 0xf); - break; + goto illegal_op; /* nop hint, in decodetree */ } /* * IT (If-Then) diff --git a/target/arm/t16.decode b/target/arm/t16.decode index ec21be7ef0..d5b046d105 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -19,6 +19,7 @@ # This file is processed by scripts/decodetree.py # =20 +&empty !extern &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot @@ -204,3 +205,19 @@ SETEND 1011 0110 010 1 E:1 000 &setend REV 1011 1010 00 ... ... @rdm REV16 1011 1010 01 ... ... @rdm REVSH 1011 1010 11 ... ... @rdm + +# Hints + +{ + YIELD 1011 1111 0001 0000 + WFE 1011 1111 0010 0000 + WFI 1011 1111 0011 0000 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1011 1111 0100 0000 + # SEVL 1011 1111 0101 0000 + + # The canonical nop has the second nibble as 0000, but the whole of the + # rest of the space is a reserved hint, behaves as nop. + NOP 1011 1111 ---- 0000 +} --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566253055; cv=none; d=zoho.com; s=zohoarc; b=dfRjLL31E7YHkNzONDTgtTmS0K6uihyRZXdXF+u/+faB5RsOnMusJzask6Gwk2jUdutKG7akQYP2HEGgmzIOXFh1Rt6U/KWNWJRPlHXIK8/P/4eLi7dxxNB/AitQz+jTkXm0P6g5nmx+2HPIE2931RplqCfLcg26VSxpWfgbU7k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566253055; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=MSRdVhU7JG8W/BPDMD9yM4+AFvL57yq4+jCtr5it5qs=; b=ickqfdtHHbHwk4yW0wKISZw8/c8pr0SWEQUU8bAGme/rC9jJ2I+vGJQP7HUIUq8EF3bw6QtF79hqn8ROBBctuzW1zQOhoDHs4cTtkXclB19/A1cVh0OECb0I5w8TaH5WYENwBEfJmvyzYWx8lbVKpWtIiuGVW4wYliI46ubA1zs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156625305580259.126228881554084; Mon, 19 Aug 2019 15:17:35 -0700 (PDT) Received: from localhost ([::1]:59750 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpy2-00034U-7I for importer@patchew.org; Mon, 19 Aug 2019 18:17:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60014) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMu-0002ru-Kz for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMt-0006tq-AC for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:12 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:36037) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMt-0006tS-4r for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:11 -0400 Received: by mail-pf1-x444.google.com with SMTP id w2so1951750pfi.3 for ; Mon, 19 Aug 2019 14:39:11 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MSRdVhU7JG8W/BPDMD9yM4+AFvL57yq4+jCtr5it5qs=; b=MfNrJqun3vCG68VZiO/VjFAj/jU5TdGWWHXIdVS8Wq/oDPKHyJLY6bsLOppK/2WW9x kp5/IbXli5q5HiorX6yS0OXGRtm6rPC49cJNXXnut18PlEmx3HAM4LZow9dr7nv/5f/T aFwFecjkaYaxQMH5fLopbSrqPQYr2jpoJDvXpS7YkRBqVUBIDOFyTBF/aUBF6lNNg/Ki kGuaqALxGeZB/1QMRtr7kUwfS89PPA9e2LITrTcLquaD+ft585s00N4AiO0HwBl1nGLn TWlcJiS00icTVhV5nMtd6/FWDMmo0z6WAodEVNJbW/ncuFsfC00J+fEaHr7WF7+ewVBO mAXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MSRdVhU7JG8W/BPDMD9yM4+AFvL57yq4+jCtr5it5qs=; b=W3kFa0R0flGQi9BMANJRxxlJrRfJHIju6bZWKvETVdpjOn7pljOjKh6aobVN1bWoTo AuX/x+jpxY74Sl2LO+WdH/4UYz0MYJyBpTxCOwfqMuyoJibaT5nXH7CKPJTYNyALpjJa RtIyTNsFBEAW5QuQjpDvPo4mHI/EmARwCvBSrtO0XFDQAOzSOd0RahSRvVDPyH8v8DFE z10g0rTjE3S59LFkv4Nu777owCgu/VUeil0lBi0mtNYsPu2fDE5i10Q6u7d1D5iFT2eV A/L+ZhF/SiswUe6nkwmB5VLH9WMQnNtUVuNEHzaZZ+Oo2mBa6iNcxBfHd/eifU0shlYE 1IiA== X-Gm-Message-State: APjAAAVg18RUesZ+ISD7W9QVl08RASS76UqKBVIq+6iLemTvkMBWg/w6 FbiLhgXsazC5ivKd2eALgpyS9hKUaR8= X-Google-Smtp-Source: APXvYqwnIyLJCqAR0QAYUg3jfsCbZ0h0uBs29QNy6dJeAh/ALB8lrUVmJEv882e7wH6srL3Ryd18Hw== X-Received: by 2002:a63:20a:: with SMTP id 10mr21611744pgc.226.1566250749834; Mon, 19 Aug 2019 14:39:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:46 -0700 Message-Id: <20190819213755.26175-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 59/68] target/arm: Split gen_nop_hint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that there all callers pass a constant value, split the switch statement into the individual trans_* functions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 67 +++++++++++++++--------------------------- 1 file changed, 24 insertions(+), 43 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 67f0202d29..9e0345adf7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3045,46 +3045,6 @@ static void gen_exception_return(DisasContext *s, TC= Gv_i32 pc) gen_rfe(s, pc, load_cpu_field(spsr)); } =20 -/* - * For WFI we will halt the vCPU until an IRQ. For WFE and YIELD we - * only call the helper when running single threaded TCG code to ensure - * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we - * just skip this instruction. Currently the SEV/SEVL instructions - * which are *one* of many ways to wake the CPU from WFE are not - * implemented so we can't sleep like WFI does. - */ -static void gen_nop_hint(DisasContext *s, int val) -{ - switch (val) { - /* When running in MTTCG we don't generate jumps to the yield and - * WFE helpers as it won't affect the scheduling of other vCPUs. - * If we wanted to more completely model WFE/SEV so we don't busy - * spin unnecessarily we would need to do something more involved. - */ - case 1: /* yield */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp =3D DISAS_YIELD; - } - break; - case 3: /* wfi */ - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp =3D DISAS_WFI; - break; - case 2: /* wfe */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp =3D DISAS_WFE; - } - break; - case 4: /* sev */ - case 5: /* sevl */ - /* TODO: Implement SEV, SEVL and WFE. May help SMP performance. = */ - default: /* nop */ - break; - } -} - #define CPU_V001 cpu_V0, cpu_V0, cpu_V1 =20 static inline void gen_neon_add(int size, TCGv_i32 t0, TCGv_i32 t1) @@ -8165,19 +8125,40 @@ DO_SMLAWX(SMLAWT, 1, 1) =20 static bool trans_YIELD(DisasContext *s, arg_YIELD *a) { - gen_nop_hint(s, 1); + /* + * When running single-threaded TCG code, use the helper to ensure that + * the next round-robin scheduled vCPU gets a crack. When running in + * MTTCG we don't generate jumps to the helper as it won't affect the + * scheduling of other vCPUs. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp =3D DISAS_YIELD; + } return true; } =20 static bool trans_WFE(DisasContext *s, arg_WFE *a) { - gen_nop_hint(s, 2); + /* + * When running single-threaded TCG code, use the helper to ensure that + * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we + * just skip this instruction. Currently the SEV/SEVL instructions, + * which are *one* of many ways to wake the CPU from WFE, are not + * implemented so we can't sleep like WFI does. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp =3D DISAS_WFE; + } return true; } =20 static bool trans_WFI(DisasContext *s, arg_WFI *a) { - gen_nop_hint(s, 3); + /* For WFI, halt the vCPU until an IRQ. */ + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp =3D DISAS_WFI; return true; } =20 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566253214; cv=none; d=zoho.com; s=zohoarc; b=mE5Fl7lVL5E9+aogOY0QFu1luK4mhAowC5futd2N3Dg0y/haYWEHN6JESjybhnMEZCDLDRLkEuoJUape1TlOaizIiHdzUKvjPv+7IVq+t02uXRjRV1JWyChAFwPM/80nl8TJVhzEKOGrzgZ/jwVInKudFjr7k/wXhYej60zY0LU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566253214; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Ltc+Iekt5p0qb7H2sxDb1ZsirxTTtPcO/0Q5mx5ZDAc=; b=Mdt/lGTFHUqPvz3J2v7KpnHUFUhwTLSECXrSj7UKcOR58A3lBDeXAj13a2+KjP8yEBRXtJ7dbamnb223vbgskyMpE1ZzZ7wgu360E87TRwMcEgCpX5W7wUkTbnySzNqlItetIPsWUML15Ab7wUwRHBrcniEYj0Lz2LO/GBslvhg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566253214099795.1029516912505; Mon, 19 Aug 2019 15:20:14 -0700 (PDT) Received: from localhost ([::1]:59816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzq0a-0007e4-KB for importer@patchew.org; Mon, 19 Aug 2019 18:20:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60040) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMw-0002uU-2f for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMu-0006ui-Og for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:13 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:45900) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMu-0006uI-JD for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:12 -0400 Received: by mail-pg1-x52a.google.com with SMTP id o13so1921690pgp.12 for ; Mon, 19 Aug 2019 14:39:12 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ltc+Iekt5p0qb7H2sxDb1ZsirxTTtPcO/0Q5mx5ZDAc=; b=AOqI2pBLdPKE0yz8n1aVZ3uJqwZsJXfmxB/GOdPSA/hBZ4ZHHvS3ufqQp5UkDrECfg V0wGtku8vdSUuJptbaxjBG8OKwdpMBgOPRfShbsDFWKxScdP13IGHiwmts4mS8w3+tZt gENOINsYfXjz/h6CSYnxye/xwOm5Ei5n1hPrjlWAqEsbjWaPyI61DSg9tN4ti48MfAxS FRMmQjfYNlWoqSYSwC1oxY/Zaht33blLwN+yrHPStfsZ8jjcktDBXQ/TVYFoWetq6ziF ELawQecE5FboJXxauR+kHY5tdZG7lCg7cUaZ/GEjS3qfk2+pjqab+jabXBRy+YxzMYNC KX4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ltc+Iekt5p0qb7H2sxDb1ZsirxTTtPcO/0Q5mx5ZDAc=; b=d321T/q23DqoAeP+EXb7/3ROyGNPhpFgKvumS5UtiiwlRSVYgu2ItxVzE29izHu0Wd vrWcxLhdF3z5D5w5BJWeyIsf5+Brg9rpZ3j2kbZud64GnSx7kctojqu5GK9ILjaPfpsh fTedjcai5PqomHv52b+OwnLClyWp0gritWSP42dNwh8RW6IMzfm03AO/2ehARdUYejlc sT6TGXq9Iu575wFqBqPlfqXkkFo+yuDZkHSZh7mU7TtUApZZuuj7s1SlwsvHu9B64PoD 4KdUCq8icGCbZ3S7Wy7wn3LSfDKephrEJWLvdeZFMW+VjOmLqSuDGuB1CSTXiQGxKd3o 501g== X-Gm-Message-State: APjAAAXgoh0b3Y/mAjfracKHB5tuOiOrA24IhR08jw/e5dVFcTuscjC1 q8Aap3NoCkGXicrTLL23cm1jVFDfrz8= X-Google-Smtp-Source: APXvYqw31Z+a4S8bGc1TztxMTlaMGD0qlTEXTEAeS1cKy9k4t6it5/26fMsSH3HrGDFAerzJyNVI9A== X-Received: by 2002:a17:90a:8a11:: with SMTP id w17mr11126377pjn.139.1566250751227; Mon, 19 Aug 2019 14:39:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:47 -0700 Message-Id: <20190819213755.26175-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PATCH v2 60/68] target/arm: Convert T16, push and pop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 83 ++++++------------------------------------ target/arm/t16.decode | 10 +++++ 2 files changed, 22 insertions(+), 71 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9e0345adf7..5f876290ba 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7494,6 +7494,16 @@ static int t16_setflags(DisasContext *s) return s->condexec_mask =3D=3D 0; } =20 +static int t16_push_list(DisasContext *s, int x) +{ + return (x & 0xff) | (x & 0x100) << (14 - 8); +} + +static int t16_pop_list(DisasContext *s, int x) +{ + return (x & 0xff) | (x & 0x100) << (15 - 8); +} + /* * Include the generated decoders. */ @@ -10591,7 +10601,6 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) { uint32_t val, op, rm, rd, shift, cond; int32_t offset; - int i; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10664,76 +10673,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) goto illegal_op; =20 case 4: case 5: case 0xc: case 0xd: - /* - * 0b1011_x10x_xxxx_xxxx - * - push/pop - */ - addr =3D load_reg(s, 13); - if (insn & (1 << 8)) - offset =3D 4; - else - offset =3D 0; - for (i =3D 0; i < 8; i++) { - if (insn & (1 << i)) - offset +=3D 4; - } - if ((insn & (1 << 11)) =3D=3D 0) { - tcg_gen_addi_i32(addr, addr, -offset); - } - - if (s->v8m_stackcheck) { - /* - * Here 'addr' is the lower of "old SP" and "new SP"; - * if this is a pop that starts below the limit and ends - * above it, it is UNKNOWN whether the limit check trigger= s; - * we choose to trigger. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - for (i =3D 0; i < 8; i++) { - if (insn & (1 << i)) { - if (insn & (1 << 11)) { - /* pop */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, i, tmp); - } else { - /* push */ - tmp =3D load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - /* advance to the next address. */ - tcg_gen_addi_i32(addr, addr, 4); - } - } - tmp =3D NULL; - if (insn & (1 << 8)) { - if (insn & (1 << 11)) { - /* pop pc */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - /* don't set the pc until the rest of the instruction - has completed */ - } else { - /* push lr */ - tmp =3D load_reg(s, 14); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_gen_addi_i32(addr, addr, 4); - } - if ((insn & (1 << 11)) =3D=3D 0) { - tcg_gen_addi_i32(addr, addr, -offset); - } - /* write back the new stack pointer */ - store_reg(s, 13, addr); - /* set the new PC value */ - if ((insn & 0x0900) =3D=3D 0x0900) { - store_reg_from_load(s, 15, tmp); - } - break; + /* push/pop, in decodetree */ + goto illegal_op; =20 case 1: case 3: case 9: case 11: /* czb */ rm =3D insn & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index d5b046d105..d731402036 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -221,3 +221,13 @@ REVSH 1011 1010 11 ... ... @rdm # rest of the space is a reserved hint, behaves as nop. NOP 1011 1111 ---- 0000 } + +# Push and Pop + +%push_list 0:9 !function=3Dt16_push_list +%pop_list 0:9 !function=3Dt16_pop_list + +STM 1011 010 ......... \ + &ldst_block i=3D0 b=3D1 u=3D0 w=3D1 rn=3D13 list=3D%push_l= ist +LDM_t16 1011 110 ......... \ + &ldst_block i=3D1 b=3D0 u=3D0 w=3D1 rn=3D13 list=3D%pop_li= st --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566253580; cv=none; d=zoho.com; s=zohoarc; b=f/BxaHi5z8T0GnUSnuqETtcmx1KXInicq4exR0XZifo73Q9ektQ8OeQL6xtS9guZV2/970TJdbhBt/jQ+wVcpvj10O104mSuSB1P0spfXRi9Tt+LbXO/uAZfd2kKP1vWIBYCKlC01ZQA0SmsDmReca1q5mgV0LIBm//f9K+SkOY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566253580; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=M247+waxxQ2hFTPZWsca/mTPO3c20Nu5WDueYuMimjE=; b=aZpKvaLcH90NIIB6OZYOg+bNBYI5oCN4Yfm6czS/QDbdxd67XZUdeEGV9HIlwNp33CcrqauSPuGBOEbUlyXQkP/kVsibZxVIOFZT6w5jb6ag7+dmvGa2Gct3LfcbwrjFOfuTxN02VV682hkMa3x8Pvz1Q9sQyCCKy1/b5MbjFic= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566253580004362.49482753961126; Mon, 19 Aug 2019 15:26:20 -0700 (PDT) Received: from localhost ([::1]:59986 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzq6U-0000h8-Qu for importer@patchew.org; Mon, 19 Aug 2019 18:26:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60068) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpMx-0002wu-6M for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpMw-0006vN-0h for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:14 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:44549) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpMv-0006uz-Rl for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:13 -0400 Received: by mail-pf1-x444.google.com with SMTP id c81so1937653pfc.11 for ; Mon, 19 Aug 2019 14:39:13 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 61/68] target/arm: Convert T16, Conditional branches, Supervisor call X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 26 +++----------------------- target/arm/t16.decode | 12 ++++++++++++ 2 files changed, 15 insertions(+), 23 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5f876290ba..941266df14 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10599,7 +10599,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rd, shift, cond; + uint32_t val, op, rm, rd, shift; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10738,28 +10738,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) } break; =20 - case 13: - /* conditional branch or swi */ - cond =3D (insn >> 8) & 0xf; - if (cond =3D=3D 0xe) - goto undef; - - if (cond =3D=3D 0xf) { - /* swi */ - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm =3D extract32(insn, 0, 8); - s->base.is_jmp =3D DISAS_SWI; - break; - } - /* generate a conditional jump to next instruction */ - arm_skip_unless(s, cond); - - /* jump to the offset */ - val =3D read_pc(s); - offset =3D ((int32_t)insn << 24) >> 24; - val +=3D offset << 1; - gen_jmp(s, val); - break; + case 13: /* conditional branch or swi, in decodetree */ + goto illegal_op; =20 case 14: if (insn & (1 << 11)) { diff --git a/target/arm/t16.decode b/target/arm/t16.decode index d731402036..98d60952a1 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -28,11 +28,13 @@ &rr !extern rd rm &ri !extern rd imm &r !extern rm +&i !extern imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list &setend !extern E &cps !extern mode imod M A I F +&ci !extern cond imm =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -231,3 +233,13 @@ STM 1011 010 ......... \ &ldst_block i=3D0 b=3D1 u=3D0 w=3D1 rn=3D13 list=3D%push_l= ist LDM_t16 1011 110 ......... \ &ldst_block i=3D1 b=3D0 u=3D0 w=3D1 rn=3D13 list=3D%pop_li= st + +# Conditional branches, Supervisor call + +%imm8_0x2 0:s8 !function=3Dtimes_2 + +{ + UDF 1101 1110 ---- ---- + SVC 1101 1111 imm:8 &i + B_cond_thumb 1101 cond:4 ........ &ci imm=3D%imm8_0x2 +} --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 62/68] target/arm: Convert T16, Miscellaneous 16-bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 109 ++++++++++++----------------------------- target/arm/t16.decode | 31 ++++++++---- 2 files changed, 54 insertions(+), 86 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 941266df14..dc670c9724 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10074,6 +10074,18 @@ static bool trans_TBH(DisasContext *s, arg_tbranch= *a) return op_tbranch(s, a, true); } =20 +static bool trans_CBZ(DisasContext *s, arg_CBZ *a) +{ + TCGv_i32 tmp =3D load_reg(s, a->rn); + + arm_gen_condlabel(s); + tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE, + tmp, 0, s->condlabel); + tcg_temp_free_i32(tmp); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + /* * Supervisor call */ @@ -10295,6 +10307,25 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a) return ENABLE_ARCH_7; } =20 +/* + * If-then + */ + +static bool trans_IT(DisasContext *s, arg_IT *a) +{ + /* + * No actual code generated for this insn, just setup state. + * + * Combinations of firstcond and mask which set up an 0b1111 + * condition are UNPREDICTABLE; we take the CONSTRAINED + * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, + * i.e. both meaning "execute always". + */ + s->condexec_cond =3D a->cond; + s->condexec_mask =3D a->imm; + return true; +} + /* * Legacy decoder. */ @@ -10661,83 +10692,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ case 10: /* add PC/SP (immediate), in decodetree */ + case 11: /* misc, in decodetree */ case 12: /* load/store multiple, in decodetree */ - goto illegal_op; - - case 11: - /* misc */ - op =3D (insn >> 8) & 0xf; - switch (op) { - case 0: /* add/sub (sp, immediate), in decodetree */ - case 2: /* sign/zero extend, in decodetree */ - goto illegal_op; - - case 4: case 5: case 0xc: case 0xd: - /* push/pop, in decodetree */ - goto illegal_op; - - case 1: case 3: case 9: case 11: /* czb */ - rm =3D insn & 7; - tmp =3D load_reg(s, rm); - arm_gen_condlabel(s); - if (insn & (1 << 11)) - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel); - else - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel); - tcg_temp_free_i32(tmp); - offset =3D ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3; - gen_jmp(s, read_pc(s) + offset); - break; - - case 15: /* IT, nop-hint. */ - if ((insn & 0xf) =3D=3D 0) { - goto illegal_op; /* nop hint, in decodetree */ - } - /* - * IT (If-Then) - * - * Combinations of firstcond and mask which set up an 0b1111 - * condition are UNPREDICTABLE; we take the CONSTRAINED - * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, - * i.e. both meaning "execute always". - */ - s->condexec_cond =3D (insn >> 4) & 0xe; - s->condexec_mask =3D insn & 0x1f; - /* No actual code generated for this insn, just setup state. = */ - break; - - case 0xe: /* bkpt */ - { - int imm8 =3D extract32(insn, 0, 8); - ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true)); - break; - } - - case 0xa: /* rev, and hlt */ - { - int op1 =3D extract32(insn, 6, 2); - - if (op1 =3D=3D 2) { - /* HLT */ - int imm6 =3D extract32(insn, 0, 6); - - gen_hlt(s, imm6); - break; - } - - /* Otherwise this is rev, in decodetree */ - goto illegal_op; - } - - case 6: /* setend, cps; in decodetree */ - goto illegal_op; - - default: - goto undef; - } - break; - case 13: /* conditional branch or swi, in decodetree */ goto illegal_op; =20 @@ -10793,7 +10749,6 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) } return; illegal_op: -undef: unallocated_encoding(s); } =20 diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 98d60952a1..4ecbabd364 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -210,20 +210,33 @@ REVSH 1011 1010 11 ... ... @rdm =20 # Hints =20 +%it_cond 5:3 !function=3Dtimes_2 + { - YIELD 1011 1111 0001 0000 - WFE 1011 1111 0010 0000 - WFI 1011 1111 0011 0000 + { + YIELD 1011 1111 0001 0000 + WFE 1011 1111 0010 0000 + WFI 1011 1111 0011 0000 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1011 1111 0100 0000 - # SEVL 1011 1111 0101 0000 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1011 1111 0100 0000 + # SEVL 1011 1111 0101 0000 =20 - # The canonical nop has the second nibble as 0000, but the whole of the - # rest of the space is a reserved hint, behaves as nop. - NOP 1011 1111 ---- 0000 + # The canonical nop has the second nibble as 0000, but the whole of the + # rest of the space is a reserved hint, behaves as nop. + NOP 1011 1111 ---- 0000 + } + IT 1011 1111 ... imm:5 &ci cond=3D%it_cond } =20 +# Miscellaneous 16-bit instructions + +%imm6_9_3 9:1 3:5 !function=3Dtimes_2 + +HLT 1011 1010 10 imm:6 &i +BKPT 1011 1110 imm:8 &i +CBZ 1011 nz:1 0.1 ..... rn:3 imm=3D%imm6_9_3 + # Push and Pop =20 %push_list 0:9 !function=3Dt16_push_list --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5Xh6zbX+N9ttY9MdN7vquKBp46pmYyv37TGDy5UrKa0=; b=GEauZHcmeYZyYb7r0mtCqhm7fEgMEQr7ln33eZAolSBWsVQIW2vrWi9MsyV6MO0nuy maE5eUhj8CdPEf5/8mYnq1Pd0hx0xe7PTnZgBlyxLaTRbCYIraHcv1ON8rArq/Fa5KQp VEgOys8hsO6GeLmjs2iY9e+MVqgVmSdXynB0PFf4g/YgqafiHuVPjyKI1zaD9e0akV7i 2nktUOkpludSh3/dB79fB6Mrd1k4liQVNvJf54E3zUmv+ut6v+C1Pkvh0ApTx2kQTPtv FY2VQQxLPA3RV7e1vmXcM7ZiUacUfwzOWZcobk6UaAXJVIlnRQqgQFD0Do5VklrFlHmY /gew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5Xh6zbX+N9ttY9MdN7vquKBp46pmYyv37TGDy5UrKa0=; b=pk4OKtzLt0shfwE1dawNSC5o2CaGBYwZZLh4PQT2tDuGjJcQ0yddwegLwQGqIFgM8w zbMevdW4JB3jdf0Ha0mHoUL/fu2/wfZ/OwgcKCACiGd5N6REiEcRb9H20joONqQtwwnF yHrl9QUsMWT2pSMxxb91YEAAvso8PEWHnoXmEg3UECF6TUiLf0oy64Y425+r5xH3OttA 6C4Nj5m/RQ6xW9sX7fBJrdVyN8Idy4H8GVjN9guTEWiXHpg9x18PpLhqzQEICBsd0mnz g8o8Hs29ay5y3C7uE0Xo97dcbj62n1AiQa9x5qF40lD1dZMkmItML2z6018FeJjlJesu P42w== X-Gm-Message-State: APjAAAV5aRZ/oP4VoadW3vbRyur9jzyENXmN/lMr/WA4z2meoNlviTMI VPDo/7uPRmI4FfHX/2BgFI1ChFiGcUk= X-Google-Smtp-Source: APXvYqyeSGA4P+L5UTMPgvjSHTSXK4apIn129eMpfidfuqS7MaZzAw9BbcHLUlnzF2mxMbihA5ayqQ== X-Received: by 2002:a63:1f03:: with SMTP id f3mr21525885pgf.249.1566250754989; Mon, 19 Aug 2019 14:39:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:50 -0700 Message-Id: <20190819213755.26175-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v2 63/68] target/arm: Convert T16, shift immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 26 ++------------------------ target/arm/t16.decode | 8 ++++++++ 2 files changed, 10 insertions(+), 24 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index dc670c9724..dc3c9049cd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10630,7 +10630,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rd, shift; + uint32_t val, rd; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10642,29 +10642,7 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) /* fall back to legacy decoder */ =20 switch (insn >> 12) { - case 0: case 1: - - rd =3D insn & 7; - op =3D (insn >> 11) & 3; - if (op =3D=3D 3) { - /* - * 0b0001_1xxx_xxxx_xxxx - * - Add, subtract (three low registers) - * - Add, subtract (two low registers and immediate) - * In decodetree. - */ - goto illegal_op; - } else { - /* shift immediate */ - rm =3D (insn >> 3) & 7; - shift =3D (insn >> 6) & 0x1f; - tmp =3D load_reg(s, rm); - gen_arm_shift_im(tmp, op, shift, s->condexec_mask =3D=3D 0); - if (!s->condexec_mask) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - } - break; + case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree = */ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ goto illegal_op; case 4: diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 4ecbabd364..1adad20804 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -126,6 +126,14 @@ ADD_rri 10101 rd:3 ........ \ STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm =20 +# Shift (immediate) + +@shift_i ..... shim:5 rm:3 rd:3 &s_rrr_shi %s rn=3D%reg_0 + +MOV_rxri 000 00 ..... ... ... @shift_i shty=3D0 # LSL +MOV_rxri 000 01 ..... ... ... @shift_i shty=3D1 # LSR +MOV_rxri 000 10 ..... ... ... @shift_i shty=3D2 # ASR + # Add/subtract (three low registers) =20 @addsub_3 ....... rm:3 rn:3 rd:3 \ --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GQyk/IPAzG6M9shM4zauPndvY+PKuQRptTNum9FjIF4=; b=U1Wa2JjkTtEr8I1MOovLSN8jz9r2NAb/+fR4a83qgEvzMQuaFsju0+ydUzL0JrnKM6 v+JknZURt457WLs4EfvWFAZKCBTTgtK0mGa8bP7Rp54ZKB7iQaqW3SHvJkSUZlxwF/r9 FmsrQGeiPUgb/MFOwXYN/Sr/Gwb3XhNmiJVPiccAApx6KIP2mYhzZtEX5Y2TMZCAllP9 f8IqslOlr/xJxRwzhQTe8GTxCjJiQseyMDE8fiDR7n8z5IIB4BudpxxgFHGkedYnpb4e Aki75HoVSeR9vmPZtpS0yb8kD4Yb4eoO6viR47pqnO+P/6fjeceudHgkWobJUlNDNT2H e9+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GQyk/IPAzG6M9shM4zauPndvY+PKuQRptTNum9FjIF4=; b=ONtY4pXv2h6RXOB1dlqCclxxwPU1vTNhNUGjubbjZcX1joSTpfZgGzrK7jt+u0b/zT bbDYP5NXz9QVWz9T2TaKLwn4hxzI1uXxElqMF/mx1n61Zo8R3jijJOVdcrMy6g10Of8s 4oBQNLkvU0cI7i+1Z5j/JFcjbGM8V/KRvSk0clZpBXsHTD8hQmIT9Zw89SVqAuDscIcX guC5XptOquJYcxewFk+vAbZYeP+zmumBLxLBezVgNgn8M7UsJakBJb6AkNJCczc1jxC8 C+nVVj7PYwxgZdeVRFN0XPM3/83lkeCFx2bwnnrzipOiOhgjb2IugJ18pE83g3ck9oRr VKhg== X-Gm-Message-State: APjAAAVKj+duo1qAXfcuI2qm3BIsynJa6FOG2SynerbNOZ63kQKneWsa TILdIz+s+MQ5masm/OJamT60MPwJZfE= X-Google-Smtp-Source: APXvYqxcNaDqZvZOulLjPj/TjCmD7suyGdAYrU6iBHMuWZUM0xpeSaNovaH+WoKHbFMTXJXbjR6zTw== X-Received: by 2002:a63:30c6:: with SMTP id w189mr21114425pgw.398.1566250756266; Mon, 19 Aug 2019 14:39:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:51 -0700 Message-Id: <20190819213755.26175-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 64/68] target/arm: Convert T16, load (literal) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 42 ++---------------------------------------- target/arm/t16.decode | 4 ++++ 2 files changed, 6 insertions(+), 40 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index dc3c9049cd..1882057402 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -963,14 +963,6 @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, = TCGv_i32 val, \ TCGv_i32 a32, int index) \ { \ gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \ -} \ -static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \ - TCGv_i32 val, \ - TCGv_i32 a32, int index, \ - ISSInfo issinfo) \ -{ \ - gen_aa32_ld##SUFF(s, val, a32, index); \ - disas_set_da_iss(s, OPC, issinfo); \ } =20 #define DO_GEN_ST(SUFF, OPC) \ @@ -978,14 +970,6 @@ static inline void gen_aa32_st##SUFF(DisasContext *s, = TCGv_i32 val, \ TCGv_i32 a32, int index) \ { \ gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \ -} \ -static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \ - TCGv_i32 val, \ - TCGv_i32 a32, int index, \ - ISSInfo issinfo) \ -{ \ - gen_aa32_st##SUFF(s, val, a32, index); \ - disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \ } =20 static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) @@ -1034,9 +1018,7 @@ static inline void gen_aa32_st64(DisasContext *s, TCG= v_i64 val, gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data); } =20 -DO_GEN_LD(8s, MO_SB) DO_GEN_LD(8u, MO_UB) -DO_GEN_LD(16s, MO_SW) DO_GEN_LD(16u, MO_UW) DO_GEN_LD(32u, MO_UL) DO_GEN_ST(8, MO_UB) @@ -10630,11 +10612,10 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, rd; + uint32_t val; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 addr; =20 if (disas_t16(s, insn)) { return; @@ -10644,26 +10625,7 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) switch (insn >> 12) { case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree = */ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ - goto illegal_op; - case 4: - if (insn & (1 << 11)) { - rd =3D (insn >> 8) & 7; - /* load pc-relative. Bit 1 of PC is ignored. */ - addr =3D add_reg_for_lit(s, 15, (insn & 0xff) * 4); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), - rd | ISSIs16Bit); - tcg_temp_free_i32(addr); - store_reg(s, rd, tmp); - break; - } - - /* - * - Data-processing (two low registers), in decodetree - * - data processing extended, branch and exchange, in decodetree - */ - goto illegal_op; - + case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree= */ case 5: /* load/store register offset, in decodetree */ case 6: /* load/store word immediate offset, in decodetree */ case 7: /* load/store byte immediate offset, in decodetree */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 1adad20804..f87e6fde50 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -113,6 +113,10 @@ LDRH_ri 10001 ..... ... ... @ldst_= ri_2 STR_ri 10010 ... ........ @ldst_spec_i rn=3D13 LDR_ri 10011 ... ........ @ldst_spec_i rn=3D13 =20 +# Load (PC-relative) + +LDR_ri 01001 ... ........ @ldst_spec_i rn=3D15 + # Add PC/SP (immediate) =20 ADR 10100 rd:3 ........ imm=3D%imm8_0x4 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566253827; cv=none; d=zoho.com; s=zohoarc; b=A536ZUqS+8r/+ExbGG6r+PzvdfPyme81WB+T8+mgrHbWeKbKnj4bUO0SVW8MgNzs+louQJpie4u4O9oOFLivMQ+ao3LxOgrx6uMcMBH5A3U3JT+QNXtKlLkm1l12m+DSa6rZSwlYL39c8wgsC4gv0CuhLAfo/RElndHjJ3ZpaA4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566253827; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=F8Uj+UTtvG6sIw1y6R0jwFOyJpam+CLYahliKmILVI4=; b=QEnRsOIuikDaGohH74VdMlkw6grOpVNhrPMh7IuF/NPsBNueCNyylxM+l7NDQwEx7PyYbLroHpTwgK++S9pVeNUVxl/iqt2yTR+vGPeB1abm+kB4v5zwPBXzkodjtfgOSV4gkxhmhZws8ZtgmYM6tBlMDd/XBpx4IfR1Q8/c2G4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566253827456884.2380312895979; Mon, 19 Aug 2019 15:30:27 -0700 (PDT) Received: from localhost ([::1]:60078 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzqAU-0006VH-4U for importer@patchew.org; Mon, 19 Aug 2019 18:30:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60172) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpN2-000360-5Q for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpN1-0006z6-5K for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:20 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:37991) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpN1-0006ya-0D for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:19 -0400 Received: by mail-pf1-x42e.google.com with SMTP id o70so1949909pfg.5 for ; Mon, 19 Aug 2019 14:39:18 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F8Uj+UTtvG6sIw1y6R0jwFOyJpam+CLYahliKmILVI4=; b=irfuP3oRrcyd33uu9iKXwEpcdxetk2P0tjB0PoYBA546Oze5UHJwMuU/0t4BOy78aU vjNdc99u84aTm0H7+HVl/T6U8xmzkS6RaU9DH0N1qn8vqucC+t3Gthb886tdpXOxBZtU n6zW3vN2+hDzdY63rwXQu0SmeuFs6iAwRzB8t6vvPJi8T8r34M1JOx4/Fx20L0avAHGj 8r14fbeXS1tNhIBLS0SL/CnMzDQeclXn7wqk2gsSvvE5sHsokxkRwiR+wGyeM1uEYN+J KFvTEOSNf/FjtzvZIuA03Gm30a+vihXvfc5uOQfkvbOAnZYDDTz5wfN79E/oUqv9A/5G J4sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F8Uj+UTtvG6sIw1y6R0jwFOyJpam+CLYahliKmILVI4=; b=SlTH0pxMnav/N7KegjMV+0UHF0H8QMlAa7hQp//vjlcaiFSx7MQKdKElf9XP+279iS a37V6uLnOAnnp7bTIAa4L0euLQ/KhAOOMCkfY8pg2rpukDcPivzgtFJSAOQLK301anu1 E9OuhoONecb9ntcGzUFeuVoJHBMn2UuXh1dIlP8HsdHIF19ZRvCuuxeug2Y5epSgcEPX yUcoTyQQS8FTcVjfiDD2JW0TtXYRFjjztptC0bKgD3yA/yErZucVFZRhIHfUXe39MOK+ 23bIA0i2nI5bzQ2KcQ2QUxzfeOt1/O7QE8hYLXcys8iMdVKhPQVYpUht0dRYhaXqoieV hg1g== X-Gm-Message-State: APjAAAXhGhdcieQR1k5ffEsgp1Fz+3pdp14Hm7nohPx62st+22tg3q1u dDrNUWHFBUMubLIHX37EstL8V03dTDE= X-Google-Smtp-Source: APXvYqzGJ9JCKs57Z+yEEmKol3q9IyWbFYiRMjnVKEdZPVyvgk5uIZJNDY9PWE+yC0Rt6HAnb8l+Ng== X-Received: by 2002:a63:b64:: with SMTP id a36mr22298999pgl.215.1566250757679; Mon, 19 Aug 2019 14:39:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:52 -0700 Message-Id: <20190819213755.26175-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42e Subject: [Qemu-devel] [PATCH v2 65/68] target/arm: Convert T16, Unconditional branch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 9 ++------- target/arm/t16.decode | 6 ++++++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 1882057402..51b14d409f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10612,7 +10612,6 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10656,12 +10655,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) gen_bx(s, tmp); break; } - /* unconditional branch */ - val =3D read_pc(s); - offset =3D ((int32_t)insn << 21) >> 21; - val +=3D offset << 1; - gen_jmp(s, val); - break; + /* unconditional branch, in decodetree */ + goto illegal_op; =20 case 15: /* thumb_insn_is_16bit() ensures we can't get here for diff --git a/target/arm/t16.decode b/target/arm/t16.decode index f87e6fde50..35a5b03118 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -268,3 +268,9 @@ LDM_t16 1011 110 ......... \ SVC 1101 1111 imm:8 &i B_cond_thumb 1101 cond:4 ........ &ci imm=3D%imm8_0x2 } + +# Unconditional Branch + +%imm11_0x2 0:s11 !function=3Dtimes_2 + +B 11100 ........... &i imm=3D%imm11_0x2 --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566253888; cv=none; d=zoho.com; s=zohoarc; b=SQVXX9fUs5dD2q+d9i8/yNC0EE71NoJWBAx4chgOd55Tidb6O2JEnIAW6ziTdIa0NR8NqZBdhGs1XgXO788R1nCgjTmkOORoOemOeA2BZlRYOo53PY8aR2KiTcHm8KT733Igd5QmEV1Clm3e1yQMiW6Rn7jktoMu/5EvyJ+RU7E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566253888; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=CE2MOpYeaURMh2McMQcADxkv9nuiol4iRofGvabxWa4=; b=neBSWoi/3h+hY0hgtaSGzOEqZnOZ472cQpRdhMuorRIsqbY/G4T+DfzCJU4Mq+7ItlseYLuM03opfok07DkJrKmyIrmJBIep2ShOuxIcRvVZQyKPMx7y3CTOBbXfv+Czx4keoIoMwcj5wxjKTjW/tX2pFntmInxjwvoiUDhKiy8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156625388840536.8326547708582; Mon, 19 Aug 2019 15:31:28 -0700 (PDT) Received: from localhost ([::1]:60110 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzqBT-0007v3-8m for importer@patchew.org; Mon, 19 Aug 2019 18:31:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60207) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpN3-00038b-Kj for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpN2-00071E-A0 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:21 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:43243) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpN2-0006zq-4J for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:20 -0400 Received: by mail-pg1-x52a.google.com with SMTP id k3so1922701pgb.10 for ; Mon, 19 Aug 2019 14:39:20 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CE2MOpYeaURMh2McMQcADxkv9nuiol4iRofGvabxWa4=; b=bHPuMY7AdYlyafexynlB/HZikO0mKlbdgJFNk15y7TjKMMC1G3aISNOKnFA0wi0nIx tmysV2g7ohX3GwfAYUJ3cjEBxifX7GVN/OQsfYcVW31Arh4bTxOisGwDaN9A/DVlpI4g wog512+IqdFpBhkT6qDB9n7y/sl6eFXqtYKghc429RFBY/7FRR+gF2QmBuJ1Bo5D3S3a sH/nOtI9FYsbRS+RqRTpqNKpC8dW060TwaaQSkCp9P3Q0zobi/cdkcHQC2nsolGVGH8w e5rQKR7u2JnzpGRLk8QdNQUF6vz+PWGYLQeHbw+Yaz88AQJYvdMd5jSkfI6XRwAd8hj0 BOGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CE2MOpYeaURMh2McMQcADxkv9nuiol4iRofGvabxWa4=; b=NBeEgXNiC0Jj7/oLJ0/DE6H11lUMydq6qzcHZ8/wZVXuZVcfnL0JrCF3DPgQzDf6Md 35IBKOvj6NWc2HIOryUtlFpfl8NRKLLmlXI3Vcq/w4xRy/dZK15A9vLEo1w1jHeQmgWp Fs4tOvVvXebyP+Rb6HZoWquukOveVqB5keMXVXBH8+fMku0Y0DJTjuMbjKtV6OqoKoOf KFXP+ecAQUwssQvgjJrB9YunvjB7M5ZKqnnliyRxgldeVByuDNFb8J+yR6PucBCS4Ysm lDoJCTKKVtXAT14FqmFYmeRIr4gccjnJJhJo1QrRCa5eSj9DSdn8n981XQl2PQcVKLsV GYbA== X-Gm-Message-State: APjAAAV8L3/pekr7yro5H08UxlfVE6YK/JPWAjCtflbaEKWE/Kud3EIV ZIxY6YDwl1vnT7QMGbyrjS4eRHllnHI= X-Google-Smtp-Source: APXvYqygFXL1x6wvHNEU/vjUqOE6QqlQKoR43l5eXOnrYJzSg9bmfC4YIxj827+4Ckvxqjid5N6g7Q== X-Received: by 2002:a17:90a:3465:: with SMTP id o92mr22412655pjb.20.1566250758891; Mon, 19 Aug 2019 14:39:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:53 -0700 Message-Id: <20190819213755.26175-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PATCH v2 66/68] target/arm: Convert T16, long branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 89 +++++++++++++++++++----------------------- target/arm/t16.decode | 3 ++ 2 files changed, 43 insertions(+), 49 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 51b14d409f..f8997a8424 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10025,6 +10025,44 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i= *a) return true; } =20 +static bool trans_BL_BLX_prefix(DisasContext *s, arg_BL_BLX_prefix *a) +{ + /* + * thumb_insn_is_16bit() ensures we can't get here for + * a Thumb2 CPU, so this must be a thumb1 split BL/BLX. + */ + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + tcg_gen_movi_i32(cpu_R[14], read_pc(s) + (a->imm << 12)); + return true; +} + +static bool trans_BL_suffix(DisasContext *s, arg_BL_suffix *a) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + tcg_gen_addi_i32(tmp, cpu_R[14], (a->imm << 1) | 1); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_bx(s, tmp); + return true; +} + +static bool trans_BLX_suffix(DisasContext *s, arg_BLX_suffix *a) +{ + TCGv_i32 tmp; + + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + if (!ENABLE_ARCH_5) { + return false; + } + tmp =3D tcg_temp_new_i32(); + tcg_gen_addi_i32(tmp, cpu_R[14], a->imm << 1); + tcg_gen_andi_i32(tmp, tmp, -4); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_bx(s, tmp); + return true; +} + static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) { TCGv_i32 addr, tmp; @@ -10612,10 +10650,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - int32_t offset; - TCGv_i32 tmp; - TCGv_i32 tmp2; - if (disas_t16(s, insn)) { return; } @@ -10634,53 +10668,10 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) case 11: /* misc, in decodetree */ case 12: /* load/store multiple, in decodetree */ case 13: /* conditional branch or swi, in decodetree */ - goto illegal_op; - case 14: - if (insn & (1 << 11)) { - /* thumb_insn_is_16bit() ensures we can't get here for - * a Thumb2 CPU, so this must be a thumb1 split BL/BLX: - * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF) - */ - assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - ARCH(5); - offset =3D ((insn & 0x7ff) << 1); - tmp =3D load_reg(s, 14); - tcg_gen_addi_i32(tmp, tmp, offset); - tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); - - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next | 1); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - break; - } - /* unconditional branch, in decodetree */ - goto illegal_op; - case 15: - /* thumb_insn_is_16bit() ensures we can't get here for - * a Thumb2 CPU, so this must be a thumb1 split BL/BLX. - */ - assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - - if (insn & (1 << 11)) { - /* 0b1111_1xxx_xxxx_xxxx : BL suffix */ - offset =3D ((insn & 0x7ff) << 1) | 1; - tmp =3D load_reg(s, 14); - tcg_gen_addi_i32(tmp, tmp, offset); - - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next | 1); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - } else { - /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */ - uint32_t uoffset =3D ((int32_t)insn << 21) >> 9; - - tcg_gen_movi_i32(cpu_R[14], read_pc(s) + uoffset); - } - break; + /* branches, in decodetree */ + goto illegal_op; } return; illegal_op: diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 35a5b03118..5ee8457efb 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -274,3 +274,6 @@ LDM_t16 1011 110 ......... \ %imm11_0x2 0:s11 !function=3Dtimes_2 =20 B 11100 ........... &i imm=3D%imm11_0x2 +BLX_suffix 11101 imm:11 &i +BL_BLX_prefix 11110 imm:s11 &i +BL_suffix 11111 imm:11 &i --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 67/68] target/arm: Clean up disas_thumb_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that everything is converted, remove the rest of the legacy decode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 27 ++------------------------- 1 file changed, 2 insertions(+), 25 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index f8997a8424..bac38e6261 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10650,32 +10650,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - if (disas_t16(s, insn)) { - return; + if (!disas_t16(s, insn)) { + unallocated_encoding(s); } - /* fall back to legacy decoder */ - - switch (insn >> 12) { - case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree = */ - case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ - case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree= */ - case 5: /* load/store register offset, in decodetree */ - case 6: /* load/store word immediate offset, in decodetree */ - case 7: /* load/store byte immediate offset, in decodetree */ - case 8: /* load/store halfword immediate offset, in decodetree */ - case 9: /* load/store from stack, in decodetree */ - case 10: /* add PC/SP (immediate), in decodetree */ - case 11: /* misc, in decodetree */ - case 12: /* load/store multiple, in decodetree */ - case 13: /* conditional branch or swi, in decodetree */ - case 14: - case 15: - /* branches, in decodetree */ - goto illegal_op; - } - return; -illegal_op: - unallocated_encoding(s); } =20 static bool insn_crosses_page(CPUARMState *env, DisasContext *s) --=20 2.17.1 From nobody Fri May 3 06:53:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1566253998; cv=none; d=zoho.com; s=zohoarc; b=XpYf8tHA6qtVmwzNFcmcDQF71IOS5se4eQPejwlydv0SJQq/Bwxphe6b+qZ167xY6Xigndkan94mzLajO8UxD8uzJdOOHCK1W7o7aofXXkQ8tW6NjhJpvZExTjD7JXpFHz9OP6NwD0TkcHW5Ihksg8JCLwkEYqMhGTtfpnXlv4g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566253998; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=pOrmu4hSyVv/uT8dsNEbfV+BcoCBHIkgixiHAKgiaBE=; b=clH77WSPCkfM1LyxNRH5OaJQleoiw9pUKhtFJG3ktGcFYpwDOpzcTrkYsiEB/NTdJlW0elv5JYLlitFseNHu23K8RaXzBRWWAYyXAH7jPvAiebCIdIJN2su11ys4O1gToxu9lZciLXUyhXhst1PKLSSYMOvfowmDyU0kq6WazlA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566253998222154.84657570125842; Mon, 19 Aug 2019 15:33:18 -0700 (PDT) Received: from localhost ([::1]:60150 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzqD9-0001qP-V8 for importer@patchew.org; Mon, 19 Aug 2019 18:33:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60253) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpN5-0003CL-QP for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpN4-00073T-M7 for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:23 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:37184) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpN4-000735-Gb for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:39:22 -0400 Received: by mail-pl1-x643.google.com with SMTP id bj8so1587466plb.4 for ; Mon, 19 Aug 2019 14:39:22 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pOrmu4hSyVv/uT8dsNEbfV+BcoCBHIkgixiHAKgiaBE=; b=szYWKgnbjQZEyqcsTvJZwySHhotNNZp7oNO0mFXiSwrXztSEMf/pZcRYx1fEL+KZR9 tmfY/8DvfXaWvxGAnVm7gPjJPZT46j2Vba0RgNh+bCQvBIpPa41tTyS2YaTQ2aRlk7C6 vCgAotQhYMekCV9dxyXfcqQS/0KsNjFhUgq0Civeddgx8VbeasuAPndSRcSQ6O/In2yN YR64X2uxYUFdA23mGwM2f3blTbBOh3R1iWArkePm2wD2M3ZjX4TjYy0Wfy64tfxF92hx UvU8nw8X4yu3uM/xBOwreT685/qPPb+5sA1eGCaNhYPQ6llll+EcEo/1Yp+llAZ6fXlX AMKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pOrmu4hSyVv/uT8dsNEbfV+BcoCBHIkgixiHAKgiaBE=; b=pSuGZhiHlLhUcLuq1ILISbRUhAblrHN99IoECIWXJ4O9iibDHbI8JMDehfl9hMy2vl G9DFrKOx9BX+TRmnUita/VoRl27XJfcu83tDuJ311J6JRUcB4308MRMIh6L479q9KeBv yB93toldfYK5fhlgl7DCvCJEtn70KWYkGoWO70NEDizKlazB6REksawWJUF0I22AX0NF 65klB0oWiAgsspA05zlbJoerWTWPUz0uSv0/03zwdoFhwCi0EhhSgssyj39HnPjlXUsF MDPjnuf0GauU2OmVQ3xK3r/yQ2nIHQrEjMVUdsvqbA9RbxKTDwkaJkKBo5tdUkP5uNyZ jq8w== X-Gm-Message-State: APjAAAVHPT4rmg/Y2VkbTrWDvB5K8U8ws08AR/aF7sHXvweX87bzQJ8p 1DrJyY46RBVUutjHw5u9OAZ6gTyX5po= X-Google-Smtp-Source: APXvYqwG71x5PrOX4J+5+jRM2Eg8cMmBpqnVHk5NuDA0yW4nLmnPD6oZL0pGRp9T4osjVV5Tsfi5iA== X-Received: by 2002:a17:902:543:: with SMTP id 61mr24756723plf.20.1566250761305; Mon, 19 Aug 2019 14:39:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:55 -0700 Message-Id: <20190819213755.26175-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 68/68] target/arm: Inline gen_bx_im into callers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There are only two remaining uses of gen_bx_im. In each case, we know the destination mode -- not changing in the case of gen_jmp or changing in the case of trans_BLX_i. Use this to simplify the surrounding code. For trans_BLX_i, use gen_jmp for the actual branch. For gen_jmp, use gen_set_pc_im to set up the single-step. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 26 +++++++------------------- 1 file changed, 7 insertions(+), 19 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index bac38e6261..9162ad113a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -765,21 +765,6 @@ static inline void gen_set_pc_im(DisasContext *s, targ= et_ulong val) tcg_gen_movi_i32(cpu_R[15], val); } =20 -/* Set PC and Thumb state from an immediate address. */ -static inline void gen_bx_im(DisasContext *s, uint32_t addr) -{ - TCGv_i32 tmp; - - s->base.is_jmp =3D DISAS_JUMP; - if (s->thumb !=3D (addr & 1)) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, addr & 1); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb)); - tcg_temp_free_i32(tmp); - } - tcg_gen_movi_i32(cpu_R[15], addr & ~1); -} - /* Set PC and Thumb state from var. var is marked as dead. */ static inline void gen_bx(DisasContext *s, TCGv_i32 var) { @@ -2706,9 +2691,8 @@ static inline void gen_jmp (DisasContext *s, uint32_t= dest) { if (unlikely(is_singlestepping(s))) { /* An indirect jump so that we still trigger the debug exception. = */ - if (s->thumb) - dest |=3D 1; - gen_bx_im(s, dest); + gen_set_pc_im(s, dest); + s->base.is_jmp =3D DISAS_JUMP; } else { gen_goto_tb(s, 0, dest); } @@ -10016,12 +10000,16 @@ static bool trans_BL(DisasContext *s, arg_i *a) =20 static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) { + TCGv_i32 tmp; + /* For A32, ARCH(5) is checked near the start of the uncond block. */ if (s->thumb && (a->imm & 2)) { return false; } tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); - gen_bx_im(s, (read_pc(s) & ~3) + a->imm + !s->thumb); + tmp =3D tcg_const_i32(!s->thumb); + store_cpu_field(tmp, thumb); + gen_jmp(s, (read_pc(s) & ~3) + a->imm); return true; } =20 --=20 2.17.1