From nobody Mon Feb 9 12:26:29 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1566169346; cv=none; d=zoho.com; s=zohoarc; b=WkwGQyS+fVC7vZxYTQvOQOcaJg3448LM+nLiVLN854rTE6SQJwNPR9CZGjvulTXQB6hIrKS0x4bxAQyHrMdkI7bOkOsSU4gutadsbNurnHIK2k7zg2rshbAAmhDnlh3BBN7UAeofRqxsYtTxk/ivd73t0FVbU5YPnuBYwStxNc0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566169346; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=N6+usWPSWhQJGCRZ9/FyR4+ht1JmLyNc20Zqal53W+c=; b=N9bxXBQyoHeOQn0YAALn21RmG5n8JaeZFwDq94IGmBfGTnLEA1nn4jPqEExZtWV06R5wCb4vieBNfgm5kmR+wHXbopolFqUCAtTvahDFFFlLoMk133C91iEtk/h5+0BirX3Pj0j9KdELmLnoCUTgKOqerkudwUUmnaoxsT4avAU= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566169346266570.9148105940116; Sun, 18 Aug 2019 16:02:26 -0700 (PDT) Received: from localhost ([::1]:43448 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzUBs-0000Y2-ER for importer@patchew.org; Sun, 18 Aug 2019 19:02:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48414) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzU4N-0000QS-Nw for qemu-devel@nongnu.org; Sun, 18 Aug 2019 18:54:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzU4M-0007qo-5t for qemu-devel@nongnu.org; Sun, 18 Aug 2019 18:54:39 -0400 Received: from mx1.redhat.com ([209.132.183.28]:36706) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hzU4L-0007qc-TE for qemu-devel@nongnu.org; Sun, 18 Aug 2019 18:54:38 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 30F068763B; Sun, 18 Aug 2019 22:54:37 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-33.brq.redhat.com [10.40.204.33]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 11A5A1C1; Sun, 18 Aug 2019 22:54:32 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 00:54:01 +0200 Message-Id: <20190818225414.22590-3-philmd@redhat.com> In-Reply-To: <20190818225414.22590-1-philmd@redhat.com> References: <20190818225414.22590-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Sun, 18 Aug 2019 22:54:37 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v4 02/15] hw/i386/pc: Extract e820 memory layout code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Zhong , Samuel Ortiz , Rob Bradford , "Michael S. Tsirkin" , Marcelo Tosatti , Li Qiang , kvm@vger.kernel.org, Christophe de Dinechin , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Suggested-by: Samuel Ortiz Reviewed-by: Li Qiang Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v3: KISS, do not use unsigned, do not add broken documentation --- hw/i386/Makefile.objs | 2 +- hw/i386/e820_memory_layout.c | 59 ++++++++++++++++++++++++++++++++++ hw/i386/e820_memory_layout.h | 42 +++++++++++++++++++++++++ hw/i386/pc.c | 61 +----------------------------------- include/hw/i386/pc.h | 11 ------- target/i386/kvm.c | 1 + 6 files changed, 104 insertions(+), 72 deletions(-) create mode 100644 hw/i386/e820_memory_layout.c create mode 100644 hw/i386/e820_memory_layout.h diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs index 5d9c9efd5f..d3374e0831 100644 --- a/hw/i386/Makefile.objs +++ b/hw/i386/Makefile.objs @@ -1,5 +1,5 @@ obj-$(CONFIG_KVM) +=3D kvm/ -obj-y +=3D multiboot.o +obj-y +=3D e820_memory_layout.o multiboot.o obj-y +=3D pc.o obj-$(CONFIG_I440FX) +=3D pc_piix.o obj-$(CONFIG_Q35) +=3D pc_q35.o diff --git a/hw/i386/e820_memory_layout.c b/hw/i386/e820_memory_layout.c new file mode 100644 index 0000000000..bcf9eaf837 --- /dev/null +++ b/hw/i386/e820_memory_layout.c @@ -0,0 +1,59 @@ +/* + * QEMU BIOS e820 routines + * + * Copyright (c) 2003-2004 Fabrice Bellard + * + * SPDX-License-Identifier: MIT + */ + +#include "qemu/osdep.h" +#include "qemu/bswap.h" +#include "e820_memory_layout.h" + +static size_t e820_entries; +struct e820_table e820_reserve; +struct e820_entry *e820_table; + +int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) +{ + int index =3D le32_to_cpu(e820_reserve.count); + struct e820_entry *entry; + + if (type !=3D E820_RAM) { + /* old FW_CFG_E820_TABLE entry -- reservations only */ + if (index >=3D E820_NR_ENTRIES) { + return -EBUSY; + } + entry =3D &e820_reserve.entry[index++]; + + entry->address =3D cpu_to_le64(address); + entry->length =3D cpu_to_le64(length); + entry->type =3D cpu_to_le32(type); + + e820_reserve.count =3D cpu_to_le32(index); + } + + /* new "etc/e820" file -- include ram too */ + e820_table =3D g_renew(struct e820_entry, e820_table, e820_entries + 1= ); + e820_table[e820_entries].address =3D cpu_to_le64(address); + e820_table[e820_entries].length =3D cpu_to_le64(length); + e820_table[e820_entries].type =3D cpu_to_le32(type); + e820_entries++; + + return e820_entries; +} + +int e820_get_num_entries(void) +{ + return e820_entries; +} + +bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *l= ength) +{ + if (idx < e820_entries && e820_table[idx].type =3D=3D cpu_to_le32(type= )) { + *address =3D le64_to_cpu(e820_table[idx].address); + *length =3D le64_to_cpu(e820_table[idx].length); + return true; + } + return false; +} diff --git a/hw/i386/e820_memory_layout.h b/hw/i386/e820_memory_layout.h new file mode 100644 index 0000000000..2a0ceb8b9c --- /dev/null +++ b/hw/i386/e820_memory_layout.h @@ -0,0 +1,42 @@ +/* + * QEMU BIOS e820 routines + * + * Copyright (c) 2003-2004 Fabrice Bellard + * + * SPDX-License-Identifier: MIT + */ + +#ifndef HW_I386_E820_H +#define HW_I386_E820_H + +/* e820 types */ +#define E820_RAM 1 +#define E820_RESERVED 2 +#define E820_ACPI 3 +#define E820_NVS 4 +#define E820_UNUSABLE 5 + +#define E820_NR_ENTRIES 16 + +struct e820_entry { + uint64_t address; + uint64_t length; + uint32_t type; +} QEMU_PACKED __attribute((__aligned__(4))); + +struct e820_table { + uint32_t count; + struct e820_entry entry[E820_NR_ENTRIES]; +} QEMU_PACKED __attribute((__aligned__(4))); + +extern struct e820_table e820_reserve; +extern struct e820_entry *e820_table; + +int e820_add_entry(uint64_t address, uint64_t length, uint32_t type); +int e820_get_num_entries(void); +bool e820_get_entry(int index, uint32_t type, + uint64_t *address, uint64_t *length); + + + +#endif diff --git a/hw/i386/pc.c b/hw/i386/pc.c index ab1fe1169a..75cdf57922 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -87,6 +87,7 @@ #include "sysemu/replay.h" #include "qapi/qmp/qerror.h" #include "config-devices.h" +#include "e820_memory_layout.h" =20 /* debug PC/ISA interrupts */ //#define DEBUG_IRQ @@ -98,22 +99,6 @@ #define DPRINTF(fmt, ...) #endif =20 -#define E820_NR_ENTRIES 16 - -struct e820_entry { - uint64_t address; - uint64_t length; - uint32_t type; -} QEMU_PACKED __attribute((__aligned__(4))); - -struct e820_table { - uint32_t count; - struct e820_entry entry[E820_NR_ENTRIES]; -} QEMU_PACKED __attribute((__aligned__(4))); - -static struct e820_table e820_reserve; -static struct e820_entry *e820_table; -static unsigned e820_entries; struct hpet_fw_config hpet_cfg =3D {.count =3D UINT8_MAX}; =20 /* Physical Address of PVH entry point read from kernel ELF NOTE */ @@ -877,50 +862,6 @@ static void handle_a20_line_change(void *opaque, int i= rq, int level) x86_cpu_set_a20(cpu, level); } =20 -int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) -{ - int index =3D le32_to_cpu(e820_reserve.count); - struct e820_entry *entry; - - if (type !=3D E820_RAM) { - /* old FW_CFG_E820_TABLE entry -- reservations only */ - if (index >=3D E820_NR_ENTRIES) { - return -EBUSY; - } - entry =3D &e820_reserve.entry[index++]; - - entry->address =3D cpu_to_le64(address); - entry->length =3D cpu_to_le64(length); - entry->type =3D cpu_to_le32(type); - - e820_reserve.count =3D cpu_to_le32(index); - } - - /* new "etc/e820" file -- include ram too */ - e820_table =3D g_renew(struct e820_entry, e820_table, e820_entries + 1= ); - e820_table[e820_entries].address =3D cpu_to_le64(address); - e820_table[e820_entries].length =3D cpu_to_le64(length); - e820_table[e820_entries].type =3D cpu_to_le32(type); - e820_entries++; - - return e820_entries; -} - -int e820_get_num_entries(void) -{ - return e820_entries; -} - -bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *l= ength) -{ - if (idx < e820_entries && e820_table[idx].type =3D=3D cpu_to_le32(type= )) { - *address =3D le64_to_cpu(e820_table[idx].address); - *length =3D le64_to_cpu(e820_table[idx].length); - return true; - } - return false; -} - /* Calculates initial APIC ID for a specific CPU index * * Currently we need to be able to calculate the APIC ID from the CPU index diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 4bb9e29114..18b31b1292 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -290,17 +290,6 @@ void pc_system_firmware_init(PCMachineState *pcms, Mem= oryRegion *rom_memory); void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, const CPUArchIdList *apic_ids, GArray *entry); =20 -/* e820 types */ -#define E820_RAM 1 -#define E820_RESERVED 2 -#define E820_ACPI 3 -#define E820_NVS 4 -#define E820_UNUSABLE 5 - -int e820_add_entry(uint64_t, uint64_t, uint32_t); -int e820_get_num_entries(void); -bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); - extern GlobalProperty pc_compat_4_0[]; extern const size_t pc_compat_4_0_len; =20 diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 2abc881324..af9a762c1d 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -41,6 +41,7 @@ #include "hw/i386/apic-msidef.h" #include "hw/i386/intel_iommu.h" #include "hw/i386/x86-iommu.h" +#include "hw/i386/e820_memory_layout.h" =20 #include "hw/pci/pci.h" #include "hw/pci/msi.h" --=20 2.20.1