From nobody Fri Dec 19 14:32:02 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1565961940; cv=none; d=zoho.com; s=zohoarc; b=UPcMgLCpDUKCvE1cFGxKHLZ+Idr0adDmp2nr7ZMdY5GO+Kkx2f17Qd1ttwgBKuqs3hEltBQ3DNzwR2NYGRraRhZ5X0JwE7KTm4XVTX5pdbZaN2tc23pCNKtf+Wz1wjYsu9mZHgcHuNdO19YGOq4LUjwXBFzH22uDC3iX+g+gZjk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565961940; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=j84/g0oOWSuF2eIUk7fO9+M3370kgvOYjABlA5jzGcs=; b=Om7jTGbD3OHONRA9W0PzKMhRk/7LBca9dgAP1unj13/Xb8VcbPLhC/rLTk9SuTAaCGzKbBpe87kHIn0HxiicXpnXF6wFfZ0GckQ929WjsoCpMUS7q4JQPb6WkshMUnPxS14+LIh6c248vROyRFlVxv0kd0VsspZATRuVg3H2Ago= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565961940283879.8637160866492; Fri, 16 Aug 2019 06:25:40 -0700 (PDT) Received: from localhost ([::1]:56026 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hycEc-0004zn-DW for importer@patchew.org; Fri, 16 Aug 2019 09:25:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35187) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hyc6m-0003KS-HX for qemu-devel@nongnu.org; Fri, 16 Aug 2019 09:17:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hyc6k-0005P0-Ls for qemu-devel@nongnu.org; Fri, 16 Aug 2019 09:17:32 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:51712) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hyc6k-0005NN-DW for qemu-devel@nongnu.org; Fri, 16 Aug 2019 09:17:30 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 207so4029479wma.1 for ; Fri, 16 Aug 2019 06:17:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 4sm8705796wro.78.2019.08.16.06.17.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2019 06:17:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=j84/g0oOWSuF2eIUk7fO9+M3370kgvOYjABlA5jzGcs=; b=wCC6gSw1wU3Z/PQeUVuV2wEGIJhI5vaajGeoahFmISh1MdCsMbiXurigpbHX2vuXPe dmrzACxBg8Ers5E0JjV897szPAKaGHr/igRQFpFhG1k3zgjhknh8yUN3qmp2zvYFrq3m MPlZPPVJK00+q7w0ZS5ClbRi03XlLxd4JY/Nl4MJKg9VypDyuP1vArhoJ6sY8zaRuGZM /AvLUUzdcfQS/zZXVUvxIBFWEOLBS5J2awO18IhQ2zZRg8fviNLWZjMRN1pa9QDPmjF+ NgcjD7EMdQ3pY3027vskUCTENLd6OZpRuXgUYxebSbejZ4B1JoydZ1A+KRk2ylqCWWr6 roqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j84/g0oOWSuF2eIUk7fO9+M3370kgvOYjABlA5jzGcs=; b=gqSrkmDu0NxTa8EEURQu3N7qjJkpJmICZtjvarX3dMf/lAW4wuur0yVObq/1gVdsXd fZFEW2H7jHdPV/GOtoCZQcwJKHq14ycpaRslPJtYd+s6OPcOG/HTEJxwVKuvaD2bwwcU Ryiuu46J/ENv6b8zJJXeMx2u+envtiXMo7YXRVxnHaM1UR5H+DErWfPIAIG4EmqmdVRr ba84Qfpm25Tb+vDChCOF/e2jJV+2AIHjImC1LOonaFWPhQYgmEXl0+yhTeqIaaS8TSr0 D8qTYfHF621XBAtA4ScZn1bDmwWhGcYu+eI7DX+fTzSG09gG4qIyf6Onr9yhsSqKaINC VBlA== X-Gm-Message-State: APjAAAW6jznANA9A7TuR9x3uzXD2RL+DZJEa1DP3Kfps6pPTrqesrqry ndawHHza+qEYY5y5jHjplEF+UZvPBnl3sg== X-Google-Smtp-Source: APXvYqwon+BkF4y2MBq90VvPNkSS9w6x2ezdic+kMd7v/dbVfhrkAcs28FUrt2fVURJUHWuIwuS+3g== X-Received: by 2002:a05:600c:22d7:: with SMTP id 23mr7773419wmg.0.1565961448455; Fri, 16 Aug 2019 06:17:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 16 Aug 2019 14:16:57 +0100 Message-Id: <20190816131719.28244-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190816131719.28244-1-peter.maydell@linaro.org> References: <20190816131719.28244-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PULL 07/29] target/arm: Introduce pc_curr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Richard Henderson Add a new field to retain the address of the instruction currently being translated. The 32-bit uses are all within subroutines used by a32 and t32. This will become less obvious when t16 support is merged with a32+t32, and having a clear definition will help. Convert aarch64 as well for consistency. Note that there is one instance of a pre-assert fprintf that used the wrong value for the address of the current instruction. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190807045335.1361-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.h | 2 +- target/arm/translate.h | 2 ++ target/arm/translate-a64.c | 21 +++++++++++---------- target/arm/translate.c | 14 ++++++++------ 4 files changed, 22 insertions(+), 17 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 9ab40872d85..9cd2b3d2389 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -25,7 +25,7 @@ void unallocated_encoding(DisasContext *s); qemu_log_mask(LOG_UNIMP, \ "%s:%d: unsupported instruction encoding 0x%08x " \ "at pc=3D%016" PRIx64 "\n", = \ - __FILE__, __LINE__, insn, s->pc - 4); \ + __FILE__, __LINE__, insn, s->pc_curr); \ unallocated_encoding(s); \ } while (0) =20 diff --git a/target/arm/translate.h b/target/arm/translate.h index b65954c669b..53ac50bc028 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -11,6 +11,8 @@ typedef struct DisasContext { const ARMISARegisters *isar; =20 target_ulong pc; + /* The address of the current instruction being translated. */ + target_ulong pc_curr; target_ulong page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 90850eadc1b..a0b557ddcec 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1234,7 +1234,7 @@ static inline AArch64DecodeFn *lookup_disas_fn(const = AArch64DecodeTable *table, */ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) { - uint64_t addr =3D s->pc + sextract32(insn, 0, 26) * 4 - 4; + uint64_t addr =3D s->pc_curr + sextract32(insn, 0, 26) * 4; =20 if (insn & (1U << 31)) { /* BL Branch with link */ @@ -1262,7 +1262,7 @@ static void disas_comp_b_imm(DisasContext *s, uint32_= t insn) sf =3D extract32(insn, 31, 1); op =3D extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ rt =3D extract32(insn, 0, 5); - addr =3D s->pc + sextract32(insn, 5, 19) * 4 - 4; + addr =3D s->pc_curr + sextract32(insn, 5, 19) * 4; =20 tcg_cmp =3D read_cpu_reg(s, rt, sf); label_match =3D gen_new_label(); @@ -1291,7 +1291,7 @@ static void disas_test_b_imm(DisasContext *s, uint32_= t insn) =20 bit_pos =3D (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); op =3D extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ - addr =3D s->pc + sextract32(insn, 5, 14) * 4 - 4; + addr =3D s->pc_curr + sextract32(insn, 5, 14) * 4; rt =3D extract32(insn, 0, 5); =20 tcg_cmp =3D tcg_temp_new_i64(); @@ -1322,7 +1322,7 @@ static void disas_cond_b_imm(DisasContext *s, uint32_= t insn) unallocated_encoding(s); return; } - addr =3D s->pc + sextract32(insn, 5, 19) * 4 - 4; + addr =3D s->pc_curr + sextract32(insn, 5, 19) * 4; cond =3D extract32(insn, 0, 4); =20 reset_btype(s); @@ -1706,7 +1706,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, TCGv_i32 tcg_syn, tcg_isread; uint32_t syndrome; =20 - gen_a64_set_pc_im(s->pc - 4); + gen_a64_set_pc_im(s->pc_curr); tmpptr =3D tcg_const_ptr(ri); syndrome =3D syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isre= ad); tcg_syn =3D tcg_const_i32(syndrome); @@ -1870,7 +1870,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) /* The pre HVC helper handles cases when HVC gets trapped * as an undefined insn by runtime configuration. */ - gen_a64_set_pc_im(s->pc - 4); + gen_a64_set_pc_im(s->pc_curr); gen_helper_pre_hvc(cpu_env); gen_ss_advance(s); gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2); @@ -1880,7 +1880,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) unallocated_encoding(s); break; } - gen_a64_set_pc_im(s->pc - 4); + gen_a64_set_pc_im(s->pc_curr); tmp =3D tcg_const_i32(syn_aa64_smc(imm16)); gen_helper_pre_smc(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -2601,7 +2601,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) =20 tcg_rt =3D cpu_reg(s, rt); =20 - clean_addr =3D tcg_const_i64((s->pc - 4) + imm); + clean_addr =3D tcg_const_i64(s->pc_curr + imm); if (is_vector) { do_fp_ld(s, rt, clean_addr, size); } else { @@ -3580,7 +3580,7 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_= t insn) offset =3D sextract64(insn, 5, 19); offset =3D offset << 2 | extract32(insn, 29, 2); rd =3D extract32(insn, 0, 5); - base =3D s->pc - 4; + base =3D s->pc_curr; =20 if (page) { /* ADRP (page based) */ @@ -11519,7 +11519,7 @@ static void disas_simd_three_reg_same_fp16(DisasCon= text *s, uint32_t insn) break; default: fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\= n", - __func__, insn, fpopcode, s->pc); + __func__, insn, fpopcode, s->pc_curr); g_assert_not_reached(); } =20 @@ -14030,6 +14030,7 @@ static void disas_a64_insn(CPUARMState *env, DisasC= ontext *s) { uint32_t insn; =20 + s->pc_curr =3D s->pc; insn =3D arm_ldl_code(env, s->pc, s->sctlr_b); s->insn =3D insn; s->pc +=3D 4; diff --git a/target/arm/translate.c b/target/arm/translate.c index de941e6b3dc..fed08c63f81 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1197,7 +1197,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) * as an undefined insn by runtime configuration (ie before * the insn really executes). */ - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->pc_curr); gen_helper_pre_hvc(cpu_env); /* Otherwise we will treat this as a real exception which * happens after execution of the insn. (The distinction matters @@ -1216,7 +1216,7 @@ static inline void gen_smc(DisasContext *s) */ TCGv_i32 tmp; =20 - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->pc_curr); tmp =3D tcg_const_i32(syn_aa32_smc()); gen_helper_pre_smc(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -3175,7 +3175,7 @@ static void gen_msr_banked(DisasContext *s, int r, in= t sysm, int rn) =20 /* Sync state because msr_banked() can raise exceptions */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->pc_curr); tcg_reg =3D load_reg(s, rn); tcg_tgtmode =3D tcg_const_i32(tgtmode); tcg_regno =3D tcg_const_i32(regno); @@ -3197,7 +3197,7 @@ static void gen_mrs_banked(DisasContext *s, int r, in= t sysm, int rn) =20 /* Sync state because mrs_banked() can raise exceptions */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->pc_curr); tcg_reg =3D tcg_temp_new_i32(); tcg_tgtmode =3D tcg_const_i32(tgtmode); tcg_regno =3D tcg_const_i32(regno); @@ -7204,7 +7204,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) } =20 gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->pc_curr); tmpptr =3D tcg_const_ptr(ri); tcg_syn =3D tcg_const_i32(syndrome); tcg_isread =3D tcg_const_i32(isread); @@ -7614,7 +7614,7 @@ static void gen_srs(DisasContext *s, tmp =3D tcg_const_i32(mode); /* get_r13_banked() will raise an exception if called from System mode= */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->pc_curr); gen_helper_get_r13_banked(addr, cpu_env, tmp); tcg_temp_free_i32(tmp); switch (amode) { @@ -12039,6 +12039,7 @@ static void arm_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) return; } =20 + dc->pc_curr =3D dc->pc; insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); dc->insn =3D insn; dc->pc +=3D 4; @@ -12107,6 +12108,7 @@ static void thumb_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu) return; } =20 + dc->pc_curr =3D dc->pc; insn =3D arm_lduw_code(env, dc->pc, dc->sctlr_b); is_16bit =3D thumb_insn_is_16bit(dc, dc->pc, insn); dc->pc +=3D 2; --=20 2.20.1