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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PULL 22/29] target/arm/kvm64: Move the get/put of fpsimd registers out X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Andrew Jones Move the getting/putting of the fpsimd registers out of kvm_arch_get/put_registers() into their own helper functions to prepare for alternatively getting/putting SVE registers. No functional change. Signed-off-by: Andrew Jones Reviewed-by: Eric Auger Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 148 +++++++++++++++++++++++++++------------------ 1 file changed, 88 insertions(+), 60 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index ddde6268b9d..0b004d5d305 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -719,13 +719,53 @@ int kvm_arm_cpreg_level(uint64_t regidx) #define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) =20 +static int kvm_arch_put_fpsimd(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + struct kvm_one_reg reg; + uint32_t fpr; + int i, ret; + + for (i =3D 0; i < 32; i++) { + uint64_t *q =3D aa64_vfp_qreg(env, i); +#ifdef HOST_WORDS_BIGENDIAN + uint64_t fp_val[2] =3D { q[1], q[0] }; + reg.addr =3D (uintptr_t)fp_val; +#else + reg.addr =3D (uintptr_t)q; +#endif + reg.id =3D AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); + ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + if (ret) { + return ret; + } + } + + reg.addr =3D (uintptr_t)(&fpr); + fpr =3D vfp_get_fpsr(env); + reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpsr); + ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + if (ret) { + return ret; + } + + reg.addr =3D (uintptr_t)(&fpr); + fpr =3D vfp_get_fpcr(env); + reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpcr); + ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + if (ret) { + return ret; + } + + return 0; +} + int kvm_arch_put_registers(CPUState *cs, int level) { struct kvm_one_reg reg; - uint32_t fpr; uint64_t val; - int i; - int ret; + int i, ret; unsigned int el; =20 ARMCPU *cpu =3D ARM_CPU(cs); @@ -815,33 +855,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) } } =20 - /* Advanced SIMD and FP registers. */ - for (i =3D 0; i < 32; i++) { - uint64_t *q =3D aa64_vfp_qreg(env, i); -#ifdef HOST_WORDS_BIGENDIAN - uint64_t fp_val[2] =3D { q[1], q[0] }; - reg.addr =3D (uintptr_t)fp_val; -#else - reg.addr =3D (uintptr_t)q; -#endif - reg.id =3D AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); - if (ret) { - return ret; - } - } - - reg.addr =3D (uintptr_t)(&fpr); - fpr =3D vfp_get_fpsr(env); - reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpsr); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); - if (ret) { - return ret; - } - - fpr =3D vfp_get_fpcr(env); - reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpcr); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_arch_put_fpsimd(cs); if (ret) { return ret; } @@ -862,14 +876,54 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } =20 +static int kvm_arch_get_fpsimd(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + struct kvm_one_reg reg; + uint32_t fpr; + int i, ret; + + for (i =3D 0; i < 32; i++) { + uint64_t *q =3D aa64_vfp_qreg(env, i); + reg.id =3D AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); + reg.addr =3D (uintptr_t)q; + ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + if (ret) { + return ret; + } else { +#ifdef HOST_WORDS_BIGENDIAN + uint64_t t; + t =3D q[0], q[0] =3D q[1], q[1] =3D t; +#endif + } + } + + reg.addr =3D (uintptr_t)(&fpr); + reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpsr); + ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + if (ret) { + return ret; + } + vfp_set_fpsr(env, fpr); + + reg.addr =3D (uintptr_t)(&fpr); + reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpcr); + ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + if (ret) { + return ret; + } + vfp_set_fpcr(env, fpr); + + return 0; +} + int kvm_arch_get_registers(CPUState *cs) { struct kvm_one_reg reg; uint64_t val; - uint32_t fpr; unsigned int el; - int i; - int ret; + int i, ret; =20 ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -958,36 +1012,10 @@ int kvm_arch_get_registers(CPUState *cs) env->spsr =3D env->banked_spsr[i]; } =20 - /* Advanced SIMD and FP registers */ - for (i =3D 0; i < 32; i++) { - uint64_t *q =3D aa64_vfp_qreg(env, i); - reg.id =3D AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); - reg.addr =3D (uintptr_t)q; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); - if (ret) { - return ret; - } else { -#ifdef HOST_WORDS_BIGENDIAN - uint64_t t; - t =3D q[0], q[0] =3D q[1], q[1] =3D t; -#endif - } - } - - reg.addr =3D (uintptr_t)(&fpr); - reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpsr); - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_arch_get_fpsimd(cs); if (ret) { return ret; } - vfp_set_fpsr(env, fpr); - - reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpcr); - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); - if (ret) { - return ret; - } - vfp_set_fpcr(env, fpr); =20 ret =3D kvm_get_vcpu_events(cpu); if (ret) { --=20 2.20.1