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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 4sm8705796wro.78.2019.08.16.06.17.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2019 06:17:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0ZnJsA94N8X7Cu7kfm4dOD2XBmDpwblF2KvIbDAt0vg=; b=TBQBwkWyuT6Stlizt1gHqQss/m5pVzDpeiWCTYtt/+L479Z1DkG+SdwtCM/DGxmg2Z vHTAuSYhijfBwHtcPEGqk2a6t3biEGyw8sjfPXXduoxB1GdldBAOdEtClXRdECr42cEH QQNCjxITB5r6ohTAWkW8lCQh+UZR0QvvYExaxMb6BRYfsLTqLSkuTdKmbVzFxYWbBvRG 957ggFtXni9KfqTiq3MjRrZiIE0XRY9BxKe87nndLOo7jGjfTV1u61CrqECd6YtY6Fzq wWCJlJIPw4/V6Gxm9gj+gS1laY2jHlIyshHLFtdLjW/+Vvlbj00t/fXJMsgC5OeCL5Ip 4BaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0ZnJsA94N8X7Cu7kfm4dOD2XBmDpwblF2KvIbDAt0vg=; b=JUHMarBuAiRmKMqrPzAs2OucAxhKTHHwmKKmo9pWzi5Uw8Vz3l8vzaK+7slaTWv3ip BJjrxitGTtU+Pz3vp+CX9YwGCfxv2X3/Ob46GbM5FbLoYHHszMAta0kmDNNdncpa7Al7 uEgz84+Xt8Il33inrov8yt2PRIadWie6yQpv1VbH57DxGvYN7L7FhnNgz4ILXp9flO/v strMFb53FvgRMldaWw5UvTSFUZPn7j2p7Jb0knyv7AvBIw6eNb0EWkCe5kwSZ3S6Wv6+ +/gJBZ+DIiUrYy7eQUtE0H34dZAOm3cTEcTj/VmKT0VVRscESPdy1YqOgJiDuDk0bqsC clUA== X-Gm-Message-State: APjAAAV7980IWsQGhn89NQBygFExozNnNmsUvYq8Xuin7+r4WibJc0QU 7pM+dDWOKMGFwbSi5AyYRZ2ZbKEArU/0hA== X-Google-Smtp-Source: APXvYqyKqvPa1VJSPpgsSl6OFFleDEiFJGFezepRpT1QF7So9mhrR6JM0ElSwdmZa0+7aUQ1YV8W1Q== X-Received: by 2002:a5d:518d:: with SMTP id k13mr11384527wrv.349.1565961442809; Fri, 16 Aug 2019 06:17:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 16 Aug 2019 14:16:51 +0100 Message-Id: <20190816131719.28244-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190816131719.28244-1-peter.maydell@linaro.org> References: <20190816131719.28244-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 01/29] target/arm: generate a custom MIDR for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Alex Benn=C3=A9e While most features are now detected by probing the ID_* registers kernels can (and do) use MIDR_EL1 for working out of they have to apply errata. This can trip up warnings in the kernel as it tries to work out if it should apply workarounds to features that don't actually exist in the reported CPU type. Avoid this problem by synthesising our own MIDR value. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190726113950.7499-1-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 6 ++++++ target/arm/cpu64.c | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 94c990cddbd..67f2af0e169 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1611,6 +1611,12 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1) /* * System register ID fields. */ +FIELD(MIDR_EL1, REVISION, 0, 4) +FIELD(MIDR_EL1, PARTNUM, 4, 12) +FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) +FIELD(MIDR_EL1, VARIANT, 20, 4) +FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) + FIELD(ID_ISAR0, SWAP, 0, 4) FIELD(ID_ISAR0, BITCOUNT, 4, 4) FIELD(ID_ISAR0, BITFIELD, 8, 4) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1901997a064..ee55237a9b2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -296,6 +296,25 @@ static void aarch64_max_initfn(Object *obj) uint32_t u; aarch64_a57_initfn(obj); =20 + /* + * Reset MIDR so the guest doesn't mistake our 'max' CPU type for = a real + * one and try to apply errata workarounds or use impdef features = we + * don't provide. + * An IMPLEMENTER field of 0 means "reserved for software use"; + * ARCHITECTURE must be 0xf indicating "v7 or later, check ID regi= sters + * to see which features are present"; + * the VARIANT, PARTNUM and REVISION fields are all implementation + * defined and we choose to define PARTNUM just in case guest + * code needs to distinguish this QEMU CPU from other software + * implementations, though this shouldn't be needed. + */ + t =3D FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); + t =3D FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); + t =3D FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); + t =3D FIELD_DP64(t, MIDR_EL1, VARIANT, 0); + t =3D FIELD_DP64(t, MIDR_EL1, REVISION, 0); + cpu->midr =3D t; + t =3D cpu->isar.id_aa64isar0; t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); --=20 2.20.1