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X-Received-From: 2607:f8b0:4864:20::b41 Subject: [Qemu-devel] [RFC PATCH v3 32/46] target/i386: introduce gvec-based code generator macros X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Code generators defined using these macros rely on a gvec operation (i.e. tcg_gen_gvec_*). Signed-off-by: Jan Bobek --- target/i386/translate.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index b28d651b82..75652afb45 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -23,6 +23,7 @@ #include "disas/disas.h" #include "exec/exec-all.h" #include "tcg-op.h" +#include "tcg-op-gvec.h" #include "exec/cpu_ldst.h" #include "exec/translator.h" =20 @@ -5351,6 +5352,18 @@ INSNOP_LDST(xmm_t0, Mhq) tcg_temp_free_i32(arg4_r32); \ } =20 +#define DEF_GEN_INSN2_GVEC(mnem, gvec, opT1, opT2, vece, oprsz, maxsz) \ + GEN_INSN2(mnem, opT1, opT2) \ + { \ + tcg_gen_gvec_ ## gvec(vece, arg1, arg2, oprsz, maxsz); \ + } + +#define DEF_GEN_INSN3_GVEC(mnem, gvec, opT1, opT2, opT3, vece, oprsz, maxs= z) \ + GEN_INSN3(mnem, opT1, opT2, opT3) \ + { \ + tcg_gen_gvec_ ## gvec(vece, arg1, arg2, arg3, oprsz, maxsz); \ + } + static void gen_sse_ng(CPUX86State *env, DisasContext *s, int b) { enum { --=20 2.20.1