From nobody Sun Feb 8 21:52:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1565767553; cv=none; d=zoho.com; s=zohoarc; b=YLPBOVcjjR3Ifd3Hoyf7mVJk10L7uFkzLDOrdZFpIFHTgyeaYe7lte9rQ/1pru/n0c9gwkIweXAwJmPUBhTqBP9NeNNuCqi5f+5r4Mkik39ZSF+bfkDcs1SOqyqUDtX4C163pThBfSZM+MjWBNBVzHyyRVLFuZIIIxAtNC3Nj1Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565767553; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=NCC5+tj0S0YB8XSpJAk6XkBwokwEXJA9m0NLrklRvPg=; b=nYV9aavL46qGnKMY7z2inVTrXO5g9kdPqwJu4N1zjtIFlTG86qRa/oyCkFrFwm1n5ztFArAl2tdsCJem/gxmROR601FMAfhJe7gqCRgrCyQF2VimG8TXhx0pZXFouzKNU/tQRW3c+Hl3sdtD1HLvd70145OLQBtknuA2jTY2he0= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565767553533100.68076729200504; Wed, 14 Aug 2019 00:25:53 -0700 (PDT) Received: from localhost ([::1]:57890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hxnfG-0003ba-U5 for importer@patchew.org; Wed, 14 Aug 2019 03:25:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60505) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hxndg-00029Z-Vk for qemu-devel@nongnu.org; Wed, 14 Aug 2019 03:24:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hxndf-0004eR-0i for qemu-devel@nongnu.org; Wed, 14 Aug 2019 03:24:08 -0400 Received: from mx1.redhat.com ([209.132.183.28]:55866) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hxnde-0004dg-S6; Wed, 14 Aug 2019 03:24:06 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 471CC4E919; Wed, 14 Aug 2019 07:24:05 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-4.ams2.redhat.com [10.36.117.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6FB5660852; Wed, 14 Aug 2019 07:24:03 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Wed, 14 Aug 2019 09:23:50 +0200 Message-Id: <20190814072355.15333-2-david@redhat.com> In-Reply-To: <20190814072355.15333-1-david@redhat.com> References: <20190814072355.15333-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Wed, 14 Aug 2019 07:24:05 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v2 1/6] s390x/mmu: ASC selection in s390_cpu_get_phys_page_debug() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Let's select the ASC before calling the function. This is a prepararion to remove the ASC magic depending on the access mode from mmu_translate. There is currently no way to distinguish if we have code or data access. For now, we were using code access, because especially when debugging with the gdbstub, we want to read and disassemble what we single-step. Reviewed-by: Thomas Huth Reviewed-by: Cornelia Huck Signed-off-by: David Hildenbrand --- target/s390x/helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/s390x/helper.c b/target/s390x/helper.c index 13ae9909ad..c5fb8966b6 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -58,6 +58,11 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr = vaddr) vaddr &=3D 0x7fffffff; } =20 + /* We want to read the code (e.g., see what we are single-stepping).*/ + if (asc !=3D PSW_ASC_HOME) { + asc =3D PSW_ASC_PRIMARY; + } + if (mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, fals= e)) { return -1; } --=20 2.21.0 From nobody Sun Feb 8 21:52:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1565767551; cv=none; d=zoho.com; s=zohoarc; b=UaQVSfoXRrL4PCA/Z5Oci8rXbmm0WjnfK/UCgNVa6quHC6/RF6W2KeI4jV3Clsg3d6oY5eFRvYqYUH+a2qKC2LBcciM2QxnCuWXbUDWpRM5s5ZtEsdQEIAdQNSVFJIYs++Xr8TfpbzhtqBVzjpeOgXXr/BR65yp8g1/QJdU35/g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565767551; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=fX8s4qPUQfmBv2lpe6fuutsIkQ0Cer1U9F33WeLFKUM=; b=UMLZLDK6+Evt8gxjF/4V2BnmzH9CbBRTMk9QGv39RHdVkcBlHSmLJD/+acohvJQp9JJ7soCxL0AvdlKX8ztLctsXbRxS1dAjdqzB/v284OZbFjD9LkA+1wxedk5nmLC0B14EoJ2LBtxRxmy9RZXxsmkRo1EtkdHAAO98PQ2rc7g= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15657675512761009.8473839515245; Wed, 14 Aug 2019 00:25:51 -0700 (PDT) Received: from localhost ([::1]:57892 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hxnfK-0003iL-3g for importer@patchew.org; Wed, 14 Aug 2019 03:25:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60543) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hxndk-0002BK-58 for qemu-devel@nongnu.org; Wed, 14 Aug 2019 03:24:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hxndi-0004gK-Vh for qemu-devel@nongnu.org; Wed, 14 Aug 2019 03:24:12 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46866) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hxndg-0004et-Tj; Wed, 14 Aug 2019 03:24:09 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 60F957CB80; Wed, 14 Aug 2019 07:24:07 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-4.ams2.redhat.com [10.36.117.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8FBDE808DF; Wed, 14 Aug 2019 07:24:05 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Wed, 14 Aug 2019 09:23:51 +0200 Message-Id: <20190814072355.15333-3-david@redhat.com> In-Reply-To: <20190814072355.15333-1-david@redhat.com> References: <20190814072355.15333-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Wed, 14 Aug 2019 07:24:07 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v2 2/6] s390x/tcg: Rework MMU selection for instruction fetches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Instructions are always fetched from primary address space, except when in home address mode. Perform the selection directly in cpu_mmu_index(). get_mem_index() is only used to perform data access, instructions are fetched via cpu_lduw_code(), which translates to cpu_mmu_index(env, true). We don't care about restricting the access permissions of the TLB entries anymore, as we no longer enter PRIMARY entries into the SECONDARY MMU. Cleanup related code a bit. Signed-off-by: David Hildenbrand Reviewed-by: Thomas Huth --- target/s390x/cpu.h | 7 +++++++ target/s390x/mmu_helper.c | 38 +++++++++++++++----------------------- 2 files changed, 22 insertions(+), 23 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index a606547b4d..c34992bb2e 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -332,6 +332,13 @@ static inline int cpu_mmu_index(CPUS390XState *env, bo= ol ifetch) return MMU_REAL_IDX; } =20 + if (ifetch) { + if ((env->psw.mask & PSW_MASK_ASC) =3D=3D PSW_ASC_HOME) { + return MMU_HOME_IDX; + } + return MMU_PRIMARY_IDX; + } + switch (env->psw.mask & PSW_MASK_ASC) { case PSW_ASC_PRIMARY: return MMU_PRIMARY_IDX; diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 6e9c4d6151..c34e8d2021 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -349,8 +349,9 @@ int mmu_translate(CPUS390XState *env, target_ulong vadd= r, int rw, uint64_t asc, { static S390SKeysState *ss; static S390SKeysClass *skeyclass; - int r =3D -1; + uint64_t asce; uint8_t key; + int r; =20 if (unlikely(!ss)) { ss =3D s390_get_skeys_device(); @@ -380,36 +381,21 @@ int mmu_translate(CPUS390XState *env, target_ulong va= ddr, int rw, uint64_t asc, =20 if (!(env->psw.mask & PSW_MASK_DAT)) { *raddr =3D vaddr; - r =3D 0; - goto out; + goto nodat; } =20 switch (asc) { case PSW_ASC_PRIMARY: PTE_DPRINTF("%s: asc=3Dprimary\n", __func__); - r =3D mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, fl= ags, - rw, exc); + asce =3D env->cregs[1]; break; case PSW_ASC_HOME: PTE_DPRINTF("%s: asc=3Dhome\n", __func__); - r =3D mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, f= lags, - rw, exc); + asce =3D env->cregs[13]; break; case PSW_ASC_SECONDARY: PTE_DPRINTF("%s: asc=3Dsecondary\n", __func__); - /* - * Instruction: Primary - * Data: Secondary - */ - if (rw =3D=3D MMU_INST_FETCH) { - r =3D mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cre= gs[1], - raddr, flags, rw, exc); - *flags &=3D ~(PAGE_READ | PAGE_WRITE); - } else { - r =3D mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->c= regs[7], - raddr, flags, rw, exc); - *flags &=3D ~(PAGE_EXEC); - } + asce =3D env->cregs[7]; break; case PSW_ASC_ACCREG: default: @@ -417,11 +403,17 @@ int mmu_translate(CPUS390XState *env, target_ulong va= ddr, int rw, uint64_t asc, break; } =20 - out: + /* perform the DAT translation */ + r =3D mmu_translate_asce(env, vaddr, asc, asce, raddr, flags, rw, exc); + if (r) { + return r; + } + +nodat: /* Convert real address -> absolute address */ *raddr =3D mmu_real2abs(env, *raddr); =20 - if (r =3D=3D 0 && *raddr < ram_size) { + if (*raddr < ram_size) { if (skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) { trace_get_skeys_nonzero(r); return 0; @@ -441,7 +433,7 @@ int mmu_translate(CPUS390XState *env, target_ulong vadd= r, int rw, uint64_t asc, } } =20 - return r; + return 0; } =20 /** --=20 2.21.0 From nobody Sun Feb 8 21:52:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565767642435295.19048722607045; Wed, 14 Aug 2019 00:27:22 -0700 (PDT) Received: from localhost ([::1]:57914 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hxngi-0005sc-5y for importer@patchew.org; Wed, 14 Aug 2019 03:27:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60544) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hxndk-0002BU-7N for qemu-devel@nongnu.org; Wed, 14 Aug 2019 03:24:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hxndj-0004gg-5D for qemu-devel@nongnu.org; Wed, 14 Aug 2019 03:24:12 -0400 Received: from mx1.redhat.com ([209.132.183.28]:56966) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hxndi-0004fl-W4; Wed, 14 Aug 2019 03:24:11 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7A462C0035AC; Wed, 14 Aug 2019 07:24:09 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-4.ams2.redhat.com [10.36.117.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id A9EA560852; Wed, 14 Aug 2019 07:24:07 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Wed, 14 Aug 2019 09:23:52 +0200 Message-Id: <20190814072355.15333-4-david@redhat.com> In-Reply-To: <20190814072355.15333-1-david@redhat.com> References: <20190814072355.15333-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Wed, 14 Aug 2019 07:24:09 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v2 3/6] s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Whenever we modify a storage key, we shuld flush the TLBs of all CPUs, so the MMU fault handling code can properly consider the changed storage key (to e.g., properly set the reference and change bit on the next accesses). These functions are barely used in modern Linux guests, so the performance implications are neglectable for now. This is a preparation for better reference and change bit handling for TCG, which will require more MMU changes. Reviewed-by: Cornelia Huck Signed-off-by: David Hildenbrand --- target/s390x/mem_helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 29d9eaa5b7..ed54265e03 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1815,6 +1815,8 @@ void HELPER(sske)(CPUS390XState *env, uint64_t r1, ui= nt64_t r2) =20 key =3D (uint8_t) r1; skeyclass->set_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key); + /* TODO: Flush only entries with this target address */ + tlb_flush_all_cpus_synced(env_cpu(env)); } =20 /* reset reference bit extended */ @@ -1843,6 +1845,8 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) if (skeyclass->set_skeys(ss, r2 / TARGET_PAGE_SIZE, 1, &key)) { return 0; } + /* TODO: Flush only entries with this target address */ + tlb_flush_all_cpus_synced(env_cpu(env)); =20 /* * cc --=20 2.21.0 From nobody Sun Feb 8 21:52:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 14 Aug 2019 03:24:12 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 978FB30860DC; Wed, 14 Aug 2019 07:24:11 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-4.ams2.redhat.com [10.36.117.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id C36FC60852; Wed, 14 Aug 2019 07:24:09 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Wed, 14 Aug 2019 09:23:53 +0200 Message-Id: <20190814072355.15333-5-david@redhat.com> In-Reply-To: <20190814072355.15333-1-david@redhat.com> References: <20190814072355.15333-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.44]); Wed, 14 Aug 2019 07:24:11 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v2 4/6] s390x/mmu: Trace the right value if setting/getting the storage key fails X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We want to trace the actual return value, not "0". Reviewed-by: Cornelia Huck Signed-off-by: David Hildenbrand Reviewed-by: Thomas Huth --- target/s390x/mmu_helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index c34e8d2021..d22c6b9c81 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -414,7 +414,8 @@ nodat: *raddr =3D mmu_real2abs(env, *raddr); =20 if (*raddr < ram_size) { - if (skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) { + r =3D skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key); + if (r) { trace_get_skeys_nonzero(r); return 0; } @@ -427,7 +428,8 @@ nodat: key |=3D SK_C; } =20 - if (skeyclass->set_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) { + r =3D skeyclass->set_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key); + if (r) { trace_set_skeys_nonzero(r); return 0; } --=20 2.21.0 From nobody Sun Feb 8 21:52:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 14 Aug 2019 03:24:14 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B08CF3082E8E; Wed, 14 Aug 2019 07:24:13 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-4.ams2.redhat.com [10.36.117.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id DF26460852; Wed, 14 Aug 2019 07:24:11 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Wed, 14 Aug 2019 09:23:54 +0200 Message-Id: <20190814072355.15333-6-david@redhat.com> In-Reply-To: <20190814072355.15333-1-david@redhat.com> References: <20190814072355.15333-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.46]); Wed, 14 Aug 2019 07:24:13 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v2 5/6] s390x/mmu: Better storage key reference and change bit handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Any access sets the reference bit. In case we have a read-fault, we should not allow writes to the TLB entry if the change bit was not already set. This is a preparation for proper storage-key reference/change bit handling in TCG and a fix for KVM whereby read accesses would set the change bit (old KVM versions without the ioctl to carry out the translation). Reviewed-by: Cornelia Huck Signed-off-by: David Hildenbrand --- target/s390x/mmu_helper.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index d22c6b9c81..6cc81a29b6 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -420,14 +420,28 @@ nodat: return 0; } =20 - if (*flags & PAGE_READ) { - key |=3D SK_R; - } - - if (*flags & PAGE_WRITE) { + switch (rw) { + case MMU_DATA_LOAD: + case MMU_INST_FETCH: + /* + * The TLB entry has to remain write-protected on read-faults = if + * the storage key does not indicate a change already. Otherwi= se + * we might miss setting the change bit on write accesses. + */ + if (!(key & SK_C)) { + *flags &=3D ~PAGE_WRITE; + } + break; + case MMU_DATA_STORE: key |=3D SK_C; + break; + default: + g_assert_not_reached(); } =20 + /* Any store/fetch sets the reference bit */ + key |=3D SK_R; + r =3D skeyclass->set_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key); if (r) { trace_set_skeys_nonzero(r); --=20 2.21.0 From nobody Sun Feb 8 21:52:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1565767803; cv=none; d=zoho.com; s=zohoarc; b=CEEnkB3611zOontLBz9AZ47jG92GyfaWq5NlUP6cmq/CCyfWDby2kjSRLfIO83Ckds+Ii9IqwUrRvq5JAViOvMuMF5bXORTQLVKLapACUVIxlEbWRKVpHwVPActvat6S6WGKGph2b1zWSRoJx3f9jryrXILnq8PThST0b3hUUPs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565767803; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=kqAvrkqcYvorT1J0MQIrNfvXyOlUQGazHITXayf5WZA=; b=S4xwFWJjNvkEyDOwJDyPrHJH3XukdMqXEVqKxYnSvqH8bXRmB42g6jehQh0jHS3EKEE2M5rdLEaA5X/sKmiFzPBpwFKcEDpLfwyExBuZwR/fsjk1c3irG+H+HlXzXdR4nnz6K+l67PgHR/viDk7cdZvZgD+NrFJrYYBZDy7jqW8= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565767803397271.4199639733997; Wed, 14 Aug 2019 00:30:03 -0700 (PDT) Received: from localhost ([::1]:57934 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hxnjO-0008DJ-FI for importer@patchew.org; Wed, 14 Aug 2019 03:30:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60637) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hxndq-0002H4-CL for qemu-devel@nongnu.org; Wed, 14 Aug 2019 03:24:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hxndo-0004jx-ON for qemu-devel@nongnu.org; Wed, 14 Aug 2019 03:24:18 -0400 Received: from mx1.redhat.com ([209.132.183.28]:38832) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hxndo-0004jb-Gv; Wed, 14 Aug 2019 03:24:16 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id C82093086211; Wed, 14 Aug 2019 07:24:15 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-4.ams2.redhat.com [10.36.117.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 04E0860852; Wed, 14 Aug 2019 07:24:13 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Wed, 14 Aug 2019 09:23:55 +0200 Message-Id: <20190814072355.15333-7-david@redhat.com> In-Reply-To: <20190814072355.15333-1-david@redhat.com> References: <20190814072355.15333-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.42]); Wed, 14 Aug 2019 07:24:15 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v2 6/6] s390x/mmu: Factor out storage key handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Factor it out, add a comment how it all works, and also use it in the REAL MMU. Reviewed-by: Cornelia Huck Signed-off-by: David Hildenbrand Reviewed-by: Thomas Huth --- target/s390x/mmu_helper.c | 113 +++++++++++++++++++++++--------------- 1 file changed, 69 insertions(+), 44 deletions(-) diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 6cc81a29b6..e125837d68 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -334,6 +334,73 @@ static int mmu_translate_asce(CPUS390XState *env, targ= et_ulong vaddr, return r; } =20 +static void mmu_handle_skey(target_ulong addr, int rw, int *flags) +{ + static S390SKeysClass *skeyclass; + static S390SKeysState *ss; + uint8_t key; + int rc; + + if (unlikely(!ss)) { + ss =3D s390_get_skeys_device(); + skeyclass =3D S390_SKEYS_GET_CLASS(ss); + } + + /* + * Whenever we create a new TLB entry, we set the storage key reference + * bit. In case we allow write accesses, we set the storage key change + * bit. Whenever the guest changes the storage key, we have to flush t= he + * TLBs of all CPUs (the whole TLB or all affected entries), so that t= he + * next reference/change will result in an MMU fault and make us prope= rly + * update the storage key here. + * + * Note 1: "record of references ... is not necessarily accurate", + * "change bit may be set in case no storing has occurred". + * -> We can set reference/change bits even on exceptions. + * Note 2: certain accesses seem to ignore storage keys. For example, + * DAT translation does not set reference bits for table acces= ses. + * + * TODO: key-controlled protection. Only CPU accesses make use of the + * PSW key. CSS accesses are different - we have to pass in the = key. + * + * TODO: we have races between getting and setting the key. + */ + if (addr < ram_size) { + rc =3D skeyclass->get_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key); + if (rc) { + trace_get_skeys_nonzero(rc); + return; + } + + switch (rw) { + case MMU_DATA_LOAD: + case MMU_INST_FETCH: + /* + * The TLB entry has to remain write-protected on read-faults = if + * the storage key does not indicate a change already. Otherwi= se + * we might miss setting the change bit on write accesses. + */ + if (!(key & SK_C)) { + *flags &=3D ~PAGE_WRITE; + } + break; + case MMU_DATA_STORE: + key |=3D SK_C; + break; + default: + g_assert_not_reached(); + } + + /* Any store/fetch sets the reference bit */ + key |=3D SK_R; + + rc =3D skeyclass->set_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key); + if (rc) { + trace_set_skeys_nonzero(rc); + } + } +} + /** * Translate a virtual (logical) address into a physical (absolute) addres= s. * @param vaddr the virtual address @@ -347,16 +414,9 @@ static int mmu_translate_asce(CPUS390XState *env, targ= et_ulong vaddr, int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t= asc, target_ulong *raddr, int *flags, bool exc) { - static S390SKeysState *ss; - static S390SKeysClass *skeyclass; uint64_t asce; - uint8_t key; int r; =20 - if (unlikely(!ss)) { - ss =3D s390_get_skeys_device(); - skeyclass =3D S390_SKEYS_GET_CLASS(ss); - } =20 *flags =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, a= sc)) { @@ -413,42 +473,7 @@ nodat: /* Convert real address -> absolute address */ *raddr =3D mmu_real2abs(env, *raddr); =20 - if (*raddr < ram_size) { - r =3D skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key); - if (r) { - trace_get_skeys_nonzero(r); - return 0; - } - - switch (rw) { - case MMU_DATA_LOAD: - case MMU_INST_FETCH: - /* - * The TLB entry has to remain write-protected on read-faults = if - * the storage key does not indicate a change already. Otherwi= se - * we might miss setting the change bit on write accesses. - */ - if (!(key & SK_C)) { - *flags &=3D ~PAGE_WRITE; - } - break; - case MMU_DATA_STORE: - key |=3D SK_C; - break; - default: - g_assert_not_reached(); - } - - /* Any store/fetch sets the reference bit */ - key |=3D SK_R; - - r =3D skeyclass->set_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key); - if (r) { - trace_set_skeys_nonzero(r); - return 0; - } - } - + mmu_handle_skey(*raddr, rw, flags); return 0; } =20 @@ -566,6 +591,6 @@ int mmu_translate_real(CPUS390XState *env, target_ulong= raddr, int rw, =20 *addr =3D mmu_real2abs(env, raddr & TARGET_PAGE_MASK); =20 - /* TODO: storage key handling */ + mmu_handle_skey(*addr, rw, flags); return 0; } --=20 2.21.0