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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id l189sm119049433pfl.7.2019.08.09.10.11.56 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 09 Aug 2019 10:11:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=ytkVX0l93V8o0cYS4Oq6t62B9ZsJBOcYFtRg7HNNvw8=; b=OAh8az9D3ZF272uDEsz4bf6PbWDxKUa72Iouu7bUj/0XwOG8R+ydJ66Qp1idhNsXWk VSkNV7s+SVOGcxCDS6IaWeqPk0pvrP95MqKBGM2TkY/x3nfbgIds97F5yNTuhgdqvFf/ iFpChpPIBb29wnBb27DeAe7XnBTuijCLhKScout51dRJnNNT5uSbHHlO6B5dt+W6Cq+/ wUln9RomXdU52Edlrc7MzgllELLd7LprsH/Eps/gjn7oPwA1iwku1dGgGO2O4Re+K2CO PnZ0NfdbGMM9t94dS5dz0deW6v0S6O4Zhbiaojy4E2WkGcW4c2cYRTkO/4DQT7j1sAZL oQaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ytkVX0l93V8o0cYS4Oq6t62B9ZsJBOcYFtRg7HNNvw8=; b=dSWTj1pgSwXcH+hTj6PItGuv613aKIpbKLIiCh8jwQOYPL81G2HCTSzzOue26YJ0rI 5BaSqKpvKRb/aQWWZVcWcnMcU/akwNiQwPAbtUNchKeP9Nw/2ANrMNq10jHzvO7T8/u9 umf9Uf88pLITrVMvQX+bTe9vKNA17K0d8hAkD33MOymbTe+eFq2dr1NAg49hetCopg/p wzgR0Hn3023JLzX57mxaPxt1c3mwMfEG+JmDydeeuNXS1w/qyr3SzPbycj3Mof3CMtc5 oH7V7KcCXTqIQ060cMU3mK6bb2sGQ/lhxNeLggB2he+Z+11bfAXSuMt6y+plcb4MCcQ/ qp2w== X-Gm-Message-State: APjAAAX9XxxDn/TRqvVUmpjFKiPpBmD8MBI7EBC3SFZYlMkcsiaWtQBy 9g2kbN+erAByxRd3cFGNUtwOfxNGQNM= X-Google-Smtp-Source: APXvYqySxdZhIkOeZjsh+xEfUzMrOT9e9uqx6jgRH9jodXLonQ9Ds0TYzh8cPkIhj/P+RcDQ+1szew== X-Received: by 2002:a62:874d:: with SMTP id i74mr22155960pfe.94.1565370718261; Fri, 09 Aug 2019 10:11:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 9 Aug 2019 10:11:56 -0700 Message-Id: <20190809171156.3476-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH] linux-user: Add AT_HWCAP2 for aarch64-linux-user X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the HWCAP2_* bits from kernel version v5.3-rc3. Enable the bits corresponding to ARMv8.5-CondM and ARMv8.5-FRINT. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/elfload.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) --- The HWCAP2_FLAGM2 and HWCAP2_FRINT bits came in during the=20 last merge window and will be in the upcoming v5.3 release. We don't yet implement any of the other extensions that make up the rest of the HWCAP2 bits. r~ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index bd43c4817d..4fd2f46f18 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -606,9 +606,23 @@ enum { ARM_HWCAP_A64_SB =3D 1 << 29, ARM_HWCAP_A64_PACA =3D 1 << 30, ARM_HWCAP_A64_PACG =3D 1UL << 31, + + ARM_HWCAP2_A64_DCPODP =3D 1 << 0, + ARM_HWCAP2_A64_SVE2 =3D 1 << 1, + ARM_HWCAP2_A64_SVEAES =3D 1 << 2, + ARM_HWCAP2_A64_SVEPMULL =3D 1 << 3, + ARM_HWCAP2_A64_SVEBITPERM =3D 1 << 4, + ARM_HWCAP2_A64_SVESHA3 =3D 1 << 5, + ARM_HWCAP2_A64_SVESM4 =3D 1 << 6, + ARM_HWCAP2_A64_FLAGM2 =3D 1 << 7, + ARM_HWCAP2_A64_FRINT =3D 1 << 8, }; =20 -#define ELF_HWCAP get_elf_hwcap() +#define ELF_HWCAP get_elf_hwcap() +#define ELF_HWCAP2 get_elf_hwcap2() + +#define GET_FEATURE_ID(feat, hwcap) \ + do { if (cpu_isar_feature(feat, cpu)) { hwcaps |=3D hwcap; } } while (= 0) =20 static uint32_t get_elf_hwcap(void) { @@ -620,8 +634,6 @@ static uint32_t get_elf_hwcap(void) hwcaps |=3D ARM_HWCAP_A64_CPUID; =20 /* probe for the extra features */ -#define GET_FEATURE_ID(feat, hwcap) \ - do { if (cpu_isar_feature(feat, cpu)) { hwcaps |=3D hwcap; } } while (= 0) =20 GET_FEATURE_ID(aa64_aes, ARM_HWCAP_A64_AES); GET_FEATURE_ID(aa64_pmull, ARM_HWCAP_A64_PMULL); @@ -644,11 +656,22 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); =20 -#undef GET_FEATURE_ID + return hwcaps; +} + +static uint32_t get_elf_hwcap2(void) +{ + ARMCPU *cpu =3D ARM_CPU(thread_cpu); + uint32_t hwcaps =3D 0; + + GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); + GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); =20 return hwcaps; } =20 +#undef GET_FEATURE_ID + #endif /* not TARGET_AARCH64 */ #endif /* TARGET_ARM */ =20 --=20 2.17.1