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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id t9sm24347921pji.18.2019.08.06.21.53.52 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 06 Aug 2019 21:53:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wDovHb8+ljpi4sI8lS1gqNoa7uBRHGNbFn35mP5+duU=; b=OqT2BEgIEQuSd8ShFb3RaeD82r3Bh/yyMtSbdIegm7GtN/0mckol0Dk8e4CEQ9atBS 9r584wbilgkg7XYqXAxTZ/Uxjvr74kX+H+fcN5OLDoQrHPej+ca94YDPcy9ho4UFNHuq ZdnJQSASU/HJCbEY0RmnonneN3CaLWvi4c5YJMIdM3skY9kjrWlhOkzPq0h4FNTPtpF+ NDGqmRGJC7P2Dbijt1aF5MRIQ7tXbvmWZVm5abW+IuVdH2qccZW43718n7Zu5MWaNhyt FDDbnnBNlT3Asfqqscp+nh/92mCtHE19TCW8vUIY4ssvYsDsTzK22aIE+Zk6/NvcrpXA fBLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wDovHb8+ljpi4sI8lS1gqNoa7uBRHGNbFn35mP5+duU=; b=FypQEuLpaaC74GX2Y3RjfuMPciLQ7KD6xF6ci6I4QtB+z8/b57lQyWd230LtiDoyFf L+l4ZX82zLs+8HE1BNjysZJ/eskHhdMdq/1YTECuNNfWSja/7wEI3+dc9Z3vDTr9TfR8 yz6sqHg2BCfV6oNUUZr0oLdKjgHuBDNVLJ/7IubhLZQFvASjIRwBLd+A5/bVrzD+Xa+Y H/qWUrjjWj+7aIRLkJLAuTZH7dPg1OTVakvVGIWA0ZKKuTMecdyeMGgNQRfc6skCo/od XZ+rLURGl7GRczE3vJmLFL17a1FEtv5VxTM2OjeP+6ZNf6zvkQ+N86JKxIFWbafwKCc9 X0+w== X-Gm-Message-State: APjAAAUDoc9c4fn+4coI2xjPyVgXELjxBZPBwHtW5s7MESGLLl2nCFxR jsqCSI4RnM7DwSW1NP7ke1iqu/9ZGh0= X-Google-Smtp-Source: APXvYqwF4b+4wAIQm78Yxq8+GdyAEojxYNT4zArU45A676At5fa82rQ9GY2S0xP5zRaYOJvVuyikrg== X-Received: by 2002:a17:90a:2385:: with SMTP id g5mr6788791pje.12.1565153633487; Tue, 06 Aug 2019 21:53:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 6 Aug 2019 21:53:32 -0700 Message-Id: <20190807045335.1361-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190807045335.1361-1-richard.henderson@linaro.org> References: <20190807045335.1361-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 08/11] target/arm: Replace offset with pc in gen_exception_internal_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The offset is variable depending on the instruction set. Passing in the actual value is clearer in intent. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 8 ++++---- target/arm/translate.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 92aa6db12e..c8504d221a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -266,9 +266,9 @@ static void gen_exception(int excp, uint32_t syndrome, = uint32_t target_el) tcg_temp_free_i32(tcg_excp); } =20 -static void gen_exception_internal_insn(DisasContext *s, int offset, int e= xcp) +static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int = excp) { - gen_a64_set_pc_im(s->base.pc_next - offset); + gen_a64_set_pc_im(pc); gen_exception_internal(excp); s->base.is_jmp =3D DISAS_NORETURN; } @@ -1938,7 +1938,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) break; } #endif - gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); } else { unsupported_encoding(s, insn); } @@ -14234,7 +14234,7 @@ static bool aarch64_tr_breakpoint_check(DisasContex= tBase *dcbase, CPUState *cpu, /* End the TB early; it likely won't be executed */ dc->base.is_jmp =3D DISAS_TOO_MANY; } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we diff --git a/target/arm/translate.c b/target/arm/translate.c index 7a05ecae87..e6b18ecdaf 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1256,10 +1256,10 @@ static inline void gen_smc(DisasContext *s) s->base.is_jmp =3D DISAS_SMC; } =20 -static void gen_exception_internal_insn(DisasContext *s, int offset, int e= xcp) +static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int = excp) { gen_set_condexec(s); - gen_set_pc_im(s, s->base.pc_next - offset); + gen_set_pc_im(s, pc); gen_exception_internal(excp); s->base.is_jmp =3D DISAS_NORETURN; } @@ -1311,7 +1311,7 @@ static inline void gen_hlt(DisasContext *s, int imm) s->current_el !=3D 0 && #endif (imm =3D=3D (s->thumb ? 0x3c : 0xf000))) { - gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); return; } =20 @@ -11953,7 +11953,7 @@ static bool arm_tr_breakpoint_check(DisasContextBas= e *dcbase, CPUState *cpu, /* End the TB early; it's likely not going to be executed */ dc->base.is_jmp =3D DISAS_TOO_MANY; } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we --=20 2.17.1