From nobody Fri Oct 3 20:22:40 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565117941; cv=none; d=zoho.com; s=zohoarc; b=BN0VVN/mEDdjkqe6kX9Mm4ZeF9REFCyEu03rko00AOkgea1RYtFrTGi7w2TYpAxdurl7xd1F10RRhdxu2uUCbX1pBxWzzma2Ad0vAyFCInD0LlF2tXr1/cyTv+2KGEY19av9EuBMiN6hdMfqbzouJFI3R/yUPphjQnaM/ObxIog= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565117941; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=bKAnCCEs7kx+/jXzMFHF48goTlQl8c6tpxmAZ2MwweY=; b=hdwkVu9ua+ZoQwlxL3scT36W0tdR4zUmO3eORr0qL1YNrluVW1OEcTI47Jj71x5Y3wFJia360a1mHjOXxjqzPP8n1FrtMHWPRcDouH8xOhIBlBhPaSrUBfvyNCTO/dYNUSslYCxBqSS7yrWKnafVKYGu3KJdTkfe+fQkR0ele7E= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565117941140432.5116096466677; Tue, 6 Aug 2019 11:59:01 -0700 (PDT) Received: from localhost ([::1]:35704 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hv4fk-00011I-5N for importer@patchew.org; Tue, 06 Aug 2019 14:59:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41093) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hv4dx-0004OF-Vs for qemu-devel@nongnu.org; Tue, 06 Aug 2019 14:57:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hv4dw-00074A-Ei for qemu-devel@nongnu.org; Tue, 06 Aug 2019 14:57:09 -0400 Received: from mga14.intel.com ([192.55.52.115]:31802) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hv4dw-0006yc-6J for qemu-devel@nongnu.org; Tue, 06 Aug 2019 14:57:08 -0400 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Aug 2019 11:57:00 -0700 Received: from sjchrist-coffee.jf.intel.com ([10.54.74.41]) by orsmga003.jf.intel.com with ESMTP; 06 Aug 2019 11:56:59 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,353,1559545200"; d="scan'208";a="176715072" From: Sean Christopherson To: Eduardo Habkost , Igor Mammedov , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Cornelia Huck , Eric Blake , Markus Armbruster , Marcelo Tosatti Date: Tue, 6 Aug 2019 11:56:33 -0700 Message-Id: <20190806185649.2476-5-sean.j.christopherson@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190806185649.2476-1-sean.j.christopherson@intel.com> References: <20190806185649.2476-1-sean.j.christopherson@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.115 Subject: [Qemu-devel] [RFC PATCH 04/20] i386: Add primary SGX CPUID and MSR defines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Add CPUID defines for SGX and SGX Launch Control (LC), as well as defines for their associated FEATURE_CONTROL MSR bits. Define the Launch Enclave Public Key Hash MSRs (LE Hash MSRs), which exist when SGX LC is present (in CPUID), and are writable when SGX LC is enabled (in FEATURE_CONTROL). Signed-off-by: Sean Christopherson --- target/i386/cpu.c | 4 ++-- target/i386/cpu.h | 10 ++++++++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 19751e37a7..f529fb0dc8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1041,7 +1041,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { [FEAT_7_0_EBX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { - "fsgsbase", "tsc-adjust", NULL, "bmi1", + "fsgsbase", "tsc-adjust", "sgx", "bmi1", "hle", "avx2", NULL, "smep", "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL, @@ -1067,7 +1067,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { "la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL, NULL, "cldemote", NULL, "movdiri", - "movdir64b", NULL, NULL, NULL, + "movdir64b", NULL, "sgxlc", NULL, }, .cpuid =3D { .eax =3D 7, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8b3dc5533e..62adb2e0d0 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -350,9 +350,17 @@ typedef enum X86Seg { #define MSR_IA32_TSCDEADLINE 0x6e0 =20 #define FEATURE_CONTROL_LOCKED (1<<0) +#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) +#define FEATURE_CONTROL_SGX_LC (1<<17) +#define FEATURE_CONTROL_SGX (1<<18) #define FEATURE_CONTROL_LMCE (1<<20) =20 +#define MSR_IA32_SGXLEPUBKEYHASH0 0x8c +#define MSR_IA32_SGXLEPUBKEYHASH1 0x8d +#define MSR_IA32_SGXLEPUBKEYHASH2 0x8e +#define MSR_IA32_SGXLEPUBKEYHASH3 0x8f + #define MSR_P6_PERFCTR0 0xc1 =20 #define MSR_IA32_SMBASE 0x9e @@ -641,6 +649,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_SVM_PFTHRESHOLD (1U << 12) =20 #define CPUID_7_0_EBX_FSGSBASE (1U << 0) +#define CPUID_7_0_EBX_SGX (1U << 2) #define CPUID_7_0_EBX_BMI1 (1U << 3) #define CPUID_7_0_EBX_HLE (1U << 4) #define CPUID_7_0_EBX_AVX2 (1U << 5) @@ -684,6 +693,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ #define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */ #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */ +#define CPUID_7_0_ECX_SGX_LC (1U << 30) =20 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Ins= tructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulat= ion Single Precision */ --=20 2.22.0