From nobody Fri Oct 3 20:22:40 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565118000; cv=none; d=zoho.com; s=zohoarc; b=H3ddI+DL/eKd83Ep2DDtzgN1llExdcVgG94IPX+H55WFSc3BUzG8fTAsCgmjaTiKabYWPaXtB7WWskMGXxRvOyTNtQGBXIeuksgIbfH6Ia+LeTdzLy0CteWjAyZl6eLqzjw56H4O8p6H84QiglI2fb7LqSxRyWMAqSKhF8P0Z/w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565118000; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=LnGemadPn3ltsdIr4sHVT/v11LqgISaJoBbop6/SGz8=; b=jxFmtNvK25nu4GPitPTVg1tnHGvRk9UnikHn08o74ibQ4SHaQgG3ysQo3IoUCRnhbIjZESOlancfhDdxu10S+jLcwpsOQtEWjeFElHZ3Kx80zmkd8UsXCEouN164UM8qhw3AmN7/EUOGA/cKobVk18xiu43jZl7hfbRhUZv629Y= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565118000341651.9170651798735; Tue, 6 Aug 2019 12:00:00 -0700 (PDT) Received: from localhost ([::1]:35728 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hv4gh-0004Lq-8e for importer@patchew.org; Tue, 06 Aug 2019 14:59:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41185) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hv4dz-0004Ot-9y for qemu-devel@nongnu.org; Tue, 06 Aug 2019 14:57:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hv4dx-00076W-Oc for qemu-devel@nongnu.org; Tue, 06 Aug 2019 14:57:11 -0400 Received: from mga14.intel.com ([192.55.52.115]:31811) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hv4dx-00072G-FL for qemu-devel@nongnu.org; Tue, 06 Aug 2019 14:57:09 -0400 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Aug 2019 11:57:00 -0700 Received: from sjchrist-coffee.jf.intel.com ([10.54.74.41]) by orsmga003.jf.intel.com with ESMTP; 06 Aug 2019 11:57:00 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,353,1559545200"; d="scan'208";a="176715111" From: Sean Christopherson To: Eduardo Habkost , Igor Mammedov , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Cornelia Huck , Eric Blake , Markus Armbruster , Marcelo Tosatti Date: Tue, 6 Aug 2019 11:56:45 -0700 Message-Id: <20190806185649.2476-17-sean.j.christopherson@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190806185649.2476-1-sean.j.christopherson@intel.com> References: <20190806185649.2476-1-sean.j.christopherson@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.115 Subject: [Qemu-devel] [RFC PATCH 16/20] hw/i386/pc: Account for SGX EPC sections when calculating device memory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Add helpers to detect if SGX EPC exists above 4g, and if so, where SGX EPC above 4g ends. Use the helpers to adjust the device memory range if SGX EPC exists above 4g. Note that SGX EPC is currently hardcoded to reside above 4g. Signed-off-by: Sean Christopherson --- hw/i386/pc.c | 10 +++++++++- include/hw/i386/sgx-epc.h | 12 ++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 8c8b404799..614d464394 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1882,8 +1882,14 @@ void pc_memory_init(PCMachineState *pcms, exit(EXIT_FAILURE); } =20 + if (sgx_epc_above_4g(pcms->sgx_epc)) { + machine->device_memory->base =3D sgx_epc_above_4g_end(pcms->sg= x_epc); + } else { + machine->device_memory->base =3D + 0x100000000ULL + pcms->above_4g_mem_size; + } machine->device_memory->base =3D - ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB); + ROUND_UP(machine->device_memory->base, 1 * GiB); =20 if (pcmc->enforce_aligned_dimm) { /* size device region assuming 1G page max alignment per slot = */ @@ -1962,6 +1968,8 @@ uint64_t pc_pci_hole64_start(void) if (!pcmc->broken_reserved_end) { hole64_start +=3D memory_region_size(&ms->device_memory->mr); } + } else if (sgx_epc_above_4g(pcms->sgx_epc)) { + hole64_start =3D sgx_epc_above_4g_end(pcms->sgx_epc); } else { hole64_start =3D 0x100000000ULL + pcms->above_4g_mem_size; } diff --git a/include/hw/i386/sgx-epc.h b/include/hw/i386/sgx-epc.h index 91ed4773e3..136449cd80 100644 --- a/include/hw/i386/sgx-epc.h +++ b/include/hw/i386/sgx-epc.h @@ -60,4 +60,16 @@ extern int sgx_epc_enabled; void pc_machine_init_sgx_epc(PCMachineState *pcms); int sgx_epc_get_section(int section_nr, uint64_t *addr, uint64_t *size); =20 +static inline bool sgx_epc_above_4g(SGXEPCState *sgx_epc) +{ + return sgx_epc !=3D NULL; +} + +static inline uint64_t sgx_epc_above_4g_end(SGXEPCState *sgx_epc) +{ + assert(sgx_epc !=3D NULL && sgx_epc->base >=3D 0x100000000ULL); + + return sgx_epc->base + sgx_epc->size; +} + #endif --=20 2.22.0