From nobody Sun Apr 28 20:27:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1565019250; cv=none; d=zoho.com; s=zohoarc; b=mxGJmjl94uktZfy8k5GAvXKKuYbH5iNB9iEyyuxoGH1fCG+83cfnthj89tfPtghOT/mncnFrT5SpT++PPVBd2VQAufZqKBIrQrwtapi1LVoP6GkT+P6qwIVmceBjNdIBp2dK1m4tCEeB0h5dbSjY5gCDQNSbULy8q5KfshsdiNM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565019250; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=qH7eS5T7DMSQ0pvB+4XT5onTtIP3sfPs7gZbNyjSBp8=; b=Z5dMgux7jBNmLQCy2xHPL5BjR5fVDzDKIlR8+apdlz+HVSgeEfPt5yZFpqaG8Gljv1hIX/XKhJrWK1CgD38WKSzjRrCb+egxV8WHKwI8LujKUWdVxgXAEot11vwX7MLEVBdMw2tg+RNG/H3SYgzS24TvGy/+PTWub2C+7EDUwyU= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565019250762652.9848441710207; Mon, 5 Aug 2019 08:34:10 -0700 (PDT) Received: from localhost ([::1]:54978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1huezx-0007Gd-Ol for importer@patchew.org; Mon, 05 Aug 2019 11:34:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52039) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1huevy-0002Wa-Ek for qemu-devel@nongnu.org; Mon, 05 Aug 2019 11:30:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1huevx-0000SW-Gu for qemu-devel@nongnu.org; Mon, 05 Aug 2019 11:30:02 -0400 Received: from mx1.redhat.com ([209.132.183.28]:56078) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1huevx-0000SA-8k; Mon, 05 Aug 2019 11:30:01 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7B834308FBA0; Mon, 5 Aug 2019 15:30:00 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-48.ams2.redhat.com [10.36.117.48]) by smtp.corp.redhat.com (Postfix) with ESMTP id 32CA160C83; Mon, 5 Aug 2019 15:29:55 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Mon, 5 Aug 2019 17:29:39 +0200 Message-Id: <20190805152947.28536-2-david@redhat.com> In-Reply-To: <20190805152947.28536-1-david@redhat.com> References: <20190805152947.28536-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.43]); Mon, 05 Aug 2019 15:30:00 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v1 1/9] s390x/mmu: Better ASC selection in s390_cpu_get_phys_page_debug() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Ilya Leoshkevich , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Let's select the ASC before calling the function and use MMU_DATA_LOAD. This is a preparation to: - Remove the ASC magic depending on the access mode from mmu_translate - Implement IEP support, where we could run into access exceptions trying to fetch instructions Signed-off-by: David Hildenbrand --- target/s390x/helper.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/s390x/helper.c b/target/s390x/helper.c index 13ae9909ad..08166558a0 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -58,7 +58,15 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr = vaddr) vaddr &=3D 0x7fffffff; } =20 - if (mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, fals= e)) { + /* + * We want to read the code, however, not run into access exceptions + * (especially, IEP). + */ + if (asc !=3D PSW_ASC_HOME) { + asc =3D PSW_ASC_PRIMARY; + } + + if (mmu_translate(env, vaddr, MMU_DATA_LOAD, asc, &raddr, &prot, false= )) { return -1; } return raddr; --=20 2.21.0 From nobody Sun Apr 28 20:27:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Mon, 05 Aug 2019 11:30:21 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B52E281DF2; Mon, 5 Aug 2019 15:30:05 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-48.ams2.redhat.com [10.36.117.48]) by smtp.corp.redhat.com (Postfix) with ESMTP id C1D7E60F80; Mon, 5 Aug 2019 15:30:00 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Mon, 5 Aug 2019 17:29:40 +0200 Message-Id: <20190805152947.28536-3-david@redhat.com> In-Reply-To: <20190805152947.28536-1-david@redhat.com> References: <20190805152947.28536-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Mon, 05 Aug 2019 15:30:05 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v1 2/9] s390x/tcg: Rework MMU selection for instruction fetches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Ilya Leoshkevich , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Instructions are always fetched from primary address space, except when in home address mode. Perform the selection directly in cpu_mmu_index(). get_mem_index() is only used to perform data access, instructions are fetched via cpu_lduw_code(), which translates to cpu_mmu_index(env, true). We don't care about restricting the access permissions of the TLB entries anymore, as we no longer enter PRIMARY entries into the SECONDARY MMU. Signed-off-by: David Hildenbrand --- target/s390x/cpu.h | 7 +++++++ target/s390x/mmu_helper.c | 15 ++------------- 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index a606547b4d..c34992bb2e 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -332,6 +332,13 @@ static inline int cpu_mmu_index(CPUS390XState *env, bo= ol ifetch) return MMU_REAL_IDX; } =20 + if (ifetch) { + if ((env->psw.mask & PSW_MASK_ASC) =3D=3D PSW_ASC_HOME) { + return MMU_HOME_IDX; + } + return MMU_PRIMARY_IDX; + } + switch (env->psw.mask & PSW_MASK_ASC) { case PSW_ASC_PRIMARY: return MMU_PRIMARY_IDX; diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 6e9c4d6151..9c0d9b5c5f 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -397,19 +397,8 @@ int mmu_translate(CPUS390XState *env, target_ulong vad= dr, int rw, uint64_t asc, break; case PSW_ASC_SECONDARY: PTE_DPRINTF("%s: asc=3Dsecondary\n", __func__); - /* - * Instruction: Primary - * Data: Secondary - */ - if (rw =3D=3D MMU_INST_FETCH) { - r =3D mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cre= gs[1], - raddr, flags, rw, exc); - *flags &=3D ~(PAGE_READ | PAGE_WRITE); - } else { - r =3D mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->c= regs[7], - raddr, flags, rw, exc); - *flags &=3D ~(PAGE_EXEC); - } + r =3D mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->cregs= [7], + raddr, flags, rw, exc); break; case PSW_ASC_ACCREG: default: --=20 2.21.0 From nobody Sun Apr 28 20:27:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1565019414; cv=none; d=zoho.com; s=zohoarc; b=ByvOXeYXiOrkeCQz9i8WmBKyRXsDBAGSx9FABop9o48Yz2dnOK702gTE+mebhARjYy7XzCSiTwGWZfUeCbNmSThFElkXakKbmdpBnwSsTid6mHnOsw7zYEmdUWT98dNYW1Ds4Ju2fU70c5CYF81apbGuoBtb5VSicgYWysIak/M= ARC-Message-Signature: i=1; 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Mon, 5 Aug 2019 15:30:05 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Mon, 5 Aug 2019 17:29:41 +0200 Message-Id: <20190805152947.28536-4-david@redhat.com> In-Reply-To: <20190805152947.28536-1-david@redhat.com> References: <20190805152947.28536-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Mon, 05 Aug 2019 15:30:10 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v1 3/9] s390x/mmu: DAT translation rewrite X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Ilya Leoshkevich , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Let's rewrite the DAT translation in a non-recursive way, similar to arch/s390/kvm/gaccess.c:guest_translate() in KVM. This makes the code much easier to read, compare and maintain. Use better names for the region/section/page table entries and for the macros to extract relevant parts from virtual address. Introduce defines for all defined bits, this will come in handy soon. All access exceptions now directly go via trigger_access_exception(), at a central point. DAT protection checks are performed at a central place. Also, we now catch and indicate invalid addresses of page tables. All table entries are accessed via read_table_entry(). Signed-off-by: David Hildenbrand --- target/s390x/cpu.h | 77 +++++--- target/s390x/mem_helper.c | 13 +- target/s390x/mmu_helper.c | 360 +++++++++++++++++--------------------- 3 files changed, 229 insertions(+), 221 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index c34992bb2e..1ff14250bd 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -554,26 +554,63 @@ QEMU_BUILD_BUG_ON(sizeof(SysIB) !=3D 4096); #define ASCE_TYPE_SEGMENT 0x00 /* segment table type = */ #define ASCE_TABLE_LENGTH 0x03 /* region table length = */ =20 -#define REGION_ENTRY_ORIGIN (~0xfffULL) /* region/segment table origin = */ -#define REGION_ENTRY_RO 0x200 /* region/segment protection bit= */ -#define REGION_ENTRY_TF 0xc0 /* region/segment table offset = */ -#define REGION_ENTRY_INV 0x20 /* invalid region table entry = */ -#define REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mas= k */ -#define REGION_ENTRY_TYPE_R1 0x0c /* region first table type = */ -#define REGION_ENTRY_TYPE_R2 0x08 /* region second table type = */ -#define REGION_ENTRY_TYPE_R3 0x04 /* region third table type = */ -#define REGION_ENTRY_LENGTH 0x03 /* region third length = */ - -#define SEGMENT_ENTRY_ORIGIN (~0x7ffULL) /* segment table origin */ -#define SEGMENT_ENTRY_FC 0x400 /* format control */ -#define SEGMENT_ENTRY_RO 0x200 /* page protection bit */ -#define SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ - -#define VADDR_PX 0xff000 /* page index bits */ - -#define PAGE_RO 0x200 /* HW read-only bit */ -#define PAGE_INVALID 0x400 /* HW invalid bit */ -#define PAGE_RES0 0x800 /* bit must be zero */ +#define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL +#define REGION_ENTRY_P 0x0000000000000200ULL +#define REGION_ENTRY_TF 0x00000000000000c0ULL +#define REGION_ENTRY_I 0x0000000000000020ULL +#define REGION_ENTRY_TT 0x000000000000000cULL +#define REGION_ENTRY_TL 0x0000000000000003ULL + +#define REGION_ENTRY_TT_REGION1 0x000000000000000cULL +#define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL +#define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL + +#define REGION3_ENTRY_RFAA 0xffffffff80000000ULL +#define REGION3_ENTRY_AV 0x0000000000010000ULL +#define REGION3_ENTRY_ACC 0x000000000000f000ULL +#define REGION3_ENTRY_F 0x0000000000000800ULL +#define REGION3_ENTRY_FC 0x0000000000000400ULL +#define REGION3_ENTRY_IEP 0x0000000000000100ULL +#define REGION3_ENTRY_CR 0x0000000000000010ULL + +#define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL +#define SEGMENT_ENTRY_SFAA 0xfffffffffff80000ULL +#define SEGMENT_ENTRY_AV 0x0000000000010000ULL +#define SEGMENT_ENTRY_ACC 0x000000000000f000ULL +#define SEGMENT_ENTRY_F 0x0000000000000800ULL +#define SEGMENT_ENTRY_FC 0x0000000000000400ULL +#define SEGMENT_ENTRY_P 0x0000000000000200ULL +#define SEGMENT_ENTRY_IEP 0x0000000000000100ULL +#define SEGMENT_ENTRY_I 0x0000000000000020ULL +#define SEGMENT_ENTRY_CS 0x0000000000000010ULL +#define SEGMENT_ENTRY_TT 0x000000000000000cULL + +#define SEGMENT_ENTRY_TT_REGION1 0x000000000000000cULL +#define SEGMENT_ENTRY_TT_REGION2 0x0000000000000008ULL +#define SEGMENT_ENTRY_TT_REGION3 0x0000000000000004ULL +#define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL + +#define PAGE_ENTRY_0 0x0000000000000800ULL +#define PAGE_ENTRY_I 0x0000000000000400ULL +#define PAGE_ENTRY_P 0x0000000000000200ULL +#define PAGE_ENTRY_IEP 0x0000000000000100ULL + +#define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL +#define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL +#define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL +#define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL +#define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL + +#define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> = 53) +#define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> = 42) +#define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> = 31) +#define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> = 20) +#define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12) + +#define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> = 62) +#define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> = 51) +#define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> = 40) +#define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> = 29) =20 #define SK_C (0x1 << 1) #define SK_R (0x1 << 2) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 29d9eaa5b7..46cc0d66f7 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1936,9 +1936,9 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, ui= nt64_t r2, uint32_t m4) /* addresses are not wrapped in 24/31bit mode but table index = is */ raddr =3D table + ((index + i) & 0x7ff) * sizeof(entry); entry =3D cpu_ldq_real_ra(env, raddr, ra); - if (!(entry & REGION_ENTRY_INV)) { + if (!(entry & REGION_ENTRY_I)) { /* we are allowed to not store if already invalid */ - entry |=3D REGION_ENTRY_INV; + entry |=3D REGION_ENTRY_I; cpu_stq_real_ra(env, raddr, entry, ra); } } @@ -1963,17 +1963,18 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto,= uint64_t vaddr, =20 /* Compute the page table entry address */ pte_addr =3D (pto & SEGMENT_ENTRY_ORIGIN); - pte_addr +=3D (vaddr & VADDR_PX) >> 9; + pte_addr +=3D VADDR_PAGE_TX(vaddr) * 8; =20 /* Mark the page table entry as invalid */ pte =3D cpu_ldq_real_ra(env, pte_addr, ra); - pte |=3D PAGE_INVALID; + pte |=3D PAGE_ENTRY_I; + cpu_stq_real_ra(env, pte_addr, pte, ra); =20 /* XXX we exploit the fact that Linux passes the exact virtual address here - it's not obliged to! */ if (m4 & 1) { - if (vaddr & ~VADDR_PX) { + if (vaddr & ~VADDR_PAGE_TX_MASK) { tlb_flush_page(cs, page); /* XXX 31-bit hack */ tlb_flush_page(cs, page ^ 0x80000000); @@ -1982,7 +1983,7 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, u= int64_t vaddr, tlb_flush(cs); } } else { - if (vaddr & ~VADDR_PX) { + if (vaddr & ~VADDR_PAGE_TX_MASK) { tlb_flush_page_all_cpus_synced(cs, page); /* XXX 31-bit hack */ tlb_flush_page_all_cpus_synced(cs, page ^ 0x80000000); diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 9c0d9b5c5f..de7798284d 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -72,44 +72,6 @@ static void trigger_access_exception(CPUS390XState *env,= uint32_t type, } } =20 -static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, - uint64_t asc, int rw, bool exc) -{ - uint64_t tec; - - tec =3D vaddr | (rw =3D=3D MMU_DATA_STORE ? FS_WRITE : FS_READ) | 4 | = asc >> 46; - - DPRINTF("%s: trans_exc_code=3D%016" PRIx64 "\n", __func__, tec); - - if (!exc) { - return; - } - - trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, tec); -} - -static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, - uint32_t type, uint64_t asc, int rw, bool e= xc) -{ - int ilen =3D ILEN_AUTO; - uint64_t tec; - - tec =3D vaddr | (rw =3D=3D MMU_DATA_STORE ? FS_WRITE : FS_READ) | asc = >> 46; - - DPRINTF("%s: trans_exc_code=3D%016" PRIx64 "\n", __func__, tec); - - if (!exc) { - return; - } - - /* Code accesses have an undefined ilc. */ - if (rw =3D=3D MMU_INST_FETCH) { - ilen =3D 2; - } - - trigger_access_exception(env, type, ilen, tec); -} - /* check whether the address would be proteted by Low-Address Protection */ static bool is_low_address(uint64_t addr) { @@ -155,183 +117,171 @@ target_ulong mmu_real2abs(CPUS390XState *env, targe= t_ulong raddr) return raddr; } =20 -/* Decode page table entry (normal 4KB page) */ -static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr, - uint64_t asc, uint64_t pt_entry, - target_ulong *raddr, int *flags, int rw, bool= exc) +static inline int read_table_entry(hwaddr gaddr, uint64_t *entry) { - if (pt_entry & PAGE_INVALID) { - DPRINTF("%s: PTE=3D0x%" PRIx64 " invalid\n", __func__, pt_entry); - trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw, exc); - return -1; + /* + * According to the PoP, these table addresses are "unpredictably real + * or absolute". Also, "it is unpredictable whether the address wraps + * or an addressing exception is recognized". + * + * We treat them as absolute addresses and don't wrap them. + */ + if (address_space_read(&address_space_memory, gaddr, MEMTXATTRS_UNSPEC= IFIED, + (uint8_t *)entry, sizeof(*entry)) !=3D MEMTX_OK= ) { + return -EFAULT; } - if (pt_entry & PAGE_RES0) { - trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc); - return -1; - } - if (pt_entry & PAGE_RO) { - *flags &=3D ~PAGE_WRITE; - } - - *raddr =3D pt_entry & ASCE_ORIGIN; - - PTE_DPRINTF("%s: PTE=3D0x%" PRIx64 "\n", __func__, pt_entry); - + *entry =3D be64_to_cpu(*entry); return 0; } =20 -/* Decode segment table entry */ -static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr, - uint64_t asc, uint64_t st_entry, - target_ulong *raddr, int *flags, int rw, - bool exc) -{ - CPUState *cs =3D env_cpu(env); - uint64_t origin, offs, pt_entry; - - if (st_entry & SEGMENT_ENTRY_RO) { - *flags &=3D ~PAGE_WRITE; - } - - if ((st_entry & SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) { - /* Decode EDAT1 segment frame absolute address (1MB page) */ - *raddr =3D (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff); - PTE_DPRINTF("%s: SEG=3D0x%" PRIx64 "\n", __func__, st_entry); - return 0; - } - - /* Look up 4KB page entry */ - origin =3D st_entry & SEGMENT_ENTRY_ORIGIN; - offs =3D (vaddr & VADDR_PX) >> 9; - pt_entry =3D ldq_phys(cs->as, origin + offs); - PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " =3D> 0x%016" PRIx64 "\n= ", - __func__, origin, offs, pt_entry); - return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw, = exc); -} - -/* Decode region table entries */ -static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr, - uint64_t asc, uint64_t entry, int level, - target_ulong *raddr, int *flags, int rw, - bool exc) -{ - CPUState *cs =3D env_cpu(env); - uint64_t origin, offs, new_entry; - const int pchks[4] =3D { - PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS, - PGM_REG_SEC_TRANS, PGM_REG_FIRST_TRANS - }; - - PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, entry); - - origin =3D entry & REGION_ENTRY_ORIGIN; - offs =3D (vaddr >> (17 + 11 * level / 4)) & 0x3ff8; - - new_entry =3D ldq_phys(cs->as, origin + offs); - PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " =3D> 0x%016" PRIx64 "\n= ", - __func__, origin, offs, new_entry); - - if ((new_entry & REGION_ENTRY_INV) !=3D 0) { - DPRINTF("%s: invalid region\n", __func__); - trigger_page_fault(env, vaddr, pchks[level / 4], asc, rw, exc); - return -1; - } - - if ((new_entry & REGION_ENTRY_TYPE_MASK) !=3D level) { - trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc); - return -1; - } - - if (level =3D=3D ASCE_TYPE_SEGMENT) { - return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, fl= ags, - rw, exc); - } - - /* Check region table offset and length */ - offs =3D (vaddr >> (28 + 11 * (level - 4) / 4)) & 3; - if (offs < ((new_entry & REGION_ENTRY_TF) >> 6) - || offs > (new_entry & REGION_ENTRY_LENGTH)) { - DPRINTF("%s: invalid offset or len (%lx)\n", __func__, new_entry); - trigger_page_fault(env, vaddr, pchks[level / 4 - 1], asc, rw, exc); - return -1; - } - - if ((env->cregs[0] & CR0_EDAT) && (new_entry & REGION_ENTRY_RO)) { - *flags &=3D ~PAGE_WRITE; - } - - /* yet another region */ - return mmu_translate_region(env, vaddr, asc, new_entry, level - 4, - raddr, flags, rw, exc); -} - static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, - uint64_t asc, uint64_t asce, target_ulong *r= addr, - int *flags, int rw, bool exc) + uint64_t asce, target_ulong *raddr, int *fla= gs) { - int level; - int r; + const bool edat1 =3D (env->cregs[0] & CR0_EDAT) && + s390_has_feat(S390_FEAT_EDAT); + const int asce_tl =3D asce & ASCE_TABLE_LENGTH; + const int asce_p =3D asce & ASCE_PRIVATE_SPACE; + hwaddr gaddr =3D asce & ASCE_ORIGIN; + uint64_t entry; =20 if (asce & ASCE_REAL_SPACE) { - /* direct mapping */ *raddr =3D vaddr; return 0; } =20 - level =3D asce & ASCE_TYPE_MASK; - switch (level) { + switch (asce & ASCE_TYPE_MASK) { case ASCE_TYPE_REGION1: - if ((vaddr >> 62) > (asce & ASCE_TABLE_LENGTH)) { - trigger_page_fault(env, vaddr, PGM_REG_FIRST_TRANS, asc, rw, e= xc); - return -1; + if (VADDR_REGION1_TL(vaddr) > asce_tl) { + return PGM_REG_FIRST_TRANS; } + gaddr +=3D VADDR_REGION1_TX(vaddr) * 8; break; case ASCE_TYPE_REGION2: - if (vaddr & 0xffe0000000000000ULL) { - DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64 - " 0xffe0000000000000ULL\n", __func__, vaddr); - trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc); - return -1; + if (VADDR_REGION1_TX(vaddr)) { + return PGM_ASCE_TYPE; } - if ((vaddr >> 51 & 3) > (asce & ASCE_TABLE_LENGTH)) { - trigger_page_fault(env, vaddr, PGM_REG_SEC_TRANS, asc, rw, exc= ); - return -1; + if (VADDR_REGION2_TL(vaddr) > asce_tl) { + return PGM_REG_SEC_TRANS; } + gaddr +=3D VADDR_REGION2_TX(vaddr) * 8; break; case ASCE_TYPE_REGION3: - if (vaddr & 0xfffffc0000000000ULL) { - DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64 - " 0xfffffc0000000000ULL\n", __func__, vaddr); - trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc); - return -1; + if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr)) { + return PGM_ASCE_TYPE; } - if ((vaddr >> 40 & 3) > (asce & ASCE_TABLE_LENGTH)) { - trigger_page_fault(env, vaddr, PGM_REG_THIRD_TRANS, asc, rw, e= xc); - return -1; + if (VADDR_REGION3_TL(vaddr) > asce_tl) { + return PGM_REG_THIRD_TRANS; } + gaddr +=3D VADDR_REGION3_TX(vaddr) * 8; break; case ASCE_TYPE_SEGMENT: - if (vaddr & 0xffffffff80000000ULL) { - DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64 - " 0xffffffff80000000ULL\n", __func__, vaddr); - trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc); - return -1; + if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr) || + VADDR_REGION3_TX(vaddr)) { + return PGM_ASCE_TYPE; } - if ((vaddr >> 29 & 3) > (asce & ASCE_TABLE_LENGTH)) { - trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw, exc= ); - return -1; + if (VADDR_SEGMENT_TL(vaddr) > asce_tl) { + return PGM_SEGMENT_TRANS; } + gaddr +=3D VADDR_SEGMENT_TX(vaddr) * 8; + break; + } + switch (asce & ASCE_TYPE_MASK) { + case ASCE_TYPE_REGION1: + if (read_table_entry(gaddr, &entry)) { + return PGM_ADDRESSING; + } + if (entry & REGION_ENTRY_I) { + return PGM_REG_FIRST_TRANS; + } + if ((entry & REGION_ENTRY_TT) !=3D REGION_ENTRY_TT_REGION1) { + return PGM_TRANS_SPEC; + } + if (VADDR_REGION2_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 || + VADDR_REGION2_TL(vaddr) > (entry & REGION_ENTRY_TL)) { + return PGM_REG_SEC_TRANS; + } + if (edat1 && (entry & REGION_ENTRY_P)) { + *flags &=3D ~PAGE_WRITE; + } + gaddr =3D (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION2_TX(vaddr) = * 8; + /* FALL THROUGH */ + case ASCE_TYPE_REGION2: + if (read_table_entry(gaddr, &entry)) { + return PGM_ADDRESSING; + } + if (entry & REGION_ENTRY_I) { + return PGM_REG_SEC_TRANS; + } + if ((entry & REGION_ENTRY_TT) !=3D REGION_ENTRY_TT_REGION2) { + return PGM_TRANS_SPEC; + } + if (VADDR_REGION3_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 || + VADDR_REGION3_TL(vaddr) > (entry & REGION_ENTRY_TL)) { + return PGM_REG_THIRD_TRANS; + } + if (edat1 && (entry & REGION_ENTRY_P)) { + *flags &=3D ~PAGE_WRITE; + } + gaddr =3D (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION3_TX(vaddr) = * 8; + /* FALL THROUGH */ + case ASCE_TYPE_REGION3: + if (read_table_entry(gaddr, &entry)) { + return PGM_ADDRESSING; + } + if (entry & REGION_ENTRY_I) { + return PGM_REG_THIRD_TRANS; + } + if ((entry & REGION_ENTRY_TT) !=3D REGION_ENTRY_TT_REGION3) { + return PGM_TRANS_SPEC; + } + if (edat1 && (entry & REGION_ENTRY_P)) { + *flags &=3D ~PAGE_WRITE; + } + if (VADDR_SEGMENT_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 || + VADDR_SEGMENT_TL(vaddr) > (entry & REGION_ENTRY_TL)) { + return PGM_SEGMENT_TRANS; + } + gaddr =3D (entry & REGION_ENTRY_ORIGIN) + VADDR_SEGMENT_TX(vaddr) = * 8; + /* FALL THROUGH */ + case ASCE_TYPE_SEGMENT: + if (read_table_entry(gaddr, &entry)) { + return PGM_ADDRESSING; + } + if (entry & SEGMENT_ENTRY_I) { + return PGM_SEGMENT_TRANS; + } + if ((entry & SEGMENT_ENTRY_TT) !=3D SEGMENT_ENTRY_TT_SEGMENT) { + return PGM_TRANS_SPEC; + } + if ((entry & SEGMENT_ENTRY_CS) && asce_p) { + return PGM_TRANS_SPEC; + } + if (entry & SEGMENT_ENTRY_P) { + *flags &=3D ~PAGE_WRITE; + } + if (edat1 && (entry & SEGMENT_ENTRY_FC)) { + *raddr =3D entry & SEGMENT_ENTRY_SFAA; + return 0; + } + gaddr =3D (entry & SEGMENT_ENTRY_ORIGIN) + VADDR_PAGE_TX(vaddr) * = 8; break; } =20 - r =3D mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags,= rw, - exc); - if (!r && rw =3D=3D MMU_DATA_STORE && !(*flags & PAGE_WRITE)) { - trigger_prot_fault(env, vaddr, asc, rw, exc); - return -1; + if (read_table_entry(gaddr, &entry)) { + return PGM_ADDRESSING; + } + if (entry & PAGE_ENTRY_I) { + return PGM_PAGE_TRANS; + } + if (entry & PAGE_ENTRY_0) { + return PGM_TRANS_SPEC; + } + if (entry & PAGE_ENTRY_P) { + *flags &=3D ~PAGE_WRITE; } =20 - return r; + *raddr =3D entry & TARGET_PAGE_MASK; + return 0; } =20 /** @@ -347,9 +297,14 @@ static int mmu_translate_asce(CPUS390XState *env, targ= et_ulong vaddr, int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t= asc, target_ulong *raddr, int *flags, bool exc) { + /* Code accesses have an undefined ilc, let's use 2 bytes. */ + const int ilen =3D (rw =3D=3D MMU_INST_FETCH) ? 2 : ILEN_AUTO; + uint64_t tec =3D (vaddr & TARGET_PAGE_MASK) | (asc >> 46) | + (rw =3D=3D MMU_DATA_STORE ? FS_WRITE : FS_READ); + uint64_t asce; static S390SKeysState *ss; static S390SKeysClass *skeyclass; - int r =3D -1; + int r; uint8_t key; =20 if (unlikely(!ss)) { @@ -380,25 +335,21 @@ int mmu_translate(CPUS390XState *env, target_ulong va= ddr, int rw, uint64_t asc, =20 if (!(env->psw.mask & PSW_MASK_DAT)) { *raddr =3D vaddr; - r =3D 0; - goto out; + goto nodat; } =20 switch (asc) { case PSW_ASC_PRIMARY: PTE_DPRINTF("%s: asc=3Dprimary\n", __func__); - r =3D mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, fl= ags, - rw, exc); + asce =3D env->cregs[1]; break; case PSW_ASC_HOME: PTE_DPRINTF("%s: asc=3Dhome\n", __func__); - r =3D mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, f= lags, - rw, exc); + asce =3D env->cregs[13]; break; case PSW_ASC_SECONDARY: PTE_DPRINTF("%s: asc=3Dsecondary\n", __func__); - r =3D mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->cregs= [7], - raddr, flags, rw, exc); + asce =3D env->cregs[7]; break; case PSW_ASC_ACCREG: default: @@ -406,11 +357,30 @@ int mmu_translate(CPUS390XState *env, target_ulong va= ddr, int rw, uint64_t asc, break; } =20 - out: + /* perform the translation */ + r =3D mmu_translate_asce(env, vaddr, asce, raddr, flags); + if (r) { + if (exc) { + trigger_access_exception(env, r, ilen, tec); + } + return -1; + } + + /* check for DAT protection */ + if (rw =3D=3D MMU_DATA_STORE && !(*flags & PAGE_WRITE)) { + if (exc) { + /* DAT sets bit 61 only */ + tec |=3D 0x4; + trigger_access_exception(env, PGM_PROTECTION, ilen, tec); + } + return -1; + } + +nodat: /* Convert real address -> absolute address */ *raddr =3D mmu_real2abs(env, *raddr); =20 - if (r =3D=3D 0 && *raddr < ram_size) { + if (*raddr < ram_size) { if (skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) { trace_get_skeys_nonzero(r); return 0; @@ -430,7 +400,7 @@ int mmu_translate(CPUS390XState *env, target_ulong vadd= r, int rw, uint64_t asc, } } =20 - return r; + return 0; } =20 /** --=20 2.21.0 From nobody Sun Apr 28 20:27:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Mon, 05 Aug 2019 11:30:19 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3C1E63084295; Mon, 5 Aug 2019 15:30:13 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-48.ams2.redhat.com [10.36.117.48]) by smtp.corp.redhat.com (Postfix) with ESMTP id CF64960F88; Mon, 5 Aug 2019 15:30:10 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Mon, 5 Aug 2019 17:29:42 +0200 Message-Id: <20190805152947.28536-5-david@redhat.com> In-Reply-To: <20190805152947.28536-1-david@redhat.com> References: <20190805152947.28536-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.40]); Mon, 05 Aug 2019 15:30:13 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v1 4/9] s390x/mmu: Add EDAT2 translation support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Ilya Leoshkevich , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This only adds basic support to the DAT translation, but no EDAT2 support for TCG. E.g., the gdbstub under kvm uses this function, too, to translate virtual addresses. Signed-off-by: David Hildenbrand Reviewed-by: Thomas Huth --- target/s390x/mmu_helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index de7798284d..5c9c7d385d 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -139,6 +139,7 @@ static int mmu_translate_asce(CPUS390XState *env, targe= t_ulong vaddr, { const bool edat1 =3D (env->cregs[0] & CR0_EDAT) && s390_has_feat(S390_FEAT_EDAT); + const bool edat2 =3D edat1 && s390_has_feat(S390_FEAT_EDAT_2); const int asce_tl =3D asce & ASCE_TABLE_LENGTH; const int asce_p =3D asce & ASCE_PRIVATE_SPACE; hwaddr gaddr =3D asce & ASCE_ORIGIN; @@ -234,9 +235,16 @@ static int mmu_translate_asce(CPUS390XState *env, targ= et_ulong vaddr, if ((entry & REGION_ENTRY_TT) !=3D REGION_ENTRY_TT_REGION3) { return PGM_TRANS_SPEC; } + if (edat2 && (entry & REGION3_ENTRY_CR) && asce_p) { + return PGM_TRANS_SPEC; + } if (edat1 && (entry & REGION_ENTRY_P)) { *flags &=3D ~PAGE_WRITE; } + if (edat2 && (entry & REGION3_ENTRY_FC)) { + *raddr =3D entry & REGION3_ENTRY_RFAA; + return 0; + } if (VADDR_SEGMENT_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 || VADDR_SEGMENT_TL(vaddr) > (entry & REGION_ENTRY_TL)) { return PGM_SEGMENT_TRANS; --=20 2.21.0 From nobody Sun Apr 28 20:27:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1565019160; cv=none; d=zoho.com; s=zohoarc; b=RS+Wy8i1+tcsNtLNk895k15z5Y2dK+/rhIfOtobwEsG2UOfo+zNKrJDWFhtXVqxAn97OXZn+0yZKCq651+Oetu/eef1V8vVeOTVHFDfR3mfZF8wYYmYGFfphFpyyU5UoBiBO6M5s3zp5569Vpz1Fe8Rtn05k2cCJ0DK1dO7HokY= ARC-Message-Signature: i=1; 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Mon, 5 Aug 2019 15:30:13 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Mon, 5 Aug 2019 17:29:43 +0200 Message-Id: <20190805152947.28536-6-david@redhat.com> In-Reply-To: <20190805152947.28536-1-david@redhat.com> References: <20190805152947.28536-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Mon, 05 Aug 2019 15:30:17 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v1 5/9] s390x/mmu: Implement access-exception-fetch/store-indication facility X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Ilya Leoshkevich , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We always have to indicate whether it is a fetch or a store for all access exceptions. This is only missing for LAP exceptions. Signed-off-by: David Hildenbrand --- target/s390x/mmu_helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 5c9c7d385d..f3e988e4fd 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -333,7 +333,7 @@ int mmu_translate(CPUS390XState *env, target_ulong vadd= r, int rw, uint64_t asc, *flags |=3D PAGE_WRITE_INV; if (is_low_address(vaddr) && rw =3D=3D MMU_DATA_STORE) { if (exc) { - trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0= ); + trigger_access_exception(env, PGM_PROTECTION, ilen, tec); } return -EACCES; } @@ -511,6 +511,8 @@ void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr= _t ra) int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw, target_ulong *addr, int *flags) { + uint64_t tec =3D (raddr & TARGET_PAGE_MASK) | + (rw =3D=3D MMU_DATA_STORE ? FS_WRITE : FS_READ); const bool lowprot_enabled =3D env->cregs[0] & CR0_LOWPROT; =20 *flags =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -518,7 +520,7 @@ int mmu_translate_real(CPUS390XState *env, target_ulong= raddr, int rw, /* see comment in mmu_translate() how this works */ *flags |=3D PAGE_WRITE_INV; if (is_low_address(raddr) && rw =3D=3D MMU_DATA_STORE) { - trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0); + trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, tec); return -EACCES; } } --=20 2.21.0 From nobody Sun Apr 28 20:27:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1565019186; cv=none; d=zoho.com; s=zohoarc; b=gLGYE3PPZtAOlMQkfyEmA57kb43WJ+5mSMTuzhK+ZrhQo7o+1/wnzYzbwuqLwl9o5COLqAraiACfZhlT1M84/V516qTMj0TdU6fnP9f2Dr77BzG3Sp3lRm+pFz9k5QPzcfvZfVo8A/3EHJsUMUnLMNw+ezJHVgXqhTbQYdz9Br8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565019186; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=CjQN0mX+l13l9TSxxCShItDrxa1WhktKHKS/xp14XMQ=; b=cJSptFck+W3f0IGbQT8Rk3Nazn/Ovuaw3msuRqBvzb2LkfvGv0f0yhhDhAWsXzhEjU2lqWEc1r/HcddJf1FVqsYc7/TXdZFVhnzr3dEDV1saXfC0wIzVV6tfdfSfz1SPMF/yaVv6FwiH/72CF7qUymMyZH0byMl+Cap4me4743M= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565019186123392.28190154512765; Mon, 5 Aug 2019 08:33:06 -0700 (PDT) Received: from localhost ([::1]:54958 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hueyv-0005Ty-57 for importer@patchew.org; Mon, 05 Aug 2019 11:33:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52234) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1huewZ-0003X1-MV for qemu-devel@nongnu.org; Mon, 05 Aug 2019 11:30:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1huewY-0000sT-PM for qemu-devel@nongnu.org; Mon, 05 Aug 2019 11:30:39 -0400 Received: from mx1.redhat.com ([209.132.183.28]:64436) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1huewY-0000rS-K4; Mon, 05 Aug 2019 11:30:38 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E01B0C0546D5; Mon, 5 Aug 2019 15:30:37 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-48.ams2.redhat.com [10.36.117.48]) by smtp.corp.redhat.com (Postfix) with ESMTP id 124196114C; Mon, 5 Aug 2019 15:30:17 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Mon, 5 Aug 2019 17:29:44 +0200 Message-Id: <20190805152947.28536-7-david@redhat.com> In-Reply-To: <20190805152947.28536-1-david@redhat.com> References: <20190805152947.28536-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Mon, 05 Aug 2019 15:30:38 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v1 6/9] s390x/mmu: Implement enhanced suppression-on-protection facility 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Ilya Leoshkevich , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We already implement ESOP-1. For ESOP-2, we only have to indicate all protection exceptions properly. Due to EDAT-1, we already indicate DAT exceptions properly. We don't trigger KCP/ALCP/IEP exceptions yet. So all we have to do is set the TEID (TEC) to the right values (bit 56, 60, 61) in case of LAP. We don't have any side-effects (e.g., no guarded-storage facility), therefore, bit 64 of the TEID (TEC) is always 0. Signed-off-by: David Hildenbrand --- target/s390x/mmu_helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index f3e988e4fd..631cc29c28 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -333,6 +333,8 @@ int mmu_translate(CPUS390XState *env, target_ulong vadd= r, int rw, uint64_t asc, *flags |=3D PAGE_WRITE_INV; if (is_low_address(vaddr) && rw =3D=3D MMU_DATA_STORE) { if (exc) { + /* LAP sets bit 56 */ + tec |=3D 0x80; trigger_access_exception(env, PGM_PROTECTION, ilen, tec); } return -EACCES; @@ -520,6 +522,8 @@ int mmu_translate_real(CPUS390XState *env, target_ulong= raddr, int rw, /* see comment in mmu_translate() how this works */ *flags |=3D PAGE_WRITE_INV; if (is_low_address(raddr) && rw =3D=3D MMU_DATA_STORE) { + /* LAP sets bit 56 */ + tec |=3D 0x80; trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, tec); return -EACCES; } --=20 2.21.0 From nobody Sun Apr 28 20:27:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Mon, 05 Aug 2019 11:30:49 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8975585537; Mon, 5 Aug 2019 15:30:47 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-48.ams2.redhat.com [10.36.117.48]) by smtp.corp.redhat.com (Postfix) with ESMTP id 35AF0BABB; Mon, 5 Aug 2019 15:30:38 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Mon, 5 Aug 2019 17:29:45 +0200 Message-Id: <20190805152947.28536-8-david@redhat.com> In-Reply-To: <20190805152947.28536-1-david@redhat.com> References: <20190805152947.28536-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Mon, 05 Aug 2019 15:30:47 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v1 7/9] s390x/mmu: Implement Instruction-Execution-Protection Facility X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Ilya Leoshkevich , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" IEP support in the mmu is fairly easy. Set the right permissions for TLB entries and properly report an exception. Make sure to handle EDAT-2 by setting bit 56/60/61 of the TEID (TEC) to the right values. Signed-off-by: David Hildenbrand Reviewed-by: Thomas Huth --- target/s390x/cpu.h | 1 + target/s390x/mmu_helper.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 1ff14250bd..9a8318b3aa 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -311,6 +311,7 @@ extern const struct VMStateDescription vmstate_s390_cpu; #define CR0_EDAT 0x0000000000800000ULL #define CR0_AFP 0x0000000000040000ULL #define CR0_VECTOR 0x0000000000020000ULL +#define CR0_IEP 0x0000000000100000ULL #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL #define CR0_CKC_SC 0x0000000000000800ULL diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 631cc29c28..83e241c430 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -140,6 +140,8 @@ static int mmu_translate_asce(CPUS390XState *env, targe= t_ulong vaddr, const bool edat1 =3D (env->cregs[0] & CR0_EDAT) && s390_has_feat(S390_FEAT_EDAT); const bool edat2 =3D edat1 && s390_has_feat(S390_FEAT_EDAT_2); + const bool iep =3D (env->cregs[0] & CR0_IEP) && + s390_has_feat(S390_FEAT_INSTRUCTION_EXEC_PROT); const int asce_tl =3D asce & ASCE_TABLE_LENGTH; const int asce_p =3D asce & ASCE_PRIVATE_SPACE; hwaddr gaddr =3D asce & ASCE_ORIGIN; @@ -242,6 +244,9 @@ static int mmu_translate_asce(CPUS390XState *env, targe= t_ulong vaddr, *flags &=3D ~PAGE_WRITE; } if (edat2 && (entry & REGION3_ENTRY_FC)) { + if (iep && (entry & REGION3_ENTRY_IEP)) { + *flags &=3D ~PAGE_EXEC; + } *raddr =3D entry & REGION3_ENTRY_RFAA; return 0; } @@ -268,6 +273,9 @@ static int mmu_translate_asce(CPUS390XState *env, targe= t_ulong vaddr, *flags &=3D ~PAGE_WRITE; } if (edat1 && (entry & SEGMENT_ENTRY_FC)) { + if (iep && (entry & SEGMENT_ENTRY_IEP)) { + *flags &=3D ~PAGE_EXEC; + } *raddr =3D entry & SEGMENT_ENTRY_SFAA; return 0; } @@ -287,6 +295,9 @@ static int mmu_translate_asce(CPUS390XState *env, targe= t_ulong vaddr, if (entry & PAGE_ENTRY_P) { *flags &=3D ~PAGE_WRITE; } + if (iep && (entry & PAGE_ENTRY_IEP)) { + *flags &=3D ~PAGE_EXEC; + } =20 *raddr =3D entry & TARGET_PAGE_MASK; return 0; @@ -386,6 +397,16 @@ int mmu_translate(CPUS390XState *env, target_ulong vad= dr, int rw, uint64_t asc, return -1; } =20 + /* check for Instruction-Execution-Protection */ + if (rw =3D=3D MMU_INST_FETCH && !(*flags & PAGE_EXEC)) { + if (exc) { + /* IEP sets bit 56 and 61 */ + tec |=3D 0x84; + trigger_access_exception(env, PGM_PROTECTION, ilen, tec); + } + return -1; + } + nodat: /* Convert real address -> absolute address */ *raddr =3D mmu_real2abs(env, *raddr); --=20 2.21.0 From nobody Sun Apr 28 20:27:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 5 Aug 2019 15:30:49 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-48.ams2.redhat.com [10.36.117.48]) by smtp.corp.redhat.com (Postfix) with ESMTP id D54726B49B; Mon, 5 Aug 2019 15:30:47 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Mon, 5 Aug 2019 17:29:46 +0200 Message-Id: <20190805152947.28536-9-david@redhat.com> In-Reply-To: <20190805152947.28536-1-david@redhat.com> References: <20190805152947.28536-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.45]); Mon, 05 Aug 2019 15:30:50 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v1 8/9] s390x/cpumodel: Prepare for changes of QEMU model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Ilya Leoshkevich , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Setup the 4.1 compatibility model so we can add new features to the LATEST model. Signed-off-by: David Hildenbrand Reviewed-by: Cornelia Huck Reviewed-by: Thomas Huth --- hw/s390x/s390-virtio-ccw.c | 2 ++ target/s390x/gen-features.c | 6 +++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 593b34e0e2..c815a65ee9 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -671,7 +671,9 @@ DEFINE_CCW_MACHINE(4_2, "4.2", true); =20 static void ccw_machine_4_1_instance_options(MachineState *machine) { + static const S390FeatInit qemu_cpu_feat =3D { S390_FEAT_LIST_QEMU_V4_1= }; ccw_machine_4_2_instance_options(machine); + s390_set_qemu_cpu_model(0x2964, 13, 2, qemu_cpu_feat); } =20 static void ccw_machine_4_1_class_options(MachineClass *mc) diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c index 49a650ac52..7e82f2f004 100644 --- a/target/s390x/gen-features.c +++ b/target/s390x/gen-features.c @@ -698,11 +698,14 @@ static uint16_t qemu_V4_0[] =3D { S390_FEAT_ZPCI, }; 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Mon, 5 Aug 2019 15:30:52 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-48.ams2.redhat.com [10.36.117.48]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2EE325C2E2; Mon, 5 Aug 2019 15:30:50 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Mon, 5 Aug 2019 17:29:47 +0200 Message-Id: <20190805152947.28536-10-david@redhat.com> In-Reply-To: <20190805152947.28536-1-david@redhat.com> References: <20190805152947.28536-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Mon, 05 Aug 2019 15:30:52 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.2 v1 9/9] s390x/cpumodel: Add new TCG features to QEMU cpu model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Janosch Frank , David Hildenbrand , Cornelia Huck , Ilya Leoshkevich , Halil Pasic , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We now implement a bunch of new facilities we can properly indicate. ESOP-1/ESOP-2 handling is discussed in the PoP Chafter 3-15 ("Suppression on Protection"). The "Basic suppression-on-protection (SOP) facility" is a core part of z/Architecture without a facility indication. ESOP-2 is indicated by ESOP-1 + Side-effect facility ("ESOP-2"). Besides ESOP-2, the side-effect facility is only relevant for the guarded-storage facility (we don't implement). S390_ESOP: - We indicate DAT exeptions by setting bit 61 of the TEID (TEC) to 1 and bit 60 to zero. We don't trigger ALCP exceptions yet. Also, we set bit 0-51 and bit 62/63 to the right values. S390_ACCESS_EXCEPTION_FS_INDICATION: - The TEID (TEC) properly indicates in bit 52/53 on any access if it was a fetch or a store S390_SIDE_EFFECT_ACCESS_ESOP2: - We have no side-effect accesses (esp., we don't implement the guarded-storage faciliy), we correctly set bit 64 of the TEID (TEC) to 0 (no side-effect). - ESOP2: We properly set bit 56, 60, 61 in the TEID (TEC) to indicate the type of protection. We don't trigger KCP/ALCP exceptions yet. S390_INSTRUCTION_EXEC_PROT: - The MMU properly detects and indicates the exception on instruction fetch= es - Protected TLB entries will never get PAGE_EXEC set. There is no need to fake the abscence of any of the facilities - without the facilities, some bits of the TEID (TEC) are simply unpredictable. As IEP was added with z14 and we currently implement a z13, add it to the MAX model instead. Signed-off-by: David Hildenbrand --- target/s390x/gen-features.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c index 7e82f2f004..6e78d40d9a 100644 --- a/target/s390x/gen-features.c +++ b/target/s390x/gen-features.c @@ -704,12 +704,16 @@ static uint16_t qemu_V4_1[] =3D { }; =20 static uint16_t qemu_LATEST[] =3D { + S390_FEAT_ACCESS_EXCEPTION_FS_INDICATION, + S390_FEAT_SIDE_EFFECT_ACCESS_ESOP2, + S390_FEAT_ESOP, }; =20 /* add all new definitions before this point */ static uint16_t qemu_MAX[] =3D { /* generates a dependency warning, leave it out for now */ S390_FEAT_MSA_EXT_5, + S390_FEAT_INSTRUCTION_EXEC_PROT, }; =20 /****** END FEATURE DEFS ******/ --=20 2.21.0