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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x20sm65233782wmc.1.2019.08.05.06.09.54 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 05 Aug 2019 06:09:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TVwlsu2eYeCMvi9/271IWIXUfOnAUkIydke54giXF70=; b=zyhcc+a4ZwnmGVAXruVbu99CrPHaSpYJiB/lvHcpyrKUb0MNwKfx4EBShRtRXBph2C qk5AM09ovzvdn0BdzTyCHvoHHv9hm6M8x68T5t8Z7wRGGCquDoqLJWcIJOt2nK5cT0MF FyZbiDp+aOoCGgUL1fwv4tY3fIry9tzNScpeFk1EO+BCZbH3+POuJb/ikZgDE6AFVyQ3 TKg/B0YqG0gop/EUZds9F363ZPpyTBJbjMfK7K0lAJagLFWfR3V+6dOpELhLacOQDitm kPcvD8bvlo86QcSfuo6XmiqsvsaZFdtGCx0MmJxxYtN6OrAF8VIrUvc1EwSmLHtHM9cm hGvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TVwlsu2eYeCMvi9/271IWIXUfOnAUkIydke54giXF70=; b=gg8HoaOiPEK4qWalTX+WFCSsQOD2+K5vM+kS+p9IDBHp+IcYGfjDQ6NaV5b2cjtiJ4 zEdDNIL6GPPtYyD4+lNy6WUrC6SKvZ6K7OZNZHkr1rMQTRmHf8rcpEj2gM/Nyu5Q4bCa AvWQTmQ2XwCj2DIcY8UivrFp6uK8lCi27INTVDw8FWvp3AMMOb/cFbWAO0Zed60LwsGp fZFcwIJV/psCHrVVJfY5FzL57t3dW2MHsAbflBzmpt6JVityc989SgmDeCArwdRcxeA9 pC/a/pquEwanBP4wY6xYkHteZff13CapwAeGMoDvUmBDvcOSiGlSdetcGMNbX6F9kWgc z0Cw== X-Gm-Message-State: APjAAAVsS7fWYvjjZhN1Hoffa41M7GMgBeG+4vTIM/xjhtWKMg4Eqny0 AJa5M4fM+3+7TYJtPP5lATc7bfOmNsX7Pg== X-Google-Smtp-Source: APXvYqw4M6n3hjc4jeRxxE1Z9hAdIJnHoBE1H5w+qgrel+e2Ae28Dp4j8tsSgEV91uR7W3ZztVqQfg== X-Received: by 2002:adf:aac8:: with SMTP id i8mr2937607wrc.56.1565010595799; Mon, 05 Aug 2019 06:09:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 5 Aug 2019 14:09:51 +0100 Message-Id: <20190805130952.4415-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190805130952.4415-1-peter.maydell@linaro.org> References: <20190805130952.4415-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 1/2] target/arm: Factor out 'generate singlestep exception' function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Factor out code to 'generate a singlestep exception', which is currently repeated in four places. To do this we need to also pull the identical copies of the gen-exception() function out of translate-a64.c and translate.c into translate.h. (There is a bug in the code: we're taking the exception to the wrong target EL. This will be simpler to fix if there's only one place to do it.) Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.h | 23 +++++++++++++++++++++++ target/arm/translate-a64.c | 19 ++----------------- target/arm/translate.c | 20 ++------------------ 3 files changed, 27 insertions(+), 35 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index a20f6e20568..45053190baa 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -2,6 +2,7 @@ #define TARGET_ARM_TRANSLATE_H =20 #include "exec/translator.h" +#include "internals.h" =20 =20 /* internal defines */ @@ -232,6 +233,28 @@ static inline void gen_ss_advance(DisasContext *s) } } =20 +static inline void gen_exception(int excp, uint32_t syndrome, + uint32_t target_el) +{ + TCGv_i32 tcg_excp =3D tcg_const_i32(excp); + TCGv_i32 tcg_syn =3D tcg_const_i32(syndrome); + TCGv_i32 tcg_el =3D tcg_const_i32(target_el); + + gen_helper_exception_with_syndrome(cpu_env, tcg_excp, + tcg_syn, tcg_el); + + tcg_temp_free_i32(tcg_el); + tcg_temp_free_i32(tcg_syn); + tcg_temp_free_i32(tcg_excp); +} + +/* Generate an architectural singlestep exception */ +static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) +{ + gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, isv, ex), + default_exception_el(s)); +} + /* * Given a VFP floating point constant encoded into an 8 bit immediate in = an * instruction, expand it to the actual constant value of the specified diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d3231477a27..f6729b96fd0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -253,19 +253,6 @@ static void gen_exception_internal(int excp) tcg_temp_free_i32(tcg_excp); } =20 -static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) -{ - TCGv_i32 tcg_excp =3D tcg_const_i32(excp); - TCGv_i32 tcg_syn =3D tcg_const_i32(syndrome); - TCGv_i32 tcg_el =3D tcg_const_i32(target_el); - - gen_helper_exception_with_syndrome(cpu_env, tcg_excp, - tcg_syn, tcg_el); - tcg_temp_free_i32(tcg_el); - tcg_temp_free_i32(tcg_syn); - tcg_temp_free_i32(tcg_excp); -} - static void gen_exception_internal_insn(DisasContext *s, int offset, int e= xcp) { gen_a64_set_pc_im(s->pc - offset); @@ -305,8 +292,7 @@ static void gen_step_complete_exception(DisasContext *s) * of the exception, and our syndrome information is always correct. */ gen_ss_advance(s); - gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), - default_exception_el(s)); + gen_swstep_exception(s, 1, s->is_ldex); s->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -14261,8 +14247,7 @@ static void aarch64_tr_translate_insn(DisasContextB= ase *dcbase, CPUState *cpu) * bits should be zero. */ assert(dc->base.num_insns =3D=3D 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); + gen_swstep_exception(dc, 0, 0); dc->base.is_jmp =3D DISAS_NORETURN; } else { disas_a64_insn(env, dc); diff --git a/target/arm/translate.c b/target/arm/translate.c index 7853462b21b..19b9d8f2725 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -282,20 +282,6 @@ static void gen_exception_internal(int excp) tcg_temp_free_i32(tcg_excp); } =20 -static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) -{ - TCGv_i32 tcg_excp =3D tcg_const_i32(excp); - TCGv_i32 tcg_syn =3D tcg_const_i32(syndrome); - TCGv_i32 tcg_el =3D tcg_const_i32(target_el); - - gen_helper_exception_with_syndrome(cpu_env, tcg_excp, - tcg_syn, tcg_el); - - tcg_temp_free_i32(tcg_el); - tcg_temp_free_i32(tcg_syn); - tcg_temp_free_i32(tcg_excp); -} - static void gen_step_complete_exception(DisasContext *s) { /* We just completed step of an insn. Move from Active-not-pending @@ -308,8 +294,7 @@ static void gen_step_complete_exception(DisasContext *s) * of the exception, and our syndrome information is always correct. */ gen_ss_advance(s); - gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), - default_exception_el(s)); + gen_swstep_exception(s, 1, s->is_ldex); s->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -12024,8 +12009,7 @@ static bool arm_pre_translate_insn(DisasContext *dc) * bits should be zero. */ assert(dc->base.num_insns =3D=3D 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); + gen_swstep_exception(dc, 0, 0); dc->base.is_jmp =3D DISAS_NORETURN; return true; } --=20 2.20.1 From nobody Sun Apr 28 11:59:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1565010669; cv=none; d=zoho.com; s=zohoarc; b=Y/89Z50FDBx6bykB8uOJUQF/TX3WIvEOtgzzZb8pKi7/dKNe/Uv03ru7dhcXFewRWXGewtE8AyAa+FQSZQx4dGFastyBAJd6cG+sih2EC+EQOclV1ShIQO0oDYdQGkIPVlCE04tndFgiKN3aLfJUPbsofvwJ4BuGWptPcixS5pw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565010669; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=EGU+/MpxT8YGsEWvI+W5cKlSVCq/nVM+/LNMb9QzO4c=; b=Cly5vzKTPvhKDufpg4yhT9YkQckRxDqhuvzaetBHSUO3oS1ualaGoW/+ID3/0GX86bhConagRxlQhMCDqS4e8mJJvVpBH/HA9lO7QIXUi6neQKFJmGnkjROJyAz4boV2OZ3XIbi1AGgyq2Jg3BlhcV4rCW5j4TVLwZTXQUT9Sfc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565010669545704.8776623773224; Mon, 5 Aug 2019 06:11:09 -0700 (PDT) Received: from localhost ([::1]:53762 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1huclY-00034W-EC for importer@patchew.org; Mon, 05 Aug 2019 09:11:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52778) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1huckS-0000Zk-0f for qemu-devel@nongnu.org; Mon, 05 Aug 2019 09:10:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1huckQ-00048e-6J for qemu-devel@nongnu.org; Mon, 05 Aug 2019 09:09:59 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:37069) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1huckP-00047q-W2 for qemu-devel@nongnu.org; Mon, 05 Aug 2019 09:09:58 -0400 Received: by mail-wr1-x442.google.com with SMTP id n9so59286444wrr.4 for ; Mon, 05 Aug 2019 06:09:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x20sm65233782wmc.1.2019.08.05.06.09.55 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 05 Aug 2019 06:09:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=EGU+/MpxT8YGsEWvI+W5cKlSVCq/nVM+/LNMb9QzO4c=; b=Skq7d1PQQKXxFfH2kBZuqrlsKs2tQBGi3UzIQBCmxL67trB3L7Vk26REcFp7wkj1Dd rXBhaaHOYFtjnCEiYv/6JOeo/cnMxX89KCrMKy+yXypK8dDMdk3ohpwjlBcVDrU2nAVG NHCmJft3LidBo8Y7lAcuMoxYSWKdoQhhMljJFfTrGY428O8ywENkxrhSB4IwVaAGvLGx hagIdEQ8DM4xNPXD3Kw9IssVdLlTeB69IWiSR24Ak4fht072PqcAEAWdamZ6+T9UvyYA h80S5IlHdlsNo/QnJeIcpKDphmsO2u4R4oOX2oIcwQIwsOgf9r34ote8wU90nu4+Wu9k o0kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EGU+/MpxT8YGsEWvI+W5cKlSVCq/nVM+/LNMb9QzO4c=; b=K+A2kRQMhWsdRH52aztsR9K6goBbizouxdKHw+v6ZpHkymYtENS6jYUW5D8lx2L6QY efu8EJsss6TdSLj5thL8LTwKIJw2SiuIdxFFlq6NO/2gktgXbPgl5kQwnKKYuy2mkrax /bMOEL4mX6zlkVJr/jUJyuERH2OATbeNptr+IBAHFUHs1tEzvCMReETHlM7pSpPN9rRt oaWH4ggwUfuqMmzz0FMTJ6Vm2lm4QcKZFYYiJRGaWt1KmsWCwC2VaVDwhc8hUcUh3zmt 2VEsiCHeGdB1Bps87VfLWW5p+BpmHtr4MBpOjuMJ61ZEi5xfcfq1JJiTjen5YkAuiJy3 abDw== X-Gm-Message-State: APjAAAWIdZtasPNBXd5hp4DUlKWvSUPNJQqy3kOi5BvchSiFzNEwyzI5 IUb96/BbQGMR3wGOzy9ARFPkkg== X-Google-Smtp-Source: APXvYqxMQVQ0c1c2tYLsA8gBlQWBr8kNv1iLHwt/IedU9qG50h+w9Mx613ojRnZLxVngj+m1WHHQJQ== X-Received: by 2002:adf:df10:: with SMTP id y16mr140679568wrl.302.1565010596914; Mon, 05 Aug 2019 06:09:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 5 Aug 2019 14:09:52 +0100 Message-Id: <20190805130952.4415-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190805130952.4415-1-peter.maydell@linaro.org> References: <20190805130952.4415-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 2/2] target/arm: Fix routing of singlestep exceptions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When generating an architectural single-step exception we were routing it to the "default exception level", which is to say the same exception level we execute at except that EL0 exceptions go to EL1. This is incorrect because the debug exception level can be configured by the guest for situations such as single stepping of EL0 and EL1 code by EL2. We have to track the target debug exception level in the TB flags, because it is dependent on CPU state like HCR_EL2.TGE and MDCR_EL2.TDE. (That we were previously calling the arm_debug_target_el() function to determine dc->ss_same_el is itself a bug, though one that would only have manifested as incorrect syndrome information.) Since we are out of TB flag bits unless we want to expand into the cs_base field, we share some bits with the M-profile only HANDLER and STACKCHECK bits, since only A-profile has this singlestep. Fixes: https://bugs.launchpad.net/qemu/+bug/1838913 Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- In theory it would be possible to use just a single TB flag bit, because other than the route_to_el2 bool, all the state arm_debug_target_el() checks is either constant or known from other TB flags. But I think trying to do this would be pretty hard to maintain and might well break anyway with future architectural changes. Slightly less painfully we could reclaim the existing TBFLAG_ANY_SS_ACTIVE, since the debug target EL can't be 0 and is irrelevant if SS is not active, so we could arrange for SS_ACTIVE to be DEBUG_TARGET_EL =3D=3D 0. But we're going to have to overspill into cs_base pretty soon anyway so I'm not too keen on being very stingy with the current flags word at the expense of maintainability. --- target/arm/cpu.h | 5 +++++ target/arm/translate.h | 15 +++++++++++---- target/arm/helper.c | 6 ++++++ target/arm/translate-a64.c | 2 +- target/arm/translate.c | 4 +++- 5 files changed, 26 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 94c990cddbd..23ca6c79144 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3142,6 +3142,11 @@ FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) FIELD(TBFLAG_ANY, BE_DATA, 23, 1) +/* + * For A-profile only, target EL for debug exceptions. + * Note that this overlaps with the M-profile-only HANDLER and STACKCHECK = bits. + */ +FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) =20 /* Bit usage when in AArch32 state: */ FIELD(TBFLAG_A32, THUMB, 0, 1) diff --git a/target/arm/translate.h b/target/arm/translate.h index 45053190baa..b65954c669b 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -50,6 +50,8 @@ typedef struct DisasContext { uint32_t svc_imm; int aarch64; int current_el; + /* Debug target exception level for single-step exceptions */ + int debug_target_el; GHashTable *cp_regs; uint64_t features; /* CPU features bits */ /* Because unallocated encodings generate different exception syndrome @@ -70,8 +72,6 @@ typedef struct DisasContext { * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. */ bool is_ldex; - /* True if a single-step exception will be taken to the current EL */ - bool ss_same_el; /* True if v8.3-PAuth is active. */ bool pauth_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ @@ -251,8 +251,15 @@ static inline void gen_exception(int excp, uint32_t sy= ndrome, /* Generate an architectural singlestep exception */ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) { - gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, isv, ex), - default_exception_el(s)); + bool same_el =3D (s->debug_target_el =3D=3D s->current_el); + + /* + * If singlestep is targeting a lower EL than the current one, + * then s->ss_active must be false and we can never get here. + */ + assert(s->debug_target_el >=3D s->current_el); + + gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target= _el); } =20 /* diff --git a/target/arm/helper.c b/target/arm/helper.c index b74c23a9bc0..24806c16ca2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11170,6 +11170,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, } } =20 + if (!arm_feature(env, ARM_FEATURE_M)) { + int target_el =3D arm_debug_target_el(env); + + flags =3D FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, target_el= ); + } + *pflags =3D flags; *cs_base =3D 0; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f6729b96fd0..90850eadc1b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14180,7 +14180,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->ss_active =3D FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); dc->pstate_ss =3D FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); dc->is_ldex =3D false; - dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); + dc->debug_target_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_= EL); =20 /* Bound the number of insns to execute to those left on the page. */ bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; diff --git a/target/arm/translate.c b/target/arm/translate.c index 19b9d8f2725..b32508cd2f9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11882,7 +11882,9 @@ static void arm_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) dc->ss_active =3D FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); dc->pstate_ss =3D FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); dc->is_ldex =3D false; - dc->ss_same_el =3D false; /* Can't be true since EL_d must be AArch64 = */ + if (!arm_feature(env, ARM_FEATURE_M)) { + dc->debug_target_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TAR= GET_EL); + } =20 dc->page_start =3D dc->base.pc_first & TARGET_PAGE_MASK; =20 --=20 2.20.1