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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.03 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3Vv1PJfuLW2Q3y6jhZwS+VA5WdsiwenJEhdiHqcPU8E=; b=Y6m4R1UgmbocM8caPBMrteJtERSrOeJiLGnM3FPGwmGvHF1A8Jb61r+XJbxj43PlWF B5y6PhvJZrCKursx25LMzydByDVTzhvucAfy446c2Q4hxyNzGTI8d8WiqCWUdberr7Kj XkF89KpMLlQBNygZxWlYdoksgbNQP0iXwFpIz+R4zrGbvRErBodIME22Cm1l62poJiTx qc6O0x1PhiJGWaM6/owU9OxUYbJU6znzRCJNW9CYcJz2fWPj0HeIH0BnErk4XUS4pGCl pH7HGPzyFuuQ/6bX9YtBHNn4C6+JGOb6+kj8V1s07E3xuoVEJ7tmN814k5Qex7Knr9cr 6kTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3Vv1PJfuLW2Q3y6jhZwS+VA5WdsiwenJEhdiHqcPU8E=; b=jtRLRRyCxOzXSGzDunW5m7B3FauPoC9I5pl+566EmjEDJ/fjUP4CAOqtqCPBv9yE8h 0qneSCocOLE6loq+SmRbiOGai8B8kdEoYEDOMqqZEI8hSl66dj/aGjs3I35QB+LQ2cm4 psAzNjcYyRQOJGr0SpQwJxZMSy+wMhtmGGThC5AK/qtiXzxfrgHawpxoVmqE6bbsgViO CjyEQ6EzRzCEywM+1XvfJG022vFjMHABYQpgVbTWFtxoKLhWg0iBECzeLqWWlcbDuGdQ VS0d4LM2/7k34swRDuBYDQ7inhh+N/NDCgeSvsYfZYu2ZI0rfF3CtSAYHvTjwVzbum/S Yn7g== X-Gm-Message-State: APjAAAWYbgU6BspKQtHH2TdLLQw0zZUBuWfge2423v0ZDc+tbuZpfui0 NPtqzFoJ0Ym13hitq2pi8OwC5jUeTV4= X-Google-Smtp-Source: APXvYqwElKJuSKp+zFrcUjqRod6t4pk2yXi5P8txvmjGa8EcrsWx5h0RSCHbx4q4R95sSU+q8ZKxgQ== X-Received: by 2002:a17:902:f082:: with SMTP id go2mr143791348plb.25.1564858084208; Sat, 03 Aug 2019 11:48:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:27 -0700 Message-Id: <20190803184800.8221-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 01/34] cputlb: Add tlb_set_asid_for_mmuidx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Although we can't do much with ASIDs except remember them, this will allow cleanups within target/ that should make things clearer. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- v2: Assert cpu_is_self; only flush idx w/ asid mismatch. v3: Improve asid comment. --- include/exec/cpu-all.h | 11 +++++++++++ include/exec/cpu-defs.h | 2 ++ include/exec/exec-all.h | 19 +++++++++++++++++++ accel/tcg/cputlb.c | 26 ++++++++++++++++++++++++++ 4 files changed, 58 insertions(+) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 536ea58f81..40b140cbba 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -439,4 +439,15 @@ static inline CPUTLB *env_tlb(CPUArchState *env) return &env_neg(env)->tlb; } =20 +/** + * cpu_tlb(env) + * @cpu: The generic CPUState + * + * Return the CPUTLB state associated with the cpu. + */ +static inline CPUTLB *cpu_tlb(CPUState *cpu) +{ + return &cpu_neg(cpu)->tlb; +} + #endif /* CPU_ALL_H */ diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 9bc713a70b..b42986d822 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -169,6 +169,8 @@ typedef struct CPUTLBDesc { size_t n_used_entries; /* The next index to use in the tlb victim table. */ size_t vindex; + /* The current ASID for this tlb, if used; otherwise ignored. */ + uint32_t asid; /* The tlb victim table, in two parts. */ CPUTLBEntry vtable[CPU_VTLB_SIZE]; CPUIOTLBEntry viotlb[CPU_VTLB_SIZE]; diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 16034ee651..9c77aa5bf9 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -225,6 +225,21 @@ void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint1= 6_t idxmap); * depend on when the guests translation ends the TB. */ void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); +/** + * tlb_set_asid_for_mmuidx: + * @cpu: Originating cpu + * @asid: Address Space Identifier + * @idxmap: bitmap of MMU indexes to set to @asid + * @depmap: bitmap of dependent MMU indexes + * + * Set an ASID for all of @idxmap. If any previous ASID was different, + * then we will flush the mmu idx. If a flush is required, then also flush + * all dependent mmu indicies in @depmap. This latter is typically used + * for secondary page resolution, for implementing virtualization within + * the guest. + */ +void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid, + uint16_t idxmap, uint16_t dep_idxmap); /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for @@ -310,6 +325,10 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced= (CPUState *cpu, uint16_t idxmap) { } +static inline void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid, + uint16_t idxmap, uint16_t depma= p) +{ +} #endif =20 #define CODE_GEN_ALIGN 16 /* must be >=3D of the size of a icach= e line */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index bb9897b25a..c68f57755b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -540,6 +540,32 @@ void tlb_flush_page_all_cpus_synced(CPUState *src, tar= get_ulong addr) tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); } =20 +void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid, uint16_t idxmap, + uint16_t depmap) +{ + CPUTLB *tlb =3D cpu_tlb(cpu); + uint16_t work, to_flush =3D 0; + + /* It doesn't make sense to set context across cpus. */ + assert_cpu_is_self(cpu); + + /* + * We don't support ASIDs except for trivially. + * If there is any change, then we must flush the TLB. + */ + for (work =3D idxmap; work !=3D 0; work &=3D work - 1) { + int mmu_idx =3D ctz32(work); + if (tlb->d[mmu_idx].asid !=3D asid) { + tlb->d[mmu_idx].asid =3D asid; + to_flush |=3D 1 << mmu_idx; + } + } + if (to_flush) { + to_flush |=3D depmap; + tlb_flush_by_mmuidx_async_work(cpu, RUN_ON_CPU_HOST_INT(to_flush)); + } +} + /* update the TLBs so that writes to code in the virtual page 'addr' can be detected */ void tlb_protect_code(ram_addr_t ram_addr) --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858205; cv=none; d=zoho.com; s=zohoarc; b=INxwXOTBL8V59gZ/s9FG2GL5reZie0k1GcUR0Pyjniv8UUQlmq15kZ04u+RiS/nNNjIwH6RjGVGabhxGOUVlld3qrkEIf4DniqFzEHNeMngHQgB5U4QhUuKTJ8guksazr1KE5F6O6TOu1iOCJKmqoZNmQ9+IZw0Qpx7U4tNgcvw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858205; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=OzH9oAANiLbbz3MZqOd0740wSKDkRIpOzsZLTONmMZs=; b=fOlFvyAPkw+4Gk08yanopGPuFdFyfn8/+mlbUwLAvY2iH4PUlbJCbHhNkGyIvPV+CTEBQU6P0TXHnu0DtKwsS0kX0fJRo9RxnsQ+yk8niAtEPrtkscbqgB8+9eI6p9orMoU1QJbtW8H81P57vlVvCD3oOdqzhHGkeLIhlqKDdjs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858205373228.06537666035183; Sat, 3 Aug 2019 11:50:05 -0700 (PDT) Received: from localhost ([::1]:41360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz6S-0001Mr-FG for importer@patchew.org; Sat, 03 Aug 2019 14:50:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60495) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz4a-0005vH-3K for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz4Y-00075V-OO for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:08 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:40878) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz4Y-00074y-J2 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:06 -0400 Received: by mail-pf1-x443.google.com with SMTP id p184so37618535pfp.7 for ; Sat, 03 Aug 2019 11:48:06 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.04 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OzH9oAANiLbbz3MZqOd0740wSKDkRIpOzsZLTONmMZs=; b=POoyQ7p+raLFWdXdMAzpyzaP2JaDBIv6nyVaZb9BfgIy2h7Mrrv6IJN3cSSEJntlw5 fyjBeZs76EWn/Or6CbrU6PLJ1BCKSmRURYCh4ha3iDIM+5H4TlNZPQdCdwiX5W9Fp0Ee aswnR4wlqWtWQXx2paH4aGQY1c09aAtCPGHlqIQFNTe5xZgzADjy6HMgjLbaiCAlDmRs hhe/82vasY2whCT2XBPfo/RsXzWAh3RH9J/ywRIinWZ58/xgy3dkpNzVgCKgV8FvkYcC 4iXcMs8vs3kMvuW0wVWCymak7Ouftt5En+eVh42Dr1EM1IHppVJKxWULZeme/RoHJKWT a2uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OzH9oAANiLbbz3MZqOd0740wSKDkRIpOzsZLTONmMZs=; b=G8Vwueu4DCcV72hxMCKddVYazxtV8S5YDmepDfcefUUOu+X6syHDkLlHzckFCKlL/a K61eU/cIVD+EQSSkNQjM1VUjj5MiuQoGo2PuiLPvE7S6UM3UAMpeLX0H10osPkVTmzCF lWrTJlth9pqod6gU4rcnLvmyDd0OyZEFkSdmBDAZlcu6fU0U2dAcR4pHRgGREWqaLHkW JlQj06HQDigybmgcE3pkGdau5ZGvoc6ccYwrF2cW/DVeVFcqS35kT2ye1WIMywirn++4 lLrbmKrXDBfnz9nRErHyTOMIZzGM8VDWgOcKfX3Sx91qjyuRpA4cgAb20FQz41L8PRCL QuSg== X-Gm-Message-State: APjAAAWG7EZI1rfZsQBlinFBFpdz6SNc1gEdUoKgwLO4+CiOknTCPjmx mLSqjI5CKeNw44tc6PG56DcKCpjo4g8= X-Google-Smtp-Source: APXvYqwTLu7ABi2FWZUOwwgpSILNwSA+C/RSS5DD/SvL/tVWU2hv+DPvqD1M9Ws27BnCjY9yntlgyw== X-Received: by 2002:a63:8a49:: with SMTP id y70mr35691142pgd.271.1564858085297; Sat, 03 Aug 2019 11:48:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:28 -0700 Message-Id: <20190803184800.8221-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 02/34] cputlb: Add tlb_flush_asid_by_mmuidx and friends X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Since we have remembered ASIDs, we can further minimize flushing by comparing against the one we want to flush. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 16 ++++++++++++ include/qom/cpu.h | 2 ++ accel/tcg/cputlb.c | 55 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 9c77aa5bf9..0d890e1e60 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -240,6 +240,22 @@ void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu= , uint16_t idxmap); */ void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid, uint16_t idxmap, uint16_t dep_idxmap); +/** + * tlb_flush_asid_by_mmuidx: + * @cpu: Originating CPU of the flush + * @asid: Address Space Identifier + * @idxmap: bitmap of MMU indexes to flush if asid matches + * + * For each mmu index, if @asid matches the value previously saved via + * tlb_set_asid_for_mmuidx, flush the index. + */ +void tlb_flush_asid_by_mmuidx(CPUState *cpu, uint32_t asid, uint16_t idxma= p); +/* Similarly, broadcasting to all cpus. */ +void tlb_flush_asid_by_mmuidx_all_cpus(CPUState *cpu, uint32_t asid, + uint16_t idxmap); +/* Similarly, waiting for the broadcast to complete. */ +void tlb_flush_asid_by_mmuidx_all_cpus_synced(CPUState *cpu, uint32_t asid, + uint16_t idxmap); /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 5ee0046b62..c072dd4c47 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -285,12 +285,14 @@ typedef union { unsigned long host_ulong; void *host_ptr; vaddr target_ptr; + uint64_t uint64; } run_on_cpu_data; =20 #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr =3D (p)}) #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int =3D (i)}) #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong =3D (ul)}) #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr =3D (v)}) +#define RUN_ON_CPU_UINT64(i) ((run_on_cpu_data){.uint64 =3D (i)}) #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) =20 typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c68f57755b..62baaa9ca6 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -540,6 +540,61 @@ void tlb_flush_page_all_cpus_synced(CPUState *src, tar= get_ulong addr) tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); } =20 +static void tlb_flush_asid_by_mmuidx_async_work(CPUState *cpu, + run_on_cpu_data data) +{ + CPUTLB *tlb =3D cpu_tlb(cpu); + uint32_t asid =3D data.uint64; + uint16_t idxmap =3D data.uint64 >> 32; + uint16_t to_flush =3D 0, work; + + assert_cpu_is_self(cpu); + + for (work =3D idxmap; work !=3D 0; work &=3D work - 1) { + int mmu_idx =3D ctz32(work); + if (tlb->d[mmu_idx].asid =3D=3D asid) { + to_flush |=3D 1 << mmu_idx; + } + } + + if (to_flush) { + tlb_flush_by_mmuidx_async_work(cpu, RUN_ON_CPU_HOST_INT(to_flush)); + } +} + +void tlb_flush_asid_by_mmuidx(CPUState *cpu, uint32_t asid, uint16_t idxma= p) +{ + uint64_t asid_idx =3D deposit64(asid, 32, 32, idxmap); + + if (cpu->created && !qemu_cpu_is_self(cpu)) { + async_run_on_cpu(cpu, tlb_flush_asid_by_mmuidx_async_work, + RUN_ON_CPU_UINT64(asid_idx)); + } else { + tlb_flush_asid_by_mmuidx_async_work(cpu, RUN_ON_CPU_UINT64(asid_id= x)); + } +} + +void tlb_flush_asid_by_mmuidx_all_cpus(CPUState *src_cpu, + uint32_t asid, uint16_t idxmap) +{ + uint64_t asid_idx =3D deposit64(asid, 32, 32, idxmap); + + flush_all_helper(src_cpu, tlb_flush_asid_by_mmuidx_async_work, + RUN_ON_CPU_UINT64(asid_idx)); + tlb_flush_asid_by_mmuidx_async_work(src_cpu, RUN_ON_CPU_UINT64(asid_id= x)); +} + +void tlb_flush_asid_by_mmuidx_all_cpus_synced(CPUState *src_cpu, + uint32_t asid, uint16_t idxm= ap) +{ + uint64_t asid_idx =3D deposit64(asid, 32, 32, idxmap); + + flush_all_helper(src_cpu, tlb_flush_asid_by_mmuidx_async_work, + RUN_ON_CPU_UINT64(asid_idx)); + async_safe_run_on_cpu(src_cpu, tlb_flush_asid_by_mmuidx_async_work, + RUN_ON_CPU_UINT64(asid_idx)); +} + void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid, uint16_t idxmap, uint16_t depmap) { --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.05 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZRDl/Ha+kclTizhs/nHDa+7096PsBT003cOS/ic3LTY=; b=gO1RyuEd4amyO2ZioV4wbCAXOswiL3HZaFPh3uZiBfDdBs1Hxj4qjpDVT1qE0w/Y/2 TCd2HoUEIsZPPem9Sz4MGxM/lb1njDYhPyBetZ/OwHnPIEzVBjbKvUEgzkOgoR7OROsX 6ZpH958pzmLMtWIKbj5Y4qSTIb//ClcMqUwrWF171EWHWOApxSfxo3aGH5/NWGz9Mkcf 7tGdzP7xNMG3EGKmDxY9z/BV/WmykaIb3Ly0LCXkcQ69cDzoIi3wfnUrz/9eFRauToxG 4zQ6QIJUBVIpNf21r0pUdtcFJya++VW7hA8RaVngSFKC9duw8Agsy07xLAL5UiIw99KD xv1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZRDl/Ha+kclTizhs/nHDa+7096PsBT003cOS/ic3LTY=; b=JPhRNJPyK7BD2gA73Y8EYBCvOnTVVbW3P7OxudxFbDibcK+cGTAOI1psqxuGrVC56h YGpqC+EsJak9sn6OuF/ekeEdQZ0J8f/wJN/6IqOznfkFJMUstcH6EXbbSv4PKpejI9ZF QuWdUe/zB54GDWnSFVgXOVpa9xYbUCNn9n/RbnKT5em/vYw4Rou/XOyf5deWaO0L5oFD ua8B+iMKnVRASbdVWLhT+hAov9CSxDOCmqGu1nBNcLJ+tlQeEwqb8K2rj4zbBgIprj8G JegF+bdjH4MW+/Ieahbhlk11KIGdSmLqZTj7PiGTWaLJZadk9zOK7yGns+zxsk7YVB6U IhWg== X-Gm-Message-State: APjAAAVPoUEUkLFREKb8LxArpqz8KYHjuGfEcsQeSYy1OGQ5XTdlyWVv wkxWc1hkjYIYUadbV3N6Un8CXOjsQao= X-Google-Smtp-Source: APXvYqyQADm81TOq7pTG3uu8C1tSxFfVRBTYH3eUA/V0wxpc15KUvnS2t3SKs/oEQ28Fzd7eP77Ppw== X-Received: by 2002:a17:902:8a8a:: with SMTP id p10mr139797676plo.88.1564858086446; Sat, 03 Aug 2019 11:48:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:29 -0700 Message-Id: <20190803184800.8221-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 03/34] target/arm: Install ASIDs for long-form from EL1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) In addition to providing the core with the current ASID, this minimizes both the number of flushes due to non-changing ASID as well as the set of mmu_idx that are affected by each flush. In particular, updates to the secure mode registers flushes only the relevant secure mode mmu_idx's, and similarly non-secure updates only affect non-secure mmu_idx's. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.c | 73 +++++++++++++++++++++++++++++---------------- 1 file changed, 48 insertions(+), 25 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b74c23a9bc..2a65f4127e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3327,6 +3327,36 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +/* Called after a change to any of TTBR*_EL1 or TTBCR_EL1. */ +static void update_lpae_el1_asid(CPUARMState *env, int secure) +{ + CPUState *cs =3D env_cpu(env); + uint64_t ttbr0, ttbr1, ttcr; + int asid, idxmask; + + switch (secure) { + case ARM_CP_SECSTATE_S: + ttbr0 =3D env->cp15.ttbr0_s; + ttbr1 =3D env->cp15.ttbr1_s; + ttcr =3D env->cp15.tcr_el[3].raw_tcr; + /* Note that cp15.ttbr0_s =3D=3D cp15.ttbr0_el[3], so S1E3 is affe= cted. */ + /* ??? Secure EL3 really using the ASID field? Doesn't make sense= . */ + idxmask =3D ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0 | ARMMMUIdxBit= _S1E3; + break; + case ARM_CP_SECSTATE_NS: + ttbr0 =3D env->cp15.ttbr0_ns; + ttbr1 =3D env->cp15.ttbr1_ns; + ttcr =3D env->cp15.tcr_el[1].raw_tcr; + idxmask =3D ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + break; + default: + g_assert_not_reached(); + } + asid =3D extract64(ttcr & TTBCR_A1 ? ttbr1 : ttbr0, 48, 16); + + tlb_set_asid_for_mmuidx(cs, asid, idxmask, 0); +} + static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -3363,18 +3393,16 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, = const ARMCPRegInfo *ri, static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D env_archcpu(env); TCR *tcr =3D raw_ptr(env, ri); =20 - if (arm_feature(env, ARM_FEATURE_LPAE)) { - /* With LPAE the TTBCR could result in a change of ASID - * via the TTBCR.A1 bit, so do a TLB flush. - */ - tlb_flush(CPU(cpu)); - } /* Preserve the high half of TCR_EL1, set via TTBCR2. */ value =3D deposit64(tcr->raw_tcr, 0, 32, value); vmsa_ttbcr_raw_write(env, ri, value); + + if (arm_feature(env, ARM_FEATURE_LPAE)) { + /* The A1 bit controls which ASID is active. */ + update_lpae_el1_asid(env, ri->secure); + } } =20 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) @@ -3392,24 +3420,19 @@ static void vmsa_ttbcr_reset(CPUARMState *env, cons= t ARMCPRegInfo *ri) static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D env_archcpu(env); - TCR *tcr =3D raw_ptr(env, ri); - - /* For AArch64 the A1 bit could result in a change of ASID, so TLB flu= sh. */ - tlb_flush(CPU(cpu)); - tcr->raw_tcr =3D value; + raw_write(env, ri, value); + /* The A1 bit controls which ASID is active. */ + update_lpae_el1_asid(env, ri->secure); } =20 -static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void vmsa_ttbr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { - /* If the ASID changes (with a 64-bit write), we must flush the TLB. = */ - if (cpreg_field_is_64bit(ri) && - extract64(raw_read(env, ri) ^ value, 48, 16) !=3D 0) { - ARMCPU *cpu =3D env_archcpu(env); - tlb_flush(CPU(cpu)); - } raw_write(env, ri, value); + if (cpreg_field_is_64bit(ri)) { + /* The LPAE format (64-bit write) contains an ASID field. */ + update_lpae_el1_asid(env, ri->secure); + } } =20 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3455,12 +3478,12 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .writefn =3D vmsa_ttbr_el1_write, .resetvalue = =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .writefn =3D vmsa_ttbr_el1_write, .resetvalue = =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, @@ -3715,12 +3738,12 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr_el1_write, }, { .name =3D "TTBR1", .cp =3D 15, .crm =3D 2, .opc1 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr_el1_write, }, REGINFO_SENTINEL }; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.06 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7Rs0ix/SYQKzQx2FXXQO106tmFBYyCQIrr3vAmMEheQ=; b=vPvHAofjDh13cvA96WTwyjFAdTULJbdQ9ybEFKJfgyYtqSaKhbOjXvki83K0xHqo11 MtokYAYkf6sRn5wnU8jQawtxscZaTYUt+AZIExuMd1wZejf8tNQ1Sfi6yxddylozCGR/ KI3d3Rybp77SktK7y2d1h68Tj9aKww6QaRRuuj7ZE2Xy+9SpsnqN9lAlrxLWQFKD7vEE I2URa8cgSieAlS83ATnACU2iiRE5N6FtxZip8dABXOGRbmKe4f+YImVa8ivdnw9kphBN CKon3LMB/w6/XtDeZ5S1GPpYRfDlXnJscrpe8roUK+OHwU7g6ePJvDppWqhMq/fls1hc zdZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7Rs0ix/SYQKzQx2FXXQO106tmFBYyCQIrr3vAmMEheQ=; b=gQDFDBUKwyjrmJNxdsNzOfsPuQelXkxar2cyk05AbzOw3g4mGgDB/oeOkXdwGQ9wzU hthGnm6TL8WRZuCxgxQ4qHtO5R+VMz6EXFDRsqjbI2VcKxtryZdUzaTQOqYLyUudVeod DVuxxM7Q13qa99+Oy6sNtOT/5m0AZldm947YdmP3OqAU7kjNfRo9kgiwBTxmwblZXxBr Nv0D1S3dW4roaug4NqjAu796pqWo+CfSCjYJNRKlPKmKeojkqY/Q8TloFJ0+ZNG5rwHm JJmdGouK4hS5LqpUla0I+N4TkwwUbIB85C5eB/eu655S8FlSD82gMgSTstRX0MJlTY9A wk7g== X-Gm-Message-State: APjAAAWQ52FFqrnek7zauEwPhM6j6/Xz245CAFVAUade1F1Cy4xpupkM SMB2IfGqxkl+lgsPvC+azcyh85NFWu4= X-Google-Smtp-Source: APXvYqwfqGKZuSNSsCvI/U31pcyp3UPCGhi9soCIZOjfGaoy0K/asXvr35NSg45u3lrQ2vhhDIUEkA== X-Received: by 2002:aa7:97b7:: with SMTP id d23mr68186838pfq.203.1564858087487; Sat, 03 Aug 2019 11:48:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:30 -0700 Message-Id: <20190803184800.8221-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 04/34] target/arm: Install ASIDs for short-form from EL1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This is less complex than the LPAE case, but still we now avoid the flush in case it is only the PROCID field that is changing. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.c | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2a65f4127e..c0dc76ed41 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -551,17 +551,31 @@ static void fcse_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D env_archcpu(env); - - if (raw_read(env, ri) !=3D value && !arm_feature(env, ARM_FEATURE_PMSA) - && !extended_addresses_enabled(env)) { - /* For VMSA (when not using the LPAE long descriptor page table - * format) this register includes the ASID, so do a TLB flush. - * For PMSA it is purely a process ID and no action is needed. - */ - tlb_flush(CPU(cpu)); - } raw_write(env, ri, value); + + /* + * For VMSA (when not using the LPAE long descriptor page table format) + * this register includes the ASID. For PMSA it is purely a process ID + * and no action is needed. + */ + if (!arm_feature(env, ARM_FEATURE_PMSA) && + !extended_addresses_enabled(env)) { + CPUState *cs =3D env_cpu(env); + int asid =3D extract32(value, 0, 8); + int idxmask; + + switch (ri->secure) { + case ARM_CP_SECSTATE_S: + idxmask =3D ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + break; + case ARM_CP_SECSTATE_NS: + idxmask =3D ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + break; + default: + g_assert_not_reached(); + } + tlb_set_asid_for_mmuidx(cs, asid, idxmask, 0); + } } =20 /* IS variants of TLB operations must affect all cores */ --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858178; cv=none; d=zoho.com; s=zohoarc; b=COviDXzT8BEpNQpw86Oir1d86kFHCQ7A6vbL8vMM8Tr4QPxtomjEEOgsZp2ZzCJtWbp1k5icg92HkQjb9Uy576i3t5K4ZZuutUnAdHo9jJFE87yYKNVYGKhRLem703xv7QldpoWFOhRi7cDPOW0XhtM3Z4Gf4zU11ad+VJqCCd8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858178; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=hV2eslCkM9+11E22XGBDo1tPxuDz+vxwGvc3iXR5Q+U=; b=dpfWe69IdjsUV3rJZbvTdYFpmr4txxpZWOjIQwkb72I8f2JGviaK7/bMIqjg8DNrnkIvGVz5rRfBRGtL3rrELVVBElUmUrqdPnlbtT2T3s0By1OaZkkap44YfdNlSVLR82NTqo2YqnWdiWuhD6bu1ax4dusrKyxp71Mr0NqygAs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858178334223.48742713132276; Sat, 3 Aug 2019 11:49:38 -0700 (PDT) Received: from localhost ([::1]:41352 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz61-0008Gi-De for importer@patchew.org; Sat, 03 Aug 2019 14:49:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60581) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz4c-00063Q-T8 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz4b-00077s-TD for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:10 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:42853) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz4b-00077L-OA for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:09 -0400 Received: by mail-pf1-x443.google.com with SMTP id q10so37607192pff.9 for ; Sat, 03 Aug 2019 11:48:09 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.07 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hV2eslCkM9+11E22XGBDo1tPxuDz+vxwGvc3iXR5Q+U=; b=zeuwLZaLsuKqWvo0H7Lao3Xmq/IJ/PIq5u1FH0Yo7+Ni0P3R68YJHjwxjMrTtuaWjv 6UIrxJop+hOjmQMKQmGyUtp6T3hEuNYSt7wzQQZMeD4Whyg71621DfHr+ZDL3FNabgcM Ei6YZ1Qjm2qvwsPMXDbAodapGHrzDuKJ3WFjUAlA8hwRKF4hZoqaVeY8Cy4Zf5EQD70Q toso8YjoLAGaQ0ePImuSya6uKEGRuNX4Z83FoB9B2hX682K7shVPM9hj7y+Jn0ZN4wQE 8sVIe+ORce9HBYoAAavsZ0O0+Lb03HwTAA2v7x85Sf2HmI6PUWezWG7TUkVOBoRkMEhK GWZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hV2eslCkM9+11E22XGBDo1tPxuDz+vxwGvc3iXR5Q+U=; b=gm5CXamxZzmKFIFap4ZPFWc2mAuJjcqKYvxBE35igQ7PR1wHlBAQ4icG7YwMO65iUo guviJeT0CgEFFyEpAySZ2nXQjbwblf1tiRwtowtqACC9MaCWIDWrRpamIO02tp5wyw6r SUyNwv0Of8o+/eDTFWi30T4En4ZiYJrDhOr8k3OHl0VQHhg8IEIrCUZq1fm7uKqHEeVI 7qD8zF1l2GuXEecSyHfD0sNdxwrRpIkzjIvUjRYdnacvmpISX+EKoe+qKMlftEauGgP5 mVpfzYY81wQ2wHg7do5eSmc80gUq4G+GVvBbGzkmEf/JCpspwf8RofDRPSURZ6RPj/SL Oxsg== X-Gm-Message-State: APjAAAV/nyIJ4/7OsdaTYCwg+53KuMvCKMsFxz+Hr/+RkPHkrFTXruxv 18UVAwwLb49aYTnNBIXkdojX0T3YAYw= X-Google-Smtp-Source: APXvYqw50D1tcuFilG+lYYxJAjSIostRpVb5BrDCxdOpOTlicOOpTPm5TWnKVhKHX8m23N4E7EEppA== X-Received: by 2002:a62:8246:: with SMTP id w67mr67312952pfd.226.1564858088554; Sat, 03 Aug 2019 11:48:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:31 -0700 Message-Id: <20190803184800.8221-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 05/34] target/arm: Install ASIDs for EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The VMID is the ASID for the 2nd stage page lookup. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c0dc76ed41..65e3ffbb43 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3452,17 +3452,23 @@ static void vmsa_ttbr_el1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int vmid; =20 - /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ - if (raw_read(env, ri) !=3D value) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - raw_write(env, ri, value); - } + raw_write(env, ri, value); + + /* + * TODO: with ARMv8.1-VMID16, aarch64 must examine VTCR.VS + * (re-evaluating with changes to VTCR) then use bits [63:48]. + */ + vmid =3D extract64(value, 48, 8); + + /* + * A change in VMID to the stage2 page table (S2NS) invalidates + * the combined stage 1&2 tlbs (S12NSE1 and S12NSE0). + */ + tlb_set_asid_for_mmuidx(cs, vmid, ARMMMUIdxBit_S2NS, + ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0); } =20 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858276; cv=none; d=zoho.com; s=zohoarc; b=TMZwIz7/01Rr6/S4EgByee7P+6FkpJ4U9778QmSOE9yaT9jkEycSDjbYYgXLnqBfrl2hSn+piZZpgM0DMcvp9e5MDukuLhr4jZdqzMuS7gyfyZJmg5yyTHPJuMnqrs/5l02TVJBiprnCZyfH8c2f5Y3MnCWN8oyJKalWWw7Yjws= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858276; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=6IeFtwkeZbBPVLT5Rmllb3ExAsBhlKcdIq9EZhAeEOQ=; b=mC7Cn6o/u7V5ezauJS/eKzmpFgbkFEvPJjZ9KlGcb7bxk7PZHBjly3m9RnimnM/2bPo8IM09LOKMKx951damLrXKv6IwAWgcpeuaWYMDUsW0Ny2ia5yQtjx9rc1SlP6a03sHtvevb2HFsGCaHIh1Cyzf+pglvOlh/mH3vCLrC6Q= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858276377446.4777473347481; Sat, 3 Aug 2019 11:51:16 -0700 (PDT) Received: from localhost ([::1]:41382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz7b-0003cq-4p for importer@patchew.org; Sat, 03 Aug 2019 14:51:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60614) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz4e-00066g-AI for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz4d-000792-B7 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:12 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:35702) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz4d-00078X-6U for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:11 -0400 Received: by mail-pf1-x442.google.com with SMTP id u14so37642037pfn.2 for ; Sat, 03 Aug 2019 11:48:11 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.08 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6IeFtwkeZbBPVLT5Rmllb3ExAsBhlKcdIq9EZhAeEOQ=; b=EsBd2ZXyAs12YJkUflSxdyWDy4dQ1VA7S1sjPBpz/feC0S7PjxPutW98hpXE48BQqZ duze6YgLkmYtrK/9qzMMjqatC1CnyovW9Detsfq/azWI7VgxbyYirVQXMBjlehgbmcJY HfD0KpZXBfFvIAEmRtEXUO08hR5q6CKDMYULvli7jPWnoV3G828NSM8kGVuPxfXO3OPh PJhqZ3T4pSzJaVcrVBP52obs3ZUOSQESU5L4W+37vtXyru47NuaJCbF5BVYq754WLFDi d5+Lr6uoqePJXIa+64fy6wIuJIy/7nc3ggwjX93XLCoF3qE/rU07bekJKepVfBI8MAtS 7KTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6IeFtwkeZbBPVLT5Rmllb3ExAsBhlKcdIq9EZhAeEOQ=; b=cf9eId0d4xND7iDdrhWFiLjvakS92V4+czPW4EvFxsBFpALFqL2HiqzXmReZiyj4lG G1i1rn2g56WdpL7nmE4Kso88KEQaTj2sg0cBLFzRQGb264MZxDgJ70XG+aFxflMm0+4/ CPXAP+5dVmSWNvDScfYERSwzAZ/ClV3f+83pLekJo8pEWgl0UseJgVEX6XlLq8wDUFsw 30ZtKSGZCC0jemKHL6LfhI7tntQb30FrMBLqZqdpH5Q1QtOyPed9E1EJFwqqwMzTXreZ wbdYVIfLn7VrONypKqHTKZ35kRA6x2qqIvQsU5gZl/O3s3PygMDNziTomB+vLYEeOkuw WPvQ== X-Gm-Message-State: APjAAAX+9o0x5rPs4V6RFa8B6h20EFKVQcT+Rzz3egxBwK5rbZTl/oFf mNYHJlX/NSpiQfCryIHEDHZApIVWjyU= X-Google-Smtp-Source: APXvYqwXV2QxS3KeOZOgNnPklX8LG4SYpVuUQA9Dsz7tKOaKwVfMkcm0N83J0qPGGm/xg3pem1KQTg== X-Received: by 2002:a62:28b:: with SMTP id 133mr65294339pfc.251.1564858090005; Sat, 03 Aug 2019 11:48:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:32 -0700 Message-Id: <20190803184800.8221-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 06/34] target/arm: Define isar_feature_aa64_vh X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 94c990cddb..e6a76d14c6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3573,6 +3573,11 @@ static inline bool isar_feature_aa64_sve(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; } =20 +static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; +} + static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) !=3D 0; --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858318; cv=none; d=zoho.com; s=zohoarc; b=F4Msgg9ZDd/9mAXqOTTHt84vLY/EfGy7oGnzui0vkxNS2f4tfUiV7hQgZSiSBJtVunHBbP7SLgA5vKkDJSrFmq7+r2B2VrMwL7IPM7US6pz8D2fOjlVnasFbyL0ABNiCxMEsifJTtdjSLOfM/lLYBharLgsGoxjGSgDnqcW8f6g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858318; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=VC440BcwSuqOKz+Fo7ui0w+dupEF68UzkVylEVc+WDs=; b=jsa5scReRzIbOjFPeNqhYzHQRCKF1MdzMvzS5Wg4tJ634y3y7k6Hucc/RM8CfYioFimwj992OpkJ+G/hoKhco+g1nc1y149i8Fpk6yYooy1cYDnmTHu5eUtE63ns+ovZcwy3e24bxX4wPjXcnQVmw4BYvyXjrBEg4n24eATSSx4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858318955801.8714171818445; Sat, 3 Aug 2019 11:51:58 -0700 (PDT) Received: from localhost ([::1]:41396 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz8I-0005H6-0b for importer@patchew.org; Sat, 03 Aug 2019 14:51:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60644) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz4h-0006CX-5p for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz4e-00079o-R3 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:15 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:45989) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz4e-00079M-MD for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:12 -0400 Received: by mail-pf1-x444.google.com with SMTP id r1so37612157pfq.12 for ; Sat, 03 Aug 2019 11:48:12 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.10 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VC440BcwSuqOKz+Fo7ui0w+dupEF68UzkVylEVc+WDs=; b=xYQqIug3gmfLrgPuAZoKA+vetM7unvOZ/ZGAnj/U508vBjOOKgPiRgD1Kqn26Kleay mnfIK+wozNSd+s4VKGGZldx3aH3FaWGxLPvZSzApdwKxKPn/w3P1WTLmiXsteqysDCl9 5qMHusOO+bNqRwvYOx5bHMiJTfGTve3JxSHWI5s4Fc/AU/EgdvoZDV1W5lK1Hvt6AJyn QjDuCJJieLrHL2oW5lE9Rye5CAhZ1gL07/LDHjywbVZQNj36hHP4+cLTKme9MziVU2eT nury2BWc68bWSp+ZCFqKt7H4fT0FRLejKjejROKZDnI2jgExCs0AaBwKMV86gRws5EIh ialA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VC440BcwSuqOKz+Fo7ui0w+dupEF68UzkVylEVc+WDs=; b=V9/DNaJ+/rXuQq0xAXqOjqdt5ztjvEcCjLcnjNwWT6+WkUK1v4lxTz1bqUgEWkn8wI GvBsXSUeQfqT/maGwUE2dA1ZPI4Wd1OtNQed59aMNOt/3iygLq6WtFILOn9F2oPNQH5H aeBUOYpTS2xwAjf4/SqwnI1uSoIgzm4h/y3bIM3dhdmPX2RRrD5T8uDd66m1NPI6pgg2 Pa5/igTRa6EZtgqChDxINjkn6yvoKf1Ja65SVjytcmSnYe7wkpwPufDXFOV3A5XpDy5z x8lf19Cb9KQP18hmagu13c+6ZQQzkDmdvDjIvmXt9dK+Nb/C3YTQhTsANa3/Ct9UBVf/ 1zGQ== X-Gm-Message-State: APjAAAWVZX+plKFWIvWQJ6uBhDaX2zsUIN1uzlqsJOkXhF7Nwwmfg5vy +A0nRetZyaRFfT1zAW3ezIagl4pnxCM= X-Google-Smtp-Source: APXvYqz6lBWZaB/Djz8xzjkNxK72Fp1Nk7R2FXSOlEzz7gtgzwgysoidHM+p/ov4HizfXtY7fvjwfA== X-Received: by 2002:a62:5c47:: with SMTP id q68mr66933851pfb.205.1564858091413; Sat, 03 Aug 2019 11:48:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:33 -0700 Message-Id: <20190803184800.8221-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 07/34] target/arm: Enable HCR_E2H for VHE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/cpu.h | 7 ------- target/arm/helper.c | 6 +++++- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e6a76d14c6..e37008a4f7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1366,13 +1366,6 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define HCR_ATA (1ULL << 56) #define HCR_DCT (1ULL << 57) =20 -/* - * When we actually implement ARMv8.1-VHE we should add HCR_E2H to - * HCR_MASK and then clear it again if the feature bit is not set in - * hcr_write(). - */ -#define HCR_MASK ((1ULL << 34) - 1) - #define SCR_NS (1U << 0) #define SCR_IRQ (1U << 1) #define SCR_FIQ (1U << 2) diff --git a/target/arm/helper.c b/target/arm/helper.c index 65e3ffbb43..9a18ecf8f6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4623,7 +4623,8 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = =3D { static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) { ARMCPU *cpu =3D env_archcpu(env); - uint64_t valid_mask =3D HCR_MASK; + /* Begin with bits defined in base ARMv8.0. */ + uint64_t valid_mask =3D MAKE_64BIT_MASK(0, 34); =20 if (arm_feature(env, ARM_FEATURE_EL3)) { valid_mask &=3D ~HCR_HCD; @@ -4637,6 +4638,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) */ valid_mask &=3D ~HCR_TSC; } + if (cpu_isar_feature(aa64_vh, cpu)) { + valid_mask |=3D HCR_E2H; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D HCR_TLOR; } --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858421; cv=none; d=zoho.com; s=zohoarc; b=OvHQrnkxPj7cas6VWaxtk4VfUn7V5Axu5NybfLrQgVxXxL/yA6jKzzhPES1DpgulpQsQ28f9tMALcQWEveV7nKqNwhdl1Uj8XM8OCh0V5b+So428AOQh/i2HbbHq6QYSzOvk+pERN5Q0N0wAlEqWnM7+WfH4OyZliJopg8RPOuE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858421; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=BmJBoz3ocCwfjPIQpLnVRF2wr3dk36b5G/HujhxQoNg=; b=GqG7aRjGYblisdjHcAG531adZrJ5Lwzvr3fcoGNvMPopcII4TV/UWCGHSkBGfugqElSQoIwc94rc7fi/cKEY3JdFEKiTUrPvl/Q5KbI35AATCwM9RCrjXy6tBZvttJm+6Gt2t+cjMF1ytOfEfdVQDV2a+T91WO+wHqbdW4Us/5Y= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858421208907.1205787778858; Sat, 3 Aug 2019 11:53:41 -0700 (PDT) Received: from localhost ([::1]:41434 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz9w-000185-7B for importer@patchew.org; Sat, 03 Aug 2019 14:53:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60690) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz4k-0006EG-6L for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz4i-0007B1-06 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:18 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:37966) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz4h-00079z-3Y for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:15 -0400 Received: by mail-pl1-x641.google.com with SMTP id az7so34857647plb.5 for ; Sat, 03 Aug 2019 11:48:13 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.11 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BmJBoz3ocCwfjPIQpLnVRF2wr3dk36b5G/HujhxQoNg=; b=XOuKwYgouGDpkaX6L6Uu/ztO4LamAjukWRR1TU+AbO+9d8EmzEJYGDgd3wbWL+1eQn FoDehmYmUS91lcRg8bfPfB94G6o/PJLpxhj86ESqDCIBvqYfIH3+AH9bJvaa+UdX7iPk jvuhHyVBQD1BGOx1IIU+wgGZN8QBO/0omjs6XaXVN7XIdVAHGJE8Qnc7KKnvmQV+/jyF FLW5nklHtdH2xKYULu3K82i8NFlqdfNFh2giImdOFsgyivibizZVPqg62mqkrvHKEIF4 Vq7/+zZCwlmLTqkj/DomwraVUncNHLrHbGLpQc1/lczLH+39ypVYm5oRoVo0WJvRuhQZ bXSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BmJBoz3ocCwfjPIQpLnVRF2wr3dk36b5G/HujhxQoNg=; b=eek/sgSSHBqLoqQ61ey7tPAVSrFCZqSMNbcg0P1ROrCa0tFSGpp172eQqKLnRH32MO zJv53T8xwScPcXCmDMPh26VqINfIoGk2pquaQL6LJWvp3ZYi9Ro2Op8uXh5/egakL9T7 5qMSrdjJHTslIU9onrw0Yx6yzYmiqmsKI70QI0eplGGrIRgbSMadYCdvoZQ7VezPm+bl nUGmmxXOWp3erhG5dfAU0urwN4/XOlOwr/aui4dx5WL0UUVVxldJrrdPf6xlPIIPfFnZ dxOQ88d++/rgbT2d/EA837q2HgNZD2yAkmm2A+ka5Q/ptUOUpoxmaFVYWLbB05FD18AX lGiw== X-Gm-Message-State: APjAAAV5fIwryGzznebbwrsmIkyhh2nUIUfGORQCFXEYv6rAGyfwgEJc zDE6q2fq8BnEqjeyEm6bShQNuGqO/NM= X-Google-Smtp-Source: APXvYqy3NZ0JwOMcjCjgjaGzWuxYx3JBrhUhZSKO73Lmx08vvEg1w/X1okbZIcUL/2TTKu7mSSGoMQ== X-Received: by 2002:a17:902:bc83:: with SMTP id bb3mr140601680plb.56.1564858092641; Sat, 03 Aug 2019 11:48:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:34 -0700 Message-Id: <20190803184800.8221-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 08/34] target/arm: Add CONTEXTIDR_EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Not all of the breakpoint types are supported, but those that only examine contextidr are extended to support the new register. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/debug_helper.c | 50 +++++++++++++++++++++++++++++---------- target/arm/helper.c | 11 +++++++++ 2 files changed, 49 insertions(+), 12 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index dde80273ff..2e3e90c6a5 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -20,6 +20,7 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) int ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4); int bt; uint32_t contextidr; + uint64_t hcr_el2; =20 /* * Links to unimplemented or non-context aware breakpoints are @@ -40,24 +41,44 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) } =20 bt =3D extract64(bcr, 20, 4); - - /* - * We match the whole register even if this is AArch32 using the - * short descriptor format (in which case it holds both PROCID and ASI= D), - * since we don't implement the optional v7 context ID masking. - */ - contextidr =3D extract64(env->cp15.contextidr_el[1], 0, 32); + hcr_el2 =3D arm_hcr_el2_eff(env); =20 switch (bt) { case 3: /* linked context ID match */ - if (arm_current_el(env) > 1) { - /* Context matches never fire in EL2 or (AArch64) EL3 */ + switch (arm_current_el(env)) { + default: + /* Context matches never fire in AArch64 EL3 */ return false; + case 2: + if (!(hcr_el2 & HCR_E2H)) { + /* Context matches never fire in EL2 without E2H enabled. = */ + return false; + } + contextidr =3D env->cp15.contextidr_el[2]; + break; + case 1: + contextidr =3D env->cp15.contextidr_el[1]; + break; + case 0: + if ((hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)= ) { + contextidr =3D env->cp15.contextidr_el[2]; + } else { + contextidr =3D env->cp15.contextidr_el[1]; + } + break; } - return (contextidr =3D=3D extract64(env->cp15.dbgbvr[lbn], 0, 32)); - case 5: /* linked address mismatch (reserved in AArch64) */ + break; + + case 7: /* linked contextidr_el1 match */ + contextidr =3D env->cp15.contextidr_el[1]; + break; + case 13: /* linked contextidr_el2 match */ + contextidr =3D env->cp15.contextidr_el[2]; + break; + case 9: /* linked VMID match (reserved if no EL2) */ case 11: /* linked context ID and VMID match (reserved if no EL2) */ + case 15: /* linked full context ID match */ default: /* * Links to Unlinked context breakpoints must generate no @@ -66,7 +87,12 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) return false; } =20 - return false; + /* + * We match the whole register even if this is AArch32 using the + * short descriptor format (in which case it holds both PROCID and ASI= D), + * since we don't implement the optional v7 context ID masking. + */ + return contextidr =3D=3D (uint32_t)env->cp15.dbgbvr[lbn]; } =20 static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9a18ecf8f6..8baeb3f319 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6801,6 +6801,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, lor_reginfo); } =20 + if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { + static const ARMCPRegInfo vhe_reginfo[] =3D { + { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D= 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]= ) }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, vhe_reginfo); + } + if (cpu_isar_feature(aa64_sve, cpu)) { define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); if (arm_feature(env, ARM_FEATURE_EL2)) { --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858346; cv=none; d=zoho.com; s=zohoarc; b=Ae+a0+d1ZW1paC/UkYWb+sOXPAefULe0wXTO2zav6GC9YcA68qX8qjz1ZjqQzFN/+X5CqRcG0xbv1hc221aVB3EUmpIkQoqIfq8z/qluMueInp2uDpQXC05FLVK9kiCFrnek7FwcMtQ/B1oqwQBU5y5mnB9W75rxtohJMR88pj0= ARC-Message-Signature: i=1; a=rsa-sha256; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.12 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eXztB5+CPZYWvtJqCXCkkbobp/U8zAPLQueishTnE64=; b=AJ98DjJuyQa8Lr5B1/KRUNoK+ILQGZEY9Jv3+Ww03P6WGufe/CvR8wyHMj88ptaIR4 r0bz8uvJn0E8vEGQoHbmsxXpve9cfB66rxvlVOkP9ljpopFmHG1HcxbH8MWz7/H6q3M6 u95D3jILdArc0uyivXitYvp/ISBhXCsXQvaDnNABaopop/5PgGllnE99riLxlLbRUUc8 2uo3HYe/J1G0KDBaQFEyXM7aXMX/W/5LTHVOxlT+NvzzmkBDKDJxrQZBOVYCfq3ezmxW fV87C/o1zBtN9yOn+zD50rUqX+VBxjFC3dQUVAaej+TKRJgx1ZB5eCkudDlyeWXz1YUf Jtsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eXztB5+CPZYWvtJqCXCkkbobp/U8zAPLQueishTnE64=; b=LJubyNOzmPZGytdygDInN26K8MV3kp6LWEKzNHdvT9t04GdwXiB5bLMJQtjYCS+Vlt KKZ4GTrIpDf2/4WI9hwR0pDGpbkumqrA7kXKe581B6czCyE1hEfwrkZtseVB+Me+47vO C3UvPcpdqkR4mqGa1RJhmw3R6rubMsbouQVn9r9CD1V8/CXhZDmJZHbJDEG6K6NWMoaf deoRb4zXrC4MQ7lprV5HgVOlpbiJthFRFzCvEWPZTs8pnp4LvQLz26BFjSfkL1x2q+A7 5hbYGudtBOjnLAcI0mYMXKQWFi4OfZNY1FBC6BUOvyijDQCrOpaP9caa4T0wHImNZn5t Kkpg== X-Gm-Message-State: APjAAAVG0ukj01I3v6Oyygki7KRQkg/NvpgiT940F1Fj5h+UeQPAmkZA eA6ObP9X77QGzZmgpDI2ByYYpUWpz6s= X-Google-Smtp-Source: APXvYqxLtTrDQd2ygpe7u9I3MpwqN034hu3moDA93qP3hIuKQzIwJYfCmTIvAo5R/ZLJ4/IHyRsOnQ== X-Received: by 2002:a62:750c:: with SMTP id q12mr67644200pfc.59.1564858093677; Sat, 03 Aug 2019 11:48:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:35 -0700 Message-Id: <20190803184800.8221-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 09/34] target/arm: Add TTBR1_EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) At the same time, add writefn to TTBR0_EL2 and TCR_EL2. A later patch will update any ASID therein. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8baeb3f319..8d8b3cc40e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3449,6 +3449,12 @@ static void vmsa_ttbr_el1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, } } =20 +static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + raw_write(env, ri, value); +} + static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4844,10 +4850,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .resetvalue =3D 0 }, { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, - /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask - */ + .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, + /* no .raw_writefn or .resetfn needed as we never use mask/base_mask= */ .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, @@ -4881,7 +4885,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[2]) }, { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, .writefn =3D vmsa_tcr_ttbr_el= 2_write, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, @@ -6807,6 +6811,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D= 1, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]= ) }, + { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D = 1, + .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) }, REGINFO_SENTINEL }; define_arm_cp_regs(cpu, vhe_reginfo); --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858445; cv=none; d=zoho.com; s=zohoarc; b=eB282rAcWUAILmS8H+WS17yGkQmIx5M2uqrRDXSa6iq6wj/Lu0zdBkmkMlYJO9V//iecZEUIhEKslj0YbyXM9/Kj0Hid6Th7jOM394n+FlO4Ps/MgNkzYMxP9ECZ/OSOd6jPb4EM4yai2/1TvnPidUNqjt1B8u99xajIesHc0Bw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858445; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.13 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ebweW1bxG4mlr4zUkxD0Pv+fcpZzn603jNjjqkso5Rc=; b=dO8sJijZ1OJHBbtBkNrBGZwgxZqhDR3pnZ17F4RG48Q+rZ2YYG+zmyWKMdUWJgYasD npGZFmyiQ+SppHzUz0YshpFHT2cj/buuGGrgh6aROftTUI9XolXqun8J9P5EhmWip+ze Bp0dYd2RLKbOSIOmH3ZOElHSGMHsJ0a+RudWjmrdPGtZNqYbT3WSKKumXM3D5Q5ZjFeg f0fLiQwKRm/adsq7n+R+xANG4DA6lWtGQfIIjrlDHkyRD2yTYz1fACiEGO3OxFEHVpED oErG27FbDZuX3lNsJGA1vopDmV4jeiHvqNwZlt49WL/y73eqCBV908eDQtKxRA7afIxZ eaEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ebweW1bxG4mlr4zUkxD0Pv+fcpZzn603jNjjqkso5Rc=; b=j4nJ2iRDrxfC3uSWE9vlq507Eae+3Aa/heUaIM94opmX0YQ2lKK57JEOBJg2k5TDCK 57qr7D3cB/u2Oi+AjZqj7bqYhyTNSowC3dtiHKH8ox5QPoPV+qwq8te6YFdUC0zD5aU6 Z7nlKHrVgOB7FnCVUBgeuV2yCcYf0QZxDf395fFHB/NMjQq7bdqPn/Fy1nDHHMUz6l9K s4vBGZJiEQbwt/p8vMVtahkRlvNOoxUAX8hiW5IV62eX8rGPOuPZm/XhDdz7s+M6puYz a86edMYTBRry1AGEnvsbY/rFk4N6vOO2mAoeyQoCXZEiWqR9xGYgGZmAhI3nlQK1UMCa 4BqQ== X-Gm-Message-State: APjAAAXlyAzyCljjN0FFmL2Ily5HyhZhMVTt94OuIBeP6GSW66tMEVNK ULaRzfo9VOk/48LIv/lAsz+NT/XyML4= X-Google-Smtp-Source: APXvYqzESc5O7rN+zLAS85mB8ekDyYCTLf/IJJ0EFezaffKKgvlIv9CQteMSbBvCYvSLesZLKBEGdQ== X-Received: by 2002:a62:e710:: with SMTP id s16mr67733969pfh.183.1564858095005; Sat, 03 Aug 2019 11:48:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:36 -0700 Message-Id: <20190803184800.8221-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 10/34] target/arm: Update CNTVCT_EL0 for VHE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The virtual offset may be 0 depending on EL, E2H and TGE. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8d8b3cc40e..e2fcb03da5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2484,9 +2484,31 @@ static uint64_t gt_cnt_read(CPUARMState *env, const = ARMCPRegInfo *ri) return gt_get_countervalue(env); } =20 +static uint64_t gt_virt_cnt_offset(CPUARMState *env) +{ + uint64_t hcr; + + switch (arm_current_el(env)) { + case 2: + hcr =3D arm_hcr_el2_eff(env); + if (hcr & HCR_E2H) { + return 0; + } + break; + case 0: + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + return 0; + } + break; + } + + return env->cp15.cntvoff_el2; +} + static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) { - return gt_get_countervalue(env) - env->cp15.cntvoff_el2; + return gt_get_countervalue(env) - gt_virt_cnt_offset(env); } =20 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2501,7 +2523,13 @@ static void gt_cval_write(CPUARMState *env, const AR= MCPRegInfo *ri, static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx) { - uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? env->cp15.cntvoff_el= 2 : 0; + uint64_t offset =3D 0; + + switch (timeridx) { + case GTIMER_VIRT: + offset =3D gt_virt_cnt_offset(env); + break; + } =20 return (uint32_t)(env->cp15.c14_timer[timeridx].cval - (gt_get_countervalue(env) - offset)); @@ -2511,7 +2539,13 @@ static void gt_tval_write(CPUARMState *env, const AR= MCPRegInfo *ri, int timeridx, uint64_t value) { - uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? env->cp15.cntvoff_el= 2 : 0; + uint64_t offset =3D 0; + + switch (timeridx) { + case GTIMER_VIRT: + offset =3D gt_virt_cnt_offset(env); + break; + } =20 trace_arm_gt_tval_write(timeridx, value); env->cp15.c14_timer[timeridx].cval =3D gt_get_countervalue(env) - offs= et + --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858568; cv=none; d=zoho.com; s=zohoarc; b=iijgel+4s3tcMn9yyyWQy+CdQVGAkSsNJSxIhmcFGLclQ40lipc+KvLD7hb5pCwbSbhROAV7bToMs2+KdP3qRvdQIoWYsh0qM/gy5g+enM2cUlKpsNW55I79Qqmhr5JlPbG5hzT/NtcJmF1rqVmV0aqtqPRBdFfGV8s80xOL6w0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858568; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=XQAThtHXgFyxyKRl2tP3DLgR3ROFgj6xArwRDkS66hw=; b=Phu7SwIer45ZixHsmo1p3k9ZXGs02Wyr9zdf3AkygQvXjznjz+i90c1xIbWiGXFqfdzjsLV7LQp95JaFbnFt+mSB0bNzATPWJOlFpiqft9AevsYkqe6CLH5N89tE9o1CPVbsgOAJTd8zuLRbKSQH6J3dFvHBB/578sAqxZZXWAw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858568926802.8235431567819; Sat, 3 Aug 2019 11:56:08 -0700 (PDT) Received: from localhost ([::1]:41476 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htzCJ-0005TH-Sg for importer@patchew.org; Sat, 03 Aug 2019 14:56:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60761) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz4o-0006H5-0Z for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz4l-0007DO-KB for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:21 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:36974) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz4k-0007Bb-8h for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:18 -0400 Received: by mail-pf1-x441.google.com with SMTP id 19so37616100pfa.4 for ; Sat, 03 Aug 2019 11:48:17 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 11/34] target/arm: Add the hypervisor virtual counter X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/cpu-qom.h | 1 + target/arm/cpu.h | 11 +++++---- target/arm/cpu.c | 2 ++ target/arm/helper.c | 57 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 66 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 2049fa9612..43fc8296db 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -76,6 +76,7 @@ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); void arm_gt_htimer_cb(void *opaque); void arm_gt_stimer_cb(void *opaque); +void arm_gt_hvtimer_cb(void *opaque); =20 #define ARM_AFF0_SHIFT 0 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e37008a4f7..bba4e1f984 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -144,11 +144,12 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; =20 -#define GTIMER_PHYS 0 -#define GTIMER_VIRT 1 -#define GTIMER_HYP 2 -#define GTIMER_SEC 3 -#define NUM_GTIMERS 4 +#define GTIMER_PHYS 0 +#define GTIMER_VIRT 1 +#define GTIMER_HYP 2 +#define GTIMER_SEC 3 +#define GTIMER_HYPVIRT 4 +#define NUM_GTIMERS 5 =20 typedef struct { uint64_t raw_tcr; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ec2ab95dbe..4431330c2e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1226,6 +1226,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) arm_gt_htimer_cb, cpu); cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCA= LE, arm_gt_stimer_cb, cpu); + cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, GTIMER= _SCALE, + arm_gt_hvtimer_cb, cpu); #endif =20 cpu_exec_realizefn(cs, &local_err); diff --git a/target/arm/helper.c b/target/arm/helper.c index e2fcb03da5..e0f5627218 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2527,6 +2527,7 @@ static uint64_t gt_tval_read(CPUARMState *env, const = ARMCPRegInfo *ri, =20 switch (timeridx) { case GTIMER_VIRT: + case GTIMER_HYPVIRT: offset =3D gt_virt_cnt_offset(env); break; } @@ -2543,6 +2544,7 @@ static void gt_tval_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 switch (timeridx) { case GTIMER_VIRT: + case GTIMER_HYPVIRT: offset =3D gt_virt_cnt_offset(env); break; } @@ -2698,6 +2700,34 @@ static void gt_sec_ctl_write(CPUARMState *env, const= ARMCPRegInfo *ri, gt_ctl_write(env, ri, GTIMER_SEC, value); } =20 +static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_HYPVIRT); +} + +static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_HYPVIRT, value); +} + +static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_HYPVIRT); +} + +static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_HYPVIRT, value); +} + +static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); +} + void arm_gt_ptimer_cb(void *opaque) { ARMCPU *cpu =3D opaque; @@ -2726,6 +2756,13 @@ void arm_gt_stimer_cb(void *opaque) gt_recalc_timer(cpu, GTIMER_SEC); } =20 +void arm_gt_hvtimer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + gt_recalc_timer(cpu, GTIMER_HYPVIRT); +} + static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { /* Note that CNTFRQ is purely reads-as-written for the benefit * of software; writing it doesn't actually change the timer frequency. @@ -6849,6 +6886,26 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D = 1, .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) }, +#ifndef CONFIG_USER_ONLY + { .name =3D "CNTHV_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D= 2, + .fieldoffset =3D + offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), + .type =3D ARM_CP_IO, .access =3D PL2_RW, + .writefn =3D gt_hv_cval_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTHV_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D= 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL2_RW, + .resetfn =3D gt_hv_timer_reset, + .readfn =3D gt_hv_tval_read, .writefn =3D gt_hv_tval_write }, + { .name =3D "CNTHV_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, + .type =3D ARM_CP_IO, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D= 1, + .access =3D PL2_RW, + .fieldoffset =3D + offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl), + .writefn =3D gt_hv_ctl_write, .raw_writefn =3D raw_write }, +#endif REGINFO_SENTINEL }; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.16 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mRFuXKk2Gwl0/7zE7hzogtQkhwOwZ57w0oxCxJ+Y7Jc=; b=Asj8oSC11y4yxglFP8DeXNnuNbhJ5H8rd7ioNjaWzuzsCowqC1mNAPiEIsUeSCozYS dvCD/nEkWGZ8z1TAKV8W3HsN+S4Y/tMkc4ZLw06az1z/oR0o9l8VwaC2l8PsSA4m2DJA s1mMwV8fYotSxu0bHPk1IPSVEBcwht6j43yPtEBeyC/eaTFzkX/54dYZtFnj3Aj/GZNa RYBr6joVWEoXJIEQJj6yvTOcOxG2BzC2OcPcKzW+gClcwfjKwSc05sPG72kV7akdEADY 6OkX88XnwjFA6iLV5UIgHBLBiFk+TcEWMiDi0p3lNvuB7NHxqxu9/owgAmRzCDNkDVRE 9Avw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mRFuXKk2Gwl0/7zE7hzogtQkhwOwZ57w0oxCxJ+Y7Jc=; b=J9vKje4YqTkezCESL6jK2xgdVx5yuUezIwXYTyw6GjxZFc0sgma3KzwuqiO++5jm+z 60t71mXo2umbGUd4Ygnp65a+fumD4Ht0rfa70yblSa7kDaaeF0Mhnvjk4sJjbH/w0Kqc 4ZZvLlAGlNDB9L82Z7UGjmlHKqZJG6no4CxWqbZKvLgi3sCa3sbADRQkBFPO4e/Fz8Cj LaK1bWXuaQQzoV3MmSrTRyJsW3QviKBUTZj7Bv3mp3qq+a31/j8cTJZtqnXiqvs5Tq3X Q1bd95ITHWB4iONjB3Ky0kE7xT4I4R6gq9BPVW7+OSRB3LmwTPri8qSBSCR6Yah6xVva FXfA== X-Gm-Message-State: APjAAAXXKgZcB4CTjLxzqpLGDJ1vuWHyXcef9sTmckEhND1SIAJe15p4 LWGr3ZPCl0m4H/gSC+zYXPAiRPfasQ0= X-Google-Smtp-Source: APXvYqzsaC67n2A0m1GBWOP9CIskQBg0V0QJ7GRrNjvXmnzRoHkx79LP8TnMs0CtCeh1Z8BfQgptQw== X-Received: by 2002:aa7:9407:: with SMTP id x7mr68060916pfo.163.1564858097201; Sat, 03 Aug 2019 11:48:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:38 -0700 Message-Id: <20190803184800.8221-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 12/34] target/arm: Add VHE system register redirection and aliasing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Several of the EL1/0 registers are redirected to the EL2 version when in EL2 and HCR_EL2.E2H is set. Many of these registers have side effects. Link together the two ARMCPRegInfo structures after they have been properly instantiated. Install common dispatch routines to all of the relevant registers. The same set of registers that are redirected also have additional EL12/EL02 aliases created to access the original register that was redirected. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 44 +++++++---- target/arm/helper.c | 175 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 206 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bba4e1f984..a0f10b60eb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2455,19 +2455,6 @@ struct ARMCPRegInfo { */ ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ =20 - /* Offsets of the secure and non-secure fields in CPUARMState for the - * register if it is banked. These fields are only used during the st= atic - * registration of a register. During hashing the bank associated - * with a given security state is copied to fieldoffset which is used = from - * there on out. - * - * It is expected that register definitions use either fieldoffset or - * bank_fieldoffsets in the definition but not both. It is also expec= ted - * that both bank offsets are set when defining a banked register. Th= is - * use indicates that a register is banked. - */ - ptrdiff_t bank_fieldoffsets[2]; - /* Function for making any access checks for this register in addition= to * those specified by the 'access' permissions bits. If NULL, no extra * checks required. The access check is performed at runtime, not at @@ -2502,6 +2489,37 @@ struct ARMCPRegInfo { * fieldoffset is 0 then no reset will be done. */ CPResetFn *resetfn; + + union { + /* + * Offsets of the secure and non-secure fields in CPUARMState for + * the register if it is banked. These fields are only used during + * the static registration of a register. During hashing the bank + * associated with a given security state is copied to fieldoffset + * which is used from there on out. + * + * It is expected that register definitions use either fieldoffset + * or bank_fieldoffsets in the definition but not both. It is also + * expected that both bank offsets are set when defining a banked + * register. This use indicates that a register is banked. + */ + ptrdiff_t bank_fieldoffsets[2]; + + /* + * "Original" writefn and readfn. + * For ARMv8.1-VHE register aliases, we overwrite the read/write + * accessor functions of various EL1/EL0 to perform the runtime + * check for which sysreg should actually be modified, and then + * forwards the operation. Before overwriting the accessors, + * the original function is copied here, so that accesses that + * really do go to the EL1/EL0 version proceed normally. + * (The corresponding EL2 register is linked via opaque.) + */ + struct { + CPReadFn *orig_readfn; + CPWriteFn *orig_writefn; + }; + }; }; =20 /* Macros which are lvalues for the field in CPUARMState for the diff --git a/target/arm/helper.c b/target/arm/helper.c index e0f5627218..e9f4cae5e8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5225,6 +5225,171 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +#ifndef CONFIG_USER_ONLY +/* Test if system register redirection is to occur in the current state. = */ +static bool redirect_for_e2h(CPUARMState *env) +{ + return arm_current_el(env) =3D=3D 2 && (arm_hcr_el2_eff(env) & HCR_E2H= ); +} + +static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + CPReadFn *readfn; + + if (redirect_for_e2h(env)) { + /* Switch to the saved EL2 version of the register. */ + ri =3D ri->opaque; + readfn =3D ri->readfn; + } else { + readfn =3D ri->orig_readfn; + } + if (readfn =3D=3D NULL) { + readfn =3D raw_read; + } + return readfn(env, ri); +} + +static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPWriteFn *writefn; + + if (redirect_for_e2h(env)) { + /* Switch to the saved EL2 version of the register. */ + ri =3D ri->opaque; + writefn =3D ri->writefn; + } else { + writefn =3D ri->orig_writefn; + } + if (writefn =3D=3D NULL) { + writefn =3D raw_write; + } + writefn(env, ri, value); +} + +static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) +{ + struct E2HAlias { + uint32_t src_key, dst_key, new_key; + const char *src_name, *dst_name, *new_name; + bool (*feature)(const ARMISARegisters *id); + }; + +#define K(op0, op1, crn, crm, op2) \ + ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) + + static const struct E2HAlias aliases[] =3D { + { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), + "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, + { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), + "CPACR", "CPTR_EL2", "CPACR_EL12" }, + { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), + "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, + { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), + "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, + { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), + "TCR_EL1", "TCR_EL2", "TCR_EL12" }, + { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), + "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, + { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), + "ELR_EL1", "ELR_EL2", "ELR_EL12" }, + { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), + "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, + { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), + "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, + { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), + "ESR_EL1", "ESR_EL2", "ESR_EL12" }, + { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), + "FAR_EL1", "FAR_EL2", "FAR_EL12" }, + { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), + "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, + { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), + "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, + { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), + "VBAR", "VBAR_EL2", "VBAR_EL12" }, + { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), + "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, + { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), + "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, + { K(3, 3, 14, 2, 0), K(3, 4, 14, 2, 0), K(3, 5, 14, 2, 0), + "CNTP_TVAL_EL0", "CNTHP_TVAL_EL2", "CNTP_TVAL_EL02" }, + { K(3, 3, 14, 2, 1), K(3, 4, 14, 2, 1), K(3, 5, 14, 2, 1), + "CNTP_CTL_EL0", "CNTHP_CTL_EL2", "CNTP_CTL_EL02" }, + { K(3, 3, 14, 2, 2), K(3, 4, 14, 2, 2), K(3, 5, 14, 2, 2), + "CNTP_CVAL_EL0", "CNTHP_CVAL_EL2", "CNTP_CVAL_EL02" }, + { K(3, 3, 14, 3, 0), K(3, 4, 14, 3, 0), K(3, 5, 14, 3, 0), + "CNTV_TVAL_EL0", "CNTHV_TVAL_EL2", "CNTV_TVAL_EL02" }, + { K(3, 3, 14, 3, 1), K(3, 4, 14, 3, 1), K(3, 5, 14, 3, 1), + "CNTV_CTL_EL0", "CNTHV_CTL_EL2", "CNTV_CTL_EL02" }, + { K(3, 3, 14, 3, 2), K(3, 4, 14, 3, 2), K(3, 5, 14, 3, 2), + "CNTV_CVAL_EL0", "CNTHV_CVAL_EL2", "CNTV_CVAL_EL02" }, + /* + * CNTHV_CVAL is a special case because there is no separate + * AArch32 EL2 register to which CNTV_CVAL may be directed. + * The effect can be achieved via CNTHV_CVAL_EL2. + */ + { ENCODE_CP_REG(15, 1, 1, 0, 14, 3, 0), K(3, 4, 14, 3, 2), 0, + "CNTV_CVAL", "CNTHV_CVAL_EL2", NULL }, + + /* + * Note that redirection of ZCR is mentioned in the description + * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but + * not in the summary table. + */ + { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), + "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, + + /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ + /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ + }; +#undef K + + size_t i; + + for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { + const struct E2HAlias *a =3D &aliases[i]; + ARMCPRegInfo *src_reg, *dst_reg; + + if (a->feature && !a->feature(&cpu->isar)) { + continue; + } + + src_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->src_key); + dst_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->dst_key); + g_assert(src_reg !=3D NULL); + g_assert(dst_reg !=3D NULL); + + /* Cross-compare names to detect typos in the keys. */ + g_assert(strcmp(src_reg->name, a->src_name) =3D=3D 0); + g_assert(strcmp(dst_reg->name, a->dst_name) =3D=3D 0); + + /* None of the core system registers use opaque; we will. */ + g_assert(src_reg->opaque =3D=3D NULL); + + /* Create alias before redirection so we dup the right data. */ + if (a->new_key) { + ARMCPRegInfo *new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInf= o)); + uint32_t *new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); + bool ok; + + new_reg->name =3D a->new_name; + new_reg->type |=3D ARM_CP_ALIAS; + /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ + new_reg->access &=3D 0xf0; + + ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); + g_assert(ok); + } + + src_reg->opaque =3D dst_reg; + src_reg->orig_readfn =3D src_reg->readfn; + src_reg->orig_writefn =3D src_reg->writefn; + src_reg->readfn =3D el2_e2h_read; + src_reg->writefn =3D el2_e2h_write; + } +} +#endif + static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) { @@ -6942,6 +7107,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) : cpu_isar_feature(aa32_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } + +#ifndef CONFIG_USER_ONLY + /* + * Register redirections and aliases must be done last, + * after the registers from the other extensions have been defined. + */ + if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { + define_arm_vh_e2h_redirects_aliases(cpu); + } +#endif } =20 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.17 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h3dhwpfe86udFJHT5d1QRrLfJzUV39xxz0iIkIlTtJQ=; b=p4d9sTavIeM8PY758QFUeYiC9aPL9OxLqab6D6paLIN1R9hY6kTAp5ovqdcPtJEjFs hbtdKLSserCSJ/lKcNfOs4V5QAN547FeosbSDBPkxAGsELf7n1MbJljPhzGog2AsaHMY 3nk9SnMVuAA1PEi+xkRi0Tn4O4FhBcFpLAe/9ZaLPJciZ3JYgbXzhnt4AzBpEh9te9VQ HrV+HbTcXO6rt+mncHeJ56b3fi1f6IrPQFr4MrdKEq18q5J6di5FlnDtKybQqoWmoRtG M7ENyc1n5qV71FmxzE7YP/gGg5k97J776Lbxvlt/GuGZtDxttjFTbd0RRdA1QO0q59EX yDKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h3dhwpfe86udFJHT5d1QRrLfJzUV39xxz0iIkIlTtJQ=; b=j2cDFzqmkewQK27Fz99RDk5BfXRBuFIqbxCz9hVrMAMvwNRETUvrvtZGC0WnerDPsq dXAHzmA1aZv0sq8JB1ZGBu3lOu9GG2x7RcwoUISvPfss8haihSaPsphXd9oyhBxm4Q8c kJOJLJdk71C5gvX8JFLV0Cp8QbkeMpNkf3Vy7ghxJyWCy1mPQGWIErcfF66D/H0GaqJi h+hzkkFGzwA/SczxztI78PNAWyemNZ2oFysAt9W/VE3uq2KOfL6x+5iG8UwXrfONFqYN 6m1xfoYpEu90Eyg0Jby5xLEVKR5xyCNWDWW94xjF+JTZb3Gb7ZxlHpzEIciln9X5cr5l at4Q== X-Gm-Message-State: APjAAAW/2qFMEBAR/EzHsH4wRDR+zmI5eCU1tbVfA/h8AqXnq8jBsenf mn6ZxYJHJV+bFnclIhB72CrHFMeL0Jo= X-Google-Smtp-Source: APXvYqwDh7PaOvn/rBsLx8jUz5UsBCI4DflaOcPxvGWXN9GEl7gwV6I6QlV+vg98QfZzYyy+Db5/7A== X-Received: by 2002:a63:b20f:: with SMTP id x15mr21319515pge.453.1564858098347; Sat, 03 Aug 2019 11:48:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:39 -0700 Message-Id: <20190803184800.8221-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 13/34] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) No functional change, but unify code sequences. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.c | 118 ++++++++++++++------------------------------ 1 file changed, 37 insertions(+), 81 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e9f4cae5e8..7ecaacb276 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3898,70 +3898,61 @@ static CPAccessResult aa64_cacheop_access(CPUARMSta= te *env, * Page D4-1736 (DDI0487A.b) */ =20 +static int vae1_tlbmask(CPUARMState *env) +{ + if (arm_is_secure_below_el3(env)) { + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + } else { + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + } +} + static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, uint64_t value) { CPUState *cs =3D env_cpu(env); - bool sec =3D arm_is_secure_below_el3(env); + int mask =3D vae1_tlbmask(env); =20 - if (sec) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); =20 if (tlb_force_broadcast(env)) { tlbi_aa64_vmalle1is_write(env, NULL, value); return; } =20 + tlb_flush_by_mmuidx(cs, mask); +} + +static int vmalle1_tlbmask(CPUARMState *env) +{ + /* + * Note that the 'ALL' scope must invalidate both stage 1 and + * stage 2 translations, whereas most other scopes only invalidate + * stage 1 translations. + */ if (arm_is_secure_below_el3(env)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + } else if (arm_feature(env, ARM_FEATURE_EL2)) { + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_= S2NS; } else { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; } } =20 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Note that the 'ALL' scope must invalidate both stage 1 and - * stage 2 translations, whereas most other scopes only invalidate - * stage 1 translations. - */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vmalle1_tlbmask(env); =20 - if (arm_is_secure_below_el3(env)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - if (arm_feature(env, ARM_FEATURE_EL2)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - } else { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } - } + tlb_flush_by_mmuidx(cs, mask); } =20 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3985,28 +3976,10 @@ static void tlbi_aa64_alle3_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - /* Note that the 'ALL' scope must invalidate both stage 1 and - * stage 2 translations, whereas most other scopes only invalidate - * stage 1 translations. - */ CPUState *cs =3D env_cpu(env); - bool sec =3D arm_is_secure_below_el3(env); - bool has_el2 =3D arm_feature(env, ARM_FEATURE_EL2); + int mask =3D vmalle1_tlbmask(env); =20 - if (sec) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else if (has_el2) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - } else { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4056,20 +4029,11 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, = const ARMCPRegInfo *ri, static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, uint64_t value) { - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); - bool sec =3D arm_is_secure_below_el3(env); + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - if (sec) { - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4080,8 +4044,8 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * since we don't support flush-for-specific-ASID-only or * flush-last-level-only. */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 if (tlb_force_broadcast(env)) { @@ -4089,15 +4053,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, return; } =20 - if (arm_is_secure_below_el3(env)) { - tlb_flush_page_by_mmuidx(cs, pageaddr, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_page_by_mmuidx(cs, pageaddr, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858387; cv=none; d=zoho.com; s=zohoarc; b=b5SlB6SG4dnkMUzeZ13rZIfCq/HvmZgg79U1roh7kuenGu7FuDbT7vVG+ODUhbiSfA6LG94q65jloXRPdbqXwqzarhQTIt8CUxM5EMRztTIPMzgTgFJQ9LjFNbHfD00Y/PpWfecsappSjNuUg0V+qYx5AVamIIcyU6ZJOhDtHUg= ARC-Message-Signature: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.18 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RHV3vStI8hqe3CeMRucY7WZ1UFpWZPYBbhdsWvPNW30=; b=CilkG14hXuLfs3ajiEUbNrYQSzWSF+gJ0pP3dZAsMY0qkc2tphjlBXylPEoqETFJG4 quVMsgfQEyspFWXAEvAb4V2h7VtD1CJ/zYaMLelO4BGFvg8576uVPz49Wz3cznrWteXi lKtAY/OkT0O2bc24rV8/K0JRpwX9/XC4OlGh4TMTJ+vZiPvQ3S8HYpgaph0RzcGGwe+O IkAN7JCBC6QrUdqYnJQou3/tixjKLaCkhwiDRS1xThCclADpI5GCjvOePtvJTs4cg7BW V53y8za6pJcueTgjLRrw6454Zrj/WoZsVpWq2DCPuiWzGqC2pU/rjsab++I5xA1BGHpk nsQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RHV3vStI8hqe3CeMRucY7WZ1UFpWZPYBbhdsWvPNW30=; b=HnWnX+C4hufhAzLMCdwizB5iqD6FmPiwdLfjzLCW2GYWh17l2pDpu2R2a6HmeWlIn9 Z7NcBLgFGTP+KHvnQDoBOwzVHF2nHfFHCKpY8s+LvJUhz505GjVcjfso8eIqvIFoQVFT GCxmL9CYqGOCok7A94zNMRiGHei7dV5pCnjwjopJSAJgf2K1bEsaBZePZQIC3hXixyGt CEFaMaXuvdiOhqfw5R1RSKm2V0y3q5oBebYvEE+Hml2I/9eL0Pqg/7ZabZgx+Nlsz9e3 6gNAHXX2Gm9XZaS7atRdyKDw99q4xgvlSHvq/LPSK6jaKNwoYwiJC0oCFqEYGOI2WcrN 1eIA== X-Gm-Message-State: APjAAAUgi6KihFlahzjIm9eL3Y2CqOZ7VqfwL73JTs1bGzdF4ErGo24d VmowHQ5eb94SVGpYHyJ4l7zy2/zOpq4= X-Google-Smtp-Source: APXvYqwl5vx+KnNm6Sbam81DxSCZSW+EVMLXdFp12OSdPpGCdDvrfyo0H959RO/WqV6xe1OxTFcijg== X-Received: by 2002:a63:9e54:: with SMTP id r20mr96504867pgo.64.1564858099599; Sat, 03 Aug 2019 11:48:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:40 -0700 Message-Id: <20190803184800.8221-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 14/34] target/arm: Simplify tlb_force_broadcast alternatives X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Rather than call to a separate function and re-compute any parameters for the flush, simply use the correct flush function directly. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.c | 52 +++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7ecaacb276..185f5e4aea 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -626,56 +626,54 @@ static void tlbiall_write(CPUARMState *env, const ARM= CPRegInfo *ri, uint64_t value) { /* Invalidate all (TLBIALL) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 if (tlb_force_broadcast(env)) { - tlbiall_is_write(env, NULL, value); - return; + tlb_flush_all_cpus_synced(cs); + } else { + tlb_flush(cs); } - - tlb_flush(CPU(cpu)); } =20 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 + value &=3D TARGET_PAGE_MASK; if (tlb_force_broadcast(env)) { - tlbimva_is_write(env, NULL, value); - return; + tlb_flush_page_all_cpus_synced(cs, value); + } else { + tlb_flush_page(cs, value); } - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } =20 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by ASID (TLBIASID) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 if (tlb_force_broadcast(env)) { - tlbiasid_is_write(env, NULL, value); - return; + tlb_flush_all_cpus_synced(cs); + } else { + tlb_flush(cs); } - - tlb_flush(CPU(cpu)); } =20 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 + value &=3D TARGET_PAGE_MASK; if (tlb_force_broadcast(env)) { - tlbimvaa_is_write(env, NULL, value); - return; + tlb_flush_page_all_cpus_synced(cs, value); + } else { + tlb_flush_page(cs, value); } - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } =20 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3923,11 +3921,10 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *en= v, const ARMCPRegInfo *ri, int mask =3D vae1_tlbmask(env); =20 if (tlb_force_broadcast(env)) { - tlbi_aa64_vmalle1is_write(env, NULL, value); - return; + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); + } else { + tlb_flush_by_mmuidx(cs, mask); } - - tlb_flush_by_mmuidx(cs, mask); } =20 static int vmalle1_tlbmask(CPUARMState *env) @@ -4049,11 +4046,10 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 if (tlb_force_broadcast(env)) { - tlbi_aa64_vae1is_write(env, NULL, value); - return; + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); + } else { + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } - - tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 15/34] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part of a reorganization to the set of mmu_idx. This emphasizes that they apply to the EL1&0 regime. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 +++---- target/arm/internals.h | 4 ++-- target/arm/helper.c | 44 +++++++++++++++++++------------------- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 6 +++--- 5 files changed, 33 insertions(+), 33 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a0f10b60eb..8a3f61bc2c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2850,8 +2850,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, #define ARM_MMU_IDX_COREIDX_MASK 0x7 =20 typedef enum ARMMMUIdx { - ARMMMUIdx_S12NSE0 =3D 0 | ARM_MMU_IDX_A, - ARMMMUIdx_S12NSE1 =3D 1 | ARM_MMU_IDX_A, + ARMMMUIdx_EL10_0 =3D 0 | ARM_MMU_IDX_A, + ARMMMUIdx_EL10_1 =3D 1 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE0 =3D 4 | ARM_MMU_IDX_A, @@ -2876,8 +2876,8 @@ typedef enum ARMMMUIdx { * for use when calling tlb_flush_by_mmuidx() and friends. */ typedef enum ARMMMUIdxBit { - ARMMMUIdxBit_S12NSE0 =3D 1 << 0, - ARMMMUIdxBit_S12NSE1 =3D 1 << 1, + ARMMMUIdxBit_EL10_0 =3D 1 << 0, + ARMMMUIdxBit_EL10_1 =3D 1 << 1, ARMMMUIdxBit_S1E2 =3D 1 << 2, ARMMMUIdxBit_S1E3 =3D 1 << 3, ARMMMUIdxBit_S1SE0 =3D 1 << 4, diff --git a/target/arm/internals.h b/target/arm/internals.h index 232d963875..fafefdc59e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -808,8 +808,8 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_S12NSE0: - case ARMMMUIdx_S12NSE1: + case ARMMMUIdx_EL10_0: + case ARMMMUIdx_EL10_1: case ARMMMUIdx_S1NSE0: case ARMMMUIdx_S1NSE1: case ARMMMUIdx_S1E2: diff --git a/target/arm/helper.c b/target/arm/helper.c index 185f5e4aea..e391654638 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -569,7 +569,7 @@ static void contextidr_write(CPUARMState *env, const AR= MCPRegInfo *ri, idxmask =3D ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; break; case ARM_CP_SECSTATE_NS: - idxmask =3D ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + idxmask =3D ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; break; default: g_assert_not_reached(); @@ -682,8 +682,8 @@ static void tlbiall_nsnh_write(CPUARMState *env, const = ARMCPRegInfo *ri, CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | + ARMMMUIdxBit_EL10_1 | + ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_S2NS); } =20 @@ -693,8 +693,8 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, con= st ARMCPRegInfo *ri, CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | + ARMMMUIdxBit_EL10_1 | + ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_S2NS); } =20 @@ -3047,7 +3047,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, format64 =3D arm_s1_regime_using_lpae_format(env, mmu_idx); =20 if (arm_feature(env, ARM_FEATURE_EL2)) { - if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUI= dx_S12NSE1) { + if (mmu_idx =3D=3D ARMMMUIdx_EL10_0 || mmu_idx =3D=3D ARMMMUId= x_EL10_1) { format64 |=3D env->cp15.hcr_el2 & (HCR_VM | HCR_DC); } else { format64 |=3D arm_current_el(env) =3D=3D 2; @@ -3146,11 +3146,11 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) break; case 4: /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ - mmu_idx =3D ARMMMUIdx_S12NSE1; + mmu_idx =3D ARMMMUIdx_EL10_1; break; case 6: /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ - mmu_idx =3D ARMMMUIdx_S12NSE0; + mmu_idx =3D ARMMMUIdx_EL10_0; break; default: g_assert_not_reached(); @@ -3208,10 +3208,10 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_EL10_1; break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_EL10_0; break; default: g_assert_not_reached(); @@ -3430,7 +3430,7 @@ static void update_lpae_el1_asid(CPUARMState *env, in= t secure) ttbr0 =3D env->cp15.ttbr0_ns; ttbr1 =3D env->cp15.ttbr1_ns; ttcr =3D env->cp15.tcr_el[1].raw_tcr; - idxmask =3D ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + idxmask =3D ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; break; default: g_assert_not_reached(); @@ -3540,10 +3540,10 @@ static void vttbr_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 /* * A change in VMID to the stage2 page table (S2NS) invalidates - * the combined stage 1&2 tlbs (S12NSE1 and S12NSE0). + * the combined stage 1&2 tlbs (EL10_1 and EL10_0). */ tlb_set_asid_for_mmuidx(cs, vmid, ARMMMUIdxBit_S2NS, - ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0); + ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0); } =20 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { @@ -3901,7 +3901,7 @@ static int vae1_tlbmask(CPUARMState *env) if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; } else { - return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; } } =20 @@ -3937,9 +3937,9 @@ static int vmalle1_tlbmask(CPUARMState *env) if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { - return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_= S2NS; + return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_S2= NS; } else { - return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; } } =20 @@ -8801,8 +8801,8 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMM= UIdx mmu_idx) */ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { - if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS= E1) { - mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); + if (mmu_idx =3D=3D ARMMMUIdx_EL10_0 || mmu_idx =3D=3D ARMMMUIdx_EL10_1= ) { + mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_EL10_0); } return mmu_idx; } @@ -8845,8 +8845,8 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) return true; default: return false; - case ARMMMUIdx_S12NSE0: - case ARMMMUIdx_S12NSE1: + case ARMMMUIdx_EL10_0: + case ARMMMUIdx_EL10_1: g_assert_not_reached(); } } @@ -10750,7 +10750,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { - if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS= E1) { + if (mmu_idx =3D=3D ARMMMUIdx_EL10_0 || mmu_idx =3D=3D ARMMMUIdx_EL10_1= ) { /* Call ourselves recursively to do the stage 1 and then stage 2 * translations. */ @@ -11281,7 +11281,7 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) if (el < 2 && arm_is_secure_below_el3(env)) { return ARMMMUIdx_S1SE0 + el; } else { - return ARMMMUIdx_S12NSE0 + el; + return ARMMMUIdx_EL10_0 + el; } } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d3231477a2..ece749fe03 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -113,8 +113,8 @@ static inline int get_a64_user_mem_index(DisasContext *= s) ARMMMUIdx useridx; =20 switch (s->mmu_idx) { - case ARMMMUIdx_S12NSE1: - useridx =3D ARMMMUIdx_S12NSE0; + case ARMMMUIdx_EL10_1: + useridx =3D ARMMMUIdx_EL10_0; break; case ARMMMUIdx_S1SE1: useridx =3D ARMMMUIdx_S1SE0; diff --git a/target/arm/translate.c b/target/arm/translate.c index 7853462b21..afff595726 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -153,9 +153,9 @@ static inline int get_a32_user_mem_index(DisasContext *= s) */ switch (s->mmu_idx) { case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */ - case ARMMMUIdx_S12NSE0: - case ARMMMUIdx_S12NSE1: - return arm_to_core_mmu_idx(ARMMMUIdx_S12NSE0); + case ARMMMUIdx_EL10_0: + case ARMMMUIdx_EL10_1: + return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0); case ARMMMUIdx_S1E3: case ARMMMUIdx_S1SE0: case ARMMMUIdx_S1SE1: --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.20 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=la7qxtvs05jrNqcA9h6vjUFPOQjXr0T0i1pOh4sumx8=; b=BPtXKMjQXEwSqf4ihkATokxXgdqYfxy91qDkVzIxkd8iyWIMNJcnybknDrqwLuSPO0 v+TTl6BOSG4nU+HVMi5sEAifBXSQchp0yeklueMV0O6rn821vBeKviV8RKtAPheLeoaN 4wZ8hwpcZ7AXYMhodmsLtWVbVGU5S+bMhZBtn1zhKcZ9e4sR5kEs1CSG3XPhYb369n2J B8Hp4xd9ZjqVXqXoKH2CHlj3R+mNrbFbbvG/hhjeDssuLwzTjTJrzP+ZIeJfmZIT8cMy FPZJxvYz7PvoLF6DG6sCYS+w9gHkTEEzgYeqMwH1a67K+LJ2gIxts7rsHFdkyunLSV+A b5qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=la7qxtvs05jrNqcA9h6vjUFPOQjXr0T0i1pOh4sumx8=; b=NR658wglXv3f7H5DDqZgtNabFnTy1Dv+/nbDbxAVKtlgovnn4qG5Ec0KPH0kVXQzdY o1QmdFDvVP0Mk+F8ukU9prGEwYmHy/6+rahS5Mzyfz6EjuVNO9lMUU6ANAtVLJXm9o4K 5wbSNiGfVl0U8WL2yjkd6IfzPnJBKLth6m1S/2J8cf6dW9nU7foSKlotSKM1PfrEDCJr Rjbhv74+EjDJM3+rxSfdRDgD71ZA8CGS6MJm77cYwgpL5Kub2STX52q2ZiDGYvyOzWQc MceB+UDgCZ1tdBBitYhwUEWsw29y4HlmCgn//zM7ebOVD2MQy9GCg0ZjGTHwuCKGBWWS N/Zw== X-Gm-Message-State: APjAAAURxCRyUWOo63/BVISTpr9eBUDht9oKiqYrWPqPWQNaZy6I0BCD XNRZVEPWD3ZYId9enqzfLnHuUBjQsFk= X-Google-Smtp-Source: APXvYqxuDAEGyeqJ0ZmaCVWpz2kKBg/VgvLK6A+238W+QhyfAL22XuxwQM85UonPGZLE9FD9b9NZeA== X-Received: by 2002:a63:fd57:: with SMTP id m23mr64994336pgj.204.1564858101921; Sat, 03 Aug 2019 11:48:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:42 -0700 Message-Id: <20190803184800.8221-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 16/34] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The EL1&0 regime is the only one that uses 2-stage translation. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 +-- target/arm/internals.h | 2 +- target/arm/helper.c | 54 +++++++++++++++++++------------------- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 2 +- 5 files changed, 32 insertions(+), 32 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8a3f61bc2c..14730d29c6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2856,7 +2856,7 @@ typedef enum ARMMMUIdx { ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE0 =3D 4 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE1 =3D 5 | ARM_MMU_IDX_A, - ARMMMUIdx_S2NS =3D 6 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M, ARMMMUIdx_MUserNegPri =3D 2 | ARM_MMU_IDX_M, @@ -2882,7 +2882,7 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_S1E3 =3D 1 << 3, ARMMMUIdxBit_S1SE0 =3D 1 << 4, ARMMMUIdxBit_S1SE1 =3D 1 << 5, - ARMMMUIdxBit_S2NS =3D 1 << 6, + ARMMMUIdxBit_Stage2 =3D 1 << 6, ARMMMUIdxBit_MUser =3D 1 << 0, ARMMMUIdxBit_MPriv =3D 1 << 1, ARMMMUIdxBit_MUserNegPri =3D 1 << 2, diff --git a/target/arm/internals.h b/target/arm/internals.h index fafefdc59e..1caa15e7e0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -813,7 +813,7 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_S1NSE0: case ARMMMUIdx_S1NSE1: case ARMMMUIdx_S1E2: - case ARMMMUIdx_S2NS: + case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: diff --git a/target/arm/helper.c b/target/arm/helper.c index e391654638..6c8eddfdf4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -684,7 +684,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const = ARMCPRegInfo *ri, tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | - ARMMMUIdxBit_S2NS); + ARMMMUIdxBit_Stage2); } =20 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -695,7 +695,7 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, con= st ARMCPRegInfo *ri, tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | - ARMMMUIdxBit_S2NS); + ARMMMUIdxBit_Stage2); } =20 static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -716,7 +716,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 pageaddr =3D sextract64(value << 12, 0, 40); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2); } =20 static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -732,7 +732,7 @@ static void tlbiipas2_is_write(CPUARMState *env, const = ARMCPRegInfo *ri, pageaddr =3D sextract64(value << 12, 0, 40); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S2NS); + ARMMMUIdxBit_Stage2); } =20 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3539,10 +3539,10 @@ static void vttbr_write(CPUARMState *env, const ARM= CPRegInfo *ri, vmid =3D extract64(value, 48, 8); =20 /* - * A change in VMID to the stage2 page table (S2NS) invalidates + * A change in VMID to the stage2 page table (Stage2) invalidates * the combined stage 1&2 tlbs (EL10_1 and EL10_0). */ - tlb_set_asid_for_mmuidx(cs, vmid, ARMMMUIdxBit_S2NS, + tlb_set_asid_for_mmuidx(cs, vmid, ARMMMUIdxBit_Stage2, ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0); } =20 @@ -3937,7 +3937,7 @@ static int vmalle1_tlbmask(CPUARMState *env) if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { - return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_S2= NS; + return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_St= age2; } else { return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; } @@ -4091,7 +4091,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env,= const ARMCPRegInfo *ri, =20 pageaddr =3D sextract64(value << 12, 0, 48); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2); } =20 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, @@ -4107,7 +4107,7 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *en= v, const ARMCPRegInfo *ri, pageaddr =3D sextract64(value << 12, 0, 48); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S2NS); + ARMMMUIdxBit_Stage2); } =20 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, @@ -8690,7 +8690,7 @@ void arm_cpu_do_interrupt(CPUState *cs) static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_S2NS: + case ARMMMUIdx_Stage2: case ARMMMUIdx_S1E2: return 2; case ARMMMUIdx_S1E3: @@ -8744,7 +8744,7 @@ static inline bool regime_translation_disabled(CPUARM= State *env, } } =20 - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* HCR.DC means HCR.VM behaves as 1 */ return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; } @@ -8775,7 +8775,7 @@ static inline bool regime_translation_big_endian(CPUA= RMState *env, static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) { - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { return env->cp15.vttbr_el2; } if (ttbrn =3D=3D 0) { @@ -8790,7 +8790,7 @@ static inline uint64_t regime_ttbr(CPUARMState *env, = ARMMMUIdx mmu_idx, /* Return the TCR controlling this translation regime */ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { return &env->cp15.vtcr_el2; } return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; @@ -8977,7 +8977,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu= _idx, bool is_aa64, bool have_wxn; int wxn =3D 0; =20 - assert(mmu_idx !=3D ARMMMUIdx_S2NS); + assert(mmu_idx !=3D ARMMMUIdx_Stage2); =20 user_rw =3D simple_ap_to_rw_prot_is_user(ap, true); if (is_user) { @@ -9069,7 +9069,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, ARMMMUFaultInfo *fi) { if ((mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1) && - !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { + !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { target_ulong s2size; hwaddr s2pa; int s2prot; @@ -9086,7 +9086,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, pcacheattrs =3D &cacheattrs; } =20 - ret =3D get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, + ret =3D get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa, &txattrs, &s2prot, &s2size, fi, pcacheatt= rs); if (ret) { assert(fi->type !=3D ARMFault_None); @@ -9558,7 +9558,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, tsz =3D extract32(tcr, 0, 6); using64k =3D extract32(tcr, 14, 1); using16k =3D extract32(tcr, 15, 1); - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* VTCR_EL2 */ tbi =3D tbid =3D hpd =3D false; } else { @@ -9619,7 +9619,7 @@ static ARMVAParameters aa32_va_parameters(CPUARMState= *env, uint32_t va, int select, tsz; bool epd, hpd; =20 - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* VTCR */ bool sext =3D extract32(tcr, 4, 1); bool sign =3D extract32(tcr, 3, 1); @@ -9721,7 +9721,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, level =3D 1; /* There is no TTBR1 for EL2 */ ttbr1_valid =3D (el !=3D 2); - addrsize =3D (mmu_idx =3D=3D ARMMMUIdx_S2NS ? 40 : 32); + addrsize =3D (mmu_idx =3D=3D ARMMMUIdx_Stage2 ? 40 : 32); inputsize =3D addrsize - param.tsz; } =20 @@ -9772,7 +9772,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, goto do_fault; } =20 - if (mmu_idx !=3D ARMMMUIdx_S2NS) { + if (mmu_idx !=3D ARMMMUIdx_Stage2) { /* The starting level depends on the virtual address size (which c= an * be up to 48 bits) and the translation granule size. It indicates * the number of strides (stride bits at a time) needed to @@ -9872,7 +9872,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, attrs =3D extract64(descriptor, 2, 10) | (extract64(descriptor, 52, 12) << 10); =20 - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* Stage 2 table descriptors do not include any attribute fiel= ds */ break; } @@ -9903,7 +9903,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, ap =3D extract32(attrs, 4, 2); xn =3D extract32(attrs, 12, 1); =20 - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { ns =3D true; *prot =3D get_S2prot(env, ap, xn); } else { @@ -9930,7 +9930,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, } =20 if (cacheattrs !=3D NULL) { - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { cacheattrs->attrs =3D convert_stage2_attrs(env, extract32(attrs, 0, 4= )); } else { @@ -9951,7 +9951,7 @@ do_fault: fi->type =3D fault_type; fi->level =3D level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ - fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_S2NS); + fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_Stage2); return true; } =20 @@ -10765,13 +10765,13 @@ bool get_phys_addr(CPUARMState *env, target_ulong= address, prot, page_size, fi, cacheattrs); =20 /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { + if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2))= { *phys_ptr =3D ipa; return ret; } =20 /* S1 is done. Now do S2 translation. */ - ret =3D get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2= NS, + ret =3D get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_St= age2, phys_ptr, attrs, &s2_prot, page_size, fi, cacheattrs !=3D NULL ? &cacheattrs2 := NULL); @@ -10813,7 +10813,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, /* Fast Context Switch Extension. This doesn't exist at all in v8. * In v7 and earlier it affects all stage 1 translations. */ - if (address < 0x02000000 && mmu_idx !=3D ARMMMUIdx_S2NS + if (address < 0x02000000 && mmu_idx !=3D ARMMMUIdx_Stage2 && !arm_feature(env, ARM_FEATURE_V8)) { if (regime_el(env, mmu_idx) =3D=3D 3) { address +=3D env->cp15.fcseidr_s; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ece749fe03..73801c5df7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -119,7 +119,7 @@ static inline int get_a64_user_mem_index(DisasContext *= s) case ARMMMUIdx_S1SE1: useridx =3D ARMMMUIdx_S1SE0; break; - case ARMMMUIdx_S2NS: + case ARMMMUIdx_Stage2: g_assert_not_reached(); default: useridx =3D s->mmu_idx; diff --git a/target/arm/translate.c b/target/arm/translate.c index afff595726..995010834f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -172,7 +172,7 @@ static inline int get_a32_user_mem_index(DisasContext *= s) case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPrivNegPri: return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri); - case ARMMMUIdx_S2NS: + case ARMMMUIdx_Stage2: default: g_assert_not_reached(); } --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858615; cv=none; d=zoho.com; s=zohoarc; b=KS640Qb+raIBAvw5/jLRb7lXelPQtWiYYAdpITnjdg4N8XPx23011zFjN9oCYjlubCa/4g37ES+ZtKQ3pYQwjl1NNJT1JRdjp7TCrvaiMsBLeV70E+J7/7aH05wNt7YTeBbqtBI/rWtsNjAwfZ1xiTSsaxw4ZpKgBHQpSwel5RU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858615; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=VjzDc7lTBTDRBT8iLvPhCchzYrLI8WxMxxlUTCAkZXM=; b=LDfdeZOGEX71b6Ma9zYpqemoAx7rQ/67nihLXWvRo29H19cIWzQD3QdowpOFpVVDmhOQSyPco1vvrBkW4vu/Q4gUcmyO6XQWj4ERcJQSCl2xtM7AGAGaiacffUZoeIweJxpXNhovhmdCU3hPPsUOQFO/mCmmImr0l2A1dRexW1A= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858615414677.6858486377353; Sat, 3 Aug 2019 11:56:55 -0700 (PDT) Received: from localhost ([::1]:41504 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htzD2-0007G0-4L for importer@patchew.org; Sat, 03 Aug 2019 14:56:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60933) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz4v-0006RF-LA for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz4u-0007Hr-3C for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:29 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:38245) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz4s-0007FV-0S for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:26 -0400 Received: by mail-pg1-x542.google.com with SMTP id z14so437902pga.5 for ; Sat, 03 Aug 2019 11:48:24 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.22 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VjzDc7lTBTDRBT8iLvPhCchzYrLI8WxMxxlUTCAkZXM=; b=foiUfcT4TZ5uqUsirjpWFshpuOkx97FJ2aHGsrr2Exo2r1R41xS2WETc3BUtHfu3DO KMmV+Hj+0kZJkHsz5iJ/21oELQtf9X3pjUJ3tDn5bc8qWUWPJgvhbdNcPMaKTYgDc6Uo 7zDHJnElftLUjsgZEwqx1tFDhhsm2nqiX75IDNEkesSlwxLhvWXDCkI3+4+WDZHMExEX ORTyQjTbU0S7KJvx8OFa5ADWSNIA723y6NSkjb+D6hRyDWxfYdPptpB9gC8O4DgYs+MG N7YGVGJcZIgMkUijoYAQr+3DzAyl+bOHBZeZalhb4HliwSwAenmUo1SuHRwEbpxW/+vp CfEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VjzDc7lTBTDRBT8iLvPhCchzYrLI8WxMxxlUTCAkZXM=; b=VBA5qzSNG5lJffNnC+gxjalNKJ9eqA4GoWU5EjV8d6x2C+oxZQk5KGPavk/ZqWLm/j TYgzHB6f3Zyah29bugP4pdJ87obe9ytPcEJMCbZeUp6O3aSDTL22kEmo2ZNYhZGac/38 5kl6p7HAXhXdo1GBaMB7LrBY0yt2mHrf+nO6Vrm0g6GcNhNznxP7dnMyJO+S/RbetNO8 qzl6+Yw03HX4TbfdIJiI1FL84XEFfFS8pDyQnHo71UQbRrDLXDwko0Xp8sFK78elAIab vZ+Emysdg8CrEoF+uJ1CQko1WS01hE1fpdm/L2NW+dzIw5PL9kpaIS52p76kOQqmMUG8 c8yw== X-Gm-Message-State: APjAAAUPUYYP7Qq7hewUoKRqaW25oeKOqpT7EqZ6N1U8DZ6oPgm+1GUA jV9hyaQvAISO+6xINMvxI6DXFyG4YvQ= X-Google-Smtp-Source: APXvYqwZJw5wzrwj5JvENZPajDYPfjvpWFmNLA6M/tsMs6aK2CMwaqGfABhlU8bR1r5DjvvjNdyvrQ== X-Received: by 2002:aa7:9217:: with SMTP id 23mr66753521pfo.239.1564858103240; Sat, 03 Aug 2019 11:48:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:43 -0700 Message-Id: <20190803184800.8221-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 17/34] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part of a reorganization to the set of mmu_idx. The EL1&0 regime is the only one that uses 2-stage translation. Spelling out Stage avoids confusion with Secure. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 6 +++--- target/arm/helper.c | 24 ++++++++++++------------ 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 14730d29c6..ade558f63c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2868,8 +2868,8 @@ typedef enum ARMMMUIdx { /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ - ARMMMUIdx_S1NSE0 =3D 0 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_S1NSE1 =3D 1 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; =20 /* Bit macros for the core-mmu-index values for each index, diff --git a/target/arm/internals.h b/target/arm/internals.h index 1caa15e7e0..cd9b1acb20 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -810,8 +810,8 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_EL10_0: case ARMMMUIdx_EL10_1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_S1E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: @@ -966,7 +966,7 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env); #ifdef CONFIG_USER_ONLY static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) { - return ARMMMUIdx_S1NSE0; + return ARMMMUIdx_Stage1_E0; } #else ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index 6c8eddfdf4..4c0c314c1a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3119,10 +3119,10 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_S1E3; break; case 2: - mmu_idx =3D ARMMMUIdx_S1NSE1; + mmu_idx =3D ARMMMUIdx_Stage1_E1; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; break; default: g_assert_not_reached(); @@ -3135,10 +3135,10 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_S1SE0; break; case 2: - mmu_idx =3D ARMMMUIdx_S1NSE0; + mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3192,7 +3192,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx =3D ARMMMUIdx_S1E2; @@ -3205,7 +3205,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_EL10_1; @@ -8698,8 +8698,8 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) case ARMMMUIdx_S1SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; case ARMMMUIdx_S1SE1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -8757,7 +8757,7 @@ static inline bool regime_translation_disabled(CPUARM= State *env, } =20 if ((env->cp15.hcr_el2 & HCR_DC) && - (mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1)) { + (mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St= age1_E1)) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; } @@ -8802,7 +8802,7 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMM= UIdx mmu_idx) static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { if (mmu_idx =3D=3D ARMMMUIdx_EL10_0 || mmu_idx =3D=3D ARMMMUIdx_EL10_1= ) { - mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_EL10_0); + mmu_idx +=3D (ARMMMUIdx_Stage1_E0 - ARMMMUIdx_EL10_0); } return mmu_idx; } @@ -8837,7 +8837,7 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: case ARMMMUIdx_MUserNegPri: @@ -9068,7 +9068,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, hwaddr addr, MemTxAttrs txattrs, ARMMMUFaultInfo *fi) { - if ((mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1) && + if ((mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St= age1_E1) && !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { target_ulong s2size; hwaddr s2pa; --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858668; cv=none; d=zoho.com; s=zohoarc; b=J3T9wbh5bIy97ItEiidw3DIDjWOgJfFYM3BFO3uJhyMhGFg0JCtuGsxndTJMheG4wl7dPX6pLUnR5V1FSfHZy3yYjY30GXtEQY4IW/lyto+u0V0UFh6N68+/r/3K2Cn9jyX/h+kU6YtP4dk/VtWduCEOVrzqCcH5SZ08CdnSRwE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858668; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=w216qTj/BYqjTL2Y/6Uaoyzbe1vK0P5jhQZ1rUoxx+c=; b=WQ5cynfFGP6t486RJ019BYJqYe3bDsXgmtEyuUjQA5PFYqWJBlfHs1kIt4SvF2WY5lSDYcVNmv6q05WeVNMzwZaSMuI42hjVzPrG6Gqif8VOITyvSRzUGswkvJgcjDusEpxXqqqbAdsPgvJz09nN8h4T/K2CV2TvsX6NauY4x24= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858668554350.98619164391073; Sat, 3 Aug 2019 11:57:48 -0700 (PDT) Received: from localhost ([::1]:41528 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htzDv-0001iu-KA for importer@patchew.org; Sat, 03 Aug 2019 14:57:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60948) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz4v-0006SW-UP for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz4u-0007IA-5M for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:29 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:32976) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz4s-0007GQ-2f for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:28 -0400 Received: by mail-pf1-x441.google.com with SMTP id g2so37628919pfq.0 for ; Sat, 03 Aug 2019 11:48:25 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.23 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=w216qTj/BYqjTL2Y/6Uaoyzbe1vK0P5jhQZ1rUoxx+c=; b=VshZ5FZ/nArFkQFQb7nU4aHDQVOFJUdHPmPlru4x3yPa9mSn0gl9yvoND9TEAFdOZ/ yZDA96+cgmGMBx7Kd/2wPOrIMj8+T9rscFkIG/DFJFaWLDKmpNXRmdAC7BY3QAh5/jvs 5M23Pm9CHPl3z0WDwuzKlj/lXdcKQ+7oExXe3KgIEq/xuF7yfX9x2PEr4qul3sD5Qscz p9krloOMxMIqH4GP5Kt9q53d8YEnBOpWCFb5E8jySL0nmi3ZQC2hKFhl8dl/CHIb3MAb FCzUU/cMHasVZ10ACJvfF8ECDP8ix230+IDYMbU0tE1LH169onpvcRG5XTkEs+KYNHA0 yQ6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=w216qTj/BYqjTL2Y/6Uaoyzbe1vK0P5jhQZ1rUoxx+c=; b=SkMM6B6W+CSQSrMu+lEakFq9h4+pyYs+XMD/9eFf1bI2bZtcqWi7bVhsTrxnOeNGxX tfXli+u++snNIx8bgyvBhrVqxLXrDOoKaMAd5tk/W4pw4/X/ZapdeFcri9yfLSK4Mf5g crHw1/iInbtWHri57cG8CwToVN9OPebMj03ZUC4Cky4swcIVQXpqGQdk3/+TEUVezTmI GcCUXnIYeh0eDjvRpP3uZzpiy7azyYXtrgddq28GTHy+3FF83cdFhleox+bG6KU9HFfi aMc4J1AyDbZb918yYjq3m9e8OxNkfKgdfbFCTVYY2qVBQzqXyY+wgEUUgKhk8lkScGQs tjnA== X-Gm-Message-State: APjAAAXeWCmNVt4y1Oq5pbgZPDEkEXUb59WI+PYIiT7GWEQcuOzIUNvW viNHOyPjKzn4Qa0PtHHu29p4MOGVM08= X-Google-Smtp-Source: APXvYqyXdVksYwZ+s1iQoCEHiQRowOqGPAhXBYs2s+XtYqXfvYRskzJ9+hO7AM+2uh5En5I7/pfHwA== X-Received: by 2002:a17:90a:5884:: with SMTP id j4mr10856534pji.142.1564858104262; Sat, 03 Aug 2019 11:48:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:44 -0700 Message-Id: <20190803184800.8221-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 18/34] target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part of a reorganization to the set of mmu_idx. The Secure regimes all have a single stage translation; there is no point in pointing out that the idx is for stage1. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 ++++---- target/arm/internals.h | 4 ++-- target/arm/translate.h | 2 +- target/arm/helper.c | 30 +++++++++++++++--------------- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 6 +++--- 6 files changed, 27 insertions(+), 27 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ade558f63c..c7ce8a4da5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2854,8 +2854,8 @@ typedef enum ARMMMUIdx { ARMMMUIdx_EL10_1 =3D 1 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A, - ARMMMUIdx_S1SE0 =3D 4 | ARM_MMU_IDX_A, - ARMMMUIdx_S1SE1 =3D 5 | ARM_MMU_IDX_A, + ARMMMUIdx_SE0 =3D 4 | ARM_MMU_IDX_A, + ARMMMUIdx_SE1 =3D 5 | ARM_MMU_IDX_A, ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M, @@ -2880,8 +2880,8 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_EL10_1 =3D 1 << 1, ARMMMUIdxBit_S1E2 =3D 1 << 2, ARMMMUIdxBit_S1E3 =3D 1 << 3, - ARMMMUIdxBit_S1SE0 =3D 1 << 4, - ARMMMUIdxBit_S1SE1 =3D 1 << 5, + ARMMMUIdxBit_SE0 =3D 1 << 4, + ARMMMUIdxBit_SE1 =3D 1 << 5, ARMMMUIdxBit_Stage2 =3D 1 << 6, ARMMMUIdxBit_MUser =3D 1 << 0, ARMMMUIdxBit_MPriv =3D 1 << 1, diff --git a/target/arm/internals.h b/target/arm/internals.h index cd9b1acb20..c505cae30c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -820,8 +820,8 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_MUser: return false; case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: + case ARMMMUIdx_SE0: + case ARMMMUIdx_SE1: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: diff --git a/target/arm/translate.h b/target/arm/translate.h index a20f6e2056..715fa08e3b 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -122,7 +122,7 @@ static inline int default_exception_el(DisasContext *s) * exceptions can only be routed to ELs above 1, so we target the high= er of * 1 or the current EL. */ - return (s->mmu_idx =3D=3D ARMMMUIdx_S1SE0 && s->secure_routed_to_el3) + return (s->mmu_idx =3D=3D ARMMMUIdx_SE0 && s->secure_routed_to_el3) ? 3 : MAX(1, s->current_el); } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 4c0c314c1a..e0d4f33026 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -566,7 +566,7 @@ static void contextidr_write(CPUARMState *env, const AR= MCPRegInfo *ri, =20 switch (ri->secure) { case ARM_CP_SECSTATE_S: - idxmask =3D ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + idxmask =3D ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; break; case ARM_CP_SECSTATE_NS: idxmask =3D ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; @@ -3122,7 +3122,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_Stage1_E1; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; + mmu_idx =3D secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; break; default: g_assert_not_reached(); @@ -3132,13 +3132,13 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_S1SE0; + mmu_idx =3D ARMMMUIdx_SE0; break; case 2: mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx =3D secure ? ARMMMUIdx_SE0 : ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3192,7 +3192,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; + mmu_idx =3D secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx =3D ARMMMUIdx_S1E2; @@ -3205,13 +3205,13 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx =3D secure ? ARMMMUIdx_SE0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_EL10_1; + mmu_idx =3D secure ? ARMMMUIdx_SE1 : ARMMMUIdx_EL10_1; break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_EL10_0; + mmu_idx =3D secure ? ARMMMUIdx_SE0 : ARMMMUIdx_EL10_0; break; default: g_assert_not_reached(); @@ -3424,7 +3424,7 @@ static void update_lpae_el1_asid(CPUARMState *env, in= t secure) ttcr =3D env->cp15.tcr_el[3].raw_tcr; /* Note that cp15.ttbr0_s =3D=3D cp15.ttbr0_el[3], so S1E3 is affe= cted. */ /* ??? Secure EL3 really using the ASID field? Doesn't make sense= . */ - idxmask =3D ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0 | ARMMMUIdxBit= _S1E3; + idxmask =3D ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0 | ARMMMUIdxBit_S1E= 3; break; case ARM_CP_SECSTATE_NS: ttbr0 =3D env->cp15.ttbr0_ns; @@ -3899,7 +3899,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState= *env, static int vae1_tlbmask(CPUARMState *env) { if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; } else { return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; } @@ -3935,7 +3935,7 @@ static int vmalle1_tlbmask(CPUARMState *env) * stage 1 translations. */ if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_St= age2; } else { @@ -8695,9 +8695,9 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) return 2; case ARMMMUIdx_S1E3: return 3; - case ARMMMUIdx_S1SE0: + case ARMMMUIdx_SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; - case ARMMMUIdx_S1SE1: + case ARMMMUIdx_SE1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_MPrivNegPri: @@ -8836,7 +8836,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env= , ARMMMUIdx mmu_idx) static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_S1SE0: + case ARMMMUIdx_SE0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: @@ -11279,7 +11279,7 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) =20 el =3D arm_current_el(env); if (el < 2 && arm_is_secure_below_el3(env)) { - return ARMMMUIdx_S1SE0 + el; + return ARMMMUIdx_SE0 + el; } else { return ARMMMUIdx_EL10_0 + el; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 73801c5df7..dbe2189e51 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -116,8 +116,8 @@ static inline int get_a64_user_mem_index(DisasContext *= s) case ARMMMUIdx_EL10_1: useridx =3D ARMMMUIdx_EL10_0; break; - case ARMMMUIdx_S1SE1: - useridx =3D ARMMMUIdx_S1SE0; + case ARMMMUIdx_SE1: + useridx =3D ARMMMUIdx_SE0; break; case ARMMMUIdx_Stage2: g_assert_not_reached(); diff --git a/target/arm/translate.c b/target/arm/translate.c index 995010834f..1fc2bf8a52 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -157,9 +157,9 @@ static inline int get_a32_user_mem_index(DisasContext *= s) case ARMMMUIdx_EL10_1: return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0); case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0); + case ARMMMUIdx_SE0: + case ARMMMUIdx_SE1: + return arm_to_core_mmu_idx(ARMMMUIdx_SE0); case ARMMMUIdx_MUser: case ARMMMUIdx_MPriv: return arm_to_core_mmu_idx(ARMMMUIdx_MUser); --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858685; cv=none; d=zoho.com; s=zohoarc; b=O88K0EVA8u/2LbkoyUwNorOA0ZgyX3f0DwGfSsEy1+VI2H8g6PyTLeDoJSV1oTh6NjgGQMJRB9BAmk6wQkFVF2/p0RGMaGVs9/c2EA6LzyVDW7/Nf1GyQmRluQ++24cFLtJucIR5sHXNNg70vxP9XAy+r9H3iHSZPCv8ZrnF070= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858685; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=uNn5q4INDqZzSSWnDmMk9zDSnWJbLDXBWQcIuUU2uJI=; b=NyEHUaowIwJ1Bk6LQmgofoqVTe4I9eRYDdRaD5q4x3eqmOvIGtHGJM2Ar3A7czGQNJwS8vD3KnEUbMS7vEae9g/But2yVIT3s8s7/3g632OGph/cGMwCoykkvFY65ibwnSmQ5K0H4zZRJ3w4rtoc0peQaYN5vtLpUbLTnWjERAM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858685352949.8384415122526; Sat, 3 Aug 2019 11:58:05 -0700 (PDT) Received: from localhost ([::1]:41539 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htzEC-0002cl-E9 for importer@patchew.org; Sat, 03 Aug 2019 14:58:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60938) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz4v-0006Rr-Q4 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz4u-0007Ib-CU for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:29 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:46089) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz4u-0007HJ-4s for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:28 -0400 Received: by mail-pf1-x443.google.com with SMTP id c3so14484240pfa.13 for ; Sat, 03 Aug 2019 11:48:26 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.24 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uNn5q4INDqZzSSWnDmMk9zDSnWJbLDXBWQcIuUU2uJI=; b=Jr7Kr4c7WspWidhsMVEBqY65eKtoOdpD1vCf6jz53B3T1k0v4zi0g49FgBx3q1I7Dl BTWK7XyI/dIIKkJfmI3AbpmfrMn9f/Zzb+m+zzgjRAeUKHoRjtzmfBr43KMhTVdGoG6e R1jshS01nZ63gENO4CsOUEOID4yKeDERfXiWhVs4ZmspOYpH1022C7gHcmepqL/GlgqK xg47MUOEO+7FCLiL6o3DI+Msqbvtpd44FOF4sZFCLthzejM9lygGkgjwPtLY8k0DjeyO zm0EToUtJ4y5e6tNnTApDJ2mJgMTrHiVFPqPYTi509+wTyGFH6chjSpQwLW+tBdffG9J KlmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uNn5q4INDqZzSSWnDmMk9zDSnWJbLDXBWQcIuUU2uJI=; b=Yn/LZNYQufWF9oXJ2CyH2/Z4WPZh0DrMpeG48zXY1kWOhYRMeX87EvOpGARpqLmyLR i0qeL9YTL6lcwtkbjZpo8hm05ifBk6sT+b+sIl40j8re3zCAdevOvOs9Sz5y4/Xml+1p yLuoz7dawYYga1S+dXp7TfOhpr8zquplNQe6/eU3hEUfdMgTCVDdBwrJGo/7SW4ehwOI MS3r/MvvtA+LoIX1ggUu6hmCZo4LF67yr2HrAz9PJ1eRLZy4o8QVQjQIHUZKr7otY4pJ mVdRylKcTbaQIWmBfs52zCRgR7nPphv7TR7Ww8riiBOIjHTKWS9rCZeMyAIkP9y8/W+O j/4g== X-Gm-Message-State: APjAAAWe5M1yMlD8LjviR3Tib6h3vwtdUPOzyqsJkfxvTB0q51sZtg/k xZ3UMTZFUskvWgoe8CMADf0axjB/L4k= X-Google-Smtp-Source: APXvYqwtfwYy11Q3TnWncDpBK98jxsrjIdg5N9okbvj9A3tuTM6JF4sTI0DsYGJ09rG7Ft1hPhWZBw== X-Received: by 2002:a62:187:: with SMTP id 129mr66266219pfb.128.1564858105384; Sat, 03 Aug 2019 11:48:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:45 -0700 Message-Id: <20190803184800.8221-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 19/34] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part of a reorganization to the set of mmu_idx. The EL3 regime only has a single stage translation, and is always secure. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 2 +- target/arm/helper.c | 18 +++++++++--------- target/arm/translate.c | 2 +- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c7ce8a4da5..94337b2fb0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2853,7 +2853,7 @@ typedef enum ARMMMUIdx { ARMMMUIdx_EL10_0 =3D 0 | ARM_MMU_IDX_A, ARMMMUIdx_EL10_1 =3D 1 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, - ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A, + ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_SE0 =3D 4 | ARM_MMU_IDX_A, ARMMMUIdx_SE1 =3D 5 | ARM_MMU_IDX_A, ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, @@ -2879,7 +2879,7 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_EL10_0 =3D 1 << 0, ARMMMUIdxBit_EL10_1 =3D 1 << 1, ARMMMUIdxBit_S1E2 =3D 1 << 2, - ARMMMUIdxBit_S1E3 =3D 1 << 3, + ARMMMUIdxBit_SE3 =3D 1 << 3, ARMMMUIdxBit_SE0 =3D 1 << 4, ARMMMUIdxBit_SE1 =3D 1 << 5, ARMMMUIdxBit_Stage2 =3D 1 << 6, diff --git a/target/arm/internals.h b/target/arm/internals.h index c505cae30c..dbb46da549 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -819,7 +819,7 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_MPriv: case ARMMMUIdx_MUser: return false; - case ARMMMUIdx_S1E3: + case ARMMMUIdx_SE3: case ARMMMUIdx_SE0: case ARMMMUIdx_SE1: case ARMMMUIdx_MSPrivNegPri: diff --git a/target/arm/helper.c b/target/arm/helper.c index e0d4f33026..e5b07b4770 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3116,7 +3116,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_S1E3; + mmu_idx =3D ARMMMUIdx_SE3; break; case 2: mmu_idx =3D ARMMMUIdx_Stage1_E1; @@ -3198,7 +3198,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, mmu_idx =3D ARMMMUIdx_S1E2; break; case 6: /* AT S1E3R, AT S1E3W */ - mmu_idx =3D ARMMMUIdx_S1E3; + mmu_idx =3D ARMMMUIdx_SE3; break; default: g_assert_not_reached(); @@ -3422,9 +3422,9 @@ static void update_lpae_el1_asid(CPUARMState *env, in= t secure) ttbr0 =3D env->cp15.ttbr0_s; ttbr1 =3D env->cp15.ttbr1_s; ttcr =3D env->cp15.tcr_el[3].raw_tcr; - /* Note that cp15.ttbr0_s =3D=3D cp15.ttbr0_el[3], so S1E3 is affe= cted. */ + /* Note that cp15.ttbr0_s =3D=3D cp15.ttbr0_el[3], so SE3 is affec= ted. */ /* ??? Secure EL3 really using the ASID field? Doesn't make sense= . */ - idxmask =3D ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0 | ARMMMUIdxBit_S1E= 3; + idxmask =3D ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0 | ARMMMUIdxBit_SE3; break; case ARM_CP_SECSTATE_NS: ttbr0 =3D env->cp15.ttbr0_ns; @@ -3967,7 +3967,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3); } =20 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -3992,7 +3992,7 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env,= const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); } =20 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4020,7 +4020,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3); } =20 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -4069,7 +4069,7 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E3); + ARMMMUIdxBit_SE3); } =20 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -8693,7 +8693,7 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) case ARMMMUIdx_Stage2: case ARMMMUIdx_S1E2: return 2; - case ARMMMUIdx_S1E3: + case ARMMMUIdx_SE3: return 3; case ARMMMUIdx_SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; diff --git a/target/arm/translate.c b/target/arm/translate.c index 1fc2bf8a52..5372947e47 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -156,7 +156,7 @@ static inline int get_a32_user_mem_index(DisasContext *= s) case ARMMMUIdx_EL10_0: case ARMMMUIdx_EL10_1: return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0); - case ARMMMUIdx_S1E3: + case ARMMMUIdx_SE3: case ARMMMUIdx_SE0: case ARMMMUIdx_SE1: return arm_to_core_mmu_idx(ARMMMUIdx_SE0); --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858647; cv=none; d=zoho.com; s=zohoarc; b=ITxHUjdgOl5RND5CGsS5yhzJ/mFa84SVqQOloImFigaBJnTXeOOUeQy6NrZ+Hq0evuhAyMdcY0QB7a6HR+Bs0m6PzXeIC2a+TH5jDxYwn8sYd2rs5KPwD4FiitDePn6O9V8pev54j/l3qo+xNU3a/+N5fAJc11ZJUWRcW5LqPuo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858647; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=trlNGPogxXBK9OHHkWCBGsx/W/Lwzy6lbLUgzLGbb4A=; b=UrwoUhuOcNPCBm6hhl1xlxUWNjQGaxMRBe7o2ZtwskL/0P73wNct1IFIFwTRCDEQD2d/TBLMYbFPJV5DcBUb5lOoj8lrHkVzuhCSDLRxJaNTDdY4iUR2ZMaRubIKFIAImjdyiPcE+7s386POX/3Kmly/+wQGrNP02MWbrt+BNzo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858647868203.3720851600409; Sat, 3 Aug 2019 11:57:27 -0700 (PDT) Received: from localhost ([::1]:41525 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htzDa-0000jb-TN for importer@patchew.org; Sat, 03 Aug 2019 14:57:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60945) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz4v-0006SL-Ti for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz4u-0007Ii-DE for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:29 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:34464) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz4u-0007Hh-3m for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:28 -0400 Received: by mail-pf1-x444.google.com with SMTP id b13so37624306pfo.1 for ; Sat, 03 Aug 2019 11:48:27 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.25 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=trlNGPogxXBK9OHHkWCBGsx/W/Lwzy6lbLUgzLGbb4A=; b=odxwR9YiZlmrGzO7nK5x0AhHcuzhht7jcq0WhlNQQ435GlTLBD9THl+3O3xN+t3S8l Mjjl/Bpa3Y4ktoiHXlSVFsy3PY0tO931k7fbIopPIMSHjy37h3SnI/17cNUE7gy/eEWO BlLJR4LbROSaNtbY5CsUzRCofyePk6lM2zUIL9XeFQn/AiKmOOiO2O4UMnBgs09iUfJ2 74P6x64vngm09vFVL+36Y9sY9LtwuQIcqpG1MEzzJ2XQb9J+Q7utHiXIT/1VVam0WTxE bzKp9eTr0Kw8211EBtHNGuaNfxPHQYJvyL6LVsDJYSTXsscLU+8sM6gKGkpL2flczyrT 1LsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=trlNGPogxXBK9OHHkWCBGsx/W/Lwzy6lbLUgzLGbb4A=; b=FyZCBkJmiObRF6DnFtT8wX5b9r11/HJcyKeYJsdbyjpgva9Tu8Yvq+Jlq5YoAQ3CKT v1r1R7E/Q9mVLVry6gZvRd7h2BtzQMJYaOjSrlBQzp7bx3HrYG3OQ1peUousZUEGHdBC 4+XtZvLoHuvrKjkXZju8b/xOS/k4XV3GD9etarLTeHRq5Je8jqnELSID63IQC4yJMmvp 55yV1iE3U0Lznyk8SHTVYiRVfagd1Bks8baeu3RTvKK+wfAee19f09ja4PC+N194STGe SkvpQecYN8ZLhlvsXWwCXHVaUtvYgrT+qRSqhPE50taTnjt8xrlyLeG/UrpLLUpt9B6+ Z8JQ== X-Gm-Message-State: APjAAAXBy0hn2eFU9Uee6i4VYjjZGTsxIxf/VEoza3Bc4qxL+UKxvEpp OM2iU7sooq2Q+nNtEqHQzpcJPz5IROY= X-Google-Smtp-Source: APXvYqwxM/3UARKqJskI/oXr22WO4XWVPXzu0+asKskhLocWoSn3I8aNeHIIKljsCveP5ntCq+C9qQ== X-Received: by 2002:a17:90a:9a95:: with SMTP id e21mr10190086pjp.98.1564858106593; Sat, 03 Aug 2019 11:48:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:46 -0700 Message-Id: <20190803184800.8221-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 20/34] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part of a reorganization to the set of mmu_idx. The non-secure EL2 regime only has a single stage translation; there is no point in pointing out that the idx is for stage1. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 2 +- target/arm/helper.c | 24 ++++++++++++------------ target/arm/translate.c | 2 +- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 94337b2fb0..552269daad 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2852,7 +2852,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, typedef enum ARMMMUIdx { ARMMMUIdx_EL10_0 =3D 0 | ARM_MMU_IDX_A, ARMMMUIdx_EL10_1 =3D 1 | ARM_MMU_IDX_A, - ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 =3D 2 | ARM_MMU_IDX_A, ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_SE0 =3D 4 | ARM_MMU_IDX_A, ARMMMUIdx_SE1 =3D 5 | ARM_MMU_IDX_A, @@ -2878,7 +2878,7 @@ typedef enum ARMMMUIdx { typedef enum ARMMMUIdxBit { ARMMMUIdxBit_EL10_0 =3D 1 << 0, ARMMMUIdxBit_EL10_1 =3D 1 << 1, - ARMMMUIdxBit_S1E2 =3D 1 << 2, + ARMMMUIdxBit_E2 =3D 1 << 2, ARMMMUIdxBit_SE3 =3D 1 << 3, ARMMMUIdxBit_SE0 =3D 1 << 4, ARMMMUIdxBit_SE1 =3D 1 << 5, diff --git a/target/arm/internals.h b/target/arm/internals.h index dbb46da549..027878516f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -812,7 +812,7 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_EL10_1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_S1E2: + case ARMMMUIdx_E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: diff --git a/target/arm/helper.c b/target/arm/helper.c index e5b07b4770..69c913d824 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -740,7 +740,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); } =20 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -748,7 +748,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); } =20 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -757,7 +757,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); } =20 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -767,7 +767,7 @@ static void tlbimva_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E2); + ARMMMUIdxBit_E2); } =20 static const ARMCPRegInfo cp_reginfo[] =3D { @@ -3167,7 +3167,7 @@ static void ats1h_write(CPUARMState *env, const ARMCP= RegInfo *ri, MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; uint64_t par64; =20 - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_S1E2); + par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); } @@ -3195,7 +3195,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, mmu_idx =3D secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx =3D ARMMMUIdx_S1E2; + mmu_idx =3D ARMMMUIdx_E2; break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx =3D ARMMMUIdx_SE3; @@ -3958,7 +3958,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3984,7 +3984,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,= const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4006,7 +4006,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4059,7 +4059,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E2); + ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -4375,7 +4375,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "AT_S12E0W", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 7, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, - /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present= */ + /* AT E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ { .name =3D "AT_S1E3R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, @@ -8691,7 +8691,7 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_Stage2: - case ARMMMUIdx_S1E2: + case ARMMMUIdx_E2: return 2; case ARMMMUIdx_SE3: return 3; diff --git a/target/arm/translate.c b/target/arm/translate.c index 5372947e47..4e79dbbdfc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -152,7 +152,7 @@ static inline int get_a32_user_mem_index(DisasContext *= s) * otherwise, access as if at PL0. */ switch (s->mmu_idx) { - case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */ + case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_EL10_0: case ARMMMUIdx_EL10_1: return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0); --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.26 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C4yPNU5MzTttlOEZGJqyKcDVIL6n5tI4jir190lVFFk=; b=JQIYGZ53MtqAowkP2w6l/7Wd/j/veiwZC49CUbVDamurSfVRPozCNx6usezA+jz41x FcmDYL3K1AiLcawd29RXtu04yyoFF5MBF0VnvK2j7RA9AgFlbiY7muB6HcIZTPfCIN8D VquiPPs5H1om2PMOzAMn4ANu22yrskwBy/GIAZFPmBgUAP4LnUdPteuNPc/lpai3BJTE UtSubYeZHkeaVLT5gxt4jLGss2bT8lr9gIK7X6nXptXNWQmzX5XJH2Bc+uftMbZztPIv TmhOSdgvkx+AySe/qCfggGSQCB067RNpdLxUHbas2ZcapbVt+aOwHrDLXDik/+UfakAU yFDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C4yPNU5MzTttlOEZGJqyKcDVIL6n5tI4jir190lVFFk=; b=KAyoFcHrDDyTOCHlbAyPju2IDsB9/9Ud5DyYBKO0m8hz8CNXo/V3FotpAqDmGC7/SY 93RCOzOehf0cWK29Yjgmu8fOntjpwsfrG2RQQUxyfGbEvmlmW7R4oMXDEH87zc9SxQUR t0qcNLMGL3SiZLKorNkvObeUgRPNlSXTBK7psLzkXlAe8C/8uvivDJ5dd5+Xji5EN3uO K24QWKMs4kWjTIs8uFjKnxxuUIenDcZd0SK0DNq+Y1rIFBaVl/N0GYJ0Hzz4ZO9oKEWB EWyGwt6aRjih9yS/WtW1aZ1HWfMf+63po8rv0oIenZxobcik6kwxaIqRzUSkI61nHOl4 7vTg== X-Gm-Message-State: APjAAAWMZm6Fv9++pJwhWWrOvJiE911O+2/RUqzDLmRj03XWPPMB4CMn n1NQPS+4kHeB9OKqcKL8Ib2NNiy5RAk= X-Google-Smtp-Source: APXvYqwsvF3TjE7yXzXjfTRpgx4Mm/g8rY6+VhFa2dAecaLuIBPysJH9p21YIfbSMT99FZimcaeVaA== X-Received: by 2002:a65:6108:: with SMTP id z8mr98286967pgu.289.1564858107784; Sat, 03 Aug 2019 11:48:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:47 -0700 Message-Id: <20190803184800.8221-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 21/34] target/arm: Reorganize ARMMMUIdx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Prepare for, but do not yet implement, the EL2&0 regime and the Secure EL2 regime. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 173 ++++++++++++++++++++--------------------- target/arm/internals.h | 44 +++++------ target/arm/helper.c | 60 ++++++++++++-- target/arm/m_helper.c | 6 +- target/arm/translate.c | 1 - 5 files changed, 165 insertions(+), 119 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 552269daad..b5300f9014 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2764,7 +2764,10 @@ static inline bool arm_excp_unmasked(CPUState *cs, u= nsigned int excp_idx, * + NonSecure EL1 & 0 stage 1 * + NonSecure EL1 & 0 stage 2 * + NonSecure EL2 - * + Secure EL1 & EL0 + * + NonSecure EL2 & 0 (ARMv8.1-VHE) + * + Secure EL0 + * + Secure EL1 + * + Secure EL2 (ARMv8.4-SecEL2) * + Secure EL3 * If EL3 is 32-bit: * + NonSecure PL1 & 0 stage 1 @@ -2774,8 +2777,9 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) * * For QEMU, an mmu_idx is not quite the same as a translation regime beca= use: - * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because = they - * may differ in access permissions even if the VA->PA map is the same + * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_i= dxes, + * because they may differ in access permissions even if the VA->PA ma= p is + * the same * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage= 1+2 * translation, which means that we have one mmu_idx that deals with t= wo * concatenated translation regimes [this sort of combined s1+2 TLB is @@ -2787,19 +2791,26 @@ static inline bool arm_excp_unmasked(CPUState *cs, = unsigned int excp_idx, * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" * translation regimes, because they map reasonably well to each other * and they can't both be active at the same time. - * This gives us the following list of mmu_idx values: + * 5. we want to be able to use the TLB for accesses done as part of a + * stage1 page table walk, rather than having to walk the stage2 page + * table over and over. * - * NS EL0 (aka NS PL0) stage 1+2 - * NS EL1 (aka NS PL1) stage 1+2 + * This gives us the following list of cases: + * + * NS EL0 (aka NS PL0) EL1&0 stage 1+2 + * NS EL1 (aka NS PL1) EL1&0 stage 1+2 + * NS EL0 (aka NS PL0) EL2&0 + * NS EL2 (aka NS PL2) EL2&0 * NS EL2 (aka NS PL2) - * S EL3 (aka S PL1) * S EL0 (aka S PL0) * S EL1 (not used if EL3 is 32 bit) - * NS EL0+1 stage 2 + * S EL2 (not used if EL3 is 32 bit) + * S EL3 (aka S PL1) + * NS EL0&1 stage 2 * - * (The last of these is an mmu_idx because we want to be able to use the = TLB - * for the accesses done as part of a stage 1 page table walk, rather than - * having to walk the stage 2 page table over and over.) + * We then merge the two NS EL0 cases, and two NS EL2 cases to produce + * 8 different mmu_idx. We retain separate symbols for these four cases + * in order to simplify distinguishing them in the code. * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish NS EL0 and NS EL1 (and @@ -2837,62 +2848,88 @@ static inline bool arm_excp_unmasked(CPUState *cs, = unsigned int excp_idx, * For M profile we arrange them to have a bit for priv, a bit for negpri * and a bit for secure. */ -#define ARM_MMU_IDX_A 0x10 /* A profile */ -#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ -#define ARM_MMU_IDX_M 0x40 /* M profile */ +#define ARM_MMU_IDX_S 0x04 /* Secure */ +#define ARM_MMU_IDX_A 0x10 /* A profile */ +#define ARM_MMU_IDX_M 0x20 /* M profile */ +#define ARM_MMU_IDX_NOTLB 0x100 /* does not have a TLB */ =20 -/* meanings of the bits for M profile mmu idx values */ -#define ARM_MMU_IDX_M_PRIV 0x1 +/* Meanings of the bits for A profile mmu idx values */ +#define ARM_MMU_IDX_A_PRIV 0x3 +#define ARM_MMU_IDX_A_EL10 0x40 +#define ARM_MMU_IDX_A_EL20 0x80 + +/* Meanings of the bits for M profile mmu idx values */ +#define ARM_MMU_IDX_M_PRIV 0x1 #define ARM_MMU_IDX_M_NEGPRI 0x2 -#define ARM_MMU_IDX_M_S 0x4 =20 -#define ARM_MMU_IDX_TYPE_MASK (~0x7) +#define ARM_MMU_IDX_TYPE_MASK (ARM_MMU_IDX_A | ARM_MMU_IDX_M) #define ARM_MMU_IDX_COREIDX_MASK 0x7 =20 typedef enum ARMMMUIdx { - ARMMMUIdx_EL10_0 =3D 0 | ARM_MMU_IDX_A, - ARMMMUIdx_EL10_1 =3D 1 | ARM_MMU_IDX_A, + ARMMMUIdx_EL10_0 =3D 0 | ARM_MMU_IDX_A | ARM_MMU_IDX_A_EL10, + ARMMMUIdx_EL10_1 =3D 1 | ARM_MMU_IDX_A | ARM_MMU_IDX_A_EL10, + ARMMMUIdx_EL20_0 =3D 0 | ARM_MMU_IDX_A | ARM_MMU_IDX_A_EL20, + ARMMMUIdx_EL20_2 =3D 2 | ARM_MMU_IDX_A | ARM_MMU_IDX_A_EL20, + ARMMMUIdx_E2 =3D 2 | ARM_MMU_IDX_A, - ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A, - ARMMMUIdx_SE0 =3D 4 | ARM_MMU_IDX_A, - ARMMMUIdx_SE1 =3D 5 | ARM_MMU_IDX_A, - ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, + + /* + * While Stage2 is used by A profile, and uses a TLB, it is only + * used for page table walks and is not a valid as an arm_mmu_idx(). + * Overlap it on the non-existant non-secure el3 slot. + */ + ARMMMUIdx_Stage2 =3D 3, + + ARMMMUIdx_SE0 =3D 0 | ARM_MMU_IDX_S | ARM_MMU_IDX_A, + ARMMMUIdx_SE1 =3D 1 | ARM_MMU_IDX_S | ARM_MMU_IDX_A, + ARMMMUIdx_SE2 =3D 2 | ARM_MMU_IDX_S | ARM_MMU_IDX_A, + ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_S | ARM_MMU_IDX_A, + ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M, ARMMMUIdx_MUserNegPri =3D 2 | ARM_MMU_IDX_M, ARMMMUIdx_MPrivNegPri =3D 3 | ARM_MMU_IDX_M, - ARMMMUIdx_MSUser =3D 4 | ARM_MMU_IDX_M, - ARMMMUIdx_MSPriv =3D 5 | ARM_MMU_IDX_M, - ARMMMUIdx_MSUserNegPri =3D 6 | ARM_MMU_IDX_M, - ARMMMUIdx_MSPrivNegPri =3D 7 | ARM_MMU_IDX_M, - /* Indexes below here don't have TLBs and are used only for AT system - * instructions or for the first stage of an S12 page table walk. - */ - ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_MSUser =3D 0 | ARM_MMU_IDX_S | ARM_MMU_IDX_M, + ARMMMUIdx_MSPriv =3D 1 | ARM_MMU_IDX_S | ARM_MMU_IDX_M, + ARMMMUIdx_MSUserNegPri =3D 2 | ARM_MMU_IDX_S | ARM_MMU_IDX_M, + ARMMMUIdx_MSPrivNegPri =3D 3 | ARM_MMU_IDX_S | ARM_MMU_IDX_M, + + /* Indicies that are only used only for AT system or Stage1 walk. */ + ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_A | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_A | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; =20 -/* Bit macros for the core-mmu-index values for each index, +/* + * Bit macros for the core-mmu-index values for each index, * for use when calling tlb_flush_by_mmuidx() and friends. */ +#define TO_CORE_BIT(NAME) \ + ARMMMUIdxBit_##NAME =3D 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_M= ASK) + typedef enum ARMMMUIdxBit { - ARMMMUIdxBit_EL10_0 =3D 1 << 0, - ARMMMUIdxBit_EL10_1 =3D 1 << 1, - ARMMMUIdxBit_E2 =3D 1 << 2, - ARMMMUIdxBit_SE3 =3D 1 << 3, - ARMMMUIdxBit_SE0 =3D 1 << 4, - ARMMMUIdxBit_SE1 =3D 1 << 5, - ARMMMUIdxBit_Stage2 =3D 1 << 6, - ARMMMUIdxBit_MUser =3D 1 << 0, - ARMMMUIdxBit_MPriv =3D 1 << 1, - ARMMMUIdxBit_MUserNegPri =3D 1 << 2, - ARMMMUIdxBit_MPrivNegPri =3D 1 << 3, - ARMMMUIdxBit_MSUser =3D 1 << 4, - ARMMMUIdxBit_MSPriv =3D 1 << 5, - ARMMMUIdxBit_MSUserNegPri =3D 1 << 6, - ARMMMUIdxBit_MSPrivNegPri =3D 1 << 7, + TO_CORE_BIT(EL10_0), + TO_CORE_BIT(EL10_1), + TO_CORE_BIT(EL20_0), + TO_CORE_BIT(EL20_2), + TO_CORE_BIT(E2), + TO_CORE_BIT(Stage2), + TO_CORE_BIT(SE0), + TO_CORE_BIT(SE1), + TO_CORE_BIT(SE2), + TO_CORE_BIT(SE3), + + TO_CORE_BIT(MUser), + TO_CORE_BIT(MPriv), + TO_CORE_BIT(MUserNegPri), + TO_CORE_BIT(MPrivNegPri), + TO_CORE_BIT(MSUser), + TO_CORE_BIT(MSPriv), + TO_CORE_BIT(MSUserNegPri), + TO_CORE_BIT(MSPrivNegPri), } ARMMMUIdxBit; =20 +#undef TO_CORE_BIT + #define MMU_USER_IDX 0 =20 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) @@ -2900,44 +2937,6 @@ static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_= idx) return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; } =20 -static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) -{ - if (arm_feature(env, ARM_FEATURE_M)) { - return mmu_idx | ARM_MMU_IDX_M; - } else { - return mmu_idx | ARM_MMU_IDX_A; - } -} - -/* Return the exception level we're running at if this is our mmu_idx */ -static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) -{ - switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { - case ARM_MMU_IDX_A: - return mmu_idx & 3; - case ARM_MMU_IDX_M: - return mmu_idx & ARM_MMU_IDX_M_PRIV; - default: - g_assert_not_reached(); - } -} - -/* - * Return the MMU index for a v7M CPU with all relevant information - * manually specified. - */ -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, - bool secstate, bool priv, bool negpri); - -/* Return the MMU index for a v7M CPU in the specified security and - * privilege state. - */ -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, - bool secstate, bool priv); - -/* Return the MMU index for a v7M CPU in the specified security state */ -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); - /** * cpu_mmu_index: * @env: The cpu environment diff --git a/target/arm/internals.h b/target/arm/internals.h index 027878516f..dd0bc4377f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -769,6 +769,26 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx); +int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); + +/* + * Return the MMU index for a v7M CPU with all relevant information + * manually specified. + */ +ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, + bool secstate, bool priv, bool negpri); + +/* + * Return the MMU index for a v7M CPU in the specified security and + * privilege state. + */ +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv); + +/* Return the MMU index for a v7M CPU in the specified security state */ +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); + /* Return true if the stage 1 translation regime is using LPAE format page * tables */ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); @@ -807,29 +827,7 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) /* Return true if this address translation regime is secure */ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) { - switch (mmu_idx) { - case ARMMMUIdx_EL10_0: - case ARMMMUIdx_EL10_1: - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_E2: - case ARMMMUIdx_Stage2: - case ARMMMUIdx_MPrivNegPri: - case ARMMMUIdx_MUserNegPri: - case ARMMMUIdx_MPriv: - case ARMMMUIdx_MUser: - return false; - case ARMMMUIdx_SE3: - case ARMMMUIdx_SE0: - case ARMMMUIdx_SE1: - case ARMMMUIdx_MSPrivNegPri: - case ARMMMUIdx_MSUserNegPri: - case ARMMMUIdx_MSPriv: - case ARMMMUIdx_MSUser: - return true; - default: - g_assert_not_reached(); - } + return (mmu_idx & ARM_MMU_IDX_S) !=3D 0; } =20 /* Return the FSR value for a debug exception (watchpoint, hardware diff --git a/target/arm/helper.c b/target/arm/helper.c index 69c913d824..9c2c81c434 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8687,9 +8687,11 @@ void arm_cpu_do_interrupt(CPUState *cs) #endif /* !CONFIG_USER_ONLY */ =20 /* Return the exception level which controls this address translation regi= me */ -static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) +static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { + case ARMMMUIdx_EL20_0: + case ARMMMUIdx_EL20_2: case ARMMMUIdx_Stage2: case ARMMMUIdx_E2: return 2; @@ -8700,6 +8702,8 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) case ARMMMUIdx_SE1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_EL10_0: + case ARMMMUIdx_EL10_1: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -11262,6 +11266,41 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } =20 +ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) +{ + if (arm_feature(env, ARM_FEATURE_M)) { + return mmu_idx | ARM_MMU_IDX_M; + } + + mmu_idx |=3D ARM_MMU_IDX_A; + switch (mmu_idx) { + case 0 | ARM_MMU_IDX_A: + return ARMMMUIdx_EL10_0; + case 1 | ARM_MMU_IDX_A: + return ARMMMUIdx_EL10_1; + case ARMMMUIdx_E2: + case ARMMMUIdx_SE0: + case ARMMMUIdx_SE1: + case ARMMMUIdx_SE3: + return mmu_idx; + default: + g_assert_not_reached(); + } +} + +/* Return the exception level we're running at if this is our mmu_idx */ +int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) +{ + switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { + case ARM_MMU_IDX_A: + return mmu_idx & ARM_MMU_IDX_A_PRIV; + case ARM_MMU_IDX_M: + return mmu_idx & ARM_MMU_IDX_M_PRIV; + default: + g_assert_not_reached(); + } +} + #ifndef CONFIG_TCG ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) { @@ -11278,10 +11317,21 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) } =20 el =3D arm_current_el(env); - if (el < 2 && arm_is_secure_below_el3(env)) { - return ARMMMUIdx_SE0 + el; - } else { - return ARMMMUIdx_EL10_0 + el; + switch (el) { + case 0: + /* TODO: ARMv8.1-VHE */ + case 1: + return (arm_is_secure_below_el3(env) + ? ARMMMUIdx_SE0 + el + : ARMMMUIdx_EL10_0 + el); + case 2: + /* TODO: ARMv8.1-VHE */ + /* TODO: ARMv8.4-SecEL2 */ + return ARMMMUIdx_E2; + case 3: + return ARMMMUIdx_SE3; + default: + g_assert_not_reached(); } } =20 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 84609f446e..f745c0d067 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -126,7 +126,7 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr,= uint32_t value, hwaddr physaddr; int prot; ARMMMUFaultInfo fi =3D {}; - bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; + bool secure =3D mmu_idx & ARM_MMU_IDX_S; int exc; bool exc_secure; =20 @@ -218,7 +218,7 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest,= uint32_t addr, hwaddr physaddr; int prot; ARMMMUFaultInfo fi =3D {}; - bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; + bool secure =3D mmu_idx & ARM_MMU_IDX_S; int exc; bool exc_secure; uint32_t value; @@ -2669,7 +2669,7 @@ ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, } =20 if (secstate) { - mmu_idx |=3D ARM_MMU_IDX_M_S; + mmu_idx |=3D ARM_MMU_IDX_S; } =20 return mmu_idx; diff --git a/target/arm/translate.c b/target/arm/translate.c index 4e79dbbdfc..f25d5f18c6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -172,7 +172,6 @@ static inline int get_a32_user_mem_index(DisasContext *= s) case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPrivNegPri: return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri); - case ARMMMUIdx_Stage2: default: g_assert_not_reached(); } --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858760; cv=none; d=zoho.com; s=zohoarc; b=hbdZMfC6hAq6ZKpibKjceyfBAjFYusiIMkTymudYzZCaG212UKEVevmqAkgAbkdV7H+kn4IEVilDjmOF3hu6zcpdaCN9t0pgQSJVxh1mIDeCxG4gofxj9n81nUxvqzqnt0SgROkWiGxCifBY+iSWmWZOob+dpdzVK+9h6lL0xrA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858760; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=F8zJJPz0HoAAcPGItYsG98fn3EhRGHL9/KSAWCPhxyQ=; b=hTGpAdVmNn4vKNk/q0oE3zWVbnpvbJpEF/A8yoBu/6HK+aFlIjuBBRVigUCkJzOwsAy8kAezcGFu93F5EqjU8loqRJUnGk7CL4RyqBJX3FLlTWl+ILW+lykpBPbQhJkRZVvn5kFAAmnfVSRv5EruWlH87l1jCR7Ob1f0+qKT5KM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156485876060529.002565055972582; Sat, 3 Aug 2019 11:59:20 -0700 (PDT) Received: from localhost ([::1]:41566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htzFP-00061O-JZ for importer@patchew.org; Sat, 03 Aug 2019 14:59:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32780) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz4y-0006b2-0G for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz4w-0007KS-H7 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:31 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:37893) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz4w-0007Jh-Az for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:30 -0400 Received: by mail-pf1-x430.google.com with SMTP id y15so37633372pfn.5 for ; Sat, 03 Aug 2019 11:48:30 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.28 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F8zJJPz0HoAAcPGItYsG98fn3EhRGHL9/KSAWCPhxyQ=; b=nyYDZlSWyWGgw+mPVtlmhwfzB+jmeYrS0DerBgWFeqgL+G4q5VWZOZ8SvW5yOrpQZt OHDluovFZg0lfnnBNbYnupFrR153G38gNkqA67gqexIqco+RYNjPDDClWR8fgOPjk5BQ qnpqCzjqxWSrxhSjZ5eOopQU/pnZtFYggk0+wyZSClNmfhdb17isKnb+g1TbzwJMVhtk Gl+rsPp3ix+4j/Aw5+T6ATffS5ACO04ZxhbIp5pfMjzVEN1p4GImzqxntaCIfY/+qj4T mffVDkVALM4tRvVLgN2k3kDSiu2BT7swflBjyPLmIt0k8m82/9y5KlfaqFVLSQOHQ1zm TfTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F8zJJPz0HoAAcPGItYsG98fn3EhRGHL9/KSAWCPhxyQ=; b=o0yJNPvJSSoIYfzAAeSjesfH89itSZYHqFOerrKD4Op5WLrIwjT3fSjdiRUk1ezPX3 XaUZ/nntgySvENdhrtRv8/ELC7Br819YWsGgQFAMRAXgx2muX6JxoUbm2QIs8Bxs8gn1 dzBFDwkvzUFHd336o6/dQQ5uraYgMrr7XFzKDe8gNt+9p9i9DE/pdv+aYZ0tRROmvWSx tVd0KDiKLxwiXHurFuv/tCIJ37RACbVMhPXKO0Bhfwzufh6Lq9DNgJkCZnWegAuk+os6 5nkRuOl5QNa5wBjYs2QroRPPkcS7M5xoyajyfipmj1DFXGXl1enSPrvnN6C9I3hwCNdd z/Ow== X-Gm-Message-State: APjAAAWJ4YZnOLcxhuHBGJTAssgmB2b9LzxoF2Rxfxiz/gEkDU5wzK5Q nWYR2pxC7Vbnt3+wLuK4YhhvBzabwKw= X-Google-Smtp-Source: APXvYqy3xTj9oqSIYbTPypv1AsJSv14cGHMyy2JQWWk3EshdshfwPQgU9GhGjz63ufBmQnI88Z3QJw== X-Received: by 2002:a63:f926:: with SMTP id h38mr40174630pgi.80.1564858108975; Sat, 03 Aug 2019 11:48:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:48 -0700 Message-Id: <20190803184800.8221-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PATCH v3 22/34] target/arm: Add regime_has_2_ranges X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/internals.h | 16 ++++++++++++++++ target/arm/helper.c | 22 +++++----------------- target/arm/translate-a64.c | 3 +-- 3 files changed, 22 insertions(+), 19 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index dd0bc4377f..1b64ceeda6 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -824,6 +824,22 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) } } =20 +/* Return true if this address translation regime has two ranges. */ +static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_EL10_0: + case ARMMMUIdx_EL10_1: + case ARMMMUIdx_EL20_0: + case ARMMMUIdx_EL20_2: + return true; + default: + return false; + } +} + /* Return true if this address translation regime is secure */ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 9c2c81c434..5472424179 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9006,15 +9006,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mm= u_idx, bool is_aa64, } =20 if (is_aa64) { - switch (regime_el(env, mmu_idx)) { - case 1: - if (!is_user) { - xn =3D pxn || (user_rw & PAGE_WRITE); - } - break; - case 2: - case 3: - break; + if (regime_has_2_ranges(mmu_idx) && !is_user) { + xn =3D pxn || (user_rw & PAGE_WRITE); } } else if (arm_feature(env, ARM_FEATURE_V7)) { switch (regime_el(env, mmu_idx)) { @@ -9548,7 +9541,6 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, ARMMMUIdx mmu_idx) { uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; - uint32_t el =3D regime_el(env, mmu_idx); bool tbi, tbid, epd, hpd, using16k, using64k; int select, tsz; =20 @@ -9558,7 +9550,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, */ select =3D extract64(va, 55, 1); =20 - if (el > 1) { + if (!regime_has_2_ranges(mmu_idx)) { tsz =3D extract32(tcr, 0, 6); using64k =3D extract32(tcr, 14, 1); using16k =3D extract32(tcr, 15, 1); @@ -9714,10 +9706,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, tar= get_ulong address, param =3D aa64_va_parameters(env, address, mmu_idx, access_type !=3D MMU_INST_FETCH); level =3D 0; - /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark = it - * invalid. - */ - ttbr1_valid =3D (el < 2); + ttbr1_valid =3D regime_has_2_ranges(mmu_idx); addrsize =3D 64 - 8 * param.tbi; inputsize =3D 64 - param.tsz; } else { @@ -11368,8 +11357,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); int tbii, tbid; =20 - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - if (regime_el(env, stage1) < 2) { + if (regime_has_2_ranges(mmu_idx)) { ARMVAParameters p1 =3D aa64_va_parameters_both(env, -1, st= age1); tbid =3D (p1.tbi << 1) | p0.tbi; tbii =3D tbid & ~((p1.tbid << 1) | p0.tbid); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index dbe2189e51..06ff3a7f2e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -175,8 +175,7 @@ static void gen_top_byte_ignore(DisasContext *s, TCGv_i= 64 dst, if (tbi =3D=3D 0) { /* Load unmodified address */ tcg_gen_mov_i64(dst, src); - } else if (s->current_el >=3D 2) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ + } else if (!regime_has_2_ranges(s->mmu_idx)) { /* Force tag byte to all zero */ tcg_gen_extract_i64(dst, src, 0, 56); } else { --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.29 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=990oq3Jk2iwM+tnufP71c3BjXCbJEu9Ritd8u64nkfc=; b=QAYOiJWrEQohdb0ezaHo0wG2XvNgh80GWi42I6kfRjO7WMPazyDP9i06wrRYddoSmU uyWtoHoeIPKeWz96c/rCKqO39n5zTWue5SNHTTkA1XC6iG+6ZOMSqHc+Jnt2jYSObR7g 4LCzxJW17ZhlCD8D5oiuCWB++EnKAFLT0MCCHTQ+3lXrIzhAwhnQWkynvvh7ui4Hmnde slOiqtQA0ZYhfC0IX1XsB3XRFp5NRnCg3KJ/ArwUzKqCT7DWx7qNFsZULQdA0t2qb0o3 EwS5cLkpEZI6NqR2ovZNEd7H5962ZgpoL+IfwuIZp3XjH5BIC+RWyRx9hNIhqiqG5jbB njkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=990oq3Jk2iwM+tnufP71c3BjXCbJEu9Ritd8u64nkfc=; b=VGySwlEc4wi9KEzw61M/+cQywbEx75V8t/0C0EITqPEwSJKu1loUXtsXh8W0k4UC4U Erb3wbtld31694AUu3NfhkPjWL1yiQ0PsOQJHMvgx9dDvSYvKf469kvIK+eAlU+5kwVJ XEln+4P+Mq7xKVWmVVik0eXT7FNhETAPTNApby+txaraJErmAvNzPiMQQIEqs2w9X0bz Ts7QtQ7FfON8INmoOY/j+lgiAkCDKb2lL8Hk30uFzHWC3L4Cfq8rQY00NmRVoaC1e4Wu 4AUPwoGCqTkZprpZDt8dHreYTmuy2OErHAeFtpUWKgVEdsmi9TDOV8hM7b4WfUkauR/D 51lA== X-Gm-Message-State: APjAAAVU9CqPYgJEGYA3gZYS6A6GzSC80EBKj6PlbpyL6oYuDOyUMUmV 6RCp3AOpgHL1okvGhyQAaXMV4yE+6Zs= X-Google-Smtp-Source: APXvYqwhG6VHzfES0jWWi8+IF7AlBXj5dQ588Do/GJ4ibhrfMcKk9x05R7KxkIdGCGEbm/v8yQ3G6g== X-Received: by 2002:a17:90a:9bc5:: with SMTP id b5mr10473944pjw.109.1564858110427; Sat, 03 Aug 2019 11:48:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:49 -0700 Message-Id: <20190803184800.8221-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 23/34] target/arm: Update arm_mmu_idx for VHE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Return the indexes for the EL2&0 regime when the appropriate bits are set within HCR_EL2. This happens for initial generation in arm_mmu_idx, and reconstruction in core_to_arm_mmu_idx. In order to make this reliable, we also need a bit in TBFLAGS. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- v5: Consistently check E2H & TGE & ELUsingAArch32(EL2). --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 51 ++++++++++++++++++++++++++++++++------------- 2 files changed, 39 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b5300f9014..8d90a4fc4d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3153,6 +3153,8 @@ FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) FIELD(TBFLAG_ANY, BE_DATA, 23, 1) +/* For A profile only, if EL2 is AA64 and HCR_EL2. =3D=3D 11 */ +FIELD(TBFLAG_ANY, E2H_TGE, 22, 1) =20 /* Bit usage when in AArch32 state: */ FIELD(TBFLAG_A32, THUMB, 0, 1) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5472424179..a570d43232 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11257,21 +11257,31 @@ int fp_exception_el(CPUARMState *env, int cur_el) =20 ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) { + bool e2h; + if (arm_feature(env, ARM_FEATURE_M)) { return mmu_idx | ARM_MMU_IDX_M; } =20 mmu_idx |=3D ARM_MMU_IDX_A; + if (mmu_idx & ARM_MMU_IDX_S) { + return mmu_idx; + } + + /* + * All remaining states are non-secure, so we can directly + * access hcr_el2 for these two bits. + */ + e2h =3D (env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HC= R_TGE) + && arm_el_is_aa64(env, 2); + switch (mmu_idx) { case 0 | ARM_MMU_IDX_A: - return ARMMMUIdx_EL10_0; + return e2h ? ARMMMUIdx_EL20_0 : ARMMMUIdx_EL10_0; case 1 | ARM_MMU_IDX_A: return ARMMMUIdx_EL10_1; case ARMMMUIdx_E2: - case ARMMMUIdx_SE0: - case ARMMMUIdx_SE1: - case ARMMMUIdx_SE3: - return mmu_idx; + return e2h ? ARMMMUIdx_EL20_2 : ARMMMUIdx_E2; default: g_assert_not_reached(); } @@ -11300,25 +11310,27 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMStat= e *env, bool secstate) ARMMMUIdx arm_mmu_idx(CPUARMState *env) { int el; + bool e2h; =20 if (arm_feature(env, ARM_FEATURE_M)) { return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } =20 el =3D arm_current_el(env); + if (el =3D=3D 3 || arm_is_secure_below_el3(env)) { + return ARMMMUIdx_SE0 + el; + } + + e2h =3D (env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HC= R_TGE) + && arm_el_is_aa64(env, 2); + switch (el) { case 0: - /* TODO: ARMv8.1-VHE */ + return e2h ? ARMMMUIdx_EL20_0 : ARMMMUIdx_EL10_0; case 1: - return (arm_is_secure_below_el3(env) - ? ARMMMUIdx_SE0 + el - : ARMMMUIdx_EL10_0 + el); + return ARMMMUIdx_EL10_1; case 2: - /* TODO: ARMv8.1-VHE */ - /* TODO: ARMv8.4-SecEL2 */ - return ARMMMUIdx_E2; - case 3: - return ARMMMUIdx_SE3; + return e2h ? ARMMMUIdx_EL20_2 : ARMMMUIdx_E2; default: g_assert_not_reached(); } @@ -11428,6 +11440,17 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, =20 flags =3D FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mm= u_idx)); =20 + /* + * Include E2H in TBFLAGS so that core_to_arm_mmu_idx can + * reliably determine EL1&0 vs EL2&0 regimes. + */ + if (arm_el_is_aa64(env, 2)) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + flags =3D FIELD_DP32(flags, TBFLAG_ANY, E2H_TGE, 1); + } + } + /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: * SS_ACTIVE PSTATE.SS State --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858833; cv=none; d=zoho.com; s=zohoarc; b=G5/Ipzb7uZa74CqjVPu5bD/Q2eLH2kWqvPdJhtx7SznUTzX4uEukU1viwpQkvLm6SLIH5dbZ91CtTX8o/3q9Qh8DENZIljDK+w9o3uPKOP4d5IcYRgBM/cLihiTf88VmauM/1wQmV0dlq/OiSU+DSmpBfCcVHYk7R/VrUhFTSG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858833; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=nHfPCz5YwCEUlzjuGzWzTb7gnkajF/XBRvaJmIbxmI0=; b=FIB+h8TBeVcwUjfvvhWSjY2hdFyh5aC/+ia+5CFML5x5Eu8p7aRs0nBr7RFGLaAm6U7dUq/PqR+KgccbT7KbnT8npfl+PE+ru7mZDKVKnijxl6UBc18ZIvD1WwA+AyJtxMaci+YMjylvebYK+mYozPvhjDfkYp/IU2uqBBRoYRA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858833466459.98445391389316; Sat, 3 Aug 2019 12:00:33 -0700 (PDT) Received: from localhost ([::1]:41592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htzGa-000088-BF for importer@patchew.org; Sat, 03 Aug 2019 15:00:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32841) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz50-0006hn-85 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz4y-0007M5-Uo for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:34 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:33666) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz4y-0007La-OM for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:32 -0400 Received: by mail-pg1-x544.google.com with SMTP id n190so2542683pgn.0 for ; Sat, 03 Aug 2019 11:48:32 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.30 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nHfPCz5YwCEUlzjuGzWzTb7gnkajF/XBRvaJmIbxmI0=; b=hXxC9JbVWxcs5YnVTE4WAwREG86bgECaTH2NORht9mgPe6k9Dg2bTQSpTsz7SBlWuU QC+fxv5+FUgKq2V1gu/3cKNHYyfw/g8B7au/L2bg2YpkYwHH0Cv98WMv47VCA3swB2a1 nTLBl0vHndkP0WIYA1EK8tqZXz8oKt4SHpEMwgxLVZGJ0Wl7nsMKnWUoGQaXHBJVjJz2 eZvX91NtuWi3fa+Z83IlYexblAHHXEXauFI8A8ALj6zPdCcx6NvXUJXKitcGjf3NGEAf R6UnC+nKLtkwBr+DPP2UJ9+M7AgVayW+j8ct7QrGAryEIdARj+IJdKku/MSFucfVcw9M lyyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nHfPCz5YwCEUlzjuGzWzTb7gnkajF/XBRvaJmIbxmI0=; b=VHbrfTvdyQlq//98G1+hYaOdjV//XD7DHVfN3U6lbSlEceGHz32pB1ad5reQelX/1D gdw3l9RuFOezZTa0Dt8S4+FImveZ+pWiV6/ZLvGNO3QAO2wwckW4HtrvCwgBqwJHZZcG vBJ95dbCaW4NhR7jgoLnQwXrNZeLpDUjy1dpVQ3Fk41vPb5wap85ylaL4OjTZOytqcFW MuzWGYyZgy5VPYgL2grQ4Rw3ns+ZH+xzyA8Z9Q6hf7KZeGyH3NSEw1QkwYxXOxaBXo9b e32foA87GFxY7qjPGBqGYYySCy4vPkRZzyAVkNo4z9Qg+7Dn4lCIrMJoXTwFbTbMslV4 iZDg== X-Gm-Message-State: APjAAAUzNiEq48ANcM6mZ6zwTN1uQt3Uvmt9LuAT37FgQ5C6CQwyMepZ yjGTk1BtLbONPl2LlFR9FZmkfhJFk5E= X-Google-Smtp-Source: APXvYqx3Of1+yWCTj60XS0ZNONOuwP6m8JwYsCiapXVqwT+kjVBbmnxjspb3mk8OpmZcPOXEBs9xKg== X-Received: by 2002:a63:184b:: with SMTP id 11mr70008432pgy.112.1564858111468; Sat, 03 Aug 2019 11:48:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:50 -0700 Message-Id: <20190803184800.8221-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 24/34] target/arm: Update arm_sctlr for VHE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Use the correct sctlr for EL2&0 regime. Due to header ordering, and where arm_mmu_idx is declared, we need to move the function out of line. Use the function in many more places in order to select the correct control. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- v5: Use arm_mmu_idx() to avoid incorrectly replicating the el2&0 condition therein. Drop the change to cpu_get_dump_info, as that needs a more significant rethink of hard-coded oddness. --- target/arm/cpu.h | 11 +---------- target/arm/helper-a64.c | 2 +- target/arm/helper.c | 14 ++++++++++++-- target/arm/pauth_helper.c | 9 +-------- 4 files changed, 15 insertions(+), 21 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8d90a4fc4d..d7c5a123a3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3096,16 +3096,7 @@ static inline bool arm_sctlr_b(CPUARMState *env) (env->cp15.sctlr_el[1] & SCTLR_B) !=3D 0; } =20 -static inline uint64_t arm_sctlr(CPUARMState *env, int el) -{ - if (el =3D=3D 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - return env->cp15.sctlr_el[1]; - } else { - return env->cp15.sctlr_el[el]; - } -} - +uint64_t arm_sctlr(CPUARMState *env, int el); =20 /* Return true if the processor is in big-endian mode. */ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 060699b901..3bf1b731e7 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -70,7 +70,7 @@ static void daif_check(CPUARMState *env, uint32_t op, uint32_t imm, uintptr_t ra) { /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM= A)) { + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { raise_exception_ra(env, EXCP_UDEF, syn_aa64_sysregtrap(0, extract32(op, 0, 3), extract32(op, 3, 3), 4, diff --git a/target/arm/helper.c b/target/arm/helper.c index a570d43232..9e9d2ce99b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3867,7 +3867,7 @@ static void aa64_fpsr_write(CPUARMState *env, const A= RMCPRegInfo *ri, static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInf= o *ri, bool isread) { - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM= A)) { + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { return CP_ACCESS_TRAP; } return CP_ACCESS_OK; @@ -3886,7 +3886,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState= *env, /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless * SCTLR_EL1.UCI is set. */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UC= I)) { + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) { return CP_ACCESS_TRAP; } return CP_ACCESS_OK; @@ -8718,6 +8718,16 @@ static uint32_t regime_el(CPUARMState *env, ARMMMUId= x mmu_idx) } } =20 +uint64_t arm_sctlr(CPUARMState *env, int el) +{ + /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ + if (el =3D=3D 0) { + ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); + el =3D (mmu_idx =3D=3D ARMMMUIdx_EL20_0 ? 2 : 1); + } + return env->cp15.sctlr_el[el]; +} + #ifndef CONFIG_USER_ONLY =20 /* Return the SCTLR value which controls this address translation regime */ diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index d3194f2043..42c9141bb7 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -386,14 +386,7 @@ static void pauth_check_trap(CPUARMState *env, int el,= uintptr_t ra) =20 static bool pauth_key_enabled(CPUARMState *env, int el, uint32_t bit) { - uint32_t sctlr; - if (el =3D=3D 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr =3D env->cp15.sctlr_el[1]; - } else { - sctlr =3D env->cp15.sctlr_el[el]; - } - return (sctlr & bit) !=3D 0; + return (arm_sctlr(env, el) & bit) !=3D 0; } =20 uint64_t HELPER(pacia)(CPUARMState *env, uint64_t x, uint64_t y) --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858938; cv=none; d=zoho.com; s=zohoarc; b=CkSDyOCRtQdxJHsLPIyljW2riEWYLdM6hRIxl4wGbveJ2ee4jhrryn9KDo7el5Ov3oNFSQrKqoldr4s/6bPdVk1BGKi9QJE++REuPQd1rzZlPLGhle272gA+UHuDqQEM2AzZfijMw3fZMBB5v2Dr2+Lr7dAWxuPFjZHsn/dNHWg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858938; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=XOwe1x9jkMeobEp2gGQ1QVWfLomppnXBcfQfzlWOS/E=; b=V/slRu1TpJeYRXpfY0quVthggrebJ8fS/he6MoXxHIMFtvc1NduRz3ZHj3jRu+6munbjA2K3aTF8BnasQk/7/zRVUeu45NaLpaRtjliCWcdyXXcgZKLe2b2z+LkylZYvDCBtvcbMPGn3P/mvIFUzQEMFqdR2JO94uloIR3Vu7aw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858938152744.3202345962914; Sat, 3 Aug 2019 12:02:18 -0700 (PDT) Received: from localhost ([::1]:41640 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htzIH-00048b-3G for importer@patchew.org; Sat, 03 Aug 2019 15:02:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32862) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz51-0006ka-Bu for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz50-0007Mm-3x for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:35 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:43813) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz4z-0007MK-V4 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:34 -0400 Received: by mail-pl1-x641.google.com with SMTP id 4so27885291pld.10 for ; Sat, 03 Aug 2019 11:48:33 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.31 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XOwe1x9jkMeobEp2gGQ1QVWfLomppnXBcfQfzlWOS/E=; b=dMqUYYmRfdayPFfbUWwMEx9J2DbZBKw2F4NAJoNPOwLBmqrOuFzJaZYBpEpuXKphx1 k73GH4LZNLW8ZcfyO87kGFQQTTfXTFLE/f6gvk1z2RiesiH1K0PjhQnXIzaW3SHb/cID /w/DfIbV/75N84T2THH4vOYiInYakfJu9A7ElnolFK36pD1HyeS43c3PgOew1zddvEWX HzAcn4s9+sTMspPIHAkYjlByi0Y0pfsgypM/POeJxGLNs40YlCnb1AVJsc+MKMs4UAxx Aveu6pq6lBGaSaBO+2y82E3xXr7kW26UT0Un0Qe3PPlUksqIRPxlEERvvNnIzzlHH8ww ERrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XOwe1x9jkMeobEp2gGQ1QVWfLomppnXBcfQfzlWOS/E=; b=saSaKNMlZ9AdMs67TabjHunn5zoJUfGTuSKsXgnPU7Z88YNR3Lqo5vsKOl8D9cVyaG c/zwbnG8KJ3ert7fTIicxolPgW0HhJFgCU+CiZ4/2DfprpqqWDs23qjamwpDhPVajTLc sOxFF/TTLsHyUjP32dYw0YYJng4Ahr5TdS2BMwtp4v4dJQ+oanG9IGKU8V6oB3v95veB T6elbTDRrZ8cJheLzRpgzRLITGf3CRXgKRKcjLrCZHdDHU+ACqh5I8i6jdntQrFb951L ELjTnRP3JTZAEHCF5ZnqxnqRF1zs+DUsKu9Y8HVCbVXws6ubcbDnkQFA6925a0MExkDs uuDg== X-Gm-Message-State: APjAAAWLAvLUJT3DbXvxVVqWLFoKrsoQRrZCowmDLXqUqBUlCcqS7HZv gdYW0k1U36YTUFp8xUpk3IWpP/+r82U= X-Google-Smtp-Source: APXvYqyb1AF8sTnicyX+NAezc54dTu4e+BfaRxO4fEL/ZNln+ZX+TAvvOyDRIIAMgqa+cbIuuztDxA== X-Received: by 2002:a17:902:b48f:: with SMTP id y15mr139996271plr.268.1564858112630; Sat, 03 Aug 2019 11:48:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:51 -0700 Message-Id: <20190803184800.8221-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 25/34] target/arm: Update aa64_zva_access for EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The comment that we don't support EL2 is somewhat out of date. Update to include checks against HCR_EL2.TDZ. Signed-off-by: Richard Henderson --- target/arm/helper.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9e9d2ce99b..37c881baab 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4113,11 +4113,27 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *= env, const ARMCPRegInfo *ri, static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, bool isread) { - /* We don't implement EL2, so the only control on DC ZVA is the - * bit in the SCTLR which can prohibit access for EL0. - */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZ= E)) { - return CP_ACCESS_TRAP; + int cur_el =3D arm_current_el(env); + + if (cur_el < 2) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + + if (cur_el =3D=3D 0) { + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { + return CP_ACCESS_TRAP; + } + if (hcr & HCR_TDZ) { + return CP_ACCESS_TRAP_EL2; + } + } + } else if (hcr & HCR_TDZ) { + return CP_ACCESS_TRAP_EL2; + } } return CP_ACCESS_OK; } --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858809; cv=none; d=zoho.com; s=zohoarc; b=gU6m9Na5AGirNUGFHxcs7e+qH/N/UszsALTWdSaHLD/F79FJVgav1w0GTpk9dQpQGspTu5QVkljGLd7N5MQbGzD6fW6ydpDjAtRODkXUhsleH6qiZrCdXgC26tB8IQvh1DUmkrTvu4FGqw57gV6AXO1Y4c/7N8RF7S+bcGNPMMc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858809; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=+czGE1389+p9Ry0JcTeQCKYKOo7/YkTFZC4yltahS2c=; b=auHsRPvfOSxL91L7bVaxMpKpz3+5LM54FLzrrff3XAlJr98knT0EjIwU4EFgycaleWWeLSdkwefh1fD2cEL2tEwfp7+TFVuZBi/GdBtAS7dSKjKNlfOMaVxiUtZEefId7ZZLPpYsUzPe8kawJCZHP1eNYwJXIRvv14tAYqLv99o= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858809559435.9078406103422; Sat, 3 Aug 2019 12:00:09 -0700 (PDT) Received: from localhost ([::1]:41588 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htzGC-0008Cw-Fv for importer@patchew.org; Sat, 03 Aug 2019 15:00:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32884) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz52-0006ng-De for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz51-0007NR-BK for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:36 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:33665) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz51-0007My-2X for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:35 -0400 Received: by mail-pg1-x542.google.com with SMTP id n190so2542703pgn.0 for ; Sat, 03 Aug 2019 11:48:34 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.32 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+czGE1389+p9Ry0JcTeQCKYKOo7/YkTFZC4yltahS2c=; b=Xyjg5s19r/WRWUfR6xaWgAyr8CsYpH1Dr1oYlq23QP+aj6s+bmdUNjI9ShzPR/5bnD 8MtEvO474wOlswxFWfcG976klTMfYNrp2yo7J5Mj5ul/UI5FsIpB1iNE2+6AVR9CjG/q AayUcEl14Gm7TZL84nQm+/2sVXDCVtdUoLRPJoLyuxCe78jcvMfCya7ikbRPUnpg29y+ MGss9X0u+c9rabYdQZX7JAGTwIb3FNrEn2HiYEqMRIDE798KSq2aJMY/ykeQlm5vxoib Tm7V6QmSqeXMlMBhQFeo04Qrdfr9jYnyjyR1JSGmWLeD/g9KQGISk4DjevZtQOx1+gGz KUxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+czGE1389+p9Ry0JcTeQCKYKOo7/YkTFZC4yltahS2c=; b=pHu5ks8KiF+G/ZU080eNpWvGQS1DvPgaVNHJ9Bpmqz4kp4oTUBhsxM+7KWRm0ZgqlV XISJbK3JrMQvkQ/4zTAHl38aSFZLi3dXLM0I/gq/1rkAgniHshZX5uTjlc6WEzg1g8w2 6PMvmm632dvu9va4+0NQQKprITkg/sri9+4skFF9VgE5EDUWLfM0khFVNJRkFPWZ0GR6 tecrNNzMcgvWOcSeNo4IrhTGsXtAbjtTVod/6Sr4rU0Er2jiTMIJFcRhF4EqyI2TaDOt xj0YggKKveTQ0p3ZPkdOhfnPIKfkmp9pNW7c9kNYalJWQb8Y/xeVY2OWDS/HAf2G+B1z mJtQ== X-Gm-Message-State: APjAAAVu8Rcn0nLwvM6FB5WyJF/aiwjHoQOp2YK1TRYaD1fems3fgds4 uexalbECHmqM6/atLK98WuJbh3puwrc= X-Google-Smtp-Source: APXvYqxd5/9+viNsBVQVD55FqfdoyCeNMDAhjpNUvd3wgZV9Jk4QnMFb+7iGOnZQIhlJa1MG8uCZzQ== X-Received: by 2002:a63:784c:: with SMTP id t73mr133510686pgc.268.1564858113670; Sat, 03 Aug 2019 11:48:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:52 -0700 Message-Id: <20190803184800.8221-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 26/34] target/arm: Update ctr_el0_access for EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Update to include checks against HCR_EL2.TID2. Signed-off-by: Richard Henderson --- target/arm/helper.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 37c881baab..b8c45eb484 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5361,11 +5361,27 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) { - /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, - * but the AArch32 CTR has its own reginfo struct) - */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UC= T)) { - return CP_ACCESS_TRAP; + int cur_el =3D arm_current_el(env); + + if (cur_el < 2) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + + if (cur_el =3D=3D 0) { + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { + return CP_ACCESS_TRAP; + } + if (hcr & HCR_TID2) { + return CP_ACCESS_TRAP_EL2; + } + } + } else if (hcr & HCR_TID2) { + return CP_ACCESS_TRAP_EL2; + } } return CP_ACCESS_OK; } --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858875; cv=none; d=zoho.com; s=zohoarc; b=kyQy6aIRkznN8CczrrBWfx3mdQs5wxz6vHDRxUn3Z7bBxIRgft1q4PRxW4xo5bmB9mP7yKM0I+hlaa30uGjiNCKdmBPW3YAElWOAUb5jliR0S6xMfVkRj6l0yuLdSLuQ634hhWUR/YCZ5S2U8BhbdYwWlNWmJtHzll2N77dRjmQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858875; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=MpItA1dQTcuKZiJtCdjWs8WMTH2c/gBkJl0/pbYk+Ag=; b=bNpWvA5kpEIfE4oL7sP3+9qvkZKlXkN32Le6eF/eFXXrsqQVNUS3+zP6y+o/MW0eOfHRkah452rJUWHu5aojmj31P6/L+HIUPT+VhEhio00wRKVxDdOw4fIQXTtKXdtGz98XxogpcCmkdU0rB+snGbaggjg7mZDQNiBXoiRRZYQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858875176681.7724050426593; Sat, 3 Aug 2019 12:01:15 -0700 (PDT) Received: from localhost ([::1]:41604 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htzHG-0001g7-1s for importer@patchew.org; Sat, 03 Aug 2019 15:01:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32898) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz53-0006p4-5e for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz52-0007Nx-2h for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:37 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:37970) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz51-0007Nc-U0 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:36 -0400 Received: by mail-pl1-x644.google.com with SMTP id az7so34857836plb.5 for ; Sat, 03 Aug 2019 11:48:35 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.33 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MpItA1dQTcuKZiJtCdjWs8WMTH2c/gBkJl0/pbYk+Ag=; b=dyd6gD5w/4Z2lzudxNV49llWNQPEJUnKWUVoGSgnqRWeB254Fu61z1VLQlr3V41LAf PUcSyUdJt4beh8L3lxmOq/VU6wJutjNQ9Bm2BEiE+OKjKmv/ef84XRZmNDgk4IEmUbEh X1jSvQReMowgAPMPo40P7JTnmTGiW7nVwAU1FRYBAfV8jHXjWfRNZI6rNiRqGBzlm825 lfBfdP2/EIZlhzW8egdiiEFA8GDjYJIUQwt7pdjWMTU//wYGNPmxPqGhfCtUhtpwWScx +ifF/NZ80NPq3l2CwdHxEuuWSsCV5JhdPP/aBf25qxm66O/OUmdNyRN6y/7A5QW277e2 ozbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MpItA1dQTcuKZiJtCdjWs8WMTH2c/gBkJl0/pbYk+Ag=; b=RZHOBlOZQtUq877ifM8BfVWfZg185HsvaQVhzKW96kvGHkoXVZ9fFW5DoO4zChaClk wBrJA5jpvKTuQ1xPA3xJSj+DcrC+66rRQM3JYHdFtsP6o5EARWkJ/6+X5JPYNh8awiHt flBl/taPBb8FIQP8SoxImxGPa8jA8ywy8y+sOX6HHWIx0hCWnEJWBuc3FVT3X44IJUqm VHhBPlocyujMv3+pDyeyxVfJ9axcVBUMBYMq0dZjEUSzVXJxCDlK6RNarIjf40z9ehM3 RhKJPBU6WNuAb0R98w6ctvE6ofHm5aEU8i0TdDuZFRQNsInVwIv3pVJhHkJH/Bwx5yix dy8g== X-Gm-Message-State: APjAAAUM1dpHo3oE7eew92EP0zey11OChAeEzonN9ERw9Nw/9GKKH3/a 7yKrUkYmymGRLhkXX4Cu/3thKRX/fdY= X-Google-Smtp-Source: APXvYqxR9hfFUx1qDYkUQWg15/UHOUV54tjNdwJbJkiJo9V2NUyvUCuagpp9ouCdRYROePBGgNLE3A== X-Received: by 2002:a17:902:112c:: with SMTP id d41mr126176670pla.33.1564858114794; Sat, 03 Aug 2019 11:48:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:53 -0700 Message-Id: <20190803184800.8221-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v3 27/34] target/arm: Install asids for E2&0 translation regime X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When clearing HCR_E2H, this involves re-installing the EL1&0 asid. Signed-off-by: Richard Henderson --- target/arm/helper.c | 38 ++++++++++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b8c45eb484..9d74162bbd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3518,10 +3518,29 @@ static void vmsa_ttbr_el1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, } } =20 +static void update_el2_asid(CPUARMState *env) +{ + CPUState *cs =3D env_cpu(env); + uint64_t ttbr0, ttbr1, ttcr; + int asid, idxmask; + + ttbr0 =3D env->cp15.ttbr0_el[2]; + ttbr1 =3D env->cp15.ttbr1_el[2]; + ttcr =3D env->cp15.tcr_el[2].raw_tcr; + idxmask =3D ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL20_0; + asid =3D extract64(ttcr & TTBCR_A1 ? ttbr1 : ttbr0, 48, 16); + + tlb_set_asid_for_mmuidx(cs, asid, idxmask, 0); +} + static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { raw_write(env, ri, value); + if (arm_hcr_el2_eff(env) & HCR_E2H) { + /* We are running with EL2&0 regime and the ASID is active. */ + update_el2_asid(env); + } } =20 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4670,6 +4689,7 @@ static void hcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) ARMCPU *cpu =3D env_archcpu(env); /* Begin with bits defined in base ARMv8.0. */ uint64_t valid_mask =3D MAKE_64BIT_MASK(0, 34); + uint64_t old_value; =20 if (arm_feature(env, ARM_FEATURE_EL3)) { valid_mask &=3D ~HCR_HCD; @@ -4696,15 +4716,25 @@ static void hcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) /* Clear RES0 bits. */ value &=3D valid_mask; =20 - /* These bits change the MMU setup: + old_value =3D env->cp15.hcr_el2; + env->cp15.hcr_el2 =3D value; + + /* + * These bits change the MMU setup: * HCR_VM enables stage 2 translation * HCR_PTW forbids certain page-table setups - * HCR_DC Disables stage1 and enables stage2 translation + * HCR_DC disables stage1 and enables stage2 translation + * HCR_E2H enables E2&0 translation regime. */ - if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { + if ((old_value ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_E2H)) { tlb_flush(CPU(cpu)); + /* Also install the correct ASID for the regime. */ + if (value & HCR_E2H) { + update_el2_asid(env); + } else { + update_lpae_el1_asid(env, false); + } } - env->cp15.hcr_el2 =3D value; =20 /* * Updates to VI and VF require us to update the status of --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858637; cv=none; d=zoho.com; s=zohoarc; b=gTS9VHpM61tNFQFQQee1/MmKyLCUShCAtvEk76Nzt1V18jmxMne/5zgkqxdzKkuxXwXD0dWPx8qrPSrSYuq8r0qR05EqGdriu+tis2Dtutorma8RrP+MBc0HnrL+CGYZ8oS5ogx6nDBbm8P7hrLdmolGQltEaGAiz0jJ4gs0Wu0= ARC-Message-Signature: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.34 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AKU1gGfJD0fHB3QeRt9QRaO7IOfL7ZvP1zaRZud/BsE=; b=RzRDhP10pg0B8kssRnKpGMDyeZ0CTYSkr/iXpyetK+I8OqDcpyaHvTOEzBw9q1+vnS yRXRNdfbYkO7LoK95UnEZ+G6QuxWCyTwjDy/eBXf4WpoKjVDPqMUSIS5pHc7BzDaztVT 8f5XPqSlCC5FCy6ick5E2j062jJ91k70CN8IBZxr5CsWTIB29MKBccHdbLbERCCpFMur vS8dfJo8ddRCKHLQzpXt1t+/3sjVieV8Qz0Z01+0EuNNoAJL4eGO3RVvsKoIaltd1syB eBQh2rtbnAiKOx1WHALl/cLcW2DlglBKn8iLF0Bdx8cm3qv2uCP7WuYf68vS057Sy+1Z KX3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AKU1gGfJD0fHB3QeRt9QRaO7IOfL7ZvP1zaRZud/BsE=; b=CWo3nh0Okf/xfFRttII0SALON4RbDIJ/wUSIW5f8C2pLd5Zp76lWjhroySFnEDoecE myk3hYVC+88/FOChNm5Idv1pczLNHOXKIC6xPjLjavahP62sYi1kGK8/l/tQ1E2AkR5q 3qvPrWpDcatRjlGvNGu9Wc34lpgloAuO/9jUNlJ3f3wjRtm0Qz5LDbX13nvELfyuUUOu uEvWwt4sxh2tZBBbzkTFybD+EhDSaJtC1mixPUMvfQNV9SU67bSsueXCyqje8tYKzrFr xEV2tA9jra2CHFjAoe1brXZTuD4pkLEcVh8DkyfVt5sPvgmI7XL8ZFdPgplf9DuQxOTj UOHg== X-Gm-Message-State: APjAAAXymRkdADGaHRp77HMvyMaXw5BbGAbC0EawFYoT0qe3rDFhTzq+ oNpd+2HQSJXelb3kGxlXjlpkLUyhCOM= X-Google-Smtp-Source: APXvYqxfGRFlZW0fGSbd060rHVdWw+XBpeejBw0pnbxlt97oLl0uZuoml62TGlrd5/xB8IhgPdTSOw== X-Received: by 2002:a65:57ca:: with SMTP id q10mr133449832pgr.52.1564858116151; Sat, 03 Aug 2019 11:48:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:54 -0700 Message-Id: <20190803184800.8221-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 28/34] target/arm: Flush tlbs for E2&0 translation regime X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper.c | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9d74162bbd..984a441cc4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3917,8 +3917,11 @@ static CPAccessResult aa64_cacheop_access(CPUARMStat= e *env, =20 static int vae1_tlbmask(CPUARMState *env) { + /* Since we exclude secure first, we may read HCR_EL2 directly. */ if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; + } else if (env->cp15.hcr_el2 & HCR_E2H) { + return ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL10_0; } else { return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; } @@ -3956,6 +3959,10 @@ static int vmalle1_tlbmask(CPUARMState *env) if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { + /* Since we exclude secure first, we may read HCR_EL2 directly. */ + if (env->cp15.hcr_el2 & HCR_E2H) { + return ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL20_0; + } return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_St= age2; } else { return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; @@ -3971,13 +3978,22 @@ static void tlbi_aa64_alle1_write(CPUARMState *env,= const ARMCPRegInfo *ri, tlb_flush_by_mmuidx(cs, mask); } =20 +static int vae2_tlbmask(CPUARMState *env) +{ + if (arm_hcr_el2_eff(env) & HCR_E2H) { + return ARMMMUIdxBit_EL20_0 | ARMMMUIdxBit_EL20_2; + } else { + return ARMMMUIdxBit_E2; + } +} + static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vae2_tlbmask(env); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); + tlb_flush_by_mmuidx(cs, mask); } =20 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4002,8 +4018,9 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,= const ARMCPRegInfo *ri, uint64_t value) { CPUState *cs =3D env_cpu(env); + int mask =3D vae2_tlbmask(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4021,11 +4038,11 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, = const ARMCPRegInfo *ri, * Currently handles both VAE2 and VALE2, since we don't support * flush-last-level-only. */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vae2_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858891; cv=none; d=zoho.com; s=zohoarc; b=Mig4Kn0xIoIHxXEoPiQO0FZ5jfamMzVCwG/K4sQHUxX5UoySWkg/0XpvVOlH4OE5xQmXcDpRfAqSb8E0dToCnKcXHAxb3q7XV6sLJdj6T4Zrgvr0aOLU4Ge0sVtl3HThTrGkVZ9ljrk+GC80UVtH2E4WAvpoZyA+3l+3zRFMPgQ= ARC-Message-Signature: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.36 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4Ze85vH/aQjxlcuWsjYuHifd5A5xyc14ioC1rkP0Yto=; b=B/K5WUnnGiy111NPTwOaiQW0NtyN9hpfo4MH+vcSVcsOM/2oss8u0hV3oRVIh0AYHT Q9X/yodCD/1/kDno63G/LcVovJJW9iHlyBX9ihwk5aeRS+mLvzxOt6LWUnYKffOMdALc 8kQ9ZcY0bj3js5usQnd1daxvaGay8B7k6IRXr0W24a8TIsrx9bnj3IwL5yBIa2aCyuKT J1HSY9fImd3SmYU/7JQN3uWubz7I6BH++g0KihvBQT7bQEx2AAeNwOLZzSRTVLUjF3w0 L+JnCj9eer4GkI2V/tXWBV8W+bIl6bil4kr89MYOhpuVVxpEKi+uHWL4KIYumKvxoUev 468Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4Ze85vH/aQjxlcuWsjYuHifd5A5xyc14ioC1rkP0Yto=; b=g6Zf4BnZZTBWgxvrFkT1L7+5p2agrZpz+PBFnzYsN7fx/nlSbhmLjxrvv5zod47NsD GeWABKE/IAGPXgGi6KaATv3VJnnwzxFsq6fegrUc5LPqc+tC6banbWtAhXSQWZNYVXmk kwd8/f3G0FuvIRRx4S7q2WHJZqDNqT8h6zWfQm9/OxbDU0vKCMw6tk4Bs9rrOtwpqtD3 rEcsgRdd9lZX5o1gPs8HJsXyEf1GpkN58NR5+ZWxX4uoFJDBUFD44lLEb2O0h/MHCn+1 hVDVHffC4chKvxDpNn2f4QXCdajaK/NiucYl/exPk2dRe6t/Z/PLAp3evVURBiKf4PbM FwvA== X-Gm-Message-State: APjAAAUziHgcxg8h0nmbDwy+bS5pXoHeZBauvWiFksE0dipChpa0iUoE 18SuS8LpiJgtVVP5E8ZKtD3ioUJZIS8= X-Google-Smtp-Source: APXvYqzJFO+1FmGoDSJ9r7CICKD1CR4xMc85MG0BDcvENkf1v3+QwuGOrezYuv0NcVNbI0lt6Kk2OA== X-Received: by 2002:a17:902:9041:: with SMTP id w1mr23791104plz.132.1564858117384; Sat, 03 Aug 2019 11:48:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:55 -0700 Message-Id: <20190803184800.8221-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 29/34] target/arm: Update arm_phys_excp_target_el for TGE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The TGE bit routes all asynchronous exceptions to EL2. Signed-off-by: Richard Henderson --- target/arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 984a441cc4..a0969b78bf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7968,6 +7968,12 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint3= 2_t excp_idx, break; }; =20 + /* + * For these purposes, TGE and AMO/IMO/FMO both force the + * interrupt to EL2. Fold TGE into the bit extracted above. + */ + hcr |=3D (hcr_el2 & HCR_TGE) !=3D 0; + /* Perform a table-lookup for the target EL given the current state */ target_el =3D target_el_table[is64][scr][rw][hcr][secure][cur_el]; =20 --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858702; cv=none; d=zoho.com; s=zohoarc; b=n4IFFsGzwbDxKVFnUJa3TKOmmBpnydZ9ffZ1sG+uAH0vbbKTpL8g74PYd3jogdx2usThKrSpZTFedSkv/CiOK4cOAyhzVRQx8yXWCgCKf9AMVsHhwCz3gYNt95lbGBNKg4+FK9EEwzFs8YPry4moGTEbNMVZJPEZQsTfRXY8RTM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858702; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=x75zfy++4h7G7+9uJPGHwt0vV9wve8SgXFTPLCjlkks=; b=lX6Kw4eId7/wCtPSzghS+Igde5ZYpoBkLxrfYMGyhXFwUXQmukDZpg7/XoMpR8tjyvGOYOzvKoIXhEhPtzN9EaPeSskJXfQ2wgKzBONFX1EULbbRpsLVfxXQtO5E6XFSfrfEjZuPgRXU7kkz+ZlJ2BgmhRfx+fqKczjxnzK1TzI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564858702274102.90052397667387; Sat, 3 Aug 2019 11:58:22 -0700 (PDT) Received: from localhost ([::1]:41548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htzET-0003WJ-Ar for importer@patchew.org; Sat, 03 Aug 2019 14:58:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32999) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz5D-0006vd-HJ for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz5B-0007Rd-F7 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:46 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:45759) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz59-0007PK-J8 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:43 -0400 Received: by mail-pg1-x52d.google.com with SMTP id o13so37653279pgp.12 for ; Sat, 03 Aug 2019 11:48:39 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.37 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=x75zfy++4h7G7+9uJPGHwt0vV9wve8SgXFTPLCjlkks=; b=vSbLBug1LuIdmY3e05odA6DONIHNQKBNmeojBFBcQFRAAln5HmcZSfiO3bZML0gPB5 o8uOagH6fGlOmk8pB3PnoKl7zwdN7KJ1daKWWnv7qLvZ2hpKzvFkKkhywpFiGYe4Pgc4 H+7HCtNZ41yARIYpZ3zOhQ040U7hPn1sQ7zwAplnf+MjdUdL6jt5VYhNGQuY9GE4yg+0 3EQg3ZZYJOKjWUJrtrzD2X3w9kldGktifhfDyKwll+jqOD8QSgGsBIkTATiSDCtG9URd S4Hg6G47XIilxW10LxvEJvPMtcjlVL8kqZebme30vgQxacppg4ev4lKoDVYHeGPAXsSt hrAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=x75zfy++4h7G7+9uJPGHwt0vV9wve8SgXFTPLCjlkks=; b=TCnPg9Zx1tmu1qb11hIXkDCGjDc2PEjE2VrJf6cxhijJ3X3hZIBUEkiKZQrdWeSftI eP1vW8x7mEsn+iSQzbH9A3OG+p/X8Lna+4u6U0wGgw0eUR8yfYAzzeiGbVsZL2DbDfsn x7oXizLsyAU1AdBYsvxQSbZ376GBJHLAaUwcpaa5/ILiqRLYVTH7t86IR/GAg+mjIBGV x/YwxuG2vGrkoG7Wsr6DJygVEPL9q/2eGgPkKwoCycDdmmjcdQBGc6BO3uJ5/tcWCuoI OyKqTWh0S68emQosiAKvX+oGiiZE8OQvOWtmubIk2p2/TPpH7qebWuZc0kq0JhxqenRb Xoxg== X-Gm-Message-State: APjAAAXvivdFjVSaaubgfrmRSGSEuS9o5JlAdndu94mfcTYa18kmAqS/ 2P1MgONNOYAaOcIPHJGnGz9mPqQ+xRc= X-Google-Smtp-Source: APXvYqxZ2T2wVdpWFl09fwK3nMJTtfcpGyVFU53yW1XfeyIu/WHv9qxSV4TyuvQAJYewR7ay0JP8zA== X-Received: by 2002:a17:90a:24ac:: with SMTP id i41mr10331984pje.124.1564858118408; Sat, 03 Aug 2019 11:48:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:56 -0700 Message-Id: <20190803184800.8221-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52d Subject: [Qemu-devel] [PATCH v3 30/34] target/arm: Update regime_is_user for EL2&0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index a0969b78bf..d481716b97 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8936,6 +8936,7 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_SE0: + case ARMMMUIdx_EL20_0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858782; cv=none; d=zoho.com; s=zohoarc; b=Ntm/OOHQq/DHlbD9dT0resgQk3lraoOOB23U7zYfQQ+JnGdaKRxKaCkWmgnaevPYQZLBDeJ2oN6LKF5geli/elqkvljerKNK+UKMD7AxGhn7P1kia+D7UvdEHNPZuuZu5Sdk3AK2Grzga+0SZMIH0cQgQKpEwGxNNYvX01dMoro= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564858782; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=fQb2baX8+br9XDTjkUGb5FILfpDmjfnieLRvexjfCRg=; b=YlmbbQs32twoqFlDRpWqP/DWclZFHUL7isKJuNV9B5+ud3XRpBIYf0KbeDjssV8LW8Hn3tzrGwt+sGO7bL9f83EGU30/H7GOQOZlnGV1WVA361LJlCmZkr5ZaaLyUJF4Runmpjriy1rbYY2it48pUrk7UIzabLsW5ToZlC1Djp4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156485878199526.346837312176717; Sat, 3 Aug 2019 11:59:41 -0700 (PDT) Received: from localhost ([::1]:41578 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htzFj-0006qW-RO for importer@patchew.org; Sat, 03 Aug 2019 14:59:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33000) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz5D-0006vh-H6 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz5B-0007Ri-F9 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:47 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:43344) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz59-0007Pd-IZ for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:43 -0400 Received: by mail-pf1-x443.google.com with SMTP id i189so37625822pfg.10 for ; Sat, 03 Aug 2019 11:48:40 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.38 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fQb2baX8+br9XDTjkUGb5FILfpDmjfnieLRvexjfCRg=; b=ZHFbLtM2E06kgJw7hT0Egbeg9owC+1p6dPnG4drYYDaV1gn4UGEFq6dm4GnDGTxgJ6 yPYbHxLvHHTQ3bYaIFZwUNkS/1xDppWkvjVkOmRUqHXoI+Tf4z1UGdu1DjksEdf8uGXl +SuFpIsNLFprQtP1if5EjQGhtH8IcVn+wwwCn7GLUllKJRV88oqO8J/DCg0D5HJfDnT6 +o5weLX8BQujymbxv3/CzWAb7CFIMmM4VCf+WhyDSWqlwF8rYhiXKUZaPemUAn9/qU3C TBMaSgrAct7EUoGw408h+YJRJYNrc2S3hF6DF8YeT/KQP1YpAbN8O6n1vfsTauCdmhs1 Q2vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fQb2baX8+br9XDTjkUGb5FILfpDmjfnieLRvexjfCRg=; b=Ji/0e/9NCqsV79Pua8kJGIHSkQ3sEpueoao3DPf+DFIqbr8jwCs2MEiFgQPLP7mWbw qzgAVLWsul8rY/VZnw9MZftoPRYo8SNp08cKFuyZVCTWCqMuB6DZHhDhmWXkLpgT2UY6 EmkmTHY0RoYGA+4HirYhLfNHqsVY1Iw69MUDGX50pJv8gFnT9v5KkdwDYHh6alP4NAFR feaF31fYpYgpgwcfet0zkh4K+/hBPP0xp0tZRv7zn6lDVotlos1L3/GhpeukZ2EFR80j yMCw9/lzAdV9+WWhjz94rSv4fmFil9QmVXOm51O+p/PcuKt4raFr775tnHUvG1r5j+n+ b0hw== X-Gm-Message-State: APjAAAWvN7Qc1ZlDV6mQnvhELEaLs+1lGofN07789rODXcKc58u6upze eMHfl3E7sPqnYT2iDiqkKB5dRsKaKhA= X-Google-Smtp-Source: APXvYqxINb8Pz4XuN9P/UruqFE4PZJ/nLF369CIR3xnPOPBp6QD6RZuXQ+W29y3PmKGblH6A890Abw== X-Received: by 2002:aa7:8b10:: with SMTP id f16mr66690094pfd.44.1564858119468; Sat, 03 Aug 2019 11:48:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:57 -0700 Message-Id: <20190803184800.8221-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 31/34] target/arm: Update {fp, sve}_exception_el for VHE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When TGE+E2H are both set, CPACR_EL1 is ignored. Signed-off-by: Richard Henderson --- target/arm/helper.c | 53 ++++++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 25 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d481716b97..2939454c8a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5539,7 +5539,9 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D= { int sve_exception_el(CPUARMState *env, int el) { #ifndef CONFIG_USER_ONLY - if (el <=3D 1) { + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + + if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { bool disabled =3D false; =20 /* The CPACR.ZEN controls traps to EL1: @@ -5554,8 +5556,7 @@ int sve_exception_el(CPUARMState *env, int el) } if (disabled) { /* route_to_el2 */ - return (arm_feature(env, ARM_FEATURE_EL2) - && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1); + return hcr_el2 & HCR_TGE ? 2 : 1; } =20 /* Check CPACR.FPEN. */ @@ -11263,8 +11264,6 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val,= uint32_t bytes) int fp_exception_el(CPUARMState *env, int cur_el) { #ifndef CONFIG_USER_ONLY - int fpen; - /* CPACR and the CPTR registers don't exist before v6, so FP is * always accessible */ @@ -11292,30 +11291,34 @@ int fp_exception_el(CPUARMState *env, int cur_el) * 0, 2 : trap EL0 and EL1/PL1 accesses * 1 : trap only EL0 accesses * 3 : trap no accesses + * This register is ignored if E2H+TGE are both set. */ - fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); - switch (fpen) { - case 0: - case 2: - if (cur_el =3D=3D 0 || cur_el =3D=3D 1) { - /* Trap to PL1, which might be EL1 or EL3 */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { + int fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); + + switch (fpen) { + case 0: + case 2: + if (cur_el =3D=3D 0 || cur_el =3D=3D 1) { + /* Trap to PL1, which might be EL1 or EL3 */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + return 3; + } + return 1; + } + if (cur_el =3D=3D 3 && !is_a64(env)) { + /* Secure PL1 running at EL3 */ return 3; } - return 1; + break; + case 1: + if (cur_el =3D=3D 0) { + return 1; + } + break; + case 3: + break; } - if (cur_el =3D=3D 3 && !is_a64(env)) { - /* Secure PL1 running at EL3 */ - return 3; - } - break; - case 1: - if (cur_el =3D=3D 0) { - return 1; - } - break; - case 3: - break; } =20 /* --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564858982; cv=none; d=zoho.com; s=zohoarc; b=ZYwDBwWoe3hhMH9wZDNNVCcSgXtdzBOPzeBJgEeWPSWhW2IxYSD3oKRB3CTc+zXRZ3RxLCGLmDiyy3RmS3vfAaO/W2kfEoufqDVitnji1Ggch81g6Czk9p86LdGS/MSGOdSdVTMSelJRhhahN6xkEr2QWu6vPZhcDD7xSz0TOwQ= ARC-Message-Signature: i=1; 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X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 32/34] target/arm: Enable ARMv8.1-VHE in -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1901997a06..b1bb394c6d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -337,6 +337,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64mmfr1; t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); cpu->isar.id_aa64mmfr1 =3D t; =20 /* Replicate the same data to the 32-bit id registers. */ --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564859109; cv=none; d=zoho.com; s=zohoarc; b=DdZthIV3vdX5oACW19XDrtDglT1jO/LWP2leET87BRbdOZPcyPZ8P8SvyGR6IOaUkjDlBeHV1oi7YJ72nLlCOHyKrLESTPTuNJmGJWs0D4F5obdYDCWXyjJIoWJ/pzwfSw6tsBD96+KZ8R4fHYdpnJ6J8Vm64PJYUqLcxe4fQ54= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564859109; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=1OFhZYB7REGpAAmdzyA7otQ/hGEth32oUJ6nOIibRSY=; b=ler1GhvjdrsZxZERqX/jAvqoYphTQX7f2LytOi/LMIKSf0FySl3BauPl8nCseieB6Rk805BYxlut/i2WufdfEDlRRNK4t5QTWoYrERYfK6QU58giCyrsEbQb3kpBuKgrBUw1zdmFfYCAKwwi01q8RL/cH2ZcuQc5NNP8UfW0z70= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564859109104977.5503337571304; Sat, 3 Aug 2019 12:05:09 -0700 (PDT) Received: from localhost ([::1]:41692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htzL0-0000FY-U4 for importer@patchew.org; Sat, 03 Aug 2019 15:05:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33108) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz5K-0007GI-LZ for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz5J-0007WE-OA for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:54 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:42856) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz5J-0007QN-JI for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:53 -0400 Received: by mail-pf1-x441.google.com with SMTP id q10so37607491pff.9 for ; Sat, 03 Aug 2019 11:48:42 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.40 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1OFhZYB7REGpAAmdzyA7otQ/hGEth32oUJ6nOIibRSY=; b=Q2KjR7szqQzFJBEH2NX0Shzd0whUpZj611QA5mIAYhzgpKlRBh5ODsGM5FpzlG4XYN E60p6k7knFLoG/3l6e6jb7NjxMSe0Uv8+wqgGre6LtOAO8f9GbaDAC+QVVD/ZN5iyITN lGdwQcy388XZhoO0jJnjvMrs8PgL8MKY8f2zAiABXU4jRRFArYBaW2DC9HbECCXS3boA MVFaJlKA0Jjiem7h2Fc2fVhhL4udB+lpnGcgR8fnzJZy8uhg7VgTozjHaTNGGsA68nb+ pNMQWGe5juX6arF/6MAQUZs+Ue9hikLMS6b4/+dUo5QLrj218JfX5gH9w7La9BbmqPbo yNEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1OFhZYB7REGpAAmdzyA7otQ/hGEth32oUJ6nOIibRSY=; b=PiA56Qe461Ikjgo524YDH1tBp04+AV3VRRgNXiGQvkN7Yi5N6SeyQ2fUje4QgvDXRt uOMj9niWmdtcyy9v0T489aBsjEo5HQPX2dR449GR97yt0MF05PbqyrUik0KVGxVGzKfw EYUAWR2YkTCMOCehSHN6Xu3+4G8pYyXIcuF9lY44tC7occMjSfKZiMLEgIHWvxlwVvCp d3WC4AYge3u5p99XoIGTsY0+BnOWnYlXALLD4aekRpkDBgKsIBNBXa5uJ4DjiAV57CKP 7vEOu+rl5I7gc/vEJqvr6XzjdsHmruap9M8bzXSkLLd4o1gVAGB8QjUwf4R9uAu/Yh6T eQBQ== X-Gm-Message-State: APjAAAVEJHwRwsdPHVwFIIpIEUcLirj1kS1kpm2LIXQQ+R0hIeeL88aM a8i7F+w43qWGAi77C507n73S396lM+4= X-Google-Smtp-Source: APXvYqwcpUfQm+lN0lAiyTvKZ+LKiZdqq8LkPAnYLxLczAXe8PepUtoBWVyUkepumSba4RRwsKQ6zg== X-Received: by 2002:a62:ac11:: with SMTP id v17mr65823645pfe.236.1564858121535; Sat, 03 Aug 2019 11:48:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:59 -0700 Message-Id: <20190803184800.8221-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 33/34] target/arm: check TGE and E2H flags for EL0 pauth traps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Alex Benn=C3=A9e According to ARM ARM we should only trap from EL0 when TCG or E2H are 0. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/pauth_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index 42c9141bb7..9fa002068e 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -371,7 +371,9 @@ static void pauth_check_trap(CPUARMState *env, int el, = uintptr_t ra) if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { uint64_t hcr =3D arm_hcr_el2_eff(env); bool trap =3D !(hcr & HCR_API); - /* FIXME: ARMv8.1-VHE: trap only applies to EL1&0 regime. */ + if (el < 1) { + trap &=3D !(hcr & HCR_TGE) | !(hcr & HCR_E2H); + } /* FIXME: ARMv8.3-NV: HCR_NV trap takes precedence for ERETA[AB]. = */ if (trap) { pauth_trap(env, 2, ra); --=20 2.17.1 From nobody Sun Apr 28 09:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1564859020; cv=none; d=zoho.com; s=zohoarc; b=NVxO7Vu5NHE68s4W3SQknyBcWsngjWo2ExcJosJ/wgxU5nype7GCzDc+vG0z8vz34O5KSahZ6TTW1KMfzujTaKZRbBv53w78kMOxaWMBiPXie0znDfsUKiyB8hmetRZo656Px2YREYbhYlsHlLonkvqk2bWHaDdMmeZssuCrftc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564859020; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=VZbb1rzI4zahnAL11h/DzkD7ar6WwiCPlhOLpT3N7ho=; b=m1Jx0TZvLfYa7kRK2rWudLXUm0RXdzkzyacDy13i1uFnyqHSusUh7m/ITjR8EoC/c4gFgiAksuTPekkeBCJQ9VJhPgYhFkm6tvWZPmLeP9lPO8JhNG/+a5INR5YLGFJVYtdCGkNYX2sUxHA+nLUwpdezFYXsMKTDM/eQR8tcapM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564859020344587.5991434518216; Sat, 3 Aug 2019 12:03:40 -0700 (PDT) Received: from localhost ([::1]:41674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htzJb-0006X5-AN for importer@patchew.org; Sat, 03 Aug 2019 15:03:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33007) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1htz5D-0006vq-Hg for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1htz5B-0007SW-L1 for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:47 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:34531) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1htz5B-0007Qu-EX for qemu-devel@nongnu.org; Sat, 03 Aug 2019 14:48:45 -0400 Received: by mail-pg1-x543.google.com with SMTP id n9so31447517pgc.1 for ; Sat, 03 Aug 2019 11:48:43 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q69sm15405454pjb.0.2019.08.03.11.48.41 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 03 Aug 2019 11:48:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VZbb1rzI4zahnAL11h/DzkD7ar6WwiCPlhOLpT3N7ho=; b=XUMdfYtyP/dN0NvjiEKzLhQ81PX1aEG6yfDSVTntnAkC0mjiaPutVEuE/iwMSdBaoI W2BAVieKDVGUWnETHBzDpm1ZmGfk/R32ANvpX6bxCan8Oz3rTCsduFiqbjm7V8wqU8/b bMpmDhcVV6F2wWxm9nc7j2Bn/Ofi/Zs7IjN9iW/QZAMI2nSs5Wx6sAVyRWuS0BaY5UXm WQA5op6gMyyi/s9Nb5FAhiwqXDqXfizNoVCq7fWlZCVe/TUh3wfRLSGOd2CkAbw8Rm8S rFZi2TjdomMmBQLXmyScAFfk/5j0NKU2Smfhj+o1qrw/6SRBWfVSw12ecq7VZLD5gkW6 wutQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VZbb1rzI4zahnAL11h/DzkD7ar6WwiCPlhOLpT3N7ho=; b=bjbgNkLsAO9wuVUJHNrTXFf9vcsPcpIH0ArWblUGeH6I7RiO0Zp8GldTAufQOBDxyC XzlsmNF71GK5iruNxtdldeMq7W3EQk6Alxoo2kScjqL9jyffcLgcISJwtCecsZtZBI4Q J447CHAoltnNwfIaijU7zbpqPHLKL+Wfwoy74mME2QXGbl8MxO2j+lOMKJjjuv5I/UtW 95c+0MQHcoPdyQCl0lfnIZ6Acw/e2NuWWO3wkFVEw4+0ZMySaIxj3NeVE1o7nJAoQ7Za ayh8Hl3PTCBIqnfQHrCHq5jj7r5iDbOgT6zYN0iZiLuNWgKTyp78aoIK0ccrfvj99/hz MqhQ== X-Gm-Message-State: APjAAAWnBVr3vUvmn3nZ4bv5lnPbVxu142TKs2yprn/miMKxYZNKGz0u DJi5mrAOlFSjYy3ormgLVpH2/Alek9o= X-Google-Smtp-Source: APXvYqw7VsRRz+iBeE+9ZkwpQ3Zibt84S6Mpe2vBhl6+hXjcwsWUD8EUrwYhDFR18aHpFlkHDuvpsg== X-Received: by 2002:a17:90a:8a0b:: with SMTP id w11mr10351911pjn.125.1564858122529; Sat, 03 Aug 2019 11:48:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:48:00 -0700 Message-Id: <20190803184800.8221-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 34/34] target/arm: generate a custom MIDR for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Alex Benn=C3=A9e While most features are now detected by probing the ID_* registers kernels can (and do) use MIDR_EL1 for working out of they have to apply errata. This can trip up warnings in the kernel as it tries to work out if it should apply workarounds to features that don't actually exist in the reported CPU type. Avoid this problem by synthesising our own MIDR value. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20190726113950.7499-1-alex.bennee@linaro.org> Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 ++++++ target/arm/cpu64.c | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d7c5a123a3..6e4c97d398 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1605,6 +1605,12 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1) /* * System register ID fields. */ +FIELD(MIDR_EL1, REVISION, 0, 4) +FIELD(MIDR_EL1, PARTNUM, 4, 12) +FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) +FIELD(MIDR_EL1, VARIANT, 20, 4) +FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) + FIELD(ID_ISAR0, SWAP, 0, 4) FIELD(ID_ISAR0, BITCOUNT, 4, 4) FIELD(ID_ISAR0, BITFIELD, 8, 4) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index b1bb394c6d..3a1e98a18e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -296,6 +296,25 @@ static void aarch64_max_initfn(Object *obj) uint32_t u; aarch64_a57_initfn(obj); =20 + /* + * Reset MIDR so the guest doesn't mistake our 'max' CPU type for = a real + * one and try to apply errata workarounds or use impdef features = we + * don't provide. + * An IMPLEMENTER field of 0 means "reserved for software use"; + * ARCHITECTURE must be 0xf indicating "v7 or later, check ID regi= sters + * to see which features are present"; + * the VARIANT, PARTNUM and REVISION fields are all implementation + * defined and we choose to define PARTNUM just in case guest + * code needs to distinguish this QEMU CPU from other software + * implementations, though this shouldn't be needed. + */ + t =3D FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); + t =3D FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); + t =3D FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); + t =3D FIELD_DP64(t, MIDR_EL1, VARIANT, 0); + t =3D FIELD_DP64(t, MIDR_EL1, REVISION, 0); + cpu->midr =3D t; + t =3D cpu->isar.id_aa64isar0; t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); --=20 2.17.1