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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j16sm17320424wrp.62.2019.08.01.03.57.44 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 01 Aug 2019 03:57:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=i5yczFfVrAVlR4940QCcbKeiFq9wP+iOiA2djQVLfF0=; b=SIVOUUDmYzu8CzBNXMzZrqYbvaV+X5Fdm5H8GwoaxpNJb88ybs5sf1HNQwzwXIBwYQ lrbUca/7V2THxZsbYTcGHOQ1MtmrdyhL+Jv/maFlX+0liLv2evo+59aOnBYewHsA2b1N g46rbGEpyTKRPoSsRjbDagjGmsMOzemlKNkKZ9k2fZaSwCMa0ej/1lAgrMLaedn8Ldz/ dqOjoHnFFkRsCgs/JW8YVYXsZjn+cBWuAfiz/kDHMVPPrdcFxsK+IOWrDxrHS385MFNR wgpKpijAWEaHFNJOea7GR7z5JuOfeeQ1Ki9lf+DHnODqCujgU7g5zJeoG6Y/Wnwh3iiZ 2+UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=i5yczFfVrAVlR4940QCcbKeiFq9wP+iOiA2djQVLfF0=; b=C1ScFGLGeB2PER29acZbtVYRB5yXSeeAYr1M4dkypkeiFJjV8HbI+Lpyh0GSUkXgUz FUJDvPn9q5Pz8A8beIEN3x6GVhlOKl79Itg7dRZXHJ/OTe6ivgK676NhakpQGrG8qCM3 upZCNgGxo7EVrnz/rfJ7n/w5C/m07utavGkKsS7MHYZK7BI1mE4GHX6hK1bLItU4W+7S UQ8Lp1qmLcwqtg8wRBXDJSlOuidbFYr20v9D4ZPWvRYkxMC6vmhwVoxC32WS38IOwGW4 6WU84IoxP5mD2lW7nJUxI+u6eRRrwPzVOwZNYq3kLDWRNKemitgBV0KTl3jXghL/N6RJ Dn9g== X-Gm-Message-State: APjAAAU/5XPww2/NZoYyjXJvAbi1Ca8SWlABa4LoiqBjdPaymLDfMj0/ kSEcbrM23xxtx4isSMJbpRDeEg== X-Google-Smtp-Source: APXvYqwwM9Hawd0U9pUV1WLp+RkK3J/4CO/HAt22unUylWxWOrCpFKlaoXnVeFb9vZaDLingMcjMdQ== X-Received: by 2002:adf:de8e:: with SMTP id w14mr20438551wrl.79.1564657065815; Thu, 01 Aug 2019 03:57:45 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 1 Aug 2019 11:57:42 +0100 Message-Id: <20190801105742.20036-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH for-4.1] target/arm: Avoid bogus NSACR traps on M-profile without Security Extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In Arm v8.0 M-profile CPUs without the Security Extension and also in v7M CPUs, there is no NSACR register. However, the code we have to handle the FPU does not always check whether the ARM_FEATURE_M_SECURITY bit is set before testing whether env->v7m.nsacr permits access to the FPU. This means that for a CPU with an FPU but without the Security Extension we would always take a bogus fault when trying to stack the FPU registers on an exception entry. We could fix this by adding extra feature bit checks for all uses, but it is simpler to just make the internal value of nsacr 0x3ff ("all non-secure accesses allowed"), since this is not guest visible when the Security Extension is not present. This allows us to continue to follow the Arm ARM pseudocode which takes a similar approach. (In particular, in the v8.1 Arm ARM the register is documented as reading as 0xcff in this configuration.) Fixes: https://bugs.launchpad.net/qemu/+bug/1838475 Signed-off-by: Peter Maydell Reviewed-by: Damien Hedde --- I've marked this as for-4.1 because support for M-profile FPU is new in this release and this is a pretty bad bug for it. It probably doesn't qualify as so bad we need an rc4 but I think we need an rc4 anyway and it probably does merit putting in at that point. target/arm/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9eb40ff755f..ec2ab95dbeb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -266,6 +266,14 @@ static void arm_cpu_reset(CPUState *s) * on ARM_FEATURE_V8 (we don't let the guest see the bit). */ env->v7m.aircr =3D R_V7M_AIRCR_BFHFNMINS_MASK; + /* + * Set NSACR to indicate "NS access permitted to everything"; + * this avoids having to have all the tests of it being + * conditional on ARM_FEATURE_M_SECURITY. Note also that from + * v8.1M the guest-visible value of NSACR in a CPU without the + * Security Extension is 0xcff. + */ + env->v7m.nsacr =3D 0xcff; } =20 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends --=20 2.20.1