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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id g4sm84054164pfo.93.2019.07.31.13.38.16 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Wed, 31 Jul 2019 13:38:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OzH9oAANiLbbz3MZqOd0740wSKDkRIpOzsZLTONmMZs=; b=mkHD3+iYsbWab5cdVZchcSsYztaDNDugjO/BYtRQhaR9lWwuMtKJO1MOfTOMi+41tK vt6UkLW3JTiyThN3STPBnqE59TUW11RxDLiQ/biaUh2aO84jV77b/5fX8jYTq7pxU97z Ozu8J/5z66NiObuOQTlQzV6OEwh+egQSop9TErhKiE6aCHisL/bVRc4pTuIcb3++LkLT QlYOucEUVqXBkN7zQQoQMB62P06LSBvG8N2aZ8KN1Ipc6icCZMvXpNGcjCOT1DYMm8Xo hltZZ27joq3NsBo6CUCTa2HdLvkgt5I96hCt3h50ndDp11BSX9caNWf0FVB1+EsgxVd5 Pb8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OzH9oAANiLbbz3MZqOd0740wSKDkRIpOzsZLTONmMZs=; b=QlF/6Udy5HWs+7HJMRar5Ha1IWUZgECeJYE7eQsAkvkca1KBhbfFoo9QlAsH3Uy4Kk bOcSRUPhCdWAblNZWT0CQXBvm0zzUVvaWmPAj168oz60bNCGHsQH3Wflw59kmO3WLPNA QFFgTCmA1xQwmfHRJ00klzIZVszPGoDy9hSEDKZPucwvLEaAOYt/GXMSq4UcHlXZJoc6 XchzVx5QeOIh2Fi+/BFJmiiGafZ+HTuuwsmyvC9NrZGKLXyFVkCFF6VdY82yGAjahukq YmXACYk3LkNux59y9eHR8eOq6kN8EVHstFYlk6oam4r54vFLF7PCQV/GDqAzhgmFqHHL v4dw== X-Gm-Message-State: APjAAAUtGvJTL+mfL+IkR1Iy9jKT+EmfzMhoXJFbjAtYOdOGOBljRvDa dmBQE6kVfhtD4/pnSVnnqPup5bezxxg= X-Google-Smtp-Source: APXvYqyCh4czqu5MPOguqi5mN0IkCbCArQrhKl2imbG1TB/cUQHFz0tm3E1i7kVM2Hu07hZ8yC7ShQ== X-Received: by 2002:aa7:9407:: with SMTP id x7mr51015581pfo.163.1564605497999; Wed, 31 Jul 2019 13:38:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 31 Jul 2019 13:37:43 -0700 Message-Id: <20190731203813.30765-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190731203813.30765-1-richard.henderson@linaro.org> References: <20190731203813.30765-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v2 02/32] cputlb: Add tlb_flush_asid_by_mmuidx and friends X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Since we have remembered ASIDs, we can further minimize flushing by comparing against the one we want to flush. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 16 ++++++++++++ include/qom/cpu.h | 2 ++ accel/tcg/cputlb.c | 55 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 9c77aa5bf9..0d890e1e60 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -240,6 +240,22 @@ void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu= , uint16_t idxmap); */ void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid, uint16_t idxmap, uint16_t dep_idxmap); +/** + * tlb_flush_asid_by_mmuidx: + * @cpu: Originating CPU of the flush + * @asid: Address Space Identifier + * @idxmap: bitmap of MMU indexes to flush if asid matches + * + * For each mmu index, if @asid matches the value previously saved via + * tlb_set_asid_for_mmuidx, flush the index. + */ +void tlb_flush_asid_by_mmuidx(CPUState *cpu, uint32_t asid, uint16_t idxma= p); +/* Similarly, broadcasting to all cpus. */ +void tlb_flush_asid_by_mmuidx_all_cpus(CPUState *cpu, uint32_t asid, + uint16_t idxmap); +/* Similarly, waiting for the broadcast to complete. */ +void tlb_flush_asid_by_mmuidx_all_cpus_synced(CPUState *cpu, uint32_t asid, + uint16_t idxmap); /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 5ee0046b62..c072dd4c47 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -285,12 +285,14 @@ typedef union { unsigned long host_ulong; void *host_ptr; vaddr target_ptr; + uint64_t uint64; } run_on_cpu_data; =20 #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr =3D (p)}) #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int =3D (i)}) #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong =3D (ul)}) #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr =3D (v)}) +#define RUN_ON_CPU_UINT64(i) ((run_on_cpu_data){.uint64 =3D (i)}) #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) =20 typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c68f57755b..62baaa9ca6 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -540,6 +540,61 @@ void tlb_flush_page_all_cpus_synced(CPUState *src, tar= get_ulong addr) tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); } =20 +static void tlb_flush_asid_by_mmuidx_async_work(CPUState *cpu, + run_on_cpu_data data) +{ + CPUTLB *tlb =3D cpu_tlb(cpu); + uint32_t asid =3D data.uint64; + uint16_t idxmap =3D data.uint64 >> 32; + uint16_t to_flush =3D 0, work; + + assert_cpu_is_self(cpu); + + for (work =3D idxmap; work !=3D 0; work &=3D work - 1) { + int mmu_idx =3D ctz32(work); + if (tlb->d[mmu_idx].asid =3D=3D asid) { + to_flush |=3D 1 << mmu_idx; + } + } + + if (to_flush) { + tlb_flush_by_mmuidx_async_work(cpu, RUN_ON_CPU_HOST_INT(to_flush)); + } +} + +void tlb_flush_asid_by_mmuidx(CPUState *cpu, uint32_t asid, uint16_t idxma= p) +{ + uint64_t asid_idx =3D deposit64(asid, 32, 32, idxmap); + + if (cpu->created && !qemu_cpu_is_self(cpu)) { + async_run_on_cpu(cpu, tlb_flush_asid_by_mmuidx_async_work, + RUN_ON_CPU_UINT64(asid_idx)); + } else { + tlb_flush_asid_by_mmuidx_async_work(cpu, RUN_ON_CPU_UINT64(asid_id= x)); + } +} + +void tlb_flush_asid_by_mmuidx_all_cpus(CPUState *src_cpu, + uint32_t asid, uint16_t idxmap) +{ + uint64_t asid_idx =3D deposit64(asid, 32, 32, idxmap); + + flush_all_helper(src_cpu, tlb_flush_asid_by_mmuidx_async_work, + RUN_ON_CPU_UINT64(asid_idx)); + tlb_flush_asid_by_mmuidx_async_work(src_cpu, RUN_ON_CPU_UINT64(asid_id= x)); +} + +void tlb_flush_asid_by_mmuidx_all_cpus_synced(CPUState *src_cpu, + uint32_t asid, uint16_t idxm= ap) +{ + uint64_t asid_idx =3D deposit64(asid, 32, 32, idxmap); + + flush_all_helper(src_cpu, tlb_flush_asid_by_mmuidx_async_work, + RUN_ON_CPU_UINT64(asid_idx)); + async_safe_run_on_cpu(src_cpu, tlb_flush_asid_by_mmuidx_async_work, + RUN_ON_CPU_UINT64(asid_idx)); +} + void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid, uint16_t idxmap, uint16_t depmap) { --=20 2.17.1