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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v2 20/32] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part of a reorganization to the set of mmu_idx. The non-secure EL2 regime only has a single stage translation; there is no point in pointing out that the idx is for stage1. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 2 +- target/arm/helper.c | 24 ++++++++++++------------ target/arm/translate.c | 2 +- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 94337b2fb0..552269daad 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2852,7 +2852,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, typedef enum ARMMMUIdx { ARMMMUIdx_EL10_0 =3D 0 | ARM_MMU_IDX_A, ARMMMUIdx_EL10_1 =3D 1 | ARM_MMU_IDX_A, - ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 =3D 2 | ARM_MMU_IDX_A, ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_SE0 =3D 4 | ARM_MMU_IDX_A, ARMMMUIdx_SE1 =3D 5 | ARM_MMU_IDX_A, @@ -2878,7 +2878,7 @@ typedef enum ARMMMUIdx { typedef enum ARMMMUIdxBit { ARMMMUIdxBit_EL10_0 =3D 1 << 0, ARMMMUIdxBit_EL10_1 =3D 1 << 1, - ARMMMUIdxBit_S1E2 =3D 1 << 2, + ARMMMUIdxBit_E2 =3D 1 << 2, ARMMMUIdxBit_SE3 =3D 1 << 3, ARMMMUIdxBit_SE0 =3D 1 << 4, ARMMMUIdxBit_SE1 =3D 1 << 5, diff --git a/target/arm/internals.h b/target/arm/internals.h index dbb46da549..027878516f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -812,7 +812,7 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_EL10_1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_S1E2: + case ARMMMUIdx_E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: diff --git a/target/arm/helper.c b/target/arm/helper.c index e5b07b4770..69c913d824 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -740,7 +740,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); } =20 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -748,7 +748,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); } =20 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -757,7 +757,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); } =20 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -767,7 +767,7 @@ static void tlbimva_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E2); + ARMMMUIdxBit_E2); } =20 static const ARMCPRegInfo cp_reginfo[] =3D { @@ -3167,7 +3167,7 @@ static void ats1h_write(CPUARMState *env, const ARMCP= RegInfo *ri, MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; uint64_t par64; =20 - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_S1E2); + par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); } @@ -3195,7 +3195,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, mmu_idx =3D secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx =3D ARMMMUIdx_S1E2; + mmu_idx =3D ARMMMUIdx_E2; break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx =3D ARMMMUIdx_SE3; @@ -3958,7 +3958,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3984,7 +3984,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,= const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4006,7 +4006,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4059,7 +4059,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E2); + ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -4375,7 +4375,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "AT_S12E0W", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 7, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, - /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present= */ + /* AT E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ { .name =3D "AT_S1E3R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, @@ -8691,7 +8691,7 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_Stage2: - case ARMMMUIdx_S1E2: + case ARMMMUIdx_E2: return 2; case ARMMMUIdx_SE3: return 3; diff --git a/target/arm/translate.c b/target/arm/translate.c index 5372947e47..4e79dbbdfc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -152,7 +152,7 @@ static inline int get_a32_user_mem_index(DisasContext *= s) * otherwise, access as if at PL0. */ switch (s->mmu_idx) { - case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */ + case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_EL10_0: case ARMMMUIdx_EL10_1: return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0); --=20 2.17.1