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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v4 22/54] atomic_template: add inline trace/plugin helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Riku Voipio , aaron@os.amperecomputing.com, cota@braap.org, Paolo Bonzini , bobby.prani@gmail.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: "Emilio G. Cota" In preparation for plugin support. Signed-off-by: Emilio G. Cota Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v4 - move common stuff to atomic_common.inc.c - fix ups for widened uint16_t info - drop haddr in helpers - fix wide lines --- accel/tcg/atomic_common.inc.c | 50 +++++++++++++++++++ accel/tcg/atomic_template.h | 93 +++++++++++++++++++++-------------- accel/tcg/cputlb.c | 2 + accel/tcg/user-exec.c | 2 + 4 files changed, 111 insertions(+), 36 deletions(-) create mode 100644 accel/tcg/atomic_common.inc.c diff --git a/accel/tcg/atomic_common.inc.c b/accel/tcg/atomic_common.inc.c new file mode 100644 index 00000000000..a86098fb2de --- /dev/null +++ b/accel/tcg/atomic_common.inc.c @@ -0,0 +1,50 @@ +/* + * Common Atomic Helper Functions + * + * This file should be included before the various instantiations of + * the atomic_template.h helpers. + * + * Copyright (c) 2019 Linaro + * Written by Alex Benn=C3=A9e + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +static inline +void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr, uint16_t i= nfo) +{ + CPUState *cpu =3D env_cpu(env); + + trace_guest_mem_before_exec(cpu, addr, info); + trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST); +} + +static inline void +atomic_trace_rmw_post(CPUArchState *env, target_ulong addr, uint16_t info) +{ +} + +static inline +void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, uint16_t in= fo) +{ + trace_guest_mem_before_exec(env_cpu(env), addr, info); +} + +static inline +void atomic_trace_ld_post(CPUArchState *env, target_ulong addr, uint16_t i= nfo) +{ +} + +static inline +void atomic_trace_st_pre(CPUArchState *env, target_ulong addr, uint16_t in= fo) +{ + trace_guest_mem_before_exec(env_cpu(env), addr, info); +} + +static inline +void atomic_trace_st_post(CPUArchState *env, target_ulong addr, uint16_t i= nfo) +{ +} diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 53899bbbc21..34f891d4a62 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -59,26 +59,6 @@ # define ABI_TYPE uint32_t #endif =20 -#define ATOMIC_TRACE_RMW do { \ - uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, fa= lse, ATOMIC_MMU_IDX); \ - \ - trace_guest_mem_before_exec(env_cpu(env), addr, info); \ - trace_guest_mem_before_exec(env_cpu(env), addr, \ - info | TRACE_MEM_ST); \ - } while (0) - -#define ATOMIC_TRACE_LD do { \ - uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, fa= lse, ATOMIC_MMU_IDX); \ - \ - trace_guest_mem_before_exec(env_cpu(env), addr, info); \ - } while (0) - -# define ATOMIC_TRACE_ST do { \ - uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, tr= ue, ATOMIC_MMU_IDX); \ - \ - trace_guest_mem_before_exec(env_cpu(env), addr, info); \ - } while (0) - /* Define host-endian atomic operations. Note that END is used within the ATOMIC_NAME macro, and redefined below. */ #if DATA_SIZE =3D=3D 1 @@ -98,14 +78,17 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target= _ulong addr, ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; DATA_TYPE ret; + uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, false, + ATOMIC_MMU_IDX); =20 - ATOMIC_TRACE_RMW; + atomic_trace_rmw_pre(env, addr, info); #if DATA_SIZE =3D=3D 16 ret =3D atomic16_cmpxchg(haddr, cmpv, newv); #else ret =3D atomic_cmpxchg__nocheck(haddr, cmpv, newv); #endif ATOMIC_MMU_CLEANUP; + atomic_trace_rmw_post(env, addr, info); return ret; } =20 @@ -115,10 +98,13 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulo= ng addr EXTRA_ARGS) { ATOMIC_MMU_DECLS; DATA_TYPE val, *haddr =3D ATOMIC_MMU_LOOKUP; + uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, false, + ATOMIC_MMU_IDX); =20 - ATOMIC_TRACE_LD; + atomic_trace_ld_pre(env, addr, info); val =3D atomic16_read(haddr); ATOMIC_MMU_CLEANUP; + atomic_trace_ld_post(env, addr, info); return val; } =20 @@ -127,10 +113,13 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong = addr, { ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; + uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, true, + ATOMIC_MMU_IDX); =20 - ATOMIC_TRACE_ST; + atomic_trace_st_pre(env, addr, info); atomic16_set(haddr, val); ATOMIC_MMU_CLEANUP; + atomic_trace_st_post(env, addr, info); } #endif #else @@ -140,10 +129,13 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_= ulong addr, ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; DATA_TYPE ret; + uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, false, + ATOMIC_MMU_IDX); =20 - ATOMIC_TRACE_RMW; + atomic_trace_rmw_pre(env, addr, info); ret =3D atomic_xchg__nocheck(haddr, val); ATOMIC_MMU_CLEANUP; + atomic_trace_rmw_post(env, addr, info); return ret; } =20 @@ -154,10 +146,14 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulo= ng addr, \ ATOMIC_MMU_DECLS; \ DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; \ DATA_TYPE ret; \ + uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, \ + false, \ + ATOMIC_MMU_IDX)= ; \ \ - ATOMIC_TRACE_RMW; \ + atomic_trace_rmw_pre(env, addr, info); \ ret =3D atomic_##X(haddr, val); \ ATOMIC_MMU_CLEANUP; \ + atomic_trace_rmw_post(env, addr, info); \ return ret; \ } =20 @@ -186,8 +182,11 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulon= g addr, \ ATOMIC_MMU_DECLS; \ XDATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; \ XDATA_TYPE cmp, old, new, val =3D xval; \ + uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, \ + false, \ + ATOMIC_MMU_IDX)= ; \ \ - ATOMIC_TRACE_RMW; \ + atomic_trace_rmw_pre(env, addr, info); \ smp_mb(); \ cmp =3D atomic_read__nocheck(haddr); \ do { \ @@ -195,6 +194,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong= addr, \ cmp =3D atomic_cmpxchg__nocheck(haddr, old, new); \ } while (cmp !=3D old); \ ATOMIC_MMU_CLEANUP; \ + atomic_trace_rmw_post(env, addr, info); \ return RET; \ } =20 @@ -232,14 +232,18 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, targ= et_ulong addr, ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; DATA_TYPE ret; + uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, + false, + ATOMIC_MMU_IDX); =20 - ATOMIC_TRACE_RMW; + atomic_trace_rmw_pre(env, addr, info); #if DATA_SIZE =3D=3D 16 ret =3D atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv)); #else ret =3D atomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv)); #endif ATOMIC_MMU_CLEANUP; + atomic_trace_rmw_post(env, addr, info); return BSWAP(ret); } =20 @@ -249,10 +253,14 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ul= ong addr EXTRA_ARGS) { ATOMIC_MMU_DECLS; DATA_TYPE val, *haddr =3D ATOMIC_MMU_LOOKUP; + uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, + false, + ATOMIC_MMU_IDX); =20 - ATOMIC_TRACE_LD; + atomic_trace_ld_pre(env, addr, info); val =3D atomic16_read(haddr); ATOMIC_MMU_CLEANUP; + atomic_trace_ld_post(env, addr, info); return BSWAP(val); } =20 @@ -261,11 +269,16 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong = addr, { ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; + uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, + true, + ATOMIC_MMU_IDX); =20 - ATOMIC_TRACE_ST; + val =3D BSWAP(val); + atomic_trace_st_pre(env, addr, info); val =3D BSWAP(val); atomic16_set(haddr, val); ATOMIC_MMU_CLEANUP; + atomic_trace_st_post(env, addr, info); } #endif #else @@ -275,10 +288,14 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_= ulong addr, ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; ABI_TYPE ret; + uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, + false, + ATOMIC_MMU_IDX); =20 - ATOMIC_TRACE_RMW; + atomic_trace_rmw_pre(env, addr, info); ret =3D atomic_xchg__nocheck(haddr, BSWAP(val)); ATOMIC_MMU_CLEANUP; + atomic_trace_rmw_post(env, addr, info); return BSWAP(ret); } =20 @@ -289,10 +306,14 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulo= ng addr, \ ATOMIC_MMU_DECLS; \ DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; \ DATA_TYPE ret; \ + uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, \ + false, \ + ATOMIC_MMU_IDX)= ; \ \ - ATOMIC_TRACE_RMW; \ + atomic_trace_rmw_pre(env, addr, info); \ ret =3D atomic_##X(haddr, BSWAP(val)); \ ATOMIC_MMU_CLEANUP; \ + atomic_trace_rmw_post(env, addr, info); \ return BSWAP(ret); \ } =20 @@ -319,8 +340,11 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulon= g addr, \ ATOMIC_MMU_DECLS; \ XDATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; \ XDATA_TYPE ldo, ldn, old, new, val =3D xval; \ + uint16_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, \ + false, \ + ATOMIC_MMU_IDX)= ; \ \ - ATOMIC_TRACE_RMW; \ + atomic_trace_rmw_pre(env, addr, info); \ smp_mb(); \ ldn =3D atomic_read__nocheck(haddr); \ do { \ @@ -328,6 +352,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong= addr, \ ldn =3D atomic_cmpxchg__nocheck(haddr, ldo, BSWAP(new)); \ } while (ldo !=3D ldn); \ ATOMIC_MMU_CLEANUP; \ + atomic_trace_rmw_post(env, addr, info); \ return RET; \ } =20 @@ -355,10 +380,6 @@ GEN_ATOMIC_HELPER_FN(add_fetch, ADD, DATA_TYPE, new) #undef MEND #endif /* DATA_SIZE > 1 */ =20 -#undef ATOMIC_TRACE_ST -#undef ATOMIC_TRACE_LD -#undef ATOMIC_TRACE_RMW - #undef BSWAP #undef ABI_TYPE #undef DATA_TYPE diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 21ba71ea9dd..e4ac06041a2 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1701,6 +1701,8 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulon= g addr, uint64_t val, } while (0) #define ATOMIC_MMU_IDX oi =20 +#include "atomic_common.inc.c" + #define DATA_SIZE 1 #include "atomic_template.h" =20 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index bff1934cf1b..1c8aee943dc 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -724,6 +724,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, targe= t_ulong addr, #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) #define EXTRA_ARGS =20 +#include "atomic_common.inc.c" + #define DATA_SIZE 1 #include "atomic_template.h" =20 --=20 2.20.1