From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1564582436; cv=none; d=zoho.com; s=zohoarc; b=LoOj4QBBB3QALAb7jHw8PF5slFEvzX/Km9OxVuW0o/VvFvPqndtjtYdpT0AFOZ831+VvOLhEVcLBTEACKr6ck4uolUhJvLAzHKsx1yS31C5oO7OXMFJZvBzCLRQSJcv74TnIiyUvXuFs0+r8z6aVafuK9x8uQCaT0aycW+8udjg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564582436; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=1KdH1ZU1mN+viek04Qp1NEaN3o5hFO4OvvEkc9gzA+I=; b=GmIXzk1YtMQ4zrZLbrpm1JxIswo17oI24ezrJxmApEqRIesUuJ4GZLEmWdgwmOjXcKpOF1hj2yUDNrb1LXgy45FPFFWpp0G09EaO41A9aIcbLCc138iJZV4D1LE8JmW56EMTP0TQcvBcc3NysweUcnr0BOx/p0KDXlVBWMVD3Vk= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156458243620879.3841761795394; Wed, 31 Jul 2019 07:13:56 -0700 (PDT) Received: from localhost ([::1]:41194 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hspMZ-00004t-7b for importer@patchew.org; Wed, 31 Jul 2019 10:13:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34007) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hspLg-0006bb-Kr for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hspLf-0001ZZ-BQ for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:00 -0400 Received: from 1.mo4.mail-out.ovh.net ([178.33.248.196]:34516) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hspLf-0001YZ-5Z for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:12:59 -0400 Received: from player715.ha.ovh.net (unknown [10.109.143.175]) by mo4.mail-out.ovh.net (Postfix) with ESMTP id 69E5F1FD476 for ; Wed, 31 Jul 2019 16:12:57 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id 0FB35850B757; Wed, 31 Jul 2019 14:12:50 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:16 +0200 Message-Id: <20190731141233.1340-2-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11666856313866783718 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.248.196 Subject: [Qemu-devel] [PATCH v3 01/18] ppc/pnv: Introduce PowerNV machines with fixed CPU models X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Make the current "powernv" machine an abstract type and derive from it new machines with specific CPU models: power8 and power9. The "powernv" machine is now an alias on the "powernv9" machine. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 63 insertions(+), 7 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 4570ce8afe6a..18602b9e9bcd 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -602,9 +602,20 @@ static void pnv_chip_power9_pic_print_info(PnvChip *ch= ip, Monitor *mon) pnv_psi_pic_print_info(&chip9->psi, mon); } =20 +static bool pnv_match_cpu(const char *default_type, const char *cpu_type) +{ + PowerPCCPUClass *ppc_default =3D + POWERPC_CPU_CLASS(object_class_by_name(default_type)); + PowerPCCPUClass *ppc =3D + POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); + + return ppc_default->pvr_match(ppc_default, ppc->pvr); +} + static void pnv_init(MachineState *machine) { PnvMachineState *pnv =3D PNV_MACHINE(machine); + MachineClass *mc =3D MACHINE_GET_CLASS(machine); MemoryRegion *ram; char *fw_filename; long fw_size; @@ -664,13 +675,23 @@ static void pnv_init(MachineState *machine) } } =20 + /* + * Check compatibility of the specified CPU with the machine + * default. + */ + if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { + error_report("invalid CPU model '%s' for %s machine", + machine->cpu_type, mc->name); + exit(1); + } + /* Create the processor chips */ i =3D strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); chip_typename =3D g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), i, machine->cpu_type); if (!object_class_by_name(chip_typename)) { - error_report("invalid CPU model '%.*s' for %s machine", - i, machine->cpu_type, MACHINE_GET_CLASS(machine)->nam= e); + error_report("invalid chip model '%.*s' for %s machine", + i, machine->cpu_type, mc->name); exit(1); } =20 @@ -1348,25 +1369,43 @@ static void pnv_machine_class_props_init(ObjectClas= s *oc) NULL); } =20 -static void pnv_machine_class_init(ObjectClass *oc, void *data) +static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); XICSFabricClass *xic =3D XICS_FABRIC_CLASS(oc); + + mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER8"; + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power8_v2.0"); + + xic->icp_get =3D pnv_icp_get; + xic->ics_get =3D pnv_ics_get; + xic->ics_resend =3D pnv_ics_resend; +} + +static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER9"; + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power9_v2.0"); + + mc->alias =3D "powernv"; +} + +static void pnv_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); InterruptStatsProviderClass *ispc =3D INTERRUPT_STATS_PROVIDER_CLASS(o= c); =20 mc->desc =3D "IBM PowerNV (Non-Virtualized)"; mc->init =3D pnv_init; mc->reset =3D pnv_reset; mc->max_cpus =3D MAX_CPUS; - mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power8_v2.0"); mc->block_default_type =3D IF_IDE; /* Pnv provides a AHCI device for * storage */ mc->no_parallel =3D 1; mc->default_boot_order =3D NULL; mc->default_ram_size =3D 2 * GiB; - xic->icp_get =3D pnv_icp_get; - xic->ics_get =3D pnv_ics_get; - xic->ics_resend =3D pnv_ics_resend; ispc->print_info =3D pnv_pic_print_info; =20 pnv_machine_class_props_init(oc); @@ -1386,10 +1425,27 @@ static void pnv_machine_class_init(ObjectClass *oc,= void *data) .parent =3D TYPE_PNV9_CHIP, \ } =20 +#define DEFINE_PNV_MACHINE_TYPE(cpu, class_initfn) \ + { \ + .name =3D MACHINE_TYPE_NAME(cpu), \ + .parent =3D TYPE_PNV_MACHINE, \ + .instance_size =3D sizeof(PnvMachineState), \ + .instance_init =3D pnv_machine_instance_init, \ + .class_init =3D class_initfn, \ + .interfaces =3D (InterfaceInfo[]) { \ + { TYPE_XICS_FABRIC }, \ + { TYPE_INTERRUPT_STATS_PROVIDER }, \ + { }, \ + }, \ + } + static const TypeInfo types[] =3D { + DEFINE_PNV_MACHINE_TYPE("powernv8", pnv_machine_power8_class_init), + DEFINE_PNV_MACHINE_TYPE("powernv9", pnv_machine_power9_class_init), { .name =3D TYPE_PNV_MACHINE, .parent =3D TYPE_MACHINE, + .abstract =3D true, .instance_size =3D sizeof(PnvMachineState), .instance_init =3D pnv_machine_instance_init, .class_init =3D pnv_machine_class_init, --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 31 Jul 2019 10:13:04 -0400 Received: from player715.ha.ovh.net (unknown [10.109.159.224]) by mo69.mail-out.ovh.net (Postfix) with ESMTP id B3C9D6467C for ; Wed, 31 Jul 2019 16:13:02 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id 323B2850B7B3; Wed, 31 Jul 2019 14:12:57 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:17 +0200 Message-Id: <20190731141233.1340-3-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11668263688295975910 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.50.107 Subject: [Qemu-devel] [PATCH v3 02/18] tests/boot-serial-test: add support for all the PowerNV machines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Use the machine names specifiying the CPU type, POWER8 and POWER9. Signed-off-by: C=C3=A9dric Le Goater --- tests/boot-serial-test.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c index 24852d4c7d0b..a54d007298f7 100644 --- a/tests/boot-serial-test.c +++ b/tests/boot-serial-test.c @@ -103,7 +103,8 @@ static testdef_t tests[] =3D { { "ppc64", "pseries", "-machine cap-cfpc=3Dbroken,cap-sbbc=3Dbroken,cap-ibs=3Dbroken", "Open Firmware" }, - { "ppc64", "powernv", "-cpu POWER8", "OPAL" }, + { "ppc64", "powernv8", "", "OPAL" }, + { "ppc64", "powernv9", "", "OPAL" }, { "ppc64", "sam460ex", "-device e1000", "8086 100e" }, { "i386", "isapc", "-cpu qemu32 -device sga", "SGABIOS" }, { "i386", "pc", "-device sga", "SGABIOS" }, --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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Wed, 31 Jul 2019 10:13:10 -0400 Received: from player715.ha.ovh.net (unknown [10.108.35.74]) by mo4.mail-out.ovh.net (Postfix) with ESMTP id 0DB4B200680 for ; Wed, 31 Jul 2019 16:13:09 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id 87C93850B82A; Wed, 31 Jul 2019 14:13:02 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:18 +0200 Message-Id: <20190731141233.1340-4-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11669952537534761958 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.40.176 Subject: [Qemu-devel] [PATCH v3 03/18] ppc/xive: Introduce the XiveFabric and XivePresenter interfaces X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When the XIVE IVRE sub-engine (XiveRouter) looks for a Notification Virtual Target (NVT) to notify, it broadcasts a message on the PowerBUS to find an XIVE IVPE sub-engine (Presenter) which has the NVT dispatched on one of its HW threads, and then forwards the notification if any response was received. The current XIVE presenter model is sufficient for the pseries machine because it has a single interrupt controller device, but the PowerNV machine can have multiple chips each having its own interrupt controller. In this case, the XIVE presenter model is too simple and the CAM line matching should scan all chips of the system. We introduce a XiveFabric QOM interface which needs to be implemented by the machine. It acts as the PowerBUS interface between the interrupt controller and the system. On HW, the XIVE sub-engine responsible for the communication with the other chip is the Common Queue (CQ) bridge unit. This interface offers a 'match_nvt' handler to perform the CAM line matching when looking for a XIVE Presenter with a dispatched NVT. We also introduce a XivePresenter QOM interface to represent the XIVE Presenter (PC) sub-engine of the XIVE controller with a similar 'match_nvt' handler to perform the CAM line matching. This interface could be merged in the XiveRouter but as it is stateless and performs the XIVE IVPE sub-engine tasks, it makes sense to keep it independent. It should have its use in POWER10. Fixes: af53dbf6227a ("ppc/xive: introduce a simplified XIVE presenter") Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 54 +++++++++++++++++++++++++++++++++++++++++++ hw/intc/xive.c | 36 +++++++++++++++++++++-------- 2 files changed, 81 insertions(+), 9 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 4851ff87e795..165134ce52a5 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -368,6 +368,60 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nv= t_blk, uint32_t nvt_idx, XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs); void xive_router_notify(XiveNotifier *xn, uint32_t lisn); =20 +/* + * XIVE Presenter + */ + +typedef struct XiveTCTXMatch { + XiveTCTX *tctx; + uint8_t ring; +} XiveTCTXMatch; + +typedef struct XivePresenter XivePresenter; + +#define TYPE_XIVE_PRESENTER "xive-presenter" +#define XIVE_PRESENTER(obj) \ + INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER) +#define XIVE_PRESENTER_CLASS(klass) \ + OBJECT_CLASS_CHECK(XivePresenterClass, (klass), TYPE_XIVE_PRESENTER) +#define XIVE_PRESENTER_GET_CLASS(obj) \ + OBJECT_GET_CLASS(XivePresenterClass, (obj), TYPE_XIVE_PRESENTER) + +typedef struct XivePresenterClass { + InterfaceClass parent; + int (*match_nvt)(XivePresenter *xptr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match); +} XivePresenterClass; + +int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, + uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint32_t logic_serv); + +/* + * XIVE Fabric (Interface between Interrupt Controller and Machine) + */ + +typedef struct XiveFabric XiveFabric; + +#define TYPE_XIVE_FABRIC "xive-fabric" +#define XIVE_FABRIC(obj) \ + INTERFACE_CHECK(XiveFabric, (obj), TYPE_XIVE_FABRIC) +#define XIVE_FABRIC_CLASS(klass) \ + OBJECT_CLASS_CHECK(XiveFabricClass, (klass), TYPE_XIVE_FABRIC) +#define XIVE_FABRIC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(XiveFabricClass, (obj), TYPE_XIVE_FABRIC) + +typedef struct XiveFabricClass { + InterfaceClass parent; + int (*match_nvt)(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match); +} XiveFabricClass; + /* * XIVE END ESBs */ diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 88f2e560db0f..4bdedab13047 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1294,9 +1294,10 @@ static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) /* * The thread context register words are in big-endian format. */ -static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool cam_ignore, uint32_t logic_serv) +int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, + uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint32_t logic_serv) { uint32_t cam =3D xive_nvt_cam_line(nvt_blk, nvt_idx); uint32_t qw3w2 =3D xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); @@ -1353,11 +1354,6 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx,= uint8_t format, return -1; } =20 -typedef struct XiveTCTXMatch { - XiveTCTX *tctx; - uint8_t ring; -} XiveTCTXMatch; - static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, @@ -1383,7 +1379,8 @@ static bool xive_presenter_match(XiveRouter *xrtr, ui= nt8_t format, * Check the thread context CAM lines and record matches. We * will handle CPU exception delivery later */ - ring =3D xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx, + ring =3D xive_presenter_tctx_match(XIVE_PRESENTER(xrtr), tctx, for= mat, + nvt_blk, nvt_idx, cam_ignore, logic_serv); /* * Save the context and follow on to catch duplicates, that we @@ -1670,6 +1667,7 @@ static const TypeInfo xive_router_info =3D { .class_init =3D xive_router_class_init, .interfaces =3D (InterfaceInfo[]) { { TYPE_XIVE_NOTIFIER }, + { TYPE_XIVE_PRESENTER }, { } } }; @@ -1841,10 +1839,30 @@ static const TypeInfo xive_notifier_info =3D { .class_size =3D sizeof(XiveNotifierClass), }; =20 +/* + * XIVE Presenter + */ +static const TypeInfo xive_presenter_info =3D { + .name =3D TYPE_XIVE_PRESENTER, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(XivePresenterClass), +}; + +/* + * XIVE Fabric + */ +static const TypeInfo xive_fabric_info =3D { + .name =3D TYPE_XIVE_FABRIC, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(XiveFabricClass), +}; + static void xive_register_types(void) { type_register_static(&xive_source_info); type_register_static(&xive_notifier_info); + type_register_static(&xive_presenter_info); + type_register_static(&xive_fabric_info); type_register_static(&xive_router_info); type_register_static(&xive_end_source_info); type_register_static(&xive_tctx_info); --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1564582690; cv=none; d=zoho.com; s=zohoarc; b=G2zNWp98Y/JDctkdeR1SIWzsPQg2/FJ1G+wnlGtdrvQMTQO9TBfnP2z1Dpo0XcoS/KSSa/S5S0N+2ToVsiEK3W5DwUMZJW9DoLpDs2TY0B0A1uxl0QkKd6ufmBrWHfpuf9/Lt50iBf4W9WFqi1NXi196cOU3vRZKy9wnmGhX2lU= ARC-Message-Signature: i=1; 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Wed, 31 Jul 2019 10:18:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34154) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hspLx-0007LN-K9 for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hspLw-0001ke-Be for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:17 -0400 Received: from 2.mo177.mail-out.ovh.net ([178.33.109.80]:57891) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hspLw-0001jc-4t for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:16 -0400 Received: from player715.ha.ovh.net (unknown [10.109.146.50]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 64A87106430 for ; Wed, 31 Jul 2019 16:13:14 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id EF99B850B8AC; Wed, 31 Jul 2019 14:13:08 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:19 +0200 Message-Id: <20190731141233.1340-5-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11671641387786210278 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.109.80 Subject: [Qemu-devel] [PATCH v3 04/18] ppc/pnv: Implement the XiveFabric and XivePresenter interfaces X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The CAM line matching on the PowerNV machine now scans all chips of the system and all CPUs of a chip to find a dispatched NVT in the thread contexts. As there is now easy way to loop on the CPUs belonging to a chip, the PowerNV handler loops on all CPUs and filter out the external CPUs. Fixes: af53dbf6227a ("ppc/xive: introduce a simplified XIVE presenter") Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++ hw/ppc/pnv.c | 32 +++++++++++++++++++ 2 files changed, 108 insertions(+) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index ff1226485983..183798b81496 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -390,6 +390,80 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t = blk, uint32_t idx, return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas); } =20 +static int cpu_pir(PowerPCCPU *cpu) +{ + CPUPPCState *env =3D &cpu->env; + return env->spr_cb[SPR_PIR].default_value; +} + +static int cpu_chip_id(PowerPCCPU *cpu) +{ + int pir =3D cpu_pir(cpu); + return (pir >> 8) & 0x7f; +} + +static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu) +{ + int pir =3D cpu_pir(cpu); + int thrd_id =3D pir & 0x7f; + + return xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(thrd_id); +} + +static bool pnv_xive_is_ignored(PnvChip *chip, CPUState *cs) +{ + return chip->chip_id !=3D cpu_chip_id(POWERPC_CPU(cs)); +} + +#define PNV_CHIP_CPU_FOREACH(chip, cs) \ + CPU_FOREACH(cs) \ + if (pnv_xive_is_ignored(chip, cs)) {} else + +static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) +{ + PnvXive *xive =3D PNV_XIVE(xptr); + CPUState *cs; + int count =3D 0; + + /* + * Loop on all CPUs of the machine and filter out the CPUs + * belonging to another chip. + */ + PNV_CHIP_CPU_FOREACH(xive->chip, cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + XiveTCTX *tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc); + int ring; + + if (!pnv_xive_is_cpu_enabled(xive, cpu)) { + continue; + } + + ring =3D xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nv= t_idx, + cam_ignore, logic_serv); + /* + * Save the context and follow on to catch duplicates, that we + * don't support yet. + */ + if (ring !=3D -1) { + if (match->tctx) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " + "thread context NVT %x/%x\n", + nvt_blk, nvt_idx); + return -1; + } + + match->ring =3D ring; + match->tctx =3D tctx; + count++; + } + } + + return count; +} + static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -1795,6 +1869,7 @@ static void pnv_xive_class_init(ObjectClass *klass, v= oid *data) PnvXScomInterfaceClass *xdc =3D PNV_XSCOM_INTERFACE_CLASS(klass); XiveRouterClass *xrc =3D XIVE_ROUTER_CLASS(klass); XiveNotifierClass *xnc =3D XIVE_NOTIFIER_CLASS(klass); + XivePresenterClass *xpc =3D XIVE_PRESENTER_CLASS(klass); =20 xdc->dt_xscom =3D pnv_xive_dt_xscom; =20 @@ -1810,6 +1885,7 @@ static void pnv_xive_class_init(ObjectClass *klass, v= oid *data) xrc->get_tctx =3D pnv_xive_get_tctx; =20 xnc->notify =3D pnv_xive_notify; + xpc->match_nvt =3D pnv_xive_match_nvt; }; =20 static const TypeInfo pnv_xive_info =3D { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 18602b9e9bcd..3f6796831b68 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1322,6 +1322,35 @@ static void pnv_pic_print_info(InterruptStatsProvide= r *obj, } } =20 +static int pnv_xive_match_nvt(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, + XiveTCTXMatch *match) +{ + PnvMachineState *pnv =3D PNV_MACHINE(xfb); + int total_count =3D 0; + int i; + + for (i =3D 0; i < pnv->num_chips; i++) { + Pnv9Chip *chip9 =3D PNV9_CHIP(pnv->chips[i]); + XivePresenter *xptr =3D XIVE_PRESENTER(&chip9->xive); + XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); + int count; + + count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignor= e, + priority, logic_serv, match); + + if (count < 0) { + return count; + } + + total_count +=3D count; + } + + return total_count; +} + static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -1385,9 +1414,11 @@ static void pnv_machine_power8_class_init(ObjectClas= s *oc, void *data) static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); + XiveFabricClass *xfc =3D XIVE_FABRIC_CLASS(oc); =20 mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER9"; mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power9_v2.0"); + xfc->match_nvt =3D pnv_xive_match_nvt; =20 mc->alias =3D "powernv"; } @@ -1435,6 +1466,7 @@ static void pnv_machine_class_init(ObjectClass *oc, v= oid *data) .interfaces =3D (InterfaceInfo[]) { \ { TYPE_XICS_FABRIC }, \ { TYPE_INTERRUPT_STATS_PROVIDER }, \ + { TYPE_XIVE_FABRIC }, \ { }, \ }, \ } --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1564582578; cv=none; d=zoho.com; s=zohoarc; b=dJnCwMknG64tXDOItZqlaAXF26C73Pgqsqt4nh9/u50195h0YLwORnAoG1rLMu/sB8JncBSGYMUHQmgz8/zKYI/h2LnFaVO8lGLz9V3ndqVq762uukGjgunsFmB+mN/K/zwThhDcMizvUG1/LD6OkwsM9IEeM92a5BRN9s0Mfm0= ARC-Message-Signature: i=1; a=rsa-sha256; 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Wed, 31 Jul 2019 10:16:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34231) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hspM3-0007fM-ON for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hspM2-0001q0-84 for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:23 -0400 Received: from 7.mo7.mail-out.ovh.net ([46.105.43.131]:44663) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hspM1-0001ok-W5 for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:22 -0400 Received: from player715.ha.ovh.net (unknown [10.109.143.209]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id B993712BDED for ; Wed, 31 Jul 2019 16:13:20 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id 564BB850B92A; Wed, 31 Jul 2019 14:13:14 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:20 +0200 Message-Id: <20190731141233.1340-6-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11673330235673971686 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.43.131 Subject: [Qemu-devel] [PATCH v3 05/18] ppc/spapr: Implement the XiveFabric and XivePresenter interfaces X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The CAM line matching sequence in the pseries machine does not change much apart from the use of the new QOM interfaces. Fixes: af53dbf6227a ("ppc/xive: introduce a simplified XIVE presenter") Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/spapr_irq.h | 6 ++++++ hw/intc/spapr_xive.c | 41 ++++++++++++++++++++++++++++++++++++++ hw/ppc/spapr.c | 34 +++++++++++++++++++++++++++++++ hw/ppc/spapr_irq.c | 25 +++++++++++++++++++++++ 4 files changed, 106 insertions(+) diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index f965a58f8954..8c99b0680f97 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -30,6 +30,8 @@ int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_= t num, bool align, void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num); void spapr_irq_msi_reset(SpaprMachineState *spapr); =20 +struct XiveTCTXMatch; + typedef struct SpaprIrq { uint32_t nr_irqs; uint32_t nr_msis; @@ -49,6 +51,10 @@ typedef struct SpaprIrq { void (*set_irq)(void *opaque, int srcno, int val); const char *(*get_nodename)(SpaprMachineState *spapr); void (*init_kvm)(SpaprMachineState *spapr, Error **errp); + int (*match_nvt)(SpaprMachineState *spapr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, struct XiveTCTXMatch *match); } SpaprIrq; =20 extern SpaprIrq spapr_irq_xics; diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index ba012c7b0fdc..beb5049ad9da 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -419,6 +419,44 @@ static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr,= CPUState *cs) return spapr_cpu_state(cpu)->tctx; } =20 +static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) +{ + CPUState *cs; + int count =3D 0; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + XiveTCTX *tctx =3D spapr_cpu_state(cpu)->tctx; + int ring; + + /* + * Check the thread context CAM lines and record matches. + */ + ring =3D xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nv= t_idx, + cam_ignore, logic_serv); + /* + * Save the matching thread interrupt context and follow on to + * check for duplicates which are invalid. + */ + if (ring !=3D -1) { + if (match->tctx) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thre= ad " + "context NVT %x/%x\n", nvt_blk, nvt_idx); + return -1; + } + + match->ring =3D ring; + match->tctx =3D tctx; + count++; + } + } + + return count; +} + static const VMStateDescription vmstate_spapr_xive_end =3D { .name =3D TYPE_SPAPR_XIVE "/end", .version_id =3D 1, @@ -496,6 +534,7 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); XiveRouterClass *xrc =3D XIVE_ROUTER_CLASS(klass); + XivePresenterClass *xpc =3D XIVE_PRESENTER_CLASS(klass); =20 dc->desc =3D "sPAPR XIVE Interrupt Controller"; dc->props =3D spapr_xive_properties; @@ -508,6 +547,8 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) xrc->get_nvt =3D spapr_xive_get_nvt; xrc->write_nvt =3D spapr_xive_write_nvt; xrc->get_tctx =3D spapr_xive_get_tctx; + + xpc->match_nvt =3D spapr_xive_match_nvt; } =20 static const TypeInfo spapr_xive_info =3D { diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 115bbfb0e788..631db719f41f 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4302,6 +4302,37 @@ static void spapr_pic_print_info(InterruptStatsProvi= der *obj, spapr->irq->print_info(spapr, mon); } =20 +static int spapr_xive_match_nvt(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(xfb); + int count; + + count =3D spapr->irq->match_nvt(spapr, format, nvt_blk, nvt_idx, cam_i= gnore, + priority, logic_serv, match); + if (count < 0) { + return count; + } + + /* + * When we implement the save and restore of the thread interrupt + * contexts in the enter/exit CPU handlers of the machine and the + * escalations in QEMU, we should be able to handle non dispatched + * vCPUs. + * + * Until this is done, the sPAPR machine should find at least one + * matching context always. + */ + if (count =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\= n", + nvt_blk, nvt_idx); + } + + return count; +} + int spapr_get_vcpu_id(PowerPCCPU *cpu) { return cpu->vcpu_id; @@ -4398,6 +4429,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) PPCVirtualHypervisorClass *vhc =3D PPC_VIRTUAL_HYPERVISOR_CLASS(oc); XICSFabricClass *xic =3D XICS_FABRIC_CLASS(oc); InterruptStatsProviderClass *ispc =3D INTERRUPT_STATS_PROVIDER_CLASS(o= c); + XiveFabricClass *xfc =3D XIVE_FABRIC_CLASS(oc); =20 mc->desc =3D "pSeries Logical Partition (PAPR compliant)"; mc->ignore_boot_device_suffixes =3D true; @@ -4456,6 +4488,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) */ mc->numa_mem_align_shift =3D 28; mc->numa_mem_supported =3D true; + xfc->match_nvt =3D spapr_xive_match_nvt; =20 smc->default_caps.caps[SPAPR_CAP_HTM] =3D SPAPR_CAP_OFF; smc->default_caps.caps[SPAPR_CAP_VSX] =3D SPAPR_CAP_ON; @@ -4488,6 +4521,7 @@ static const TypeInfo spapr_machine_info =3D { { TYPE_PPC_VIRTUAL_HYPERVISOR }, { TYPE_XICS_FABRIC }, { TYPE_INTERRUPT_STATS_PROVIDER }, + { TYPE_XIVE_FABRIC }, { } }, }; diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index ff3df0bbd8cf..ff824d950f05 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -262,6 +262,7 @@ SpaprIrq spapr_irq_xics =3D { .set_irq =3D spapr_irq_set_irq_xics, .get_nodename =3D spapr_irq_get_nodename_xics, .init_kvm =3D spapr_irq_init_kvm_xics, + .match_nvt =3D NULL, /* should not be used */ }; =20 /* @@ -411,6 +412,18 @@ static void spapr_irq_init_kvm_xive(SpaprMachineState = *spapr, Error **errp) } } =20 +static int spapr_irq_match_nvt_xive(SpaprMachineState *spapr, uint8_t form= at, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *ma= tch) +{ + XivePresenter *xptr =3D XIVE_PRESENTER(spapr->xive); + XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); + + return xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, + priority, logic_serv, match); +} + /* * XIVE uses the full IRQ number space. Set it to 8K to be compatible * with XICS. @@ -436,6 +449,7 @@ SpaprIrq spapr_irq_xive =3D { .set_irq =3D spapr_irq_set_irq_xive, .get_nodename =3D spapr_irq_get_nodename_xive, .init_kvm =3D spapr_irq_init_kvm_xive, + .match_nvt =3D spapr_irq_match_nvt_xive, }; =20 /* @@ -590,6 +604,15 @@ static const char *spapr_irq_get_nodename_dual(SpaprMa= chineState *spapr) return spapr_irq_current(spapr)->get_nodename(spapr); } =20 +static int spapr_irq_match_nvt_dual(SpaprMachineState *spapr, uint8_t form= at, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *ma= tch) +{ + return spapr_irq_current(spapr)->match_nvt(spapr, format, nvt_blk, nvt= _idx, + cam_ignore, priority, logic_serv, mat= ch); +} + /* * Define values in sync with the XIVE and XICS backend */ @@ -613,6 +636,7 @@ SpaprIrq spapr_irq_dual =3D { .set_irq =3D spapr_irq_set_irq_dual, .get_nodename =3D spapr_irq_get_nodename_dual, .init_kvm =3D NULL, /* should not be used */ + .match_nvt =3D spapr_irq_match_nvt_dual, }; =20 =20 @@ -828,4 +852,5 @@ SpaprIrq spapr_irq_xics_legacy =3D { .set_irq =3D spapr_irq_set_irq_xics, .get_nodename =3D spapr_irq_get_nodename_xics, .init_kvm =3D spapr_irq_init_kvm_xics, + .match_nvt =3D NULL, /* should not be used */ }; --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1564582658; cv=none; d=zoho.com; s=zohoarc; b=KrK+ZN8bO3Ve3cOXTjttAI5s4uvKrALvVlVzmUHxMOwpPQ32uOnMU15xoY42LYE3IkHPvqyKxByngqRWKXRjymoCj5l/zZ0Qr+x/t1hE5sNV5qsbIFS0d06USp5+Akga7q0par2lxuJ9GEU0Aj+3qxRUHA0v6tKM1vX5vEt66xU= ARC-Message-Signature: i=1; a=rsa-sha256; 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Wed, 31 Jul 2019 10:17:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34282) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hspM8-0007wp-Vr for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hspM7-0001uR-N1 for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:28 -0400 Received: from 20.mo7.mail-out.ovh.net ([46.105.49.208]:32838) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hspM7-0001tm-H5 for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:27 -0400 Received: from player715.ha.ovh.net (unknown [10.108.35.74]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 314E7129E7A for ; Wed, 31 Jul 2019 16:13:26 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id B8044850B979; Wed, 31 Jul 2019 14:13:20 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:21 +0200 Message-Id: <20190731141233.1340-7-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11675019088031091686 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.49.208 Subject: [Qemu-devel] [PATCH v3 06/18] ppc/xive: Use the XiveFabric and XivePresenter interfaces X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Now that the machines have handlers implemented for the XiveFabric and XivePresenter interfaces, remove xive_presenter_match() and make use of the 'match_nvt' handler of the machine. Fixes: af53dbf6227a ("ppc/xive: introduce a simplified XIVE presenter") Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 77 +++++++++++--------------------------------------- 1 file changed, 17 insertions(+), 60 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 4bdedab13047..bec0c878705c 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1354,59 +1354,6 @@ int xive_presenter_tctx_match(XivePresenter *xptr, X= iveTCTX *tctx, return -1; } =20 -static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool cam_ignore, uint8_t priority, - uint32_t logic_serv, XiveTCTXMatch *match) -{ - CPUState *cs; - - /* - * TODO (PowerNV): handle chip_id overwrite of block field for - * hardwired CAM compares - */ - - CPU_FOREACH(cs) { - XiveTCTX *tctx =3D xive_router_get_tctx(xrtr, cs); - int ring; - - /* - * HW checks that the CPU is enabled in the Physical Thread - * Enable Register (PTER). - */ - - /* - * Check the thread context CAM lines and record matches. We - * will handle CPU exception delivery later - */ - ring =3D xive_presenter_tctx_match(XIVE_PRESENTER(xrtr), tctx, for= mat, - nvt_blk, nvt_idx, - cam_ignore, logic_serv); - /* - * Save the context and follow on to catch duplicates, that we - * don't support yet. - */ - if (ring !=3D -1) { - if (match->tctx) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thre= ad " - "context NVT %x/%x\n", nvt_blk, nvt_idx); - return false; - } - - match->ring =3D ring; - match->tctx =3D tctx; - } - } - - if (!match->tctx) { - qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n", - nvt_blk, nvt_idx); - return false; - } - - return true; -} - /* * This is our simple Xive Presenter Engine model. It is merged in the * Router as it does not require an extra object. @@ -1422,22 +1369,32 @@ static bool xive_presenter_match(XiveRouter *xrtr, = uint8_t format, * * The parameters represent what is sent on the PowerBus */ -static bool xive_presenter_notify(XiveRouter *xrtr, uint8_t format, +static bool xive_presenter_notify(uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, uint32_t logic_serv) { + XiveFabric *xfb =3D XIVE_FABRIC(qdev_get_machine()); + XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xfb); XiveTCTXMatch match =3D { .tctx =3D NULL, .ring =3D 0 }; - bool found; + int count; =20 - found =3D xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ign= ore, - priority, logic_serv, &match); - if (found) { + /* + * Ask the machine to scan the interrupt controllers for a match + */ + count =3D xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore, + priority, logic_serv, &match); + if (count < 0) { + return false; + } + + /* handle CPU exception delivery */ + if (count) { ipb_update(&match.tctx->regs[match.ring], priority); xive_tctx_notify(match.tctx, match.ring); } =20 - return found; + return count; } =20 /* @@ -1550,7 +1507,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, = uint8_t end_blk, return; } =20 - found =3D xive_presenter_notify(xrtr, format, nvt_blk, nvt_idx, + found =3D xive_presenter_notify(format, nvt_blk, nvt_idx, xive_get_field32(END_W7_F0_IGNORE, end.w7), priority, xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7= )); --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1564582591; cv=none; d=zoho.com; s=zohoarc; b=IjrPhr7pThFKoWgTSXN0nkUdt1eSWEehwHDxsh6IqooUTeVGne0cvH5EqC6IUfgTvjqqcUff/GWSOmp3oQ2qOnydlXA2FdUaV09j9obDXLUMJ+ZJKVKt9UbU7ewP8HPUglkADCo0dRDMZvr4EaFBXCuM6Z0sgXqWBV1Q9MWJyHM= ARC-Message-Signature: i=1; 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Wed, 31 Jul 2019 10:16:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34323) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hspMF-0008Hd-ME for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hspME-0001xc-2t for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:35 -0400 Received: from 8.mo179.mail-out.ovh.net ([46.105.75.26]:34968) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hspMD-0001wn-TP for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:34 -0400 Received: from player715.ha.ovh.net (unknown [10.108.42.184]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id 9A3DD13D1F1 for ; Wed, 31 Jul 2019 16:13:32 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id 25645850B9F7; Wed, 31 Jul 2019 14:13:26 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:22 +0200 Message-Id: <20190731141233.1340-8-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11676707936904448998 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.75.26 Subject: [Qemu-devel] [PATCH v3 07/18] ppc/xive: Extend the TIMA operation with a XivePresenter parameter X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The TIMA operations are performed on behalf of the XIVE IVPE sub-engine (Presenter) on the thread interrupt context registers. The current operations the model supports are simple and do not require access to the controller but more complex operations we will add will need access to the controller NVT table and to its configuration. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 7 +++--- hw/intc/pnv_xive.c | 4 +-- hw/intc/xive.c | 58 ++++++++++++++++++++++++------------------- 3 files changed, 38 insertions(+), 31 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 165134ce52a5..ba43a4a129d9 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -464,9 +464,10 @@ typedef struct XiveENDSource { #define XIVE_TM_USER_PAGE 0x3 =20 extern const MemoryRegionOps xive_tm_ops; -void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, - unsigned size); -uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size); +void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, + uint64_t value, unsigned size); +uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr off= set, + unsigned size); =20 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 183798b81496..6f53a2abbb6a 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1444,7 +1444,7 @@ static void xive_tm_indirect_write(void *opaque, hwad= dr offset, { XiveTCTX *tctx =3D pnv_xive_get_indirect_tctx(PNV_XIVE(opaque)); =20 - xive_tctx_tm_write(tctx, offset, value, size); + xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); } =20 static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset, @@ -1452,7 +1452,7 @@ static uint64_t xive_tm_indirect_read(void *opaque, h= waddr offset, { XiveTCTX *tctx =3D pnv_xive_get_indirect_tctx(PNV_XIVE(opaque)); =20 - return xive_tctx_tm_read(tctx, offset, size); + return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); } =20 static const MemoryRegionOps xive_tm_indirect_ops =3D { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index bec0c878705c..9ca015969143 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -141,19 +141,20 @@ static inline uint32_t xive_tctx_word2(uint8_t *ring) * XIVE Thread Interrupt Management Area (TIMA) */ =20 -static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset, - uint64_t value, unsigned size) +static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned si= ze) { xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); } =20 -static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned= size) +static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); } =20 -static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, - unsigned size) +static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { uint32_t qw2w2_prev =3D xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); uint32_t qw2w2; @@ -163,13 +164,14 @@ static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx,= hwaddr offset, return qw2w2; } =20 -static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, +static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr of= fset, uint64_t value, unsigned size) { tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] =3D value & 0xff; } =20 -static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned si= ze) +static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; } @@ -312,13 +314,14 @@ static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwad= dr offset, unsigned size) * state changes (side effects) in addition to setting/returning the * interrupt management area context of the processor thread. */ -static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned= size) +static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { return xive_tctx_accept(tctx, TM_QW1_OS); } =20 -static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset, - uint64_t value, unsigned size) +static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned si= ze) { xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); } @@ -327,15 +330,15 @@ static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwadd= r offset, * Adjust the IPB to allow a CPU to process event queues of other * priorities during one physical interrupt cycle. */ -static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset, - uint64_t value, unsigned size) +static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned= size) { ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); xive_tctx_notify(tctx, TM_QW1_OS); } =20 -static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset, - unsigned size) +static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { uint32_t qw1w2_prev =3D xive_tctx_word2(&tctx->regs[TM_QW1_OS]); uint32_t qw1w2; @@ -353,9 +356,11 @@ typedef struct XiveTmOp { uint8_t page_offset; uint32_t op_offset; unsigned size; - void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t valu= e, - unsigned size); - uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size); + void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, + uint64_t value, unsigned size); + uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr o= ffset, + unsigned size); } XiveTmOp; =20 static const XiveTmOp xive_tm_operations[] =3D { @@ -401,8 +406,8 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, u= nsigned size, bool write) /* * TIMA MMIO handlers */ -void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, - unsigned size) +void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, + uint64_t value, unsigned size) { const XiveTmOp *xto; =20 @@ -419,7 +424,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, = uint64_t value, qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at = TIMA " "@%"HWADDR_PRIx"\n", offset); } else { - xto->write_handler(tctx, offset, value, size); + xto->write_handler(xptr, tctx, offset, value, size); } return; } @@ -429,7 +434,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, = uint64_t value, */ xto =3D xive_tm_find_op(offset, size, true); if (xto) { - xto->write_handler(tctx, offset, value, size); + xto->write_handler(xptr, tctx, offset, value, size); return; } =20 @@ -439,7 +444,8 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, = uint64_t value, xive_tm_raw_write(tctx, offset, value, size); } =20 -uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size) +uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr off= set, + unsigned size) { const XiveTmOp *xto; =20 @@ -457,7 +463,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offse= t, unsigned size) "@%"HWADDR_PRIx"\n", offset); return -1; } - return xto->read_handler(tctx, offset, size); + return xto->read_handler(xptr, tctx, offset, size); } =20 /* @@ -465,7 +471,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offse= t, unsigned size) */ xto =3D xive_tm_find_op(offset, size, false); if (xto) { - return xto->read_handler(tctx, offset, size); + return xto->read_handler(xptr, tctx, offset, size); } =20 /* @@ -479,14 +485,14 @@ static void xive_tm_write(void *opaque, hwaddr offset, { XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current_c= pu); =20 - xive_tctx_tm_write(tctx, offset, value, size); + xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); } =20 static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) { XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current_c= pu); =20 - return xive_tctx_tm_read(tctx, offset, size); + return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); } =20 const MemoryRegionOps xive_tm_ops =3D { --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 31 Jul 2019 10:13:39 -0400 Received: from player715.ha.ovh.net (unknown [10.108.42.83]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 0A93413E7D0 for ; Wed, 31 Jul 2019 16:13:37 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id 8BB4E850BA64; Wed, 31 Jul 2019 14:13:32 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:23 +0200 Message-Id: <20190731141233.1340-9-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11678115311213186022 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.63.230 Subject: [Qemu-devel] [PATCH v3 08/18] ppc/pnv: Clarify how the TIMA is accessed on a multichip system X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The TIMA MMIO space is shared among the chips and to identify the chip from which the access is being done, the PowerBUS uses a chip field in the load/store messages. QEMU does not model these messages, so instead, we extract the chip id from the CPU PIR and do a lookup at the machine level to fetch the targeted interrupt controller. Introduce pnv_get_chip() and pnv_xive_tm_get_xive() helpers to clarify this process in pnv_xive_get_tctx(). The latter will be removed in the subsequent patches but the same principle will be kept. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 13 +++++++++++++ hw/intc/pnv_xive.c | 40 +++++++++++++++++++++++----------------- 2 files changed, 36 insertions(+), 17 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index fb123edc4e5a..72b5cbb606b5 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -182,6 +182,19 @@ static inline bool pnv_is_power9(PnvMachineState *pnv) return pnv_chip_is_power9(pnv->chips[0]); } =20 +static inline PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) +{ + int i; + + for (i =3D 0; i < pnv->num_chips; i++) { + PnvChip *chip =3D pnv->chips[i]; + if (chip->chip_id =3D=3D chip_id) { + return chip; + } + } + return NULL; +} + #define PNV_FDT_ADDR 0x01000000 #define PNV_TIMEBASE_FREQ 512000000ULL =20 diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 6f53a2abbb6a..e598857359d8 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -464,31 +464,37 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, ui= nt8_t format, return count; } =20 +/* + * The TIMA MMIO space is shared among the chips and to identify the + * chip from which the access is being done, we extract the chip id + * from the PIR. + */ +static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) +{ + PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); + PnvChip *chip; + PnvXive *xive; + + chip =3D pnv_get_chip(pnv, cpu_chip_id(cpu)); + assert(chip); + xive =3D &PNV9_CHIP(chip)->xive; + + if (!pnv_xive_is_cpu_enabled(xive, cpu)) { + xive_error(xive, "IC: CPU %x is not enabled", cpu_pir(cpu)); + } + return xive; +} + static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); - XiveTCTX *tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc); - PnvXive *xive =3D NULL; - CPUPPCState *env =3D &cpu->env; - int pir =3D env->spr_cb[SPR_PIR].default_value; + PnvXive *xive =3D pnv_xive_tm_get_xive(cpu); =20 - /* - * Perform an extra check on the HW thread enablement. - * - * The TIMA is shared among the chips and to identify the chip - * from which the access is being done, we extract the chip id - * from the PIR. - */ - xive =3D pnv_xive_get_ic((pir >> 8) & 0xf); if (!xive) { return NULL; } =20 - if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) { - xive_error(PNV_XIVE(xrtr), "IC: CPU %x is not enabled", pir); - } - - return tctx; + return XIVE_TCTX(pnv_cpu_state(cpu)->intc); } =20 /* --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1564582703; cv=none; d=zoho.com; s=zohoarc; b=VgzN6k309XZR+/wiPSZyXXZiBMDKaOk3cmEoF6wEfTGxxay1WjXfE7YwkOvf/sRajA7oc6rZQ2lMlR4a/HTcFsiSbX8JaRwDEAGXvv1MjxLyq6aCGYqo+vpv5yDF1iwF/Rhr4MtmNEzUcxRRmCcGNqxjPkW8EwobuvavBxS0N7g= ARC-Message-Signature: i=1; a=rsa-sha256; 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Wed, 31 Jul 2019 10:18:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34439) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hspMR-0000Uc-Ne for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hspMP-00026B-Um for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:47 -0400 Received: from 5.mo68.mail-out.ovh.net ([46.105.62.179]:45493) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hspMP-00024i-Oi for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:45 -0400 Received: from player715.ha.ovh.net (unknown [10.108.42.176]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 5F8E013E043 for ; Wed, 31 Jul 2019 16:13:44 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id EB5B3850BAAB; Wed, 31 Jul 2019 14:13:37 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:24 +0200 Message-Id: <20190731141233.1340-10-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11680085637226073062 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.62.179 Subject: [Qemu-devel] [PATCH v3 09/18] ppc/xive: Move the TIMA operations to the controller model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This also removes the need of the get_tctx() XiveRouter handler in the core XIVE framework. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 3 --- hw/intc/pnv_xive.c | 48 ++++++++++++++++++++++++++++++------------- hw/intc/spapr_xive.c | 41 +++++++++++++++++++++++++++--------- hw/intc/xive.c | 36 -------------------------------- 4 files changed, 65 insertions(+), 63 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index ba43a4a129d9..b34e2ad43a82 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -352,7 +352,6 @@ typedef struct XiveRouterClass { XiveNVT *nvt); int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt, uint8_t word_number); - XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs); } XiveRouterClass; =20 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_id= x, @@ -365,7 +364,6 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_b= lk, uint32_t nvt_idx, XiveNVT *nvt); int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_= idx, XiveNVT *nvt, uint8_t word_number); -XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs); void xive_router_notify(XiveNotifier *xn, uint32_t lisn); =20 /* @@ -463,7 +461,6 @@ typedef struct XiveENDSource { #define XIVE_TM_OS_PAGE 0x2 #define XIVE_TM_USER_PAGE 0x3 =20 -extern const MemoryRegionOps xive_tm_ops; void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr off= set, diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index e598857359d8..982f5eef380c 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -485,18 +485,6 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) return xive; } =20 -static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) -{ - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - PnvXive *xive =3D pnv_xive_tm_get_xive(cpu); - - if (!xive) { - return NULL; - } - - return XIVE_TCTX(pnv_cpu_state(cpu)->intc); -} - /* * The internal sources (IPIs) of the interrupt controller have no * knowledge of the XIVE chip on which they reside. Encode the block @@ -1475,6 +1463,39 @@ static const MemoryRegionOps xive_tm_indirect_ops = =3D { }, }; =20 +static void pnv_xive_tm_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); + PnvXive *xive =3D pnv_xive_tm_get_xive(cpu); + XiveTCTX *tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc); + + xive_tctx_tm_write(XIVE_PRESENTER(xive), tctx, offset, value, size); +} + +static uint64_t pnv_xive_tm_read(void *opaque, hwaddr offset, unsigned siz= e) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); + PnvXive *xive =3D pnv_xive_tm_get_xive(cpu); + XiveTCTX *tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc); + + return xive_tctx_tm_read(XIVE_PRESENTER(xive), tctx, offset, size); +} + +const MemoryRegionOps pnv_xive_tm_ops =3D { + .read =3D pnv_xive_tm_read, + .write =3D pnv_xive_tm_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + /* * Interrupt controller XSCOM region. */ @@ -1832,7 +1853,7 @@ static void pnv_xive_realize(DeviceState *dev, Error = **errp) "xive-pc", PNV9_XIVE_PC_SIZE); =20 /* Thread Interrupt Management Area (Direct) */ - memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, + memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &pnv_xive_tm_ops, xive, "xive-tima", PNV9_XIVE_TM_SIZE); =20 qemu_register_reset(pnv_xive_reset, dev); @@ -1888,7 +1909,6 @@ static void pnv_xive_class_init(ObjectClass *klass, v= oid *data) xrc->write_end =3D pnv_xive_write_end; xrc->get_nvt =3D pnv_xive_get_nvt; xrc->write_nvt =3D pnv_xive_write_nvt; - xrc->get_tctx =3D pnv_xive_get_tctx; =20 xnc->notify =3D pnv_xive_notify; xpc->match_nvt =3D pnv_xive_match_nvt; diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index beb5049ad9da..4abb099d341c 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -219,6 +219,35 @@ void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); } =20 +static void spapr_xive_tm_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + XiveTCTX *tctx =3D spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; + + xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); +} + +static uint64_t spapr_xive_tm_read(void *opaque, hwaddr offset, unsigned s= ize) +{ + XiveTCTX *tctx =3D spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; + + return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); +} + +const MemoryRegionOps spapr_xive_tm_ops =3D { + .read =3D spapr_xive_tm_read, + .write =3D spapr_xive_tm_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + static void spapr_xive_end_reset(XiveEND *end) { memset(end, 0, sizeof(*end)); @@ -328,8 +357,8 @@ static void spapr_xive_realize(DeviceState *dev, Error = **errp) qemu_register_reset(spapr_xive_reset, dev); =20 /* TIMA initialization */ - memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, - "xive.tima", 4ull << TM_SHIFT); + memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &spapr_xive_tm_ops, + xive, "xive.tima", 4ull << TM_SHIFT); sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); =20 /* @@ -412,13 +441,6 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint= 8_t nvt_blk, g_assert_not_reached(); } =20 -static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) -{ - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - - return spapr_cpu_state(cpu)->tctx; -} - static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, @@ -546,7 +568,6 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) xrc->write_end =3D spapr_xive_write_end; xrc->get_nvt =3D spapr_xive_get_nvt; xrc->write_nvt =3D spapr_xive_write_nvt; - xrc->get_tctx =3D spapr_xive_get_tctx; =20 xpc->match_nvt =3D spapr_xive_match_nvt; } diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 9ca015969143..6f74b4dcbbd4 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -480,35 +480,6 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTC= TX *tctx, hwaddr offset, return xive_tm_raw_read(tctx, offset, size); } =20 -static void xive_tm_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current_c= pu); - - xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); -} - -static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) -{ - XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current_c= pu); - - return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); -} - -const MemoryRegionOps xive_tm_ops =3D { - .read =3D xive_tm_read, - .write =3D xive_tm_write, - .endianness =3D DEVICE_BIG_ENDIAN, - .valid =3D { - .min_access_size =3D 1, - .max_access_size =3D 8, - }, - .impl =3D { - .min_access_size =3D 1, - .max_access_size =3D 8, - }, -}; - static char *xive_tctx_ring_print(uint8_t *ring) { uint32_t w2 =3D xive_tctx_word2(ring); @@ -1277,13 +1248,6 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t = nvt_blk, uint32_t nvt_idx, return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); } =20 -XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) -{ - XiveRouterClass *xrc =3D XIVE_ROUTER_GET_CLASS(xrtr); - - return xrc->get_tctx(xrtr, cs); -} - /* * Encode the HW CAM line in the block group mode format : * --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1564582644; cv=none; d=zoho.com; s=zohoarc; b=dNmfXAutctPbUqeObqje6NvqIoUwnbI3p6xBga+2LJKvONJaMlDWSTkA+0f3QF1XR1d9RQhpQig7i0skmpY/88ZT+7jidd0p0eIzL39YuMkz/z+QPvnZDu1AJkx6DgpFyJaUYqZRfBm4FQlJAFHSfOS79iNyiFT1Mr6bIU7xRkA= ARC-Message-Signature: i=1; a=rsa-sha256; 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Wed, 31 Jul 2019 10:17:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34487) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hspMW-0000k8-7b for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hspMV-0002BV-4d for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:52 -0400 Received: from 3.mo179.mail-out.ovh.net ([178.33.251.175]:42776) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hspMU-00029q-V4 for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:13:51 -0400 Received: from player715.ha.ovh.net (unknown [10.109.146.240]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id A0FBD1369BB for ; Wed, 31 Jul 2019 16:13:49 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id 442C0850BB19; Wed, 31 Jul 2019 14:13:44 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:25 +0200 Message-Id: <20190731141233.1340-11-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11681493010347166694 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.251.175 Subject: [Qemu-devel] [PATCH v3 10/18] ppc/xive: Introduce a xive_tctx_ipb_update() helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We will use it to resend missed interrupts when a vCPU context is pushed a HW thread. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 1 + hw/intc/xive.c | 15 +++++++++++---- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index b34e2ad43a82..4233773bae11 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -468,6 +468,7 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCT= X *tctx, hwaddr offset, =20 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); +void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb); =20 static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 6f74b4dcbbd4..8f6a29ff1f47 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -132,6 +132,15 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t= ring, uint8_t cppr) xive_tctx_notify(tctx, ring); } =20 +void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) +{ + uint8_t *regs =3D &tctx->regs[ring]; + + regs[TM_IPB] |=3D ipb; + regs[TM_PIPR] =3D ipb_to_pipr(regs[TM_IPB]); + xive_tctx_notify(tctx, ring); +} + static inline uint32_t xive_tctx_word2(uint8_t *ring) { return *((uint32_t *) &ring[TM_WORD2]); @@ -333,8 +342,7 @@ static void xive_tm_set_os_cppr(XivePresenter *xptr, Xi= veTCTX *tctx, static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned= size) { - ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); - xive_tctx_notify(tctx, TM_QW1_OS); + xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff)); } =20 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, @@ -1360,8 +1368,7 @@ static bool xive_presenter_notify(uint8_t format, =20 /* handle CPU exception delivery */ if (count) { - ipb_update(&match.tctx->regs[match.ring], priority); - xive_tctx_notify(match.tctx, match.ring); + xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(prior= ity)); } =20 return count; --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 31 Jul 2019 10:13:57 -0400 Received: from player715.ha.ovh.net (unknown [10.109.143.225]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 160B5189119 for ; Wed, 31 Jul 2019 16:13:55 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id 9F722850BB5D; Wed, 31 Jul 2019 14:13:49 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:26 +0200 Message-Id: <20190731141233.1340-12-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11683181858492746726 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.158.110 Subject: [Qemu-devel] [PATCH v3 11/18] ppc/xive: Synthesize interrupt from the saved IPB in the NVT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When an interrupt can not be presented to a vCPU, the XIVE presenter updates the Interrupt Pending Buffer of the XIVE NVT if backlog is activated in the END. Later, when the same vCPU is dispatched, its context is pushed in the thread context registers and the VO bit is set in the CAM line word to activate the context. The HW grabs the associated NVT to pull the pending bits, and merges them with the IPB of the TIMA. If interrupts were missed while the vCPU was not dispatched, these are synthesized in this sequence. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 5 --- include/hw/ppc/xive_regs.h | 22 +++++++++++++ hw/intc/xive.c | 67 +++++++++++++++++++++++++++++++++----- 3 files changed, 81 insertions(+), 13 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 4233773bae11..e16c3b63fc44 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -470,11 +470,6 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor = *mon); Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb); =20 -static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) -{ - return (nvt_blk << 19) | nvt_idx; -} - /* * KVM XIVE device helpers */ diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 3fdf1a83b9b6..92ff80d25456 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -232,6 +232,7 @@ typedef struct XiveNVT { uint32_t w2; uint32_t w3; uint32_t w4; +#define NVT_W4_IPB PPC_BITMASK32(16, 23) uint32_t w5; uint32_t w6; uint32_t w7; @@ -248,4 +249,25 @@ typedef struct XiveNVT { =20 #define xive_nvt_is_valid(nvt) (be32_to_cpu((nvt)->w0) & NVT_W0_VALID) =20 +/* + * The VP number space in a block is defined by the END_W6_NVT_INDEX + * field of the XIVE END + */ +#define XIVE_NVT_SHIFT 19 + +static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) +{ + return (nvt_blk << XIVE_NVT_SHIFT) | nvt_idx; +} + +static inline uint32_t xive_nvt_idx(uint32_t cam_line) +{ + return cam_line & ((1 << XIVE_NVT_SHIFT) - 1); +} + +static inline uint32_t xive_nvt_blk(uint32_t cam_line) +{ + return (cam_line >> XIVE_NVT_SHIFT) & 0xf; +} + #endif /* PPC_XIVE_REGS_H */ diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 8f6a29ff1f47..9b02ce423d66 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -44,12 +44,6 @@ static uint8_t ipb_to_pipr(uint8_t ibp) return ibp ? clz32((uint32_t)ibp << 24) : 0xff; } =20 -static void ipb_update(uint8_t *regs, uint8_t priority) -{ - regs[TM_IPB] |=3D priority_to_ipb(priority); - regs[TM_PIPR] =3D ipb_to_pipr(regs[TM_IPB]); -} - static uint8_t exception_mask(uint8_t ring) { switch (ring) { @@ -356,6 +350,55 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xpt= r, XiveTCTX *tctx, return qw1w2; } =20 +static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, + uint8_t nvt_blk, uint32_t nvt_idx) +{ + XiveNVT nvt; + uint8_t ipb; + + /* + * Grab the associated NVT to pull the pending bits, and merge + * them with the IPB of the thread interrupt context registers + */ + if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", + nvt_blk, nvt_idx); + return; + } + + ipb =3D xive_get_field32(NVT_W4_IPB, nvt.w4); + + if (ipb) { + /* Reset the NVT value */ + nvt.w4 =3D xive_set_field32(NVT_W4_IPB, nvt.w4, 0); + xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); + + /* Merge in current context */ + xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); + } +} + +/* + * Updating the OS CAM line can trigger a resend of interrupt + */ +static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned si= ze) +{ + uint32_t qw1w2 =3D value; + uint8_t nvt_blk =3D xive_nvt_blk(qw1w2); + uint32_t nvt_idx =3D xive_nvt_idx(qw1w2); + bool vo =3D !!(qw1w2 & TM_QW1W2_VO); + + /* First update the registers */ + qw1w2 =3D cpu_to_be32(qw1w2); + memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); + + /* Check the interrupt pending bits */ + if (vo) { + xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); + } +} + /* * Define a mapping of "special" operations depending on the TIMA page * offset and the size of the operation. @@ -377,6 +420,7 @@ static const XiveTmOp xive_tm_operations[] =3D { * effects */ { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL= }, + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, N= ULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, N= ULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL= }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll= }, @@ -1501,14 +1545,21 @@ static void xive_router_end_notify(XiveRouter *xrtr= , uint8_t end_blk, * - logical server : forward request to IVPE (not supported) */ if (xive_end_is_backlog(&end)) { + uint8_t ipb; + if (format =3D=3D 1) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x invalid config: F1 & backlog\n", end_blk, end_idx); return; } - /* Record the IPB in the associated NVT structure */ - ipb_update((uint8_t *) &nvt.w4, priority); + /* + * Record the IPB in the associated NVT structure for later + * use. The presenter will resend the interrupt when the vCPU + * is dispatched again on a HW thread. + */ + ipb =3D xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(pri= ority); + nvt.w4 =3D xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); =20 /* --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1564582758; cv=none; d=zoho.com; s=zohoarc; b=cEVP/cuCS5VLhksqmA0C3RrLSUhamQyMIqEGSoCboQBloVNlCfvRIPtlJVSsyTYl6qQwdhUM7Pvf+4L99MnUOHAXZnUhmOJMWeCvRFJYE8jGBkZ5ymfoVPLwbn5nNT6b3lAe+mQ/jDzFi08zJptzs+DYc7GBlCYUrdTVpQQYJG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564582758; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=6pGmu6nZUpOX35IYLV6Iti+HOUHVlV4awNtYpeDLptM=; b=gVRV9ym1yd/Hq6iTsnASJvP5l15YOZGWHLNb/eJ16OWZRMRs2CJRGVbBKUfPbHDic9qpiMRgWs2zZDfNP1mVxXCvuR8pbg/MhtxxwgbuNyFtrH/lszMS0js94pWyutFvv6GSOogyWLhrAkrGlaAXPR1JQ739vVKnWrJen8bDIig= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564582758566331.8160799854518; Wed, 31 Jul 2019 07:19:18 -0700 (PDT) Received: from localhost ([::1]:41302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hspRl-000365-Je for importer@patchew.org; Wed, 31 Jul 2019 10:19:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34568) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hspMm-0001Ok-9o for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:14:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hspMg-0002JC-Tp for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:14:08 -0400 Received: from 15.mo7.mail-out.ovh.net ([87.98.180.21]:47351) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hspMg-0002If-N6 for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:14:02 -0400 Received: from player715.ha.ovh.net (unknown [10.108.35.232]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 6133E12BD5B for ; Wed, 31 Jul 2019 16:14:01 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id F0480850BBBE; Wed, 31 Jul 2019 14:13:55 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:27 +0200 Message-Id: <20190731141233.1340-13-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11684870709012040678 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.180.21 Subject: [Qemu-devel] [PATCH v3 12/18] ppc/pnv: Remove pnv_xive_vst_size() routine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" pnv_xive_vst_size() tries to compute the size of a VSD table from the information given by FW. The number of entries of the table are deduced from the result and the MMIO regions of the ESBs and the ENDS are also resized with the computed value. But for indirect tables, the result is incorrect. An indirect table is a one page array of VSDs pointing to subpages containing XIVE virtual structures. The number of first level VSD entries is page aligned and the overall computed size of the table is too large. It can also be completely wrong when the first VSD entry is not yet initialized. Remove pnv_xive_vst_size() and use a simpler form for direct tables. This is only useful when outputting the XIVE sources on the monitor and to resize the ESB MMIO window. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 112 +++++++++++++++++---------------------------- 1 file changed, 43 insertions(+), 69 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 982f5eef380c..aba7a3f83dab 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -121,36 +121,22 @@ static uint64_t pnv_xive_vst_page_size_allowed(uint32= _t page_shift) page_shift =3D=3D 21 || page_shift =3D=3D 24; } =20 -static uint64_t pnv_xive_vst_size(uint64_t vsd) -{ - uint64_t vst_tsize =3D 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); - - /* - * Read the first descriptor to get the page size of the indirect - * table. - */ - if (VSD_INDIRECT & vsd) { - uint32_t nr_pages =3D vst_tsize / XIVE_VSD_SIZE; - uint32_t page_shift; - - vsd =3D ldq_be_dma(&address_space_memory, vsd & VSD_ADDRESS_MASK); - page_shift =3D GETFIELD(VSD_TSIZE, vsd) + 12; - - if (!pnv_xive_vst_page_size_allowed(page_shift)) { - return 0; - } - - return nr_pages * (1ull << page_shift); - } - - return vst_tsize; -} - static uint64_t pnv_xive_vst_addr_direct(PnvXive *xive, uint32_t type, uint64_t vsd, uint32_t idx) { const XiveVstInfo *info =3D &vst_infos[type]; uint64_t vst_addr =3D vsd & VSD_ADDRESS_MASK; + uint64_t vst_tsize =3D 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); + uint32_t idx_max; + + idx_max =3D vst_tsize / info->size - 1; + if (idx > idx_max) { +#ifdef XIVE_DEBUG + xive_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", + info->name, idx, idx_max); +#endif + return 0; + } =20 return vst_addr + idx * info->size; } @@ -213,7 +199,6 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32= _t type, uint8_t blk, { const XiveVstInfo *info =3D &vst_infos[type]; uint64_t vsd; - uint32_t idx_max; =20 if (blk >=3D info->max_blocks) { xive_error(xive, "VST: invalid block id %d for VST %s %d !?", @@ -230,15 +215,6 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint3= 2_t type, uint8_t blk, return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0; } =20 - idx_max =3D pnv_xive_vst_size(vsd) / info->size - 1; - if (idx > idx_max) { -#ifdef XIVE_DEBUG - xive_error(xive, "VST: %s entry %x/%x out of range [ 0 .. %x ] !?", - info->name, blk, idx, idx_max); -#endif - return 0; - } - if (VSD_INDIRECT & vsd) { return pnv_xive_vst_addr_indirect(xive, type, vsd, idx); } @@ -519,19 +495,12 @@ static uint64_t pnv_xive_pc_size(PnvXive *xive) return (~xive->regs[CQ_PC_BARM >> 3] + 1) & CQ_PC_BARM_MASK; } =20 -static uint32_t pnv_xive_nr_ipis(PnvXive *xive) +static uint32_t pnv_xive_nr_ipis(PnvXive *xive, uint8_t blk) { - uint8_t blk =3D xive->chip->chip_id; - - return pnv_xive_vst_size(xive->vsds[VST_TSEL_SBE][blk]) * SBE_PER_BYTE; -} - -static uint32_t pnv_xive_nr_ends(PnvXive *xive) -{ - uint8_t blk =3D xive->chip->chip_id; + uint64_t vsd =3D xive->vsds[VST_TSEL_SBE][blk]; + uint64_t vst_tsize =3D 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); =20 - return pnv_xive_vst_size(xive->vsds[VST_TSEL_EQDT][blk]) - / vst_infos[VST_TSEL_EQDT].size; + return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; } =20 /* @@ -664,6 +633,7 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive, u= int8_t type, XiveSource *xsrc =3D &xive->ipi_source; const XiveVstInfo *info =3D &vst_infos[type]; uint32_t page_shift =3D GETFIELD(VSD_TSIZE, vsd) + 12; + uint64_t vst_tsize =3D 1ull << page_shift; uint64_t vst_addr =3D vsd & VSD_ADDRESS_MASK; =20 /* Basic checks */ @@ -699,11 +669,16 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive,= uint8_t type, =20 case VST_TSEL_EQDT: /* - * Backing store pages for the END. Compute the number of ENDs - * provisioned by FW and resize the END ESB window accordingly. + * Backing store pages for the END. + * + * If the table is direct, we can compute the number of PQ + * entries provisioned by FW (such as skiboot) and resize the + * END ESB window accordingly. */ - memory_region_set_size(&end_xsrc->esb_mmio, pnv_xive_nr_ends(xive)= * - (1ull << (end_xsrc->esb_shift + 1))); + if (!(VSD_INDIRECT & vsd)) { + memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info-= >size) + * (1ull << xsrc->esb_shift)); + } memory_region_add_subregion(&xive->end_edt_mmio, 0, &end_xsrc->esb_mmio); break; @@ -712,11 +687,16 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive,= uint8_t type, /* * Backing store pages for the source PQ bits. The model does * not use these PQ bits backed in RAM because the XiveSource - * model has its own. Compute the number of IRQs provisioned - * by FW and resize the IPI ESB window accordingly. + * model has its own. + * + * If the table is direct, we can compute the number of PQ + * entries provisioned by FW (such as skiboot) and resize the + * ESB window accordingly. */ - memory_region_set_size(&xsrc->esb_mmio, pnv_xive_nr_ipis(xive) * - (1ull << xsrc->esb_shift)); + if (!(VSD_INDIRECT & vsd)) { + memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BY= TE + * (1ull << xsrc->esb_shift)); + } memory_region_add_subregion(&xive->ipi_edt_mmio, 0, &xsrc->esb_mmi= o); break; =20 @@ -1666,8 +1646,7 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *= mon) XiveRouter *xrtr =3D XIVE_ROUTER(xive); uint8_t blk =3D xive->chip->chip_id; uint32_t srcno0 =3D XIVE_SRCNO(blk, 0); - uint32_t nr_ipis =3D pnv_xive_nr_ipis(xive); - uint32_t nr_ends =3D pnv_xive_nr_ends(xive); + uint32_t nr_ipis =3D pnv_xive_nr_ipis(xive, blk); XiveEAS eas; XiveEND end; int i; @@ -1687,21 +1666,16 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor= *mon) } } =20 - monitor_printf(mon, "XIVE[%x] ENDT %08x .. %08x\n", blk, 0, nr_ends - = 1); - for (i =3D 0; i < nr_ends; i++) { - if (xive_router_get_end(xrtr, blk, i, &end)) { - break; - } - xive_end_pic_print_info(&end, i, mon); + monitor_printf(mon, "XIVE[%x] ENDT\n", blk); + i =3D 0; + while (!xive_router_get_end(xrtr, blk, i, &end)) { + xive_end_pic_print_info(&end, i++, mon); } =20 - monitor_printf(mon, "XIVE[%x] END Escalation %08x .. %08x\n", blk, 0, - nr_ends - 1); - for (i =3D 0; i < nr_ends; i++) { - if (xive_router_get_end(xrtr, blk, i, &end)) { - break; - } - xive_end_eas_pic_print_info(&end, i, mon); + monitor_printf(mon, "XIVE[%x] END Escalation EAT\n", blk); + i =3D 0; + while (!xive_router_get_end(xrtr, blk, i, &end)) { + xive_end_eas_pic_print_info(&end, i++, mon); } } =20 --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Wed, 31 Jul 2019 14:14:01 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:28 +0200 Message-Id: <20190731141233.1340-14-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11686559558817319910 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.172.249 Subject: [Qemu-devel] [PATCH v3 13/18] ppc/pnv: Dump the XIVE NVT table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This is to track the configuration of the base END index of the vCPU and the Interrupt Pending Buffer. The NVT IPB is updated when an interrupt can not be presented to a vCPU. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive_regs.h | 2 ++ hw/intc/pnv_xive.c | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 92ff80d25456..b228ab0ba3ea 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -229,6 +229,8 @@ typedef struct XiveNVT { uint32_t w0; #define NVT_W0_VALID PPC_BIT32(0) uint32_t w1; +#define NVT_W1_EQ_BLOCK PPC_BITMASK32(0, 3) +#define NVT_W1_EQ_INDEX PPC_BITMASK32(4, 31) uint32_t w2; uint32_t w3; uint32_t w4; diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index aba7a3f83dab..849291ee683e 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1641,6 +1641,21 @@ static const MemoryRegionOps pnv_xive_pc_ops =3D { }, }; =20 +static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx, + Monitor *mon) +{ + uint8_t eq_blk =3D xive_get_field32(NVT_W1_EQ_BLOCK, nvt->w1); + uint32_t eq_idx =3D xive_get_field32(NVT_W1_EQ_INDEX, nvt->w1); + + if (!xive_nvt_is_valid(nvt)) { + return; + } + + monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n", nvt_idx, + eq_blk, eq_idx, + xive_get_field32(NVT_W4_IPB, nvt->w4)); +} + void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) { XiveRouter *xrtr =3D XIVE_ROUTER(xive); @@ -1649,6 +1664,7 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *= mon) uint32_t nr_ipis =3D pnv_xive_nr_ipis(xive, blk); XiveEAS eas; XiveEND end; + XiveNVT nvt; int i; =20 monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, @@ -1677,6 +1693,12 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor = *mon) while (!xive_router_get_end(xrtr, blk, i, &end)) { xive_end_eas_pic_print_info(&end, i++, mon); } + + monitor_printf(mon, "XIVE[%x] NVTT\n", blk); + i =3D 0; + while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { + xive_nvt_pic_print_info(&nvt, i++, mon); + } } =20 static void pnv_xive_reset(void *dev) --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 31 Jul 2019 10:14:15 -0400 Received: from player715.ha.ovh.net (unknown [10.109.146.50]) by mo6.mail-out.ovh.net (Postfix) with ESMTP id 26EF91D9F1A for ; Wed, 31 Jul 2019 16:14:13 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id C0F3F850BC8B; Wed, 31 Jul 2019 14:14:07 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:29 +0200 Message-Id: <20190731141233.1340-15-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11688248408967384038 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.42.204 Subject: [Qemu-devel] [PATCH v3 14/18] ppc/pnv: Skip empty slots of the XIVE NVT table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We try to loop on the full table skipping empty indirect pages which are not necessarily allocated. This is useful to dump the contexts of the KVM vCPUs. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 849291ee683e..84fbfd8e27b0 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1641,6 +1641,12 @@ static const MemoryRegionOps pnv_xive_pc_ops =3D { }, }; =20 +/* + * skiboot uses an indirect NVT table with 64k subpages + */ +#define XIVE_NVT_COUNT (1 << XIVE_NVT_SHIFT) +#define XIVE_NVT_PER_PAGE (0x10000 / sizeof(XiveNVT)) + static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx, Monitor *mon) { @@ -1694,10 +1700,12 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor= *mon) xive_end_eas_pic_print_info(&end, i++, mon); } =20 - monitor_printf(mon, "XIVE[%x] NVTT\n", blk); - i =3D 0; - while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { - xive_nvt_pic_print_info(&nvt, i++, mon); + monitor_printf(mon, "XIVE[%x] NVTT %08x .. %08x\n", blk, 0, + XIVE_NVT_COUNT - 1); + for (i =3D 0; i < XIVE_NVT_COUNT; i +=3D XIVE_NVT_PER_PAGE) { + while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { + xive_nvt_pic_print_info(&nvt, i++, mon); + } } } =20 --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1564582838; cv=none; d=zoho.com; s=zohoarc; b=U65G1I0d1iIxGusdDgbNkth4RagLbNsEQkHVx0mAjwaig9ysXT6CNhK8wdz8moOY44u2l45/bM2Gcg64qCkV98vmTKjcwr7dA8qnkpYIgCFLfcqTYurCIbCxY9ukeNFJF0oxR346bT3A+jf3zDLlTSv1w5iSQmx/1Sf4/MVkhg0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564582838; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Wed, 31 Jul 2019 10:14:24 -0400 Received: from 9.mo6.mail-out.ovh.net ([87.98.171.146]:57437) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hspN0-0002VU-Ft for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:14:22 -0400 Received: from player715.ha.ovh.net (unknown [10.108.35.119]) by mo6.mail-out.ovh.net (Postfix) with ESMTP id 8B8F31D9F21 for ; Wed, 31 Jul 2019 16:14:19 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id 1F2BE850BCB7; Wed, 31 Jul 2019 14:14:13 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:30 +0200 Message-Id: <20190731141233.1340-16-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11689937259724049382 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.171.146 Subject: [Qemu-devel] [PATCH v3 15/18] ppc/pnv: Introduce a pnv_xive_block_id() helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID field overrides the hardwired chip ID in the Powerbus operations and for CAM compares. This is typically used in the one block-per-chip configuration to associate a unique block id number to each IC of the system. Simplify the model with a pnv_xive_block_id() helper and remove 'tctx_chipid' which becomes useless. The model does support multiple blocks per chip. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv_xive.h | 3 -- hw/intc/pnv_xive.c | 68 ++++++++++++++++++++------------------- 2 files changed, 35 insertions(+), 36 deletions(-) diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h index 4fdaa9247d65..f4c7caad40ee 100644 --- a/include/hw/ppc/pnv_xive.h +++ b/include/hw/ppc/pnv_xive.h @@ -72,9 +72,6 @@ typedef struct PnvXive { /* Interrupt controller registers */ uint64_t regs[0x300]; =20 - /* Can be configured by FW */ - uint32_t tctx_chipid; - /* * Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ * These are in a SRAM protected by ECC. diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 84fbfd8e27b0..6b7078aa4fde 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -83,13 +83,30 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t= word, return (word & ~mask) | ((value << ctz64(mask)) & mask); } =20 +/* + * When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID + * field overrides the hardwired chip ID in the Powerbus operations + * and for CAM compares + */ +static uint8_t pnv_xive_block_id(PnvXive *xive) +{ + uint8_t blk =3D xive->chip->chip_id; + uint64_t cfg_val =3D xive->regs[PC_TCTXT_CFG >> 3]; + + if (cfg_val & PC_TCTXT_CHIPID_OVERRIDE) { + blk =3D GETFIELD(PC_TCTXT_CHIPID, cfg_val); + } + + return blk; +} + /* * Remote access to controllers. HW uses MMIOs. For now, a simple scan * of the chips is good enough. * * TODO: Block scope support */ -static PnvXive *pnv_xive_get_ic(uint8_t blk) +static PnvXive *pnv_xive_get_remote(uint8_t blk) { PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); int i; @@ -98,7 +115,7 @@ static PnvXive *pnv_xive_get_ic(uint8_t blk) Pnv9Chip *chip9 =3D PNV9_CHIP(pnv->chips[i]); PnvXive *xive =3D &chip9->xive; =20 - if (xive->chip->chip_id =3D=3D blk) { + if (pnv_xive_block_id(xive) =3D=3D blk) { return xive; } } @@ -210,7 +227,7 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32= _t type, uint8_t blk, =20 /* Remote VST access */ if (GETFIELD(VSD_MODE, vsd) =3D=3D VSD_MODE_FORWARD) { - xive =3D pnv_xive_get_ic(blk); + xive =3D pnv_xive_get_remote(blk); =20 return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0; } @@ -358,7 +375,10 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t = blk, uint32_t idx, { PnvXive *xive =3D PNV_XIVE(xrtr); =20 - if (pnv_xive_get_ic(blk) !=3D xive) { + /* + * EAT lookups should be local to the IC + */ + if (pnv_xive_block_id(xive) !=3D blk) { xive_error(xive, "VST: EAS %x is remote !?", XIVE_SRCNO(blk, idx)); return -1; } @@ -471,7 +491,7 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno) { PnvXive *xive =3D PNV_XIVE(xn); - uint8_t blk =3D xive->chip->chip_id; + uint8_t blk =3D pnv_xive_block_id(xive); =20 xive_router_notify(xn, XIVE_SRCNO(blk, srcno)); } @@ -835,20 +855,7 @@ static void pnv_xive_ic_reg_write(void *opaque, hwaddr= offset, case PC_TCTXT_CFG: /* * TODO: block group support - * - * PC_TCTXT_CFG_BLKGRP_EN - * PC_TCTXT_CFG_HARD_CHIPID_BLK : - * Moves the chipid into block field for hardwired CAM compares. - * Block offset value is adjusted to 0b0..01 & ThrdId - * - * Will require changes in xive_presenter_tctx_match(). I am - * not sure how to handle that yet. */ - - /* Overrides hardwired chip ID with the chip ID field */ - if (val & PC_TCTXT_CHIPID_OVERRIDE) { - xive->tctx_chipid =3D GETFIELD(PC_TCTXT_CHIPID, val); - } break; case PC_TCTXT_TRACK: /* @@ -1665,7 +1672,8 @@ static void xive_nvt_pic_print_info(XiveNVT *nvt, uin= t32_t nvt_idx, void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) { XiveRouter *xrtr =3D XIVE_ROUTER(xive); - uint8_t blk =3D xive->chip->chip_id; + uint8_t blk =3D pnv_xive_block_id(xive); + uint8_t chip_id =3D xive->chip->chip_id; uint32_t srcno0 =3D XIVE_SRCNO(blk, 0); uint32_t nr_ipis =3D pnv_xive_nr_ipis(xive, blk); XiveEAS eas; @@ -1673,12 +1681,12 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor= *mon) XiveNVT nvt; int i; =20 - monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, - srcno0 + nr_ipis - 1); + monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk, + srcno0, srcno0 + nr_ipis - 1); xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); =20 - monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0, - srcno0 + nr_ipis - 1); + monitor_printf(mon, "XIVE[%x] #%d EAT %08x .. %08x\n", chip_id, blk, + srcno0, srcno0 + nr_ipis - 1); for (i =3D 0; i < nr_ipis; i++) { if (xive_router_get_eas(xrtr, blk, i, &eas)) { break; @@ -1688,20 +1696,20 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor= *mon) } } =20 - monitor_printf(mon, "XIVE[%x] ENDT\n", blk); + monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); i =3D 0; while (!xive_router_get_end(xrtr, blk, i, &end)) { xive_end_pic_print_info(&end, i++, mon); } =20 - monitor_printf(mon, "XIVE[%x] END Escalation EAT\n", blk); + monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); i =3D 0; while (!xive_router_get_end(xrtr, blk, i, &end)) { xive_end_eas_pic_print_info(&end, i++, mon); } =20 - monitor_printf(mon, "XIVE[%x] NVTT %08x .. %08x\n", blk, 0, - XIVE_NVT_COUNT - 1); + monitor_printf(mon, "XIVE[%x] #%d NVTT %08x .. %08x\n", chip_id, blk, + 0, XIVE_NVT_COUNT - 1); for (i =3D 0; i < XIVE_NVT_COUNT; i +=3D XIVE_NVT_PER_PAGE) { while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { xive_nvt_pic_print_info(&nvt, i++, mon); @@ -1715,12 +1723,6 @@ static void pnv_xive_reset(void *dev) XiveSource *xsrc =3D &xive->ipi_source; XiveENDSource *end_xsrc =3D &xive->end_source; =20 - /* - * Use the PnvChip id to identify the XIVE interrupt controller. - * It can be overriden by configuration at runtime. - */ - xive->tctx_chipid =3D xive->chip->chip_id; - /* Default page size (Should be changed at runtime to 64k) */ xive->ic_shift =3D xive->vc_shift =3D xive->pc_shift =3D 12; =20 --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Wed, 31 Jul 2019 14:14:19 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:31 +0200 Message-Id: <20190731141233.1340-17-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11691344633080220646 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.57.129 Subject: [Qemu-devel] [PATCH v3 16/18] ppc/pnv: Extend XivePresenter with a get_block_id() handler X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When doing CAM line compares, fetch the block id from the interrupt controller which can have set the PC_TCTXT_CHIPID field. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 1 + hw/intc/pnv_xive.c | 6 ++++++ hw/intc/spapr_xive.c | 6 ++++++ hw/intc/xive.c | 8 +++++--- 4 files changed, 18 insertions(+), 3 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index e16c3b63fc44..d68fb6eea46e 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -391,6 +391,7 @@ typedef struct XivePresenterClass { uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, uint32_t logic_serv, XiveTCTXMatch *match); + uint8_t (*get_block_id)(XivePresenter *xptr); } XivePresenterClass; =20 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 6b7078aa4fde..8e3ba23788f7 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -460,6 +460,11 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uin= t8_t format, return count; } =20 +static uint8_t pnv_xive_get_block_id(XivePresenter *xptr) +{ + return pnv_xive_block_id(PNV_XIVE(xptr)); +} + /* * The TIMA MMIO space is shared among the chips and to identify the * chip from which the access is being done, we extract the chip id @@ -1918,6 +1923,7 @@ static void pnv_xive_class_init(ObjectClass *klass, v= oid *data) =20 xnc->notify =3D pnv_xive_notify; xpc->match_nvt =3D pnv_xive_match_nvt; + xpc->get_block_id =3D pnv_xive_get_block_id; }; =20 static const TypeInfo pnv_xive_info =3D { diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 4abb099d341c..26fc815d3931 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -479,6 +479,11 @@ static int spapr_xive_match_nvt(XivePresenter *xptr, u= int8_t format, return count; } =20 +static uint8_t spapr_xive_get_block_id(XivePresenter *xrtr) +{ + return SPAPR_XIVE_BLOCK_ID; +} + static const VMStateDescription vmstate_spapr_xive_end =3D { .name =3D TYPE_SPAPR_XIVE "/end", .version_id =3D 1, @@ -570,6 +575,7 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) xrc->write_nvt =3D spapr_xive_write_nvt; =20 xpc->match_nvt =3D spapr_xive_match_nvt; + xpc->get_block_id =3D spapr_xive_get_block_id; } =20 static const TypeInfo spapr_xive_info =3D { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 9b02ce423d66..e79439f6b940 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1305,12 +1305,14 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t= nvt_blk, uint32_t nvt_idx, * * chip << 19 | 0000000 0 0001 thread (7Bit) */ -static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) +static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) { CPUPPCState *env =3D &POWERPC_CPU(tctx->cs)->env; uint32_t pir =3D env->spr_cb[SPR_PIR].default_value; + XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); + uint8_t blk =3D xpc->get_block_id(xptr); =20 - return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f)); + return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); } =20 /* @@ -1347,7 +1349,7 @@ int xive_presenter_tctx_match(XivePresenter *xptr, Xi= veTCTX *tctx, =20 /* PHYS ring */ if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && - cam =3D=3D xive_tctx_hw_cam_line(tctx)) { + cam =3D=3D xive_tctx_hw_cam_line(xptr, tctx)) { return TM_QW3_HV_PHYS; } =20 --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1564582803; cv=none; d=zoho.com; s=zohoarc; b=kYURHPAMKoL1trOBEO+L/hYCW2yl2F0myZD//FLlHZfK04CBLzRrLiIVJNY4ssH0kBEgtLiOS6OGEn0KN9ybb4MNdxTLuj1/78D/5TlSqKgIEevRqFIqQ2lPtbqZFwuBGa6ik2Tv8AC3euUb7iB4oGR4MtMP0323hMwOpFs47c8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564582803; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Wed, 31 Jul 2019 10:14:33 -0400 Received: from 1.mo173.mail-out.ovh.net ([178.33.111.180]:36801) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hspNA-0002cM-Cs for qemu-devel@nongnu.org; Wed, 31 Jul 2019 10:14:32 -0400 Received: from player715.ha.ovh.net (unknown [10.109.160.226]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 7C7D2114B32 for ; Wed, 31 Jul 2019 16:14:31 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id E2A38850BD9D; Wed, 31 Jul 2019 14:14:24 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:32 +0200 Message-Id: <20190731141233.1340-18-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11693314960186969062 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.111.180 Subject: [Qemu-devel] [PATCH v3 17/18] ppc/pnv: Quiesce some XIVE errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When dumping the END and NVT tables, the error logging is too noisy. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 8e3ba23788f7..df0b17772c0d 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -27,7 +27,7 @@ =20 #include "pnv_xive_regs.h" =20 -#define XIVE_DEBUG +#undef XIVE_DEBUG =20 /* * Virtual structures table (VST) @@ -172,7 +172,9 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xiv= e, uint32_t type, vsd =3D ldq_be_dma(&address_space_memory, vsd_addr); =20 if (!(vsd & VSD_ADDRESS_MASK)) { +#ifdef XIVE_DEBUG xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); +#endif return 0; } =20 @@ -193,7 +195,9 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xiv= e, uint32_t type, vsd =3D ldq_be_dma(&address_space_memory, vsd_addr); =20 if (!(vsd & VSD_ADDRESS_MASK)) { +#ifdef XIVE_DEBUG xive_error(xive, "VST: invalid %s entry %x !?", info->name, id= x); +#endif return 0; } =20 --=20 2.21.0 From nobody Wed May 1 06:11:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 31 Jul 2019 10:14:41 -0400 Received: from player715.ha.ovh.net (unknown [10.109.143.201]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id EF3A612C4A6 for ; Wed, 31 Jul 2019 16:14:36 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id 8646F850BE2D; Wed, 31 Jul 2019 14:14:31 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 31 Jul 2019 16:12:33 +0200 Message-Id: <20190731141233.1340-19-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190731141233.1340-1-clg@kaod.org> References: <20190731141233.1340-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11694722335611194342 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrleehgdejvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.251.19 Subject: [Qemu-devel] [PATCH v3 18/18] ppc/xive: Introduce a xive_os_cam_decode() helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The OS CAM line has a special encoding exploited by the HW. Provide a helper routine to hide the details to the TIMA command handlers. This also clarifies the endianness of different variables : 'qw1w2' is big-endian and 'cam' is native. Also add a check on the V bit in the TM_PULL_POOL_CTX special operation. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 40 +++++++++++++++++++++++++++++++--------- 1 file changed, 31 insertions(+), 9 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index e79439f6b940..bdc36f2a1b0b 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -339,14 +339,34 @@ static void xive_tm_set_os_pending(XivePresenter *xpt= r, XiveTCTX *tctx, xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff)); } =20 +static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, + uint32_t *nvt_idx, bool *vo) +{ + *nvt_blk =3D xive_nvt_blk(cam); + *nvt_idx =3D xive_nvt_idx(cam); + *vo =3D !!(cam & TM_QW1W2_VO); +} + static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size) { - uint32_t qw1w2_prev =3D xive_tctx_word2(&tctx->regs[TM_QW1_OS]); - uint32_t qw1w2; + uint32_t qw1w2 =3D xive_tctx_word2(&tctx->regs[TM_QW1_OS]); + uint32_t qw1w2_new; + uint32_t cam =3D be32_to_cpu(qw1w2); + uint8_t nvt_blk; + uint32_t nvt_idx; + bool vo; =20 - qw1w2 =3D xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0); - memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); + xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); + + if (!vo) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?= \n", + nvt_blk, nvt_idx); + } + + /* Invalidate CAM line */ + qw1w2_new =3D xive_set_field32(TM_QW1W2_VO, qw1w2, 0); + memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4); return qw1w2; } =20 @@ -384,13 +404,15 @@ static void xive_tctx_need_resend(XiveRouter *xrtr, X= iveTCTX *tctx, static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned si= ze) { - uint32_t qw1w2 =3D value; - uint8_t nvt_blk =3D xive_nvt_blk(qw1w2); - uint32_t nvt_idx =3D xive_nvt_idx(qw1w2); - bool vo =3D !!(qw1w2 & TM_QW1W2_VO); + uint32_t cam =3D value; + uint32_t qw1w2 =3D cpu_to_be32(cam); + uint8_t nvt_blk; + uint32_t nvt_idx; + bool vo; + + xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); =20 /* First update the registers */ - qw1w2 =3D cpu_to_be32(qw1w2); memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); =20 /* Check the interrupt pending bits */ --=20 2.21.0