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[97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.44 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4eSnwGdItsZZfZWQU9TzlBCuQSBa1+CtKc/8GLA6ttg=; b=BmS4hBPw5lamyrdx8TR9pA8Xo3AbD7c675p6vfH2K29pKeZEf644NVNaGlC35Y9KRG MIwbFQ4dcVm+HaOohT7lc+lQbLY5VLvi+gbJkbze1MeQC7wMdJDmUG981IDBq0LoESIH Bp2IJrbxlAS5acxpInOfBdWkPsG3ZBym/YlsZyylEEEdROFQPG1YADzjjehDY85MEZQg i+JJCAx2TeJjmo0EoSc7QpfGuqOWgevoMhYyofSVNNKUhG/imB7yW4uh+2PX50RgyyzF aGgNKOyG6gkSYOxpS2zghT4RKn4vp8quINMAhExSVY42ktK5purh4GHz23ki7fGX3xci 3gdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4eSnwGdItsZZfZWQU9TzlBCuQSBa1+CtKc/8GLA6ttg=; b=fvPxPvu6yvBEw39A8dRugDEkfDVC3W3oRTgr/5ijvOpRuTXI6DIFQaAVJG9QTzRR+S 0ujfLadluR+3srkBF9dSJRujGtXU9a61ippkWav4+FBGA/RDS82zp61eCMJ0bxuTSZ/5 6be5j5TBjvkpwPhgKQ/eckVFn2BPerESOWDH0PX7FDpA3c3B6aT8N0tPzTRmkjdFGDCQ c5xbkr9i3KAcMnQ3e23npomGFiFiqYBWKjsV0qnxJKJyRAsGG3Cg7pMs0XIRadM9pLSF dtJQWFNVlPB+1zSL7ohYxRwtrFtz1GfJZDbgOMnZda03OgzSenaBveyb+AxxUneROixu fINg== X-Gm-Message-State: APjAAAWuWx+0G3fjpbIiHjs0WNERioOKgTbPw+MlFadYpWLKVU2tNloW MY6DyrtHS0auLuI7wNUzh3Flyh4I0+M= X-Google-Smtp-Source: APXvYqxX3s64lb+yzIdUNn6NhNULtHyEBclez/Fat/0aX136jAcW4sBuVvFZIILJOGuXIK8OvU4ANQ== X-Received: by 2002:a63:e54:: with SMTP id 20mr90473834pgo.244.1564163505827; Fri, 26 Jul 2019 10:51:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:25 -0700 Message-Id: <20190726175032.6769-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PATCH 60/67] target/arm: Convert T16, Miscellaneous 16-bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 111 ++++++++++++----------------------------- target/arm/t16.decode | 31 ++++++++---- 2 files changed, 54 insertions(+), 88 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 97c472c8f7..f3a946d8c9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10104,6 +10104,18 @@ static bool trans_TBH(DisasContext *s, arg_tbranch= *a) return op_tbranch(s, a, true); } =20 +static bool trans_CBZ(DisasContext *s, arg_CBZ *a) +{ + TCGv_i32 tmp =3D load_reg(s, a->rn); + + arm_gen_condlabel(s); + tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE, + tmp, 0, s->condlabel); + tcg_temp_free_i32(tmp); + gen_jmp(s, s->pc_read + a->imm); + return true; +} + /* * Supervisor call */ @@ -10325,6 +10337,25 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a) return ENABLE_ARCH_7; } =20 +/* + * If-then + */ + +static bool trans_IT(DisasContext *s, arg_IT *a) +{ + /* + * No actual code generated for this insn, just setup state. + * + * Combinations of firstcond and mask which set up an 0b1111 + * condition are UNPREDICTABLE; we take the CONSTRAINED + * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, + * i.e. both meaning "execute always". + */ + s->condexec_cond =3D a->cond; + s->condexec_mask =3D a->imm; + return true; +} + /* * Legacy decoder. */ @@ -10688,85 +10719,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ case 10: /* add PC/SP (immediate), in decodetree */ + case 11: /* misc, in decodetree */ case 12: /* load/store multiple, in decodetree */ - goto illegal_op; - - case 11: - /* misc */ - op =3D (insn >> 8) & 0xf; - switch (op) { - case 0: /* add/sub (sp, immediate), in decodetree */ - case 2: /* sign/zero extend, in decodetree */ - goto illegal_op; - - case 4: case 5: case 0xc: case 0xd: - /* push/pop, in decodetree */ - goto illegal_op; - - case 1: case 3: case 9: case 11: /* czb */ - rm =3D insn & 7; - tmp =3D load_reg(s, rm); - arm_gen_condlabel(s); - if (insn & (1 << 11)) - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel); - else - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel); - tcg_temp_free_i32(tmp); - offset =3D ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3; - val =3D s->pc_read; - val +=3D offset; - gen_jmp(s, val); - break; - - case 15: /* IT, nop-hint. */ - if ((insn & 0xf) =3D=3D 0) { - goto illegal_op; /* nop hint, in decodetree */ - } - /* - * IT (If-Then) - * - * Combinations of firstcond and mask which set up an 0b1111 - * condition are UNPREDICTABLE; we take the CONSTRAINED - * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, - * i.e. both meaning "execute always". - */ - s->condexec_cond =3D (insn >> 4) & 0xe; - s->condexec_mask =3D insn & 0x1f; - /* No actual code generated for this insn, just setup state. = */ - break; - - case 0xe: /* bkpt */ - { - int imm8 =3D extract32(insn, 0, 8); - ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true)); - break; - } - - case 0xa: /* rev, and hlt */ - { - int op1 =3D extract32(insn, 6, 2); - - if (op1 =3D=3D 2) { - /* HLT */ - int imm6 =3D extract32(insn, 0, 6); - - gen_hlt(s, imm6); - break; - } - - /* Otherwise this is rev, in decodetree */ - goto illegal_op; - } - - case 6: /* setend, cps; in decodetree */ - goto illegal_op; - - default: - goto undef; - } - break; - case 13: /* conditional branch or swi, in decodetree */ goto illegal_op; =20 @@ -10822,7 +10776,6 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) } return; illegal_op: -undef: gen_illegal_op(s); } =20 diff --git a/target/arm/t16.decode b/target/arm/t16.decode index f4091c812d..17297a3032 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -210,20 +210,33 @@ REVSH 1011 1010 11 ... ... @rdm =20 # Hints =20 +%it_cond 5:3 !function=3Dtimes_2 + { - YIELD 1011 1111 0001 0000 - WFE 1011 1111 0010 0000 - WFI 1011 1111 0011 0000 + { + YIELD 1011 1111 0001 0000 + WFE 1011 1111 0010 0000 + WFI 1011 1111 0011 0000 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1011 1111 0100 0000 - # SEVL 1011 1111 0101 0000 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1011 1111 0100 0000 + # SEVL 1011 1111 0101 0000 =20 - # The canonical nop has the second nibble as 0000, but the whole of the - # rest of the space is a reserved hint, behaves as nop. - NOP 1011 1111 ---- 0000 + # The canonical nop has the second nibble as 0000, but the whole of the + # rest of the space is a reserved hint, behaves as nop. + NOP 1011 1111 ---- 0000 + } + IT 1011 1111 ... imm:5 &ci cond=3D%it_cond } =20 +# Miscellaneous 16-bit instructions + +%imm6_9_3 9:1 3:5 !function=3Dtimes_2 + +HLT 1011 1010 10 imm:6 &i +BKPT 1011 1110 imm:8 &i +CBZ 1011 nz:1 0.1 ..... rn:3 imm=3D%imm6_9_3 + # Push and Pop =20 %push_list 0:9 !function=3Dt16_push_list --=20 2.17.1