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[97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.50 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oJFhsjTpA90uLnkSb8PliACzOJvjF9fpzncu9tcD1hw=; b=aWUgNkmdWXEo6kR8q9PDUyX+wB7jKa/AFdJ6Jys42PvIqwzqopjF/6h/6ieaYqWvPv bmS1gdB5b93+PUfkw0nJgufPFpswf78rQdYN9LIvGkoAdmj+miV5T/IL/RofwvNzG1mq TBUX9h3WqEy6u9bcZZuKKmTj+17EmcuRn9f+3DqOo4ehAxSN03XEF2XU/AtEE8Mai4k+ 7n8TOPiHRtNuEWVnqcumd1oKgu2ISQ0OBpQba//8e3Hu8SuRnum7CLgbqZm2cpvzKuJY BUCu/4Fgdb5zcTH8BfxbXOv8926Gaw6SlnUIJa98zBOu7OTGOOCkvc65+GkvYPrlBAqF OOZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oJFhsjTpA90uLnkSb8PliACzOJvjF9fpzncu9tcD1hw=; b=AvoEht9Vqntz2+A6ZYoZ4+G/Y9dlzeRLKZHSOvTaHTwSvXqXFpatNvRRaHbcr8CyO+ Q0AYEGt7ulesUC1WzrYvZlxxAbTm/lfJV5bKl3BCXi1kebNMw1Ys5WvnWjdSf2wR7Ln3 09ogLQReBNVuVcpKh/cQcKrhX8aY9D2umZ2i2PJALU8D6sByXZUmTGz/+8QFaErw/WxS pU1qZ+EsOfgf7iMmsDBl5wNrA/vN3gdqA8KeXDwENd89NB4nAM9tnfjPY2h6Ao3XUzmK jaRPEnTuTs9DBqwZ+/sTuPt16GJlsBjPZyhrNI53FeNnhcesCfeDCd/hGcaU8DVbtC1x Axrw== X-Gm-Message-State: APjAAAVWgelOjOC7gZerAmE0glVfek1QRAofbGbt8O2rJMPD3HKwj/72 xVxh4H9xPvYFhB8+I0YUcjEFaCNFf28= X-Google-Smtp-Source: APXvYqwJzYMvqv4bmdcamzzmdTgWeG6TVMBHmDX5h5qRMb6yDbO5i8S4ee4+siw9TboP4O5IobLzcQ== X-Received: by 2002:a17:90a:2023:: with SMTP id n32mr95173627pjc.3.1564163451357; Fri, 26 Jul 2019 10:50:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:40 -0700 Message-Id: <20190726175032.6769-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52d Subject: [Qemu-devel] [PATCH 15/67] target/arm: Convert Saturating addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper.h | 1 - target/arm/op_helper.c | 15 --------- target/arm/translate.c | 74 +++++++++++++++++++++++++++--------------- target/arm/a32.decode | 10 ++++++ target/arm/t32.decode | 9 +++++ 5 files changed, 66 insertions(+), 43 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 132aa1682e..1fb2cb5a77 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -6,7 +6,6 @@ DEF_HELPER_3(add_saturate, i32, env, i32, i32) DEF_HELPER_3(sub_saturate, i32, env, i32, i32) DEF_HELPER_3(add_usaturate, i32, env, i32, i32) DEF_HELPER_3(sub_usaturate, i32, env, i32, i32) -DEF_HELPER_2(double_saturate, i32, env, s32) DEF_HELPER_FLAGS_2(sdiv, TCG_CALL_NO_RWG_SE, s32, s32, s32) DEF_HELPER_FLAGS_2(udiv, TCG_CALL_NO_RWG_SE, i32, i32, i32) DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 1ab91f915e..142239b03a 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -135,21 +135,6 @@ uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32= _t a, uint32_t b) return res; } =20 -uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val) -{ - uint32_t res; - if (val >=3D 0x40000000) { - res =3D ~SIGNBIT; - env->QF =3D 1; - } else if (val <=3D (int32_t)0xc0000000) { - res =3D SIGNBIT; - env->QF =3D 1; - } else { - res =3D val << 1; - } - return res; -} - uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b) { uint32_t res =3D a + b; diff --git a/target/arm/translate.c b/target/arm/translate.c index 354a52d36c..85f829c1bb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8174,6 +8174,47 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *= a) return true; } =20 +/* + * Saturating addition and subtraction + */ + +static bool op_qaddsub(DisasContext *s, arg_rrr *a, bool add, bool doub) +{ + TCGv_i32 t0, t1; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_5TE) { + return false; + } + + t0 =3D load_reg(s, a->rm); + t1 =3D load_reg(s, a->rn); + if (doub) { + gen_helper_add_saturate(t1, cpu_env, t1, t1); + } + if (add) { + gen_helper_add_saturate(t0, cpu_env, t0, t1); + } else { + gen_helper_sub_saturate(t0, cpu_env, t0, t1); + } + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +#define DO_QADDSUB(NAME, ADD, DOUB) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_qaddsub(s, a, ADD, DOUB); \ +} + +DO_QADDSUB(QADD, true, false) +DO_QADDSUB(QSUB, false, false) +DO_QADDSUB(QDADD, true, true) +DO_QADDSUB(QDSUB, false, true) + +#undef DO_QADDSUB =20 /* * Legacy decoder. @@ -8582,21 +8623,10 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) store_reg(s, rd, tmp); break; } - case 0x5: /* saturating add/subtract */ - ARCH(5TE); - rd =3D (insn >> 12) & 0xf; - rn =3D (insn >> 16) & 0xf; - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rn); - if (op1 & 2) - gen_helper_double_saturate(tmp2, cpu_env, tmp2); - if (op1 & 1) - gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2); - else - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + case 0x5: + /* Saturating addition and subtraction. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0x6: /* ERET */ if (op1 !=3D 3) { goto illegal_op; @@ -10070,18 +10100,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) op =3D ((insn >> 17) & 0x38) | ((insn >> 4) & 7); if (op < 4) { /* Saturating add/subtract. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - if (op & 1) - gen_helper_double_saturate(tmp, cpu_env, tmp); - if (op & 2) - gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp); - else - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { switch (op) { case 0x0a: /* rbit */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 71846b79fd..af6712a9e8 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -27,6 +27,7 @@ &s_rri_rot s rn rd imm rot &s_rrrr s rd rn rm ra &rrrr rd rn rm ra +&rrr rd rn rm =20 # Data-processing (register) =20 @@ -122,3 +123,12 @@ UMULL .... 0000 100 . .... .... .... 1001 .= ... @s_rdamn UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn + +# Saturating addition and subtraction + +@rndm ---- .... .... rn:4 rd:4 .... .... rm:4 &rrr + +QADD .... 0001 0000 .... .... 0000 0101 .... @rndm +QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm +QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm +QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 8e301ed2a1..7a27b5cc5c 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra +&rrr !extern rd rn rm =20 # Data-processing (register-shifted register) =20 @@ -117,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ......= .. @s_rri_rot @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 @s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra= =3D0 s=3D0 @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr +@rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr =20 { MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm @@ -128,3 +130,10 @@ UMULL 1111 1011 1010 .... .... .... 0000 ..= .. @s0_rnadm SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm + +# Data-processing (two source registers) + +QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm +QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm +QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm +QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm --=20 2.17.1