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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 59BBC1FF87; Tue, 23 Jul 2019 12:33:05 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=DWbDWaYfcxmkGXUdUBX0lMq0CUBdZuPA0MBGgprVLng=; b=WRleVK1KsOtUXGCyav3mR2h3r66Z4gFEHcejcl+/2OUqs1FPk9J5bfo+829yTQktuf vJfxYnJOwZb3cJ4S7nRuBbXndljS+eoHAjoGY1VehSauOmAiMzv55PxpxMkuTcXlpy0C cnpDUN9wXsQBdX0HLy2Q8mzwPfe1Yl8pGGauSRgRYQDoW8hlnOiBTsGJgIR27ERH8GNq JPfFpTJ3CiaLE0mjxgafi4WfPRnDqIOco+S7XOqERcH6IvAhwBnm3qLZMgVLCP73VOBt YacWIqIZsE+Df/rovuOexV5Xahxx1H7TmOpAJzu8hrMzc6iqNmoHWM1pQvUEPElf27jI tlUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=DWbDWaYfcxmkGXUdUBX0lMq0CUBdZuPA0MBGgprVLng=; b=auq0Jtbxmlroitp8ip+IOM11gj+Qi7z3h3uBOlAgXHKSfF02v7MQK7JrbvNxKLh3CO zbyxuJaTaPm0EPXbDq9MnwSk3IRj08bqyHlH5mq21FV4jKzgfs2uKq2R0Ob5SKR1LbEH M3Ysx6d0Kgzp634D1zpWwDKzO+42bA+4MeRCp6gLScL47Hkjt7d72ZPe7a6ufJvZpvX9 zRXaSJGtl6GmiibEp7ulp8+dTxAXZbClKnqIZ5jtqlsLkiErGJsUWbCDtCAXdbzBSDA+ TNO+cc4rSLSu31MNjZnQFkuvoSJpEuy9Mc6Wk88yAkuqxdJ2KKHh6Jypfmg6n3BxF4df 9Kpw== X-Gm-Message-State: APjAAAXym/ElJ7Wi9ZzkDi6CaoU3tRvrgdTGA9CgkhL/BvpVPHkz2ZAE 8tpJbbh/DcHb0c+ML2EBj+aUUQ== X-Google-Smtp-Source: APXvYqzddgK9tKugmZgAQoJeSHRWFw3WocoNVqCU4voI2N6j60LoeacRcB8VbAYm7qg+05KPghNXXA== X-Received: by 2002:adf:ab51:: with SMTP id r17mr54329617wrc.95.1563881586322; Tue, 23 Jul 2019 04:33:06 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 23 Jul 2019 12:33:01 +0100 Message-Id: <20190723113301.16867-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH for 4.2] target/arm: generate a custom MIDR for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) While most features are now detected by probing the ID_* registers kernels can (and do) use MIDR_EL1 for working out of they have to apply errata. This can trip up warnings in the kernel as it tries to work out if it should apply workarounds to features that don't actually exist in the reported CPU type. Avoid this problem by synthesising our own MIDR value using the reserved value of 0 for the implementer and telling kernels the ID registers should tell them everything they need to know. Signed-off-by: Alex Benn=C3=A9e --- v2 - don't leak QEMU version into ID reg --- target/arm/cpu.h | 6 ++++++ target/arm/cpu64.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7efbb488d9d..61eaef924e4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1605,6 +1605,12 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1) /* * System register ID fields. */ +FIELD(MIDR_EL1, REVISION, 0, 4) +FIELD(MIDR_EL1, PARTNUM, 4, 12) +FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) +FIELD(MIDR_EL1, VARIENT, 20, 4) +FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) + FIELD(ID_ISAR0, SWAP, 0, 4) FIELD(ID_ISAR0, BITCOUNT, 4, 4) FIELD(ID_ISAR0, BITFIELD, 8, 4) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index b1bb394c6dd..e88aadfd2fd 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -296,6 +296,12 @@ static void aarch64_max_initfn(Object *obj) uint32_t u; aarch64_a57_initfn(obj); =20 + /* reset MIDR so our franken-max-cpu type isn't mistaken for a rea= l one */ + t =3D FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); /* Reserved for SW = */ + t =3D FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); /* See ID_* for = details */ + /* the rest is enigmatically empty lest kernels assume it means so= mething */ + cpu->midr =3D t; + t =3D cpu->isar.id_aa64isar0; t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); --=20 2.20.1