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[97.126.117.207]) by smtp.gmail.com with ESMTPSA id i6sm32724751pgi.40.2019.07.19.14.03.51 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 19 Jul 2019 14:03:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u+zufnM9gRgzS4x3zT5MZp9Zbq0icAPgD/z46c/Vn/8=; b=EBVQdbb40qsdrjb1HYN0dW6Lmr0OYmWD72rwDfyQNsyz+PyS+xC6/EpOoV1PtvqEAf Lz9r5xH/zAkYVfzlVhns96lY0X7y+wGakxMP07jJPDbbBFlmFp0h1UmEb/dYu/oAE8Sj JzKg9n1UwD6/EUfNv+w5FdcS2xEMUxMrI+caP4qyFroemVfpwg7ixoHTn0COZ2mzI6AF PNRJbRe2sQUdsAG76Zw563yoskDt3xbfMUUeGugF3JHnjmO3Oq1CmAV9oumnfLjlWRwY 8UTucg21wUX9oWu0MJZv1nZcfat5xTnSv81y2hK8s2zQ22iC6RPGDO12wX8qbjsNp3x6 JHXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u+zufnM9gRgzS4x3zT5MZp9Zbq0icAPgD/z46c/Vn/8=; b=pd+VQ9kf1oAh42O8sObhMfXDz6+gDZarQLUQMKqe+MOcpvdM0hDI6B3WGWKRAV0Lb8 K8LRacm/6k22MlTdYINUWmX55NncD3apK+genAb5XC4Ynkuhj+UDS1oGZAzDB/X1oVae TZEDNlVM7kC2SL0jv3GxouyAX0uUW7pdEG7qS6aHJDlHc+pDZqbw/Zq9ZtKql9ttq2xE /tRMCF3foxOgUR46S3FDgFg2IS7gEE8s9X6LyBXZGlBEpF31OJDC8nANaZ+B2AwlvUjt vjyKSd/PuDPLj27eSz6qr/N0pB8z+IQml9KaM6TC9jBItPYiTOKQXOMZd03w3uZYxrmv 0oCQ== X-Gm-Message-State: APjAAAXJnqt9POyt0c5O1x/fJdKkZTCfHPEEl5ODHDnkFvs8LjHroI56 KdV+uGoVXrhJG2w/S+YfgFUY2Vdn1ks= X-Google-Smtp-Source: APXvYqx0pUvSlgCRT4udLbBs/ItH2yelyuwQ4tybmUhkNj2Xwls1fD1Nm+Lp9BXK/JPe7qL1/tVTMA== X-Received: by 2002:a17:902:9041:: with SMTP id w1mr60290622plz.132.1563570232442; Fri, 19 Jul 2019 14:03:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 19 Jul 2019 14:03:22 -0700 Message-Id: <20190719210326.15466-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190719210326.15466-1-richard.henderson@linaro.org> References: <20190719210326.15466-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH for-4.2 20/24] target/arm: Flush tlbs for E2&0 translation regime X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, beata.michalska@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 22eb056b27..fe022f51d6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3915,8 +3915,11 @@ static CPAccessResult aa64_cacheop_access(CPUARMStat= e *env, =20 static int vae1_tlbmask(CPUARMState *env) { + /* Since we exclude secure first, we may read HCR_EL2 directly. */ if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; + } else if (env->cp15.hcr_el2 & HCR_E2H) { + return ARMMMUIdxBit_E2 | ARMMMUIdxBit_E0; } else { return ARMMMUIdxBit_E1 | ARMMMUIdxBit_E0; } @@ -3954,7 +3957,12 @@ static int vmalle1_tlbmask(CPUARMState *env) if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { - return ARMMMUIdxBit_E1 | ARMMMUIdxBit_E0 | ARMMMUIdxBit_Stage2; + /* Since we exclude secure first, we may read HCR_EL2 directly. */ + if (env->cp15.hcr_el2 & HCR_E2H) { + return ARMMMUIdxBit_E2 | ARMMMUIdxBit_E0; + } else { + return ARMMMUIdxBit_E1 | ARMMMUIdxBit_E0 | ARMMMUIdxBit_Stage2; + } } else { return ARMMMUIdxBit_E1 | ARMMMUIdxBit_E0; } @@ -3969,13 +3977,22 @@ static void tlbi_aa64_alle1_write(CPUARMState *env,= const ARMCPRegInfo *ri, tlb_flush_by_mmuidx(cs, mask); } =20 +static int vae2_tlbmask(CPUARMState *env) +{ + if (arm_hcr_el2_eff(env) & HCR_E2H) { + return ARMMMUIdxBit_E0 | ARMMMUIdxBit_E2; + } else { + return ARMMMUIdxBit_E2; + } +} + static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vae2_tlbmask(env); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); + tlb_flush_by_mmuidx(cs, mask); } =20 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4000,8 +4017,9 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,= const ARMCPRegInfo *ri, uint64_t value) { CPUState *cs =3D env_cpu(env); + int mask =3D vae2_tlbmask(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4019,11 +4037,11 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, = const ARMCPRegInfo *ri, * Currently handles both VAE2 and VALE2, since we don't support * flush-last-level-only. */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vae2_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.17.1