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[97.126.117.207]) by smtp.gmail.com with ESMTPSA id i6sm32724751pgi.40.2019.07.19.14.03.50 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 19 Jul 2019 14:03:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GHJ3UWi076gcoHxg1DQBmNZO36QuD3aqqu+CJJcjV+8=; b=UI0M0X5duZMFsvuhBKChZV8Q3IonwiWAvOKRQ0Zetrx3KdqfFTWFMvrb/GUXs6gTSP EJyKZrpz2Txv9Prlf3TLzTKim9DwpUXm72h8g5B39M6yWVqCoL0cpJA/1h5sQen/Q24I YHbi66ttPl5iR+r89O/R/IXLYjZFhbI3oErz75Jn5QaQRPcjzXIvr162ErZL8fJI04tG Qcjey2zEWw+G+nR+YVLT682IIf6xTNFRt2pJ3pYh5jGdrC8A9M0af4UzelwlinfSKtAt 6292CfGkz3RpCHAuarBJmHBBcfpeFAlKzZX4bcJSH0rodErlzpmCv6+qjUejenzTVw6C A+vQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GHJ3UWi076gcoHxg1DQBmNZO36QuD3aqqu+CJJcjV+8=; b=nfqTe1xcJbD0NiXkQdZBj24ZyIMZyTBSqBasvhzwvcgiFuhcnVUlynAbN8uuW5+zRU uUO8XgXP9cj5KC8PXfcD7LNPqqUNLYUV6tKgDJ5sCnTrGOxm67u2C83aH/dYHKuh5+7t yi0anfOBzLR+VnbDTJrTiT4Taphj39vrSoe2d4G86HXk1nQgvgep+6nJ7vKPGA/VhAhy Gw7/DbnPmSiCKOsnJ8c6kvyZhgw1LxkRY9MFMTQswwyE+Wu25obU8gOneA9d7RYdc20Y 9JjRaJi6uKYpG/C0cI9R/da9ANXn6chwtL01aNKBuDJFbjY5uTA0lVGKi/p3pDXEsKyX PtPg== X-Gm-Message-State: APjAAAW4UOVNws6d40IHGo5dXVDdvOfNwz4bfj1La2vUrt4LLsFYb9b+ wEeUMvqYnAkU7kn/A3iLY/lSttr09JE= X-Google-Smtp-Source: APXvYqwVrsEqJSOGHoXP/CE81jLbFWWioMzlQxvPpGQQjlk019aPX/509MfuwBdNds12CtXAG7QKPw== X-Received: by 2002:a63:89c7:: with SMTP id v190mr54263084pgd.299.1563570231150; Fri, 19 Jul 2019 14:03:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 19 Jul 2019 14:03:21 -0700 Message-Id: <20190719210326.15466-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190719210326.15466-1-richard.henderson@linaro.org> References: <20190719210326.15466-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH for-4.2 19/24] target/arm: Install asids for E2&0 translation regime X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, beata.michalska@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When clearing HCR_E2H, this involves re-installing the E1&0 asid. Signed-off-by: Richard Henderson --- target/arm/helper.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index db13a8f9c0..22eb056b27 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3516,12 +3516,28 @@ static void vmsa_ttbr_el1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, } } =20 +static void update_el2_asid(CPUARMState *env) +{ + CPUState *cs =3D env_cpu(env); + uint64_t ttbr0, ttbr1, ttcr; + int asid, idxmask; + + ttbr0 =3D env->cp15.ttbr0_el[2]; + ttbr1 =3D env->cp15.ttbr1_el[2]; + ttcr =3D env->cp15.tcr_el[2].raw_tcr; + idxmask =3D ARMMMUIdxBit_E2 | ARMMMUIdxBit_E0; + asid =3D extract64(ttcr & TTBCR_A1 ? ttbr1 : ttbr0, 48, 16); + + tlb_set_asid_for_mmuidx(cs, asid, idxmask, 0); +} + static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { raw_write(env, ri, value); if (arm_hcr_el2_eff(env) & HCR_E2H) { - /* The ASID field is active. */ + /* We are running with EL2&0 regime and the ASID is active. */ + update_el2_asid(env); } } =20 @@ -4652,6 +4668,7 @@ static void hcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) ARMCPU *cpu =3D env_archcpu(env); /* Begin with bits defined in base ARMv8.0. */ uint64_t valid_mask =3D MAKE_64BIT_MASK(0, 34); + uint64_t old_value; =20 if (arm_feature(env, ARM_FEATURE_EL3)) { valid_mask &=3D ~HCR_HCD; @@ -4678,15 +4695,25 @@ static void hcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) /* Clear RES0 bits. */ value &=3D valid_mask; =20 - /* These bits change the MMU setup: + old_value =3D env->cp15.hcr_el2; + env->cp15.hcr_el2 =3D value; + + /* + * These bits change the MMU setup: * HCR_VM enables stage 2 translation * HCR_PTW forbids certain page-table setups - * HCR_DC Disables stage1 and enables stage2 translation + * HCR_DC disables stage1 and enables stage2 translation + * HCR_E2H enables E2&0 translation regime. */ - if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { + if ((old_value ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_E2H)) { tlb_flush(CPU(cpu)); + /* Also install the correct ASID for the regime. */ + if (value & HCR_E2H) { + update_el2_asid(env); + } else { + update_lpae_el1_asid(env, false); + } } - env->cp15.hcr_el2 =3D value; =20 /* * Updates to VI and VF require us to update the status of --=20 2.17.1