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charset="utf-8" Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 55c53c741776..085e468ea69a 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -149,13 +149,11 @@ * XIVE Notifier (Interface between Source and Router) */ =20 -typedef struct XiveNotifier { - Object parent; -} XiveNotifier; +typedef struct XiveNotifier XiveNotifier; =20 #define TYPE_XIVE_NOTIFIER "xive-notifier" #define XIVE_NOTIFIER(obj) \ - OBJECT_CHECK(XiveNotifier, (obj), TYPE_XIVE_NOTIFIER) + INTERFACE_CHECK(XiveNotifier, (obj), TYPE_XIVE_NOTIFIER) #define XIVE_NOTIFIER_CLASS(klass) \ OBJECT_CLASS_CHECK(XiveNotifierClass, (klass), TYPE_XIVE_NOTIFIER) #define XIVE_NOTIFIER_GET_CLASS(obj) \ --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Thu, 18 Jul 2019 07:54:47 -0400 Received: from player778.ha.ovh.net (unknown [10.109.143.208]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 9729F13B799 for ; Thu, 18 Jul 2019 13:54:45 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id E42BE801F262; Thu, 18 Jul 2019 11:54:39 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:05 +0200 Message-Id: <20190718115420.19919-3-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6774821216336710630 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.63.230 Subject: [Qemu-devel] [PATCH v2 02/17] ppc/pnv: add more dummy XSCOM addresses for the P9 CAPP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv_xscom.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 2b81c75f5654..3efa9c8fa13f 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -107,6 +107,16 @@ static uint64_t xscom_read_default(PnvChip *chip, uint= 32_t pcba) case 0x201302a: /* CAPP stuff */ case 0x2013801: /* CAPP stuff */ case 0x2013802: /* CAPP stuff */ + + /* P9 CAPP regs */ + case 0x2010841: + case 0x2010842: + case 0x201082a: + case 0x2010828: + case 0x4010841: + case 0x4010842: + case 0x401082a: + case 0x4010828: return 0; default: return -1; @@ -139,6 +149,16 @@ static bool xscom_write_default(PnvChip *chip, uint32_= t pcba, uint64_t val) case 0x2013801: /* CAPP stuff */ case 0x2013802: /* CAPP stuff */ =20 + /* P9 CAPP regs */ + case 0x2010841: + case 0x2010842: + case 0x201082a: + case 0x2010828: + case 0x4010841: + case 0x4010842: + case 0x401082a: + case 0x4010828: + /* P8 PRD registers */ case PRD_P8_IPOLL_REG_MASK: case PRD_P8_IPOLL_REG_STATUS: --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Thu, 18 Jul 2019 07:54:53 -0400 Received: from player778.ha.ovh.net (unknown [10.108.42.228]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id F0BB5139F42 for ; Thu, 18 Jul 2019 13:54:50 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 52E78801F2B3; Thu, 18 Jul 2019 11:54:45 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:06 +0200 Message-Id: <20190718115420.19919-4-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6776228591923858406 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.79.46 Subject: [Qemu-devel] [PATCH v2 03/17] ppc/xive: Implement TM_PULL_OS_CTX special command X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When a vCPU is not dispatched anymore on a HW thread, the Hypervisor (KVM on Linux) invalidates the OS interrupt context of a vCPU with this special command. It returns the OS CAM line value and resets the VO bit. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index cf77bdb7d34a..592c0b70f197 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -334,6 +334,17 @@ static void xive_tm_set_os_pending(XiveTCTX *tctx, hwa= ddr offset, xive_tctx_notify(tctx, TM_QW1_OS); } =20 +static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset, + unsigned size) +{ + uint32_t qw1w2_prev =3D xive_tctx_word2(&tctx->regs[TM_QW1_OS]); + uint32_t qw1w2; + + qw1w2 =3D xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0); + memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); + return qw1w2; +} + /* * Define a mapping of "special" operations depending on the TIMA page * offset and the size of the operation. @@ -360,6 +371,8 @@ static const XiveTmOp xive_tm_operations[] =3D { /* MMIOs above 2K : special operations with side effects */ { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg = }, { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, N= ULL }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx= }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx= }, { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg = }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_c= tx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_c= tx }, @@ -403,7 +416,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, = uint64_t value, if (offset & 0x800) { xto =3D xive_tm_find_op(offset, size, true); if (!xto) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at = TIMA" + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at = TIMA " "@%"HWADDR_PRIx"\n", offset); } else { xto->write_handler(tctx, offset, value, size); --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1563452401; cv=none; d=zoho.com; s=zohoarc; b=fMyPINNgbEywf5T+nl67iJXGJQ8uU1anP+GP8YeCTg9X4cBr0PQrn+5VgLtmOOMa87XI+6dOVXbPV3bXVHrGgCZg+SgdFI6tmGnAgdFwJSlOKb7to14BWtcs6+KiAgDB9mhfTqgyXz20Bti/zVwRmuYpKCSR2sE3ykceQ8hy8wY= ARC-Message-Signature: i=1; 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Thu, 18 Jul 2019 07:56:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58831) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1ho501-0004p7-Ii for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ho500-0001j5-Ab for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:01 -0400 Received: from 8.mo1.mail-out.ovh.net ([178.33.110.239]:50118) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ho500-0001i0-4z for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:00 -0400 Received: from player778.ha.ovh.net (unknown [10.108.35.59]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id A664C183803 for ; Thu, 18 Jul 2019 13:54:56 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id E27FB801F2EC; Thu, 18 Jul 2019 11:54:50 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:07 +0200 Message-Id: <20190718115420.19919-5-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6777917443433335782 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.110.239 Subject: [Qemu-devel] [PATCH v2 04/17] ppc/xive: Provide backlog support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" If backlog is activated ('b' bit) on the END, the pending priority of a missed event is recorded in the IPB field of the NVT for a later resend. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 77 +++++++++++++++++++++++++++++++------------------- 1 file changed, 48 insertions(+), 29 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 592c0b70f197..1ee5c1fe4534 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1389,46 +1389,22 @@ static bool xive_presenter_match(XiveRouter *xrtr, = uint8_t format, * * The parameters represent what is sent on the PowerBus */ -static void xive_presenter_notify(XiveRouter *xrtr, uint8_t format, +static bool xive_presenter_notify(XiveRouter *xrtr, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, uint32_t logic_serv) { - XiveNVT nvt; XiveTCTXMatch match =3D { .tctx =3D NULL, .ring =3D 0 }; bool found; =20 - /* NVT cache lookup */ - if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", - nvt_blk, nvt_idx); - return; - } - - if (!xive_nvt_is_valid(&nvt)) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", - nvt_blk, nvt_idx); - return; - } - found =3D xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ign= ore, priority, logic_serv, &match); if (found) { ipb_update(&match.tctx->regs[match.ring], priority); xive_tctx_notify(match.tctx, match.ring); - return; } =20 - /* Record the IPB in the associated NVT structure */ - ipb_update((uint8_t *) &nvt.w4, priority); - xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); - - /* - * If no matching NVT is dispatched on a HW thread : - * - update the NVT structure if backlog is activated - * - escalate (ESe PQ bits and EAS in w4-5) if escalation is - * activated - */ + return found; } =20 /* @@ -1442,6 +1418,10 @@ static void xive_router_end_notify(XiveRouter *xrtr,= uint8_t end_blk, XiveEND end; uint8_t priority; uint8_t format; + uint8_t nvt_blk; + uint32_t nvt_idx; + XiveNVT nvt; + bool found; =20 /* END cache lookup */ if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { @@ -1500,14 +1480,53 @@ static void xive_router_end_notify(XiveRouter *xrtr= , uint8_t end_blk, /* * Follows IVPE notification */ - xive_presenter_notify(xrtr, format, - xive_get_field32(END_W6_NVT_BLOCK, end.w6), - xive_get_field32(END_W6_NVT_INDEX, end.w6), + nvt_blk =3D xive_get_field32(END_W6_NVT_BLOCK, end.w6); + nvt_idx =3D xive_get_field32(END_W6_NVT_INDEX, end.w6); + + /* NVT cache lookup */ + if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", + nvt_blk, nvt_idx); + return; + } + + if (!xive_nvt_is_valid(&nvt)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", + nvt_blk, nvt_idx); + return; + } + + found =3D xive_presenter_notify(xrtr, format, nvt_blk, nvt_idx, xive_get_field32(END_W7_F0_IGNORE, end.w7), priority, xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7= )); =20 /* TODO: Auto EOI. */ + + if (found) { + return; + } + + /* + * If no matching NVT is dispatched on a HW thread : + * - specific VP: update the NVT structure if backlog is activated + * - logical server : forward request to IVPE (not supported) + */ + if (xive_end_is_backlog(&end)) { + if (format =3D=3D 1) { + qemu_log_mask(LOG_GUEST_ERROR, + "XIVE: END %x/%x invalid config: F1 & backlog\n", + end_blk, end_idx); + return; + } + /* Record the IPB in the associated NVT structure */ + ipb_update((uint8_t *) &nvt.w4, priority); + xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); + + /* + * On HW, follows a "Broadcast Backlog" to IVPEs + */ + } } =20 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1563450988; cv=none; d=zoho.com; s=zohoarc; b=ZCvXrGj1qdWnYpzcymfPZ1X6ZnEJaj3FDrEt+jQMfgkXp20jQ/d2VhsYnr3enDYiOZV840mVv8KQMYGun/ZJROpXyUXO/f7kwLHr46gv+tJW5xJd38IzcReVmdbzyH1w32lHfbt6su8CvkgF8XtIPAOejx4Es3R9h7VS4h3No6U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; 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Thu, 18 Jul 2019 07:55:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ho504-0001lu-4e for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:06 -0400 Received: from 18.mo4.mail-out.ovh.net ([188.165.54.143]:33750) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ho503-0001kk-VV for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:04 -0400 Received: from player778.ha.ovh.net (unknown [10.109.160.93]) by mo4.mail-out.ovh.net (Postfix) with ESMTP id E01391FE504 for ; Thu, 18 Jul 2019 13:55:01 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 5E10F801F328; Thu, 18 Jul 2019 11:54:56 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:08 +0200 Message-Id: <20190718115420.19919-6-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6779324815084456934 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 188.165.54.143 Subject: [Qemu-devel] [PATCH v2 05/17] ppc/xive: Provide escalation support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" If the XIVE presenter can not find the NVT dispatched on any of the HW threads, it can not deliver the interrupt. XIVE offers an escalation mechanism to handle such scenarios and inform the hypervisor that an action should be taken. Escalation is configured by setting the 'e' bit and the EAS in word 4 & 5 to let the HW look for the escalation END on which to trigger a new event. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 1ee5c1fe4534..89a09dde060b 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1527,6 +1527,22 @@ static void xive_router_end_notify(XiveRouter *xrtr,= uint8_t end_blk, * On HW, follows a "Broadcast Backlog" to IVPEs */ } + + /* + * If activated, escalate notification using the ESe PQ bits and + * the EAS in w4-5 + */ + if (!xive_end_is_escalate(&end)) { + return; + } + + /* + * The END trigger becomes an Escalation trigger + */ + xive_router_end_notify(xrtr, + xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), + xive_get_field32(END_W4_ESC_END_INDEX, end.w4), + xive_get_field32(END_W5_ESC_END_DATA, end.w5)); } =20 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1563451007; cv=none; d=zoho.com; s=zohoarc; b=F6mVbhRQ94VVXi0ZzDeYp09EhgtCYcruiUMYuh9RzYwQIRbcZtFCJeBXRsCG3yQ75Qfq6DsoBXnh6ZuEwUMXeG6jX9MofUY3umZahH3bDboYur7NXGO4MUh8Xr4ExBpPu6P05IUpdh4LoRxAua8VvO+RRisn1Ne3ljvtNPJZTXw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563451007; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=tfhGE9n0nbyhDyypRTjL3gCQdmc70anBOP0xLSiNA9Q=; b=N7Kg0yl4PLiG510/TkCGdLpx6fwjnpGHKZHzLhjW7Mav8AoZhNRS3Bdo/JALPKtBHoLH5FKedc9EA/24kc6eg4DFsAVPcOZQJxLE11pqm0GrCGlRQk0y/thVtcOj8KtQQe3XEJl4w9jdniYcLiXTBlW++AOQs0RrFO2xE8tFgmU= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1563451007101580.6838943636816; Thu, 18 Jul 2019 04:56:47 -0700 (PDT) Received: from localhost ([::1]:36832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1ho51i-0002FJ-6n for importer@patchew.org; Thu, 18 Jul 2019 07:56:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58923) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1ho50A-0005P9-IJ for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ho509-0001tF-B6 for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:10 -0400 Received: from 8.mo177.mail-out.ovh.net ([46.105.61.98]:48415) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ho509-0001pW-4G for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:09 -0400 Received: from player778.ha.ovh.net (unknown [10.109.160.230]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 8BF73FC9F0 for ; Thu, 18 Jul 2019 13:55:07 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id E297F801F36C; Thu, 18 Jul 2019 11:55:01 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:09 +0200 Message-Id: <20190718115420.19919-7-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6781013666426162150 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.61.98 Subject: [Qemu-devel] [PATCH v2 06/17] ppc/xive: Provide unconditional escalation support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When the 'u' bit is set the escalation is said to be 'unconditional' which means that the ESe PQ bits are not used. Introduce a xive_router_end_es_notify() routine to share code with the ESn notification. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive_regs.h | 2 ++ hw/intc/xive.c | 44 ++++++++++++++++++++++++++++++-------- 2 files changed, 37 insertions(+), 9 deletions(-) diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 1a8c5b5e64f0..5d02ccfeff16 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -207,6 +207,8 @@ typedef struct XiveEND { #define xive_end_is_notify(end) (be32_to_cpu((end)->w0) & END_W0_UCOND_N= OTIFY) #define xive_end_is_backlog(end) (be32_to_cpu((end)->w0) & END_W0_BACKLOG) #define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALAT= E_CTL) +#define xive_end_is_uncond_escalation(end) \ + (be32_to_cpu((end)->w0) & END_W0_UNCOND_ESCALATE) =20 static inline uint64_t xive_end_qaddr(XiveEND *end) { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 89a09dde060b..c2e7e2d4c9a9 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1407,6 +1407,27 @@ static bool xive_presenter_notify(XiveRouter *xrtr, = uint8_t format, return found; } =20 +/* + * Notification using the END ESe/ESn bit (Event State Buffer for + * escalation and notification). Profide futher coalescing in the + * Router. + */ +static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, + uint32_t end_idx, XiveEND *end, + uint32_t end_esmask) +{ + uint8_t pq =3D xive_get_field32(end_esmask, end->w1); + bool notify =3D xive_esb_trigger(&pq); + + if (pq !=3D xive_get_field32(end_esmask, end->w1)) { + end->w1 =3D xive_set_field32(end_esmask, end->w1, pq); + xive_router_write_end(xrtr, end_blk, end_idx, end, 1); + } + + /* ESe/n[Q]=3D1 : end of notification */ + return notify; +} + /* * An END trigger can come from an event trigger (IPI or HW) or from * another chip. We don't model the PowerBus but the END trigger @@ -1463,16 +1484,9 @@ static void xive_router_end_notify(XiveRouter *xrtr,= uint8_t end_blk, * even futher coalescing in the Router */ if (!xive_end_is_notify(&end)) { - uint8_t pq =3D xive_get_field32(END_W1_ESn, end.w1); - bool notify =3D xive_esb_trigger(&pq); - - if (pq !=3D xive_get_field32(END_W1_ESn, end.w1)) { - end.w1 =3D xive_set_field32(END_W1_ESn, end.w1, pq); - xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); - } - /* ESn[Q]=3D1 : end of notification */ - if (!notify) { + if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, + &end, END_W1_ESn)) { return; } } @@ -1536,6 +1550,18 @@ static void xive_router_end_notify(XiveRouter *xrtr,= uint8_t end_blk, return; } =20 + /* + * Check the END ESe (Event State Buffer for escalation) for even + * futher coalescing in the Router + */ + if (!xive_end_is_uncond_escalation(&end)) { + /* ESe[Q]=3D1 : end of notification */ + if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, + &end, END_W1_ESe)) { + return; + } + } + /* * The END trigger becomes an Escalation trigger */ --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1563451020; cv=none; d=zoho.com; s=zohoarc; b=hBJ7wNwGW4a4fcmi3vp3GFdlvr+vNLd985/NafwZJvCYCX/7PZlzl/1e9w0/Ff31RWI9C9swla5j2sk2gWk0SLk7o8psgZc71rWDXZhkE8fHVvitYbD+HYoe4Db4b4x6PVDm9J6m2Og+GBNWlkHDSaeo4pxlzbMlAcaBjUE5s1Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563451020; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Thu, 18 Jul 2019 07:55:15 -0400 Received: from 16.mo6.mail-out.ovh.net ([87.98.139.208]:59243) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ho50E-0001xd-QH for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:14 -0400 Received: from player778.ha.ovh.net (unknown [10.109.143.216]) by mo6.mail-out.ovh.net (Postfix) with ESMTP id 01B1A1D81DA for ; Thu, 18 Jul 2019 13:55:12 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 5ED45801F3B0; Thu, 18 Jul 2019 11:55:07 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:10 +0200 Message-Id: <20190718115420.19919-8-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6782421039645887462 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.139.208 Subject: [Qemu-devel] [PATCH v2 07/17] ppc/xive: Provide silent escalation support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When the 's' bit is set the escalation is said to be 'silent' or 'silent/gather'. In such configuration, the notification sequence is skipped and only the escalation sequence is performed. This is used to configure all the EQs of a vCPU to escalate on a single EQ which will then target the hypervisor. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive_regs.h | 2 ++ hw/intc/xive.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 5d02ccfeff16..69af326ebf2c 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -209,6 +209,8 @@ typedef struct XiveEND { #define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALAT= E_CTL) #define xive_end_is_uncond_escalation(end) \ (be32_to_cpu((end)->w0) & END_W0_UNCOND_ESCALATE) +#define xive_end_is_silent_escalation(end) \ + (be32_to_cpu((end)->w0) & END_W0_SILENT_ESCALATE) =20 static inline uint64_t xive_end_qaddr(XiveEND *end) { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index c2e7e2d4c9a9..8ea97ac231a4 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1463,6 +1463,13 @@ static void xive_router_end_notify(XiveRouter *xrtr,= uint8_t end_blk, xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); } =20 + /* + * When the END is silent, we skip the notification part. + */ + if (xive_end_is_silent_escalation(&end)) { + goto do_escalation; + } + /* * The W7 format depends on the F bit in W6. It defines the type * of the notification : @@ -1542,6 +1549,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, = uint8_t end_blk, */ } =20 +do_escalation: /* * If activated, escalate notification using the ESe PQ bits and * the EAS in w4-5 --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1563452045; cv=none; d=zoho.com; s=zohoarc; b=dC4iTkYBvH5lGTnL+/R8LGTKGUp8RsSWSu1MK6pufNCT22Onm26QJzX+sUIKzSukpUvt0S8mdQ8g7r9XVe75KoAuSgEaFWBIw6HSLQIP8KsMU3dYoQYhyZ/LJTMgoUm1sc/d10HmN/acGb30sw5G8nRc9PINBBzb50ORZLzA02s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563452045; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=fPsrazlK5hFrDXwXJqOF/FU4WmYdcqHup5AK4JVie20=; b=Ci87pHjoLZcIrUnYclYFN1PwgQnaWaC4GsVEbTj4KE29rnoid4JoGBtKr6gawST3R3SIGn1YkQ55307vUH7wmC0ccpRUnTzBr48XLvDgWGgCvhFv8TVOWesxHRNpfGdTqweCgYmU2AYd6VRSRLTx9W6+xrDbnkDS2f7W48iNcng= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1563452045535857.5670677199854; Thu, 18 Jul 2019 05:14:05 -0700 (PDT) Received: from localhost ([::1]:36792 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1ho517-0000WG-PL for importer@patchew.org; Thu, 18 Jul 2019 07:56:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59030) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1ho50L-0006E5-Qe for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ho50K-00023Z-8r for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:21 -0400 Received: from 19.mo3.mail-out.ovh.net ([178.32.98.231]:48599) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ho50K-00022W-3P for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:20 -0400 Received: from player778.ha.ovh.net (unknown [10.108.35.122]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 82A3721FF56 for ; Thu, 18 Jul 2019 13:55:18 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 009B3801F403; Thu, 18 Jul 2019 11:55:12 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:11 +0200 Message-Id: <20190718115420.19919-9-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6784109892959505382 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.32.98.231 Subject: [Qemu-devel] [PATCH v2 08/17] ppc/xive: Improve 'info pic' support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Provide a better output of the XIVE END structures including the escalation information and extend the PowerNV machine 'info pic' command with a dump of the END EAS table used for escalations. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 5 ---- include/hw/ppc/xive_regs.h | 6 +++++ hw/intc/pnv_xive.c | 9 +++++++ hw/intc/spapr_xive.c | 1 - hw/intc/xive.c | 48 +++++++++++++++++++++++++++++++++----- 5 files changed, 57 insertions(+), 12 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 085e468ea69a..4851ff87e795 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -355,8 +355,6 @@ typedef struct XiveRouterClass { XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs); } XiveRouterClass; =20 -void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon); - int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_id= x, XiveEAS *eas); int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_id= x, @@ -398,9 +396,6 @@ typedef struct XiveENDSource { */ #define XIVE_PRIORITY_MAX 7 =20 -void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon); -void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *= mon); - /* * XIVE Thread Interrupt Management Aera (TIMA) * diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 69af326ebf2c..3fdf1a83b9b6 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -128,6 +128,8 @@ typedef struct XiveEAS { #define xive_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS_VALID) #define xive_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS_MASKED) =20 +void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon); + static inline uint64_t xive_get_field64(uint64_t mask, uint64_t word) { return (be64_to_cpu(word) & mask) >> ctz64(mask); @@ -218,6 +220,10 @@ static inline uint64_t xive_end_qaddr(XiveEND *end) be32_to_cpu(end->w3); } =20 +void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon); +void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *= mon); +void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *= mon); + /* Notification Virtual Target (NVT) */ typedef struct XiveNVT { uint32_t w0; diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 4dc92ef1e372..ff1226485983 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1593,6 +1593,15 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor = *mon) } xive_end_pic_print_info(&end, i, mon); } + + monitor_printf(mon, "XIVE[%x] END Escalation %08x .. %08x\n", blk, 0, + nr_ends - 1); + for (i =3D 0; i < nr_ends; i++) { + if (xive_router_get_end(xrtr, blk, i, &end)) { + break; + } + xive_end_eas_pic_print_info(&end, i, mon); + } } =20 static void pnv_xive_reset(void *dev) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 3ae311d9ff7f..ba012c7b0fdc 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -143,7 +143,6 @@ static void spapr_xive_end_pic_print_info(SpaprXive *xi= ve, XiveEND *end, priority, qindex, qentries, qaddr_base, qgen); =20 xive_end_queue_pic_print_info(end, 6, mon); - monitor_printf(mon, "]"); } =20 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 8ea97ac231a4..88f2e560db0f 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1136,6 +1136,7 @@ void xive_end_queue_pic_print_info(XiveEND *end, uint= 32_t width, Monitor *mon) be32_to_cpu(qdata)); qindex =3D (qindex + 1) & (qentries - 1); } + monitor_printf(mon, "]"); } =20 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) @@ -1146,24 +1147,36 @@ void xive_end_pic_print_info(XiveEND *end, uint32_t= end_idx, Monitor *mon) uint32_t qsize =3D xive_get_field32(END_W0_QSIZE, end->w0); uint32_t qentries =3D 1 << (qsize + 10); =20 - uint32_t nvt =3D xive_get_field32(END_W6_NVT_INDEX, end->w6); + uint32_t nvt_blk =3D xive_get_field32(END_W6_NVT_BLOCK, end->w6); + uint32_t nvt_idx =3D xive_get_field32(END_W6_NVT_INDEX, end->w6); uint8_t priority =3D xive_get_field32(END_W7_F0_PRIORITY, end->w7); + uint8_t pq; =20 if (!xive_end_is_valid(end)) { return; } =20 - monitor_printf(mon, " %08x %c%c%c%c%c prio:%d nvt:%04x eq:@%08"PRIx64 - "% 6d/%5d ^%d", end_idx, + pq =3D xive_get_field32(END_W1_ESn, end->w1); + + monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", + end_idx, + pq & XIVE_ESB_VAL_P ? 'P' : '-', + pq & XIVE_ESB_VAL_Q ? 'Q' : '-', xive_end_is_valid(end) ? 'v' : '-', xive_end_is_enqueue(end) ? 'q' : '-', xive_end_is_notify(end) ? 'n' : '-', xive_end_is_backlog(end) ? 'b' : '-', xive_end_is_escalate(end) ? 'e' : '-', - priority, nvt, qaddr_base, qindex, qentries, qgen); + xive_end_is_uncond_escalation(end) ? 'u' : '-', + xive_end_is_silent_escalation(end) ? 's' : '-', + priority, nvt_blk, nvt_idx); =20 - xive_end_queue_pic_print_info(end, 6, mon); - monitor_printf(mon, "]\n"); + if (qaddr_base) { + monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", + qaddr_base, qindex, qentries, qgen); + xive_end_queue_pic_print_info(end, 6, mon); + } + monitor_printf(mon, "\n"); } =20 static void xive_end_enqueue(XiveEND *end, uint32_t data) @@ -1191,6 +1204,29 @@ static void xive_end_enqueue(XiveEND *end, uint32_t = data) end->w1 =3D xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); } =20 +void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, + Monitor *mon) +{ + XiveEAS *eas =3D (XiveEAS *) &end->w4; + uint8_t pq; + + if (!xive_end_is_escalate(end)) { + return; + } + + pq =3D xive_get_field32(END_W1_ESe, end->w1); + + monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", + end_idx, + pq & XIVE_ESB_VAL_P ? 'P' : '-', + pq & XIVE_ESB_VAL_Q ? 'Q' : '-', + xive_eas_is_valid(eas) ? 'V' : ' ', + xive_eas_is_masked(eas) ? 'M' : ' ', + (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), + (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), + (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); +} + /* * XIVE Router (aka. Virtualization Controller or IVRE) */ --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1563451035; cv=none; d=zoho.com; s=zohoarc; b=NRiiH/WinEjKLhAn4FlEjhYjzOKm5vwkweu6EGM1tjgf4VvXPOEQwdG4NOO4m2cHJocceM6O41l32qtMP8Dr+Q5FmNh4jgw74V0IjyeTRSxF6ZAm8paDBHYbDD4F9J2E1AL3I5K34JSUjQtmbF6HeI71BWXKzz8KtZbq+cKr9MY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563451035; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=c+t3Kj92KTcWj0hJ1PQzkop7x7gCZ+6iRjqFPfh0KX8=; b=ILU8oJjkpBS3lObgjDzOhMiB0C7UfYU2V5NzEmZIltbAce+NPHU0NmbDf7pd888z0WJuttSdMFhR1b7cOaw+p22r+8r1jEnHoXfvkqnp2i8l5TMA3valKOVeSVCTSqLUaOCubIHg48c3BaLJz+zp4K1Vomrw/UglOMwFHV0vRLo= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1563451035148200.86187773230097; Thu, 18 Jul 2019 04:57:15 -0700 (PDT) Received: from localhost ([::1]:36846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1ho52A-00042u-5C for importer@patchew.org; Thu, 18 Jul 2019 07:57:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59082) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1ho50Q-0006WG-T6 for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ho50P-00027d-Mo for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:26 -0400 Received: from 4.mo4.mail-out.ovh.net ([178.32.98.131]:49060) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ho50P-00026j-HB for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:25 -0400 Received: from player778.ha.ovh.net (unknown [10.108.42.176]) by mo4.mail-out.ovh.net (Postfix) with ESMTP id 242621FE191 for ; Thu, 18 Jul 2019 13:55:24 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 58C42801F490; Thu, 18 Jul 2019 11:55:18 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:12 +0200 Message-Id: <20190718115420.19919-10-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6785798742523874278 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.32.98.131 Subject: [Qemu-devel] [PATCH v2 09/17] ppc/xive: Extend XiveTCTX with a XiveRouter pointer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This is to perform lookups in the NVT table when a vCPU is dispatched and possibily resend interrupts. Future XIVE chip will use a different class for the model of the interrupt controller and we might need to change the type of 'XiveRouter *' to 'Object *' Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 2 ++ hw/intc/xive.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 4851ff87e795..206b23ecfab3 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -320,6 +320,8 @@ typedef struct XiveTCTX { qemu_irq os_output; =20 uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE]; + + struct XiveRouter *xrtr; } XiveTCTX; =20 /* diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 88f2e560db0f..1b0eccb6df40 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -573,6 +573,14 @@ static void xive_tctx_realize(DeviceState *dev, Error = **errp) Object *obj; Error *local_err =3D NULL; =20 + obj =3D object_property_get_link(OBJECT(dev), "xrtr", &local_err); + if (!obj) { + error_propagate(errp, local_err); + error_prepend(errp, "required link 'xrtr' not found: "); + return; + } + tctx->xrtr =3D XIVE_ROUTER(obj); + obj =3D object_property_get_link(OBJECT(dev), "cpu", &local_err); if (!obj) { error_propagate(errp, local_err); @@ -666,6 +674,7 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr,= Error **errp) object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); object_unref(obj); object_property_add_const_link(obj, "cpu", cpu, &error_abort); + object_property_add_const_link(obj, "xrtr", OBJECT(xrtr), &error_abort= ); object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { goto error; --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 18 Jul 2019 11:55:24 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:13 +0200 Message-Id: <20190718115420.19919-11-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6787206114223426534 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.174.144 Subject: [Qemu-devel] [PATCH v2 10/17] ppc/xive: Introduce xive_tctx_ipb_update() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We will use it to resend missed interrupts when a vCPU context is pushed a HW thread. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 1 + hw/intc/xive.c | 15 +++++++++++---- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 206b23ecfab3..51e3c37b7483 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -418,6 +418,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offse= t, unsigned size); =20 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); +void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb); =20 static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 1b0eccb6df40..be66b1fb3261 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -132,6 +132,15 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t= ring, uint8_t cppr) xive_tctx_notify(tctx, ring); } =20 +void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) +{ + uint8_t *regs =3D &tctx->regs[ring]; + + regs[TM_IPB] |=3D ipb; + regs[TM_PIPR] =3D ipb_to_pipr(regs[TM_IPB]); + xive_tctx_notify(tctx, ring); +} + static inline uint32_t xive_tctx_word2(uint8_t *ring) { return *((uint32_t *) &ring[TM_WORD2]); @@ -330,8 +339,7 @@ static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr = offset, static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size) { - ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); - xive_tctx_notify(tctx, TM_QW1_OS); + xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff)); } =20 static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset, @@ -1445,8 +1453,7 @@ static bool xive_presenter_notify(XiveRouter *xrtr, u= int8_t format, found =3D xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ign= ore, priority, logic_serv, &match); if (found) { - ipb_update(&match.tctx->regs[match.ring], priority); - xive_tctx_notify(match.tctx, match.ring); + xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(prior= ity)); } =20 return found; --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1563452380; cv=none; d=zoho.com; s=zohoarc; b=niyBmkVA1ARW+G9JqdtFt9LTQUTn4buv8JtNRL5HGMGHODtMNFsv0+NFmBMctH0gVPAXKLe4yDcqKgqzCPRub+Is5txzT/rdO/HN0h4egcEm41tvvqt/wTiikOYWGLC0WXB/WOcM58mC7k3cgRkFc2fRkT8ykCk6aHPBOlxXJOU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563452380; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Thu, 18 Jul 2019 07:55:38 -0400 Received: from 17.mo5.mail-out.ovh.net ([46.105.56.132]:39242) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ho50a-0002Hl-SW for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:37 -0400 Received: from player778.ha.ovh.net (unknown [10.109.143.109]) by mo5.mail-out.ovh.net (Postfix) with ESMTP id 48702243478 for ; Thu, 18 Jul 2019 13:55:35 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 7C6C3801F552; Thu, 18 Jul 2019 11:55:29 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:14 +0200 Message-Id: <20190718115420.19919-12-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6788894964271975398 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.56.132 Subject: [Qemu-devel] [PATCH v2 11/17] ppc/xive: Synthesize interrupt from the saved IPB in the NVT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When an interrupt can not be presented to a vCPU, the XIVE presenter updates the Interrupt Pending Buffer of the XIVE NVT if backlog is activated in the END. Later, when the same vCPU is dispatched, its context is pushed in the thread context registers and the VO bit is set in the CAM line word to activate the context. The HW grabs the associated NVT to pull the pending bits, and merges them with the IPB of the TIMA. If interrupts were missed while the vCPU was not dispatched, these are synthesized in this sequence. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 5 --- include/hw/ppc/xive_regs.h | 22 ++++++++++++ hw/intc/xive.c | 68 +++++++++++++++++++++++++++++++++----- 3 files changed, 82 insertions(+), 13 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 51e3c37b7483..251a8f2de10e 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -420,11 +420,6 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor = *mon); Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb); =20 -static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) -{ - return (nvt_blk << 19) | nvt_idx; -} - /* * KVM XIVE device helpers */ diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 3fdf1a83b9b6..92ff80d25456 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -232,6 +232,7 @@ typedef struct XiveNVT { uint32_t w2; uint32_t w3; uint32_t w4; +#define NVT_W4_IPB PPC_BITMASK32(16, 23) uint32_t w5; uint32_t w6; uint32_t w7; @@ -248,4 +249,25 @@ typedef struct XiveNVT { =20 #define xive_nvt_is_valid(nvt) (be32_to_cpu((nvt)->w0) & NVT_W0_VALID) =20 +/* + * The VP number space in a block is defined by the END_W6_NVT_INDEX + * field of the XIVE END + */ +#define XIVE_NVT_SHIFT 19 + +static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) +{ + return (nvt_blk << XIVE_NVT_SHIFT) | nvt_idx; +} + +static inline uint32_t xive_nvt_idx(uint32_t cam_line) +{ + return cam_line & ((1 << XIVE_NVT_SHIFT) - 1); +} + +static inline uint32_t xive_nvt_blk(uint32_t cam_line) +{ + return (cam_line >> XIVE_NVT_SHIFT) & 0xf; +} + #endif /* PPC_XIVE_REGS_H */ diff --git a/hw/intc/xive.c b/hw/intc/xive.c index be66b1fb3261..bcb22ad7e69a 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -44,12 +44,6 @@ static uint8_t ipb_to_pipr(uint8_t ibp) return ibp ? clz32((uint32_t)ibp << 24) : 0xff; } =20 -static void ipb_update(uint8_t *regs, uint8_t priority) -{ - regs[TM_IPB] |=3D priority_to_ipb(priority); - regs[TM_PIPR] =3D ipb_to_pipr(regs[TM_IPB]); -} - static uint8_t exception_mask(uint8_t ring) { switch (ring) { @@ -353,6 +347,56 @@ static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hw= addr offset, return qw1w2; } =20 +static void xive_tctx_need_resend(XiveTCTX *tctx, uint8_t nvt_blk, + uint32_t nvt_idx) +{ + XiveNVT nvt; + uint8_t ipb; + XiveRouter *xrtr =3D XIVE_ROUTER(tctx->xrtr); + + /* + * Grab the associated NVT to pull the pending bits, and merge + * them with the IPB of the thread interrupt context registers + */ + if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", + nvt_blk, nvt_idx); + return; + } + + ipb =3D xive_get_field32(NVT_W4_IPB, nvt.w4); + + if (ipb) { + /* Reset the NVT value */ + nvt.w4 =3D xive_set_field32(NVT_W4_IPB, nvt.w4, 0); + xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); + + /* Merge in current context */ + xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); + } +} + +/* + * Updating the OS CAM line can trigger a resend of interrupt + */ +static void xive_tm_push_os_ctx(XiveTCTX *tctx, hwaddr offset, + uint64_t value, unsigned size) +{ + uint32_t qw1w2 =3D value; + uint8_t nvt_blk =3D xive_nvt_blk(qw1w2); + uint32_t nvt_idx =3D xive_nvt_idx(qw1w2); + bool vo =3D !!(qw1w2 & TM_QW1W2_VO); + + /* First update the registers */ + qw1w2 =3D cpu_to_be32(qw1w2); + memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); + + /* Check the interrupt pending bits */ + if (vo) { + xive_tctx_need_resend(tctx, nvt_blk, nvt_idx); + } +} + /* * Define a mapping of "special" operations depending on the TIMA page * offset and the size of the operation. @@ -372,6 +416,7 @@ static const XiveTmOp xive_tm_operations[] =3D { * effects */ { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL= }, + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, N= ULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, N= ULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL= }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll= }, @@ -1586,14 +1631,21 @@ static void xive_router_end_notify(XiveRouter *xrtr= , uint8_t end_blk, * - logical server : forward request to IVPE (not supported) */ if (xive_end_is_backlog(&end)) { + uint8_t ipb; + if (format =3D=3D 1) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x invalid config: F1 & backlog\n", end_blk, end_idx); return; } - /* Record the IPB in the associated NVT structure */ - ipb_update((uint8_t *) &nvt.w4, priority); + /* + * Record the IPB in the associated NVT structure for later + * use. The presenter will resend the interrupt when the vCPU + * is dispatched again on a HW thread. + */ + ipb =3D xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(pri= ority); + nvt.w4 =3D xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); =20 /* --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1563451051; cv=none; d=zoho.com; s=zohoarc; b=fWZIoGxzv3ObIDTtrQn9IvY6QXWIGMpL1ZI6KWDqPXHmtIL5N7cd0ZtpVKHyX2zhT8GvFXFWS2YfxxuD9t6zwELY/pITsXQOJd9YD70Ozg3IX3y/jdNgGcjd4IwVbBkov33wiQfUwAQzXMFfb0fG5a8JQ3f80FRSQmvcm+x5xZ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563451051; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=OsQ55xTwEFsw1XMWT/ijyI52bUf6PO1zCSDAaiXW+3k=; b=NlJTs7F2o98hpAyttKd6td4OWI65gdbBo2annwcfQCm3CRQLD/mVGlyRci/2IkDuXB7jcu7RzmqZDr4WMHkIqPV2RXobuuFMhq6ITCfox1CfL3x/w2gm7uXMuJJcc5uRbP0+u6aoWO56VA+cTMrgzSIOhDHB0685t/AD71IfP9M= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1563451051438564.2333971385757; Thu, 18 Jul 2019 04:57:31 -0700 (PDT) Received: from localhost ([::1]:36856 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1ho52Q-00053k-H1 for importer@patchew.org; Thu, 18 Jul 2019 07:57:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59285) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1ho50k-0007s2-Un for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ho50j-0002P8-4R for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:46 -0400 Received: from 9.mo177.mail-out.ovh.net ([46.105.72.238]:36211) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ho50i-0002Nb-UY for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:55:45 -0400 Received: from player778.ha.ovh.net (unknown [10.109.159.157]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 9D5E5104368 for ; Thu, 18 Jul 2019 13:55:40 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 3DF0B801F58C; Thu, 18 Jul 2019 11:55:35 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:15 +0200 Message-Id: <20190718115420.19919-13-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6790302339583020006 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.72.238 Subject: [Qemu-devel] [PATCH v2 12/17] ppc/pnv: Remove pnv_xive_vst_size() routine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" pnv_xive_vst_size() tries to compute the size of a VSD table from the information given by FW. The number of entries of the table are deduced from the result and the MMIO regions of the ESBs and the ENDS are also resized with the computed value. But for indirect tables, the result is incorrect. An indirect table is an array, typically one page, of VSDs pointing to a page containing XIVE virtual structures. The number of first level VSD entries is page aligned and the overall computed size of the table is too large. It can also be completely wrong when the first VSD entry is not yet initialized. Remove pnv_xive_vst_size() and use a simpler form for direct tables only. This is still useful when outputting the XIVE sources on the monitor and to resize the ESB MMIO window. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 112 +++++++++++++++++---------------------------- 1 file changed, 43 insertions(+), 69 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index ff1226485983..63243253b736 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -121,36 +121,22 @@ static uint64_t pnv_xive_vst_page_size_allowed(uint32= _t page_shift) page_shift =3D=3D 21 || page_shift =3D=3D 24; } =20 -static uint64_t pnv_xive_vst_size(uint64_t vsd) -{ - uint64_t vst_tsize =3D 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); - - /* - * Read the first descriptor to get the page size of the indirect - * table. - */ - if (VSD_INDIRECT & vsd) { - uint32_t nr_pages =3D vst_tsize / XIVE_VSD_SIZE; - uint32_t page_shift; - - vsd =3D ldq_be_dma(&address_space_memory, vsd & VSD_ADDRESS_MASK); - page_shift =3D GETFIELD(VSD_TSIZE, vsd) + 12; - - if (!pnv_xive_vst_page_size_allowed(page_shift)) { - return 0; - } - - return nr_pages * (1ull << page_shift); - } - - return vst_tsize; -} - static uint64_t pnv_xive_vst_addr_direct(PnvXive *xive, uint32_t type, uint64_t vsd, uint32_t idx) { const XiveVstInfo *info =3D &vst_infos[type]; uint64_t vst_addr =3D vsd & VSD_ADDRESS_MASK; + uint64_t vst_tsize =3D 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); + uint32_t idx_max; + + idx_max =3D vst_tsize / info->size - 1; + if (idx > idx_max) { +#ifdef XIVE_DEBUG + xive_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", + info->name, idx, idx_max); +#endif + return 0; + } =20 return vst_addr + idx * info->size; } @@ -213,7 +199,6 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32= _t type, uint8_t blk, { const XiveVstInfo *info =3D &vst_infos[type]; uint64_t vsd; - uint32_t idx_max; =20 if (blk >=3D info->max_blocks) { xive_error(xive, "VST: invalid block id %d for VST %s %d !?", @@ -230,15 +215,6 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint3= 2_t type, uint8_t blk, return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0; } =20 - idx_max =3D pnv_xive_vst_size(vsd) / info->size - 1; - if (idx > idx_max) { -#ifdef XIVE_DEBUG - xive_error(xive, "VST: %s entry %x/%x out of range [ 0 .. %x ] !?", - info->name, blk, idx, idx_max); -#endif - return 0; - } - if (VSD_INDIRECT & vsd) { return pnv_xive_vst_addr_indirect(xive, type, vsd, idx); } @@ -451,19 +427,12 @@ static uint64_t pnv_xive_pc_size(PnvXive *xive) return (~xive->regs[CQ_PC_BARM >> 3] + 1) & CQ_PC_BARM_MASK; } =20 -static uint32_t pnv_xive_nr_ipis(PnvXive *xive) +static uint32_t pnv_xive_nr_ipis(PnvXive *xive, uint8_t blk) { - uint8_t blk =3D xive->chip->chip_id; - - return pnv_xive_vst_size(xive->vsds[VST_TSEL_SBE][blk]) * SBE_PER_BYTE; -} - -static uint32_t pnv_xive_nr_ends(PnvXive *xive) -{ - uint8_t blk =3D xive->chip->chip_id; + uint64_t vsd =3D xive->vsds[VST_TSEL_SBE][blk]; + uint64_t vst_tsize =3D 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); =20 - return pnv_xive_vst_size(xive->vsds[VST_TSEL_EQDT][blk]) - / vst_infos[VST_TSEL_EQDT].size; + return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; } =20 /* @@ -596,6 +565,7 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive, u= int8_t type, XiveSource *xsrc =3D &xive->ipi_source; const XiveVstInfo *info =3D &vst_infos[type]; uint32_t page_shift =3D GETFIELD(VSD_TSIZE, vsd) + 12; + uint64_t vst_tsize =3D 1ull << page_shift; uint64_t vst_addr =3D vsd & VSD_ADDRESS_MASK; =20 /* Basic checks */ @@ -631,11 +601,16 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive,= uint8_t type, =20 case VST_TSEL_EQDT: /* - * Backing store pages for the END. Compute the number of ENDs - * provisioned by FW and resize the END ESB window accordingly. + * Backing store pages for the END. + * + * If the table is direct, we can compute the number of PQ + * entries provisioned by FW (such as skiboot) and resize the + * END ESB window accordingly. */ - memory_region_set_size(&end_xsrc->esb_mmio, pnv_xive_nr_ends(xive)= * - (1ull << (end_xsrc->esb_shift + 1))); + if (!(VSD_INDIRECT & vsd)) { + memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info-= >size) + * (1ull << xsrc->esb_shift)); + } memory_region_add_subregion(&xive->end_edt_mmio, 0, &end_xsrc->esb_mmio); break; @@ -644,11 +619,16 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive,= uint8_t type, /* * Backing store pages for the source PQ bits. The model does * not use these PQ bits backed in RAM because the XiveSource - * model has its own. Compute the number of IRQs provisioned - * by FW and resize the IPI ESB window accordingly. + * model has its own. + * + * If the table is direct, we can compute the number of PQ + * entries provisioned by FW (such as skiboot) and resize the + * ESB window accordingly. */ - memory_region_set_size(&xsrc->esb_mmio, pnv_xive_nr_ipis(xive) * - (1ull << xsrc->esb_shift)); + if (!(VSD_INDIRECT & vsd)) { + memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BY= TE + * (1ull << xsrc->esb_shift)); + } memory_region_add_subregion(&xive->ipi_edt_mmio, 0, &xsrc->esb_mmi= o); break; =20 @@ -1565,8 +1545,7 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *= mon) XiveRouter *xrtr =3D XIVE_ROUTER(xive); uint8_t blk =3D xive->chip->chip_id; uint32_t srcno0 =3D XIVE_SRCNO(blk, 0); - uint32_t nr_ipis =3D pnv_xive_nr_ipis(xive); - uint32_t nr_ends =3D pnv_xive_nr_ends(xive); + uint32_t nr_ipis =3D pnv_xive_nr_ipis(xive, blk); XiveEAS eas; XiveEND end; int i; @@ -1586,21 +1565,16 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor= *mon) } } =20 - monitor_printf(mon, "XIVE[%x] ENDT %08x .. %08x\n", blk, 0, nr_ends - = 1); - for (i =3D 0; i < nr_ends; i++) { - if (xive_router_get_end(xrtr, blk, i, &end)) { - break; - } - xive_end_pic_print_info(&end, i, mon); + monitor_printf(mon, "XIVE[%x] ENDT\n", blk); + i =3D 0; + while (!xive_router_get_end(xrtr, blk, i, &end)) { + xive_end_pic_print_info(&end, i++, mon); } =20 - monitor_printf(mon, "XIVE[%x] END Escalation %08x .. %08x\n", blk, 0, - nr_ends - 1); - for (i =3D 0; i < nr_ends; i++) { - if (xive_router_get_end(xrtr, blk, i, &end)) { - break; - } - xive_end_eas_pic_print_info(&end, i, mon); + monitor_printf(mon, "XIVE[%x] END Escalation EAT\n", blk); + i =3D 0; + while (!xive_router_get_end(xrtr, blk, i, &end)) { + xive_end_eas_pic_print_info(&end, i++, mon); } } =20 --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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Thu, 18 Jul 2019 07:55:50 -0400 Received: from player778.ha.ovh.net (unknown [10.108.57.72]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id 507CD7223D for ; Thu, 18 Jul 2019 13:55:46 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 96B7C801F5D6; Thu, 18 Jul 2019 11:55:40 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:16 +0200 Message-Id: <20190718115420.19919-14-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6791991190805908454 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.75.45 Subject: [Qemu-devel] [PATCH v2 13/17] ppc/pnv: Dump the XIVE NVT table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This is to track the configuration of the base END index of the vCPU and the Interrupt Pending Buffer. The NVT IPB is updated when an interrupt can not be presented to a vCPU. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive_regs.h | 2 ++ hw/intc/pnv_xive.c | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 92ff80d25456..b228ab0ba3ea 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -229,6 +229,8 @@ typedef struct XiveNVT { uint32_t w0; #define NVT_W0_VALID PPC_BIT32(0) uint32_t w1; +#define NVT_W1_EQ_BLOCK PPC_BITMASK32(0, 3) +#define NVT_W1_EQ_INDEX PPC_BITMASK32(4, 31) uint32_t w2; uint32_t w3; uint32_t w4; diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 63243253b736..a086598c5e77 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1540,6 +1540,21 @@ static const MemoryRegionOps pnv_xive_pc_ops =3D { }, }; =20 +static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx, + Monitor *mon) +{ + uint8_t eq_blk =3D xive_get_field32(NVT_W1_EQ_BLOCK, nvt->w1); + uint32_t eq_idx =3D xive_get_field32(NVT_W1_EQ_INDEX, nvt->w1); + + if (!xive_nvt_is_valid(nvt)) { + return; + } + + monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n", nvt_idx, + eq_blk, eq_idx, + xive_get_field32(NVT_W4_IPB, nvt->w4)); +} + void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) { XiveRouter *xrtr =3D XIVE_ROUTER(xive); @@ -1548,6 +1563,7 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *= mon) uint32_t nr_ipis =3D pnv_xive_nr_ipis(xive, blk); XiveEAS eas; XiveEND end; + XiveNVT nvt; int i; =20 monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, @@ -1576,6 +1592,12 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor = *mon) while (!xive_router_get_end(xrtr, blk, i, &end)) { xive_end_eas_pic_print_info(&end, i++, mon); } + + monitor_printf(mon, "XIVE[%x] NVTT\n", blk); + i =3D 0; + while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { + xive_nvt_pic_print_info(&nvt, i++, mon); + } } =20 static void pnv_xive_reset(void *dev) --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Thu, 18 Jul 2019 07:55:54 -0400 Received: from player778.ha.ovh.net (unknown [10.109.159.69]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id AD19D113465 for ; Thu, 18 Jul 2019 13:55:51 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 2DF15801F606; Thu, 18 Jul 2019 11:55:46 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:17 +0200 Message-Id: <20190718115420.19919-15-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6793398566116101094 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.44.159 Subject: [Qemu-devel] [PATCH v2 14/17] ppc/pnv: Skip empty slots of the XIVE NVT table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We try to loop on the full table skipping empty indirect pages which are not necessarily allocated. This is useful to dump the contexts of the KVM vCPUs. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index a086598c5e77..a48f6750154e 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1540,6 +1540,12 @@ static const MemoryRegionOps pnv_xive_pc_ops =3D { }, }; =20 +/* + * skiboot uses an indirect NVT table with 64k subpages + */ +#define XIVE_NVT_COUNT (1 << XIVE_NVT_SHIFT) +#define XIVE_NVT_PER_PAGE (0x10000 / sizeof(XiveNVT)) + static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx, Monitor *mon) { @@ -1593,10 +1599,12 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor= *mon) xive_end_eas_pic_print_info(&end, i++, mon); } =20 - monitor_printf(mon, "XIVE[%x] NVTT\n", blk); - i =3D 0; - while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { - xive_nvt_pic_print_info(&nvt, i++, mon); + monitor_printf(mon, "XIVE[%x] NVTT %08x .. %08x\n", blk, 0, + XIVE_NVT_COUNT - 1); + for (i =3D 0; i < XIVE_NVT_COUNT; i +=3D XIVE_NVT_PER_PAGE) { + while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { + xive_nvt_pic_print_info(&nvt, i++, mon); + } } } =20 --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1563451502; cv=none; d=zoho.com; s=zohoarc; b=V3mmKxZh3e/Lyfed75Bx+B7B+lFDriuxdckU4D5rw+ZS4ShpGkVmUijoiRhxk5a0fbtzjI5dq/v/r3rwbt9rJG9xtY57xDY8NeDJf9OJlKB2BSXlsMLAiSfGdM2MN4sepOquZBAn9sPHmfmtIIs2rBgSGf8i/bmS/hSYFsFVQK4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563451502; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Thu, 18 Jul 2019 07:56:01 -0400 Received: from 2.mo68.mail-out.ovh.net ([46.105.52.162]:57616) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ho50y-0002Y8-Gs for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:56:00 -0400 Received: from player778.ha.ovh.net (unknown [10.108.35.119]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 542B413CE19 for ; Thu, 18 Jul 2019 13:55:57 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 913B3801F61E; Thu, 18 Jul 2019 11:55:51 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:18 +0200 Message-Id: <20190718115420.19919-16-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6795087416839801830 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.52.162 Subject: [Qemu-devel] [PATCH v2 15/17] ppc/pnv: Grab the XiveRouter object from XiveTCTX in pnv_xive_get_tctx() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" It removes a useless call to pnv_xive_get_ic() which is making some assumption on the chip_id format. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index a48f6750154e..403e8c8ca5b4 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -370,22 +370,13 @@ static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, = CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); XiveTCTX *tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc); - PnvXive *xive =3D NULL; + PnvXive *xive =3D PNV_XIVE(tctx->xrtr); CPUPPCState *env =3D &cpu->env; int pir =3D env->spr_cb[SPR_PIR].default_value; =20 /* * Perform an extra check on the HW thread enablement. - * - * The TIMA is shared among the chips and to identify the chip - * from which the access is being done, we extract the chip id - * from the PIR. */ - xive =3D pnv_xive_get_ic((pir >> 8) & 0xf); - if (!xive) { - return NULL; - } - if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) { xive_error(PNV_XIVE(xrtr), "IC: CPU %x is not enabled", pir); } --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1563451852; cv=none; d=zoho.com; s=zohoarc; b=Y4viaC071KIBIspyLSwCXkT0mWnJ/IIYSow+UdPPEJrDCMBoSx8MHbDqSqpfnNB9sYJZuZAhTL5wmykG82yTE3XK66fXAFXMxVXoVDQBNFkQUwBo/Zh0baSXIgApH1/NjrA2P/i5bTcYS0xE74Sws1MiftuyKN2IAW7vbRZ11WE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563451852; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Thu, 18 Jul 2019 07:56:05 -0400 Received: from 2.mo178.mail-out.ovh.net ([46.105.39.61]:43525) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ho512-0002gw-7a for qemu-devel@nongnu.org; Thu, 18 Jul 2019 07:56:04 -0400 Received: from player778.ha.ovh.net (unknown [10.108.57.150]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id ABE0D72364 for ; Thu, 18 Jul 2019 13:56:02 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 47B43801F659; Thu, 18 Jul 2019 11:55:57 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 18 Jul 2019 13:54:19 +0200 Message-Id: <20190718115420.19919-17-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190718115420.19919-1-clg@kaod.org> References: <20190718115420.19919-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6796494788646243302 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrieehgdegkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.39.61 Subject: [Qemu-devel] [PATCH v2 16/17] ppc/pnv: Introduce a pnv_xive_get_block_id() interface to XiveRouter X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID field overrides the hardwired chip ID in the Powerbus operations and for CAM compares. This is typically used in one block-per-chip configurations to associate a unique block id number to each IC of the system. The model does support multiple blocks per chip. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv_xive.h | 3 -- include/hw/ppc/xive.h | 2 ++ hw/intc/pnv_xive.c | 66 +++++++++++++++++++++------------------ hw/intc/spapr_xive.c | 6 ++++ hw/intc/xive.c | 10 +++++- 5 files changed, 53 insertions(+), 34 deletions(-) diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h index 4fdaa9247d65..f4c7caad40ee 100644 --- a/include/hw/ppc/pnv_xive.h +++ b/include/hw/ppc/pnv_xive.h @@ -72,9 +72,6 @@ typedef struct PnvXive { /* Interrupt controller registers */ uint64_t regs[0x300]; =20 - /* Can be configured by FW */ - uint32_t tctx_chipid; - /* * Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ * These are in a SRAM protected by ECC. diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 251a8f2de10e..8828dd1eb06c 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -355,6 +355,7 @@ typedef struct XiveRouterClass { int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt, uint8_t word_number); XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs); + uint8_t (*get_block_id)(XiveRouter *xrtr); } XiveRouterClass; =20 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_id= x, @@ -368,6 +369,7 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_b= lk, uint32_t nvt_idx, int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_= idx, XiveNVT *nvt, uint8_t word_number); XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs); +uint8_t xive_router_get_block_id(XiveRouter *xrtr); void xive_router_notify(XiveNotifier *xn, uint32_t lisn); =20 /* diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 403e8c8ca5b4..c1501a6b5bce 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -83,6 +83,23 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t = word, return (word & ~mask) | ((value << ctz64(mask)) & mask); } =20 +/* + * When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID + * field overrides the hardwired chip ID in the Powerbus operations + * and for CAM compares + */ +static uint8_t pnv_xive_block_id(PnvXive *xive) +{ + uint8_t blk =3D xive->chip->chip_id; + uint64_t cfg_val =3D xive->regs[PC_TCTXT_CFG >> 3]; + + if (cfg_val & PC_TCTXT_CHIPID_OVERRIDE) { + blk =3D GETFIELD(PC_TCTXT_CHIPID, cfg_val); + } + + return blk; +} + /* * Remote access to controllers. HW uses MMIOs. For now, a simple scan * of the chips is good enough. @@ -98,7 +115,7 @@ static PnvXive *pnv_xive_get_ic(uint8_t blk) Pnv9Chip *chip9 =3D PNV9_CHIP(pnv->chips[i]); PnvXive *xive =3D &chip9->xive; =20 - if (xive->chip->chip_id =3D=3D blk) { + if (pnv_xive_block_id(xive) =3D=3D blk) { return xive; } } @@ -384,6 +401,11 @@ static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, C= PUState *cs) return tctx; } =20 +static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr) +{ + return pnv_xive_block_id(PNV_XIVE(xrtr)); +} + /* * The internal sources (IPIs) of the interrupt controller have no * knowledge of the XIVE chip on which they reside. Encode the block @@ -394,7 +416,7 @@ static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CP= UState *cs) static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno) { PnvXive *xive =3D PNV_XIVE(xn); - uint8_t blk =3D xive->chip->chip_id; + uint8_t blk =3D pnv_xive_block_id(xive); =20 xive_router_notify(xn, XIVE_SRCNO(blk, srcno)); } @@ -758,21 +780,9 @@ static void pnv_xive_ic_reg_write(void *opaque, hwaddr= offset, case PC_TCTXT_CFG: /* * TODO: block group support - * - * PC_TCTXT_CFG_BLKGRP_EN - * PC_TCTXT_CFG_HARD_CHIPID_BLK : - * Moves the chipid into block field for hardwired CAM compares. - * Block offset value is adjusted to 0b0..01 & ThrdId - * - * Will require changes in xive_presenter_tctx_match(). I am - * not sure how to handle that yet. */ - - /* Overrides hardwired chip ID with the chip ID field */ - if (val & PC_TCTXT_CHIPID_OVERRIDE) { - xive->tctx_chipid =3D GETFIELD(PC_TCTXT_CHIPID, val); - } break; + case PC_TCTXT_TRACK: /* * PC_TCTXT_TRACK_EN: @@ -1555,7 +1565,8 @@ static void xive_nvt_pic_print_info(XiveNVT *nvt, uin= t32_t nvt_idx, void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) { XiveRouter *xrtr =3D XIVE_ROUTER(xive); - uint8_t blk =3D xive->chip->chip_id; + uint8_t blk =3D pnv_xive_block_id(xive); + uint8_t chip_id =3D xive->chip->chip_id; uint32_t srcno0 =3D XIVE_SRCNO(blk, 0); uint32_t nr_ipis =3D pnv_xive_nr_ipis(xive, blk); XiveEAS eas; @@ -1563,12 +1574,12 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor= *mon) XiveNVT nvt; int i; =20 - monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, - srcno0 + nr_ipis - 1); + monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk, + srcno0, srcno0 + nr_ipis - 1); xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); =20 - monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0, - srcno0 + nr_ipis - 1); + monitor_printf(mon, "XIVE[%x] #%d EAT %08x .. %08x\n", chip_id, blk, + srcno0, srcno0 + nr_ipis - 1); for (i =3D 0; i < nr_ipis; i++) { if (xive_router_get_eas(xrtr, blk, i, &eas)) { break; @@ -1578,20 +1589,20 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor= *mon) } } =20 - monitor_printf(mon, "XIVE[%x] ENDT\n", blk); + monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); i =3D 0; while (!xive_router_get_end(xrtr, blk, i, &end)) { xive_end_pic_print_info(&end, i++, mon); } =20 - monitor_printf(mon, "XIVE[%x] END Escalation EAT\n", blk); + monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); i =3D 0; while (!xive_router_get_end(xrtr, blk, i, &end)) { xive_end_eas_pic_print_info(&end, i++, mon); } =20 - monitor_printf(mon, "XIVE[%x] NVTT %08x .. %08x\n", blk, 0, - XIVE_NVT_COUNT - 1); + monitor_printf(mon, "XIVE[%x] #%d NVTT %08x .. %08x\n", chip_id, blk, + 0, XIVE_NVT_COUNT - 1); for (i =3D 0; i < XIVE_NVT_COUNT; i +=3D XIVE_NVT_PER_PAGE) { while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { xive_nvt_pic_print_info(&nvt, i++, mon); @@ -1605,12 +1616,6 @@ static void pnv_xive_reset(void *dev) XiveSource *xsrc =3D &xive->ipi_source; XiveENDSource *end_xsrc =3D &xive->end_source; =20 - /* - * Use the PnvChip id to identify the XIVE interrupt controller. - * It can be overriden by configuration at runtime. - */ - xive->tctx_chipid =3D xive->chip->chip_id; - /* Default page size (Should be changed at runtime to 64k) */ xive->ic_shift =3D xive->vc_shift =3D xive->pc_shift =3D 12; =20 @@ -1803,6 +1808,7 @@ static void pnv_xive_class_init(ObjectClass *klass, v= oid *data) xrc->get_nvt =3D pnv_xive_get_nvt; xrc->write_nvt =3D pnv_xive_write_nvt; xrc->get_tctx =3D pnv_xive_get_tctx; + xrc->get_block_id =3D pnv_xive_get_block_id; =20 xnc->notify =3D pnv_xive_notify; }; diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index ba012c7b0fdc..1c5fb1e0e633 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -419,6 +419,11 @@ static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr,= CPUState *cs) return spapr_cpu_state(cpu)->tctx; } =20 +static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr) +{ + return SPAPR_XIVE_BLOCK_ID; +} + static const VMStateDescription vmstate_spapr_xive_end =3D { .name =3D TYPE_SPAPR_XIVE "/end", .version_id =3D 1, @@ -508,6 +513,7 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) xrc->get_nvt =3D spapr_xive_get_nvt; xrc->write_nvt =3D spapr_xive_write_nvt; xrc->get_tctx =3D spapr_xive_get_tctx; + xrc->get_block_id =3D spapr_xive_get_block_id; } =20 static const TypeInfo spapr_xive_info =3D { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index bcb22ad7e69a..18371ab60d3a 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1340,6 +1340,13 @@ XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPU= State *cs) return xrc->get_tctx(xrtr, cs); } =20 +uint8_t xive_router_get_block_id(XiveRouter *xrtr) +{ + XiveRouterClass *xrc =3D XIVE_ROUTER_GET_CLASS(xrtr); + + return xrc->get_block_id(xrtr); +} + /* * Encode the HW CAM line in the block group mode format : * @@ -1349,8 +1356,9 @@ static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) { CPUPPCState *env =3D &POWERPC_CPU(tctx->cs)->env; uint32_t pir =3D env->spr_cb[SPR_PIR].default_value; + uint8_t blk =3D xive_router_get_block_id(XIVE_ROUTER(tctx->xrtr)); =20 - return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f)); + return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); } =20 /* --=20 2.21.0 From nobody Tue May 21 18:51:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1563452952; cv=none; d=zoho.com; s=zohoarc; b=S/HEgglYSguD4yJyp0KSXX2y3zE2E9ds+92VzSY9ZrkNuVJBGhjmKRJyq9W47imeb/iUaQyNtCUmdeaUY82A+NzNYNVBH8L3FxQFAjfezJ1cCQ4L9qxD/TsHrImR52PmGIdYk5Jm5Tg5ivPZsIQKgFRDqrWrzJ/g+pGMJp7upI4= ARC-Message-Signature: i=1; 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charset="utf-8" When dumping the END and NVT tables, the error logging is too noisy. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index c1501a6b5bce..e7acab0dff51 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -27,7 +27,7 @@ =20 #include "pnv_xive_regs.h" =20 -#define XIVE_DEBUG +#undef XIVE_DEBUG =20 /* * Virtual structures table (VST) @@ -172,7 +172,9 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xiv= e, uint32_t type, vsd =3D ldq_be_dma(&address_space_memory, vsd_addr); =20 if (!(vsd & VSD_ADDRESS_MASK)) { +#ifdef XIVE_DEBUG xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); +#endif return 0; } =20 @@ -193,7 +195,9 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xiv= e, uint32_t type, vsd =3D ldq_be_dma(&address_space_memory, vsd_addr); =20 if (!(vsd & VSD_ADDRESS_MASK)) { +#ifdef XIVE_DEBUG xive_error(xive, "VST: invalid %s entry %x !?", info->name, id= x); +#endif return 0; } =20 --=20 2.21.0