From nobody Fri May 3 15:32:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1563263310; cv=none; d=zoho.com; s=zohoarc; b=KAWGefsU/T1Pc4NmvBZqK7H5xrXIOdPD04Eq4zvk9D2ig5zFNawUlVMG4WpfDNg1/95434qssmi+aVhSxjdViixec90aZOXNBWDMAhKLAU9jB56Mv1Qwb4vjCbwjr21uPI3Laid39tjiYwM0aEzuqG9YCYk3UZJ1lowF8Vl/c3k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563263310; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=L+7wO2kOggaUar8Ju9WJ5ZTKW6vOXvHDPTa9uXHWUa8=; b=CLkDVAl6TkL+lohJjVo8YlfilSooXPRxS5/1t/w1Db9d3knR7Dxv0rPcQ0tQcrDr4gj8xthfwz36T4oxtWNoukcnlRYslXf/wINfTbhtA118actN85l1pZy6T/6yNERQ1d9dT1dBC0iTK6gc0yOYLyUnomZU/EemtrUp4q1cxjM= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156326331034960.013615084340586; Tue, 16 Jul 2019 00:48:30 -0700 (PDT) Received: from localhost ([::1]:45978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hnICI-0007WS-UO for importer@patchew.org; Tue, 16 Jul 2019 03:48:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52440) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hnIBu-0006QQ-UX for qemu-devel@nongnu.org; Tue, 16 Jul 2019 03:48:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hnIBt-0000rq-KV for qemu-devel@nongnu.org; Tue, 16 Jul 2019 03:48:02 -0400 Received: from mga04.intel.com ([192.55.52.120]:44116) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hnIBt-0000k5-El for qemu-devel@nongnu.org; Tue, 16 Jul 2019 03:48:01 -0400 Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jul 2019 00:47:53 -0700 Received: from tao-optiplex-7060.sh.intel.com ([10.239.13.104]) by orsmga007.jf.intel.com with ESMTP; 16 Jul 2019 00:47:50 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,497,1557212400"; d="scan'208";a="158066383" From: Tao Xu To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, cohuck@redhat.com, mst@redhat.com, mtosatti@redhat.com Date: Tue, 16 Jul 2019 15:44:58 +0800 Message-Id: <20190716074459.6026-2-tao3.xu@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190716074459.6026-1-tao3.xu@intel.com> References: <20190716074459.6026-1-tao3.xu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.120 Subject: [Qemu-devel] [PATCH v4 1/2] x86/cpu: Add support for UMONITOR/UMWAIT/TPAUSE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jingqi.liu@intel.com, tao3.xu@intel.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions. This patch adds support for user wait instructions in KVM. Availability of the user wait instructions is indicated by the presence of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5]. User wait instructions may be executed at any privilege level, and use IA32_UMWAIT_CONTROL MSR to set the maximum time. The patch enable the umonitor, umwait and tpause features in KVM. Because umwait and tpause can put a (psysical) CPU into a power saving state, by default we dont't expose it to kvm and enable it only when guest CPUID has it. And use QEMU command-line "-overcommit cpu-pm=3Don" (enable_cpu_pm is enabled), a VM can use UMONITOR, UMWAIT and TPAUSE instructions. If the instruction causes a delay, the amount of time delayed is called here the physical delay. The physical delay is first computed by determining the virtual delay (the time to delay relative to the VM=E2=80=99s timestamp counter). Otherwise, UMONITOR, UMWAIT and TPAUSE= cause an invalid-opcode exception(#UD). The release document ref below link: https://software.intel.com/sites/default/files/\ managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf Co-developed-by: Jingqi Liu Signed-off-by: Jingqi Liu Signed-off-by: Tao Xu --- No changes in v4. --- target/i386/cpu.c | 3 ++- target/i386/cpu.h | 1 + target/i386/kvm.c | 4 ++++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 805ce95247..9546a40d8a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1061,7 +1061,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, "avx512vbmi", "umip", "pku", - NULL /* ospke */, NULL, "avx512vbmi2", NULL, + NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, "gfni", "vaes", "vpclmulqdq", "avx512vnni", "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, "la57", NULL, NULL, NULL, @@ -5193,6 +5193,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, &cpu->mwait.ecx, &cpu->mwait.edx); env->features[FEAT_1_ECX] |=3D CPUID_EXT_MONITOR; + env->features[FEAT_7_0_ECX] |=3D CPUID_7_0_ECX_WAITPKG; } } =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 05393cf9d1..19caf82729 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -672,6 +672,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_UMIP (1U << 2) #define CPUID_7_0_ECX_PKU (1U << 3) #define CPUID_7_0_ECX_OSPKE (1U << 4) +#define CPUID_7_0_ECX_WAITPKG (1U << 5) /* UMONITOR/UMWAIT/TPAUSE Instruc= tions */ #define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */ #define CPUID_7_0_ECX_GFNI (1U << 8) #define CPUID_7_0_ECX_VAES (1U << 9) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index ec7870c6af..f8daa13f10 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -390,6 +390,10 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uin= t32_t function, if (host_tsx_blacklisted()) { ret &=3D ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE); } + } else if (function =3D=3D 7 && index =3D=3D 0 && reg =3D=3D R_ECX) { + if (enable_cpu_pm) { + ret |=3D CPUID_7_0_ECX_WAITPKG; + } } else if (function =3D=3D 7 && index =3D=3D 0 && reg =3D=3D R_EDX) { /* * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM h= osts. --=20 2.20.1 From nobody Fri May 3 15:32:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1563263310; cv=none; d=zoho.com; s=zohoarc; b=WwR4F+DdKMduPytI5sPge5khl+fP5GUXmIQulVMYFgje8JOaMzgtI6TAQkCm/TDBwHQWqApw0bO0VjqKj9M38TBB/wLnYoHrpyyyDNUlKfu/qaxhbDmv+SOAHHacvjIOqwsZdAKWa/LPVAYK7HLz+1Uw2hwEoxfABFegDE5tVOQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; 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Tue, 16 Jul 2019 03:48:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52445) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hnIBv-0006QR-AG for qemu-devel@nongnu.org; Tue, 16 Jul 2019 03:48:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hnIBu-0000sn-3v for qemu-devel@nongnu.org; Tue, 16 Jul 2019 03:48:03 -0400 Received: from mga04.intel.com ([192.55.52.120]:44116) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hnIBt-0000k5-Rr for qemu-devel@nongnu.org; Tue, 16 Jul 2019 03:48:02 -0400 Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jul 2019 00:47:54 -0700 Received: from tao-optiplex-7060.sh.intel.com ([10.239.13.104]) by orsmga007.jf.intel.com with ESMTP; 16 Jul 2019 00:47:52 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,497,1557212400"; d="scan'208";a="158066390" From: Tao Xu To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, cohuck@redhat.com, mst@redhat.com, mtosatti@redhat.com Date: Tue, 16 Jul 2019 15:44:59 +0800 Message-Id: <20190716074459.6026-3-tao3.xu@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190716074459.6026-1-tao3.xu@intel.com> References: <20190716074459.6026-1-tao3.xu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.120 Subject: [Qemu-devel] [PATCH v4 2/2] target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jingqi.liu@intel.com, tao3.xu@intel.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" UMWAIT and TPAUSE instructions use 32bits IA32_UMWAIT_CONTROL at MSR index E1H to determines the maximum time in TSC-quanta that the processor can reside in either C0.1 or C0.2. This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in guest. Co-developed-by: Jingqi Liu Signed-off-by: Jingqi Liu Signed-off-by: Tao Xu --- Changes in v4: Set IA32_UMWAIT_CONTROL 32bits --- target/i386/cpu.h | 2 ++ target/i386/kvm.c | 13 +++++++++++++ target/i386/machine.c | 20 ++++++++++++++++++++ 3 files changed, 35 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 19caf82729..e5d4c81926 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -451,6 +451,7 @@ typedef enum X86Seg { =20 #define MSR_IA32_BNDCFGS 0x00000d90 #define MSR_IA32_XSS 0x00000da0 +#define MSR_IA32_UMWAIT_CONTROL 0xe1 =20 #define XSTATE_FP_BIT 0 #define XSTATE_SSE_BIT 1 @@ -1385,6 +1386,7 @@ typedef struct CPUX86State { uint16_t fpregs_format_vmstate; =20 uint64_t xss; + uint32_t umwait; =20 TPRAccess tpr_access_type; =20 diff --git a/target/i386/kvm.c b/target/i386/kvm.c index f8daa13f10..ba0ee01598 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -91,6 +91,7 @@ static bool has_msr_hv_stimer; static bool has_msr_hv_frequencies; static bool has_msr_hv_reenlightenment; static bool has_msr_xss; +static bool has_msr_umwait; static bool has_msr_spec_ctrl; static bool has_msr_virt_ssbd; static bool has_msr_smi_count; @@ -1914,6 +1915,9 @@ static int kvm_get_supported_msrs(KVMState *s) case MSR_IA32_XSS: has_msr_xss =3D true; break; + case MSR_IA32_UMWAIT_CONTROL: + has_msr_umwait =3D true; + break; case HV_X64_MSR_CRASH_CTL: has_msr_hv_crash =3D true; break; @@ -2464,6 +2468,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_xss) { kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss); } + if (has_msr_umwait) { + kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait); + } if (has_msr_spec_ctrl) { kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl); } @@ -2863,6 +2870,9 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_xss) { kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0); } + if (has_msr_umwait) { + kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0); + } if (has_msr_spec_ctrl) { kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0); } @@ -3112,6 +3122,9 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_IA32_XSS: env->xss =3D msrs[i].data; break; + case MSR_IA32_UMWAIT_CONTROL: + env->umwait =3D msrs[i].data; + break; default: if (msrs[i].index >=3D MSR_MC0_CTL && msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { diff --git a/target/i386/machine.c b/target/i386/machine.c index 704ba6de46..861a5c5a20 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -910,6 +910,25 @@ static const VMStateDescription vmstate_xss =3D { } }; =20 +static bool umwait_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->umwait !=3D 0; +} + +static const VMStateDescription vmstate_umwait =3D { + .name =3D "cpu/umwait", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D umwait_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(env.umwait, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + #ifdef TARGET_X86_64 static bool pkru_needed(void *opaque) { @@ -1376,6 +1395,7 @@ VMStateDescription vmstate_x86_cpu =3D { &vmstate_msr_hyperv_reenlightenment, &vmstate_avx512, &vmstate_xss, + &vmstate_umwait, &vmstate_tsc_khz, &vmstate_msr_smi_count, #ifdef TARGET_X86_64 --=20 2.20.1