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X-Received-From: 2607:f8b0:4864:20::42d Subject: [Qemu-devel] [PULL 1/3] tcg: Fix mmap lock assert on translation failure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Check page flags before letting an invalid pc cause a SIGSEGV. Prepare for eventially validating PROT_EXEC. The current wrinkle being that we have a problem with our implementation of signals. We should be using a vdso like the kernel, but we instead put the trampoline on the stack. In the meantime, let PROT_READ match PROT_EXEC. Fixes: https://bugs.launchpad.net/qemu/+bug/1832353 Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 1 + include/exec/cpu_ldst_useronly_template.h | 8 +++++-- accel/tcg/translate-all.c | 29 +++++++++++++++++++++++ 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 536ea58f81..58b8915617 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -259,6 +259,7 @@ int walk_memory_regions(void *, walk_memory_regions_fn); int page_get_flags(target_ulong address); void page_set_flags(target_ulong start, target_ulong end, int flags); int page_check_range(target_ulong start, target_ulong len, int flags); +void validate_exec_access(CPUArchState *env, target_ulong s, target_ulong = l); #endif =20 CPUArchState *cpu_copy(CPUArchState *env); diff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_l= dst_useronly_template.h index bc45e2b8d4..f095415149 100644 --- a/include/exec/cpu_ldst_useronly_template.h +++ b/include/exec/cpu_ldst_useronly_template.h @@ -64,7 +64,9 @@ static inline RES_TYPE glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr) { -#if !defined(CODE_ACCESS) +#ifdef CODE_ACCESS + validate_exec_access(env, ptr, DATA_SIZE); +#else trace_guest_mem_before_exec( env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, false)); @@ -88,7 +90,9 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArch= State *env, static inline int glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr) { -#if !defined(CODE_ACCESS) +#ifdef CODE_ACCESS + validate_exec_access(env, ptr, DATA_SIZE); +#else trace_guest_mem_before_exec( env_cpu(env), ptr, trace_mem_build_info(SHIFT, true, MO_TE, false)); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 5d1e08b169..1d4a8a260f 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2600,10 +2600,39 @@ int page_check_range(target_ulong start, target_ulo= ng len, int flags) } } } + /* + * FIXME: We place the signal trampoline on the stack, + * even when the guest expects that to be in the vdso. + * Until we fix that, allow execute on any readable page. + */ + if ((flags & PAGE_EXEC) && !(p->flags & (PAGE_EXEC | PAGE_READ))) { + return -1; + } } return 0; } =20 +/* + * Called for each code read, longjmp out to issue SIGSEGV if the page(s) + * do not have execute access. + */ +void validate_exec_access(CPUArchState *env, + target_ulong ptr, target_ulong len) +{ + if (page_check_range(ptr, len, PAGE_EXEC) < 0) { + CPUState *cs =3D env_cpu(env); + CPUClass *cc =3D CPU_GET_CLASS(cs); + + /* Like tb_gen_code, release the memory lock before cpu_loop_exit.= */ + assert_memory_lock(); + mmap_unlock(); + + /* This is user-only. The target must raise an exception. */ + cc->tlb_fill(cs, ptr, 0, MMU_INST_FETCH, MMU_USER_IDX, false, 0); + g_assert_not_reached(); + } +} + /* called from signal handler: invalidate the code and unprotect the * page. Return 0 if the fault was not handled, 1 if it was handled, * and 2 if it was handled but the caller must cause the TB to be --=20 2.17.1 From nobody Tue May 7 04:27:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562658774; cv=none; d=zoho.com; s=zohoarc; b=X5ot0sh2XYaWUADRHPHjbzRclPITkCPM1MgoG212lbPfs1o2ZP48xITB8SW18dATEkhfQJsMX7MI4x3u/FGIAELSK6KBhNvvPv9xPNrUUzuIYIX0nLHtTq/DDxHuy0J8tfv6gKcvKHKs+XTedtYaPHr0IFW+l28/y6LeY3CbMeI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562658774; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=cAdcykhsBr9KRoTt+e4UsNPsrOD05Rn6WRA4P8vaXKM=; b=icITCY+AiVub7/4q9bAJjLsLxnDzFVibllPd8lkUhOGMh94RtlXAOym3ayNsfftfT7Pq5kOusn86IyUB3AHr0sKyAdO3WLtKd4TS5drACENrVs965bet3IXtZ8zvql9ZmR/i19gaGc+PHMBjrRHCzsFf3BE6yPRj5qidHtM5KwM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562658774284237.59401738358326; Tue, 9 Jul 2019 00:52:54 -0700 (PDT) Received: from localhost ([::1]:47580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hkkvi-000777-CQ for importer@patchew.org; Tue, 09 Jul 2019 03:52:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52154) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hkkty-0005jh-Tp for qemu-devel@nongnu.org; Tue, 09 Jul 2019 03:51:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hkktx-00012A-W3 for qemu-devel@nongnu.org; Tue, 09 Jul 2019 03:51:02 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:44159) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hkktx-000116-Os for qemu-devel@nongnu.org; Tue, 09 Jul 2019 03:51:01 -0400 Received: by mail-pg1-x543.google.com with SMTP id i18so9010099pgl.11 for ; Tue, 09 Jul 2019 00:51:01 -0700 (PDT) Received: from localhost.localdomain ([172.56.12.212]) by smtp.gmail.com with ESMTPSA id y22sm28237375pfo.39.2019.07.09.00.50.57 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 09 Jul 2019 00:50:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cAdcykhsBr9KRoTt+e4UsNPsrOD05Rn6WRA4P8vaXKM=; b=HYNIrH28ZpPg18i1vmo5d8l1oNT6QxQMUi1kMKAb9z5YjaRQtND+t8FXDt3/cBdw/d 6aHogVRJPt1ij8yvHdcCrSQxnsVNB4bOSv7w2ABVlGpUVnbAmXxRTl6OGSLhANPMAGJ0 mIHshu0+JpHJIARZ69TOiDIgSjUuHmefK/ZFqCxuwUZURspSMJsvF+PbzPJfdPWRfJ3Z nIfwDDxHnybLa3tsgMeDvDr/hZNdh4ZOHY1CPnWSJqdZMeBhNWv6v9DBynSHvKEeegUa cdHtz6f2bBzGRWwDnzv7H8nvlPnFspGdeNkNlbbAthRFVmGNeEVCeb1E2/9N5quYIKoc yczg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cAdcykhsBr9KRoTt+e4UsNPsrOD05Rn6WRA4P8vaXKM=; b=nfV/iZLqIcUAZs7i3QUj+ThiYb6Xs9GK8QfeqV5Eus4/yfhL9AKCfRBUGW5PulAsDW J/J/vu4iHzHBx3CSZ1fRhDEB8ogF9ZEc4/f0CxhWGFaJyPihNt4o4EwCZn3GlZSzarLQ K4Ed8XuubnyWbhSGFaaMTNXe00BnZB8nSuztlI7/TDL/sRBu/3wu+WBOlO21X7G/hoaz hNRDdObzsun817R9hS22TOa42hjaGecvh3c7AquXJq1VJZAt7R2rcQJ5EQ4P1Jc/yHsN DM5xzs+ZQPt4pO03vf9pZ/RGIPWzc6jQFhiLLh92fOFJi6nnJ7hWylrjbBioQt6pyslb XsXA== X-Gm-Message-State: APjAAAVxJPGeVAT9aoCAKq+HCfY5koT9MKKOBA/36NWWdlW3uGScFWQK uBfxwdPO5OjeCW/mqill8kmkzBsaJUnFeA== X-Google-Smtp-Source: APXvYqyrkydOQa+k3S03narlVU4z0XF3EYVXAbW1kEjjxGGVlDID32zUWrvUSv/mxAtelGnEChG8fw== X-Received: by 2002:a17:90a:3544:: with SMTP id q62mr31463542pjb.53.1562658660342; Tue, 09 Jul 2019 00:51:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 9 Jul 2019 09:50:39 +0200 Message-Id: <20190709075042.13941-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190709075042.13941-1-richard.henderson@linaro.org> References: <20190709075042.13941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PULL v2 1/2] tcg/riscv: Fix RISC-VH host build failure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Commit 269bd5d8 "cpu: Move the softmmu tlb to CPUNegativeOffsetState' broke the RISC-V host build as there are two variables that are used but not defined. This patch renames the undefined variables mask_off and table_off to the existing (but unused) mask_ofs and table_ofs variables. Signed-off-by: Alistair Francis Message-Id: <79729cc88ca509e08b5c4aa0aa8a52847af70c0f.1561039316.git.alista= ir.francis@wdc.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.inc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 1f0ae64aae..3e76bf5738 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -980,8 +980,8 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addr= l, int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; =20 - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); =20 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); --=20 2.17.1 From nobody Tue May 7 04:27:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PULL 2/3] tcg/riscv: Fix RISC-VH host build failure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Commit 269bd5d8 "cpu: Move the softmmu tlb to CPUNegativeOffsetState' broke the RISC-V host build as there are two variables that are used but not defined. This patch renames the undefined variables mask_off and table_off to the existing (but unused) mask_ofs and table_ofs variables. Signed-off-by: Alistair Francis Message-Id: <79729cc88ca509e08b5c4aa0aa8a52847af70c0f.1561039316.git.alista= ir.francis@wdc.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.inc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 1f0ae64aae..3e76bf5738 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -980,8 +980,8 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addr= l, int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; =20 - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); =20 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); --=20 2.17.1 From nobody Tue May 7 04:27:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PULL v2 2/2] tcg: Fix expansion of INDEX_op_not_vec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This operation can always be emitted, even if we need to fall back to xor. Adjust the assertions to match. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index c8fdc24f56..6714991bf4 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -90,6 +90,9 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, case INDEX_op_bitsel_vec: /* These opcodes are mandatory and should not be listed. */ g_assert_not_reached(); + case INDEX_op_not_vec: + /* These opcodes have generic expansions using the above. */ + g_assert_not_reached(); default: break; } @@ -438,11 +441,14 @@ static bool do_op2(unsigned vece, TCGv_vec r, TCGv_ve= c a, TCGOpcode opc) =20 void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a) { + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); + if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) { TCGv_vec t =3D tcg_const_ones_vec_matching(r); tcg_gen_xor_vec(0, r, a, t); tcg_temp_free_vec(t); } + tcg_swap_vecop_list(hold_list); } =20 void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a) --=20 2.17.1 From nobody Tue May 7 04:27:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PULL 3/3] tcg: Fix expansion of INDEX_op_not_vec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This operation can always be emitted, even if we need to fall back to xor. Adjust the assertions to match. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index c8fdc24f56..6714991bf4 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -90,6 +90,9 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, case INDEX_op_bitsel_vec: /* These opcodes are mandatory and should not be listed. */ g_assert_not_reached(); + case INDEX_op_not_vec: + /* These opcodes have generic expansions using the above. */ + g_assert_not_reached(); default: break; } @@ -438,11 +441,14 @@ static bool do_op2(unsigned vece, TCGv_vec r, TCGv_ve= c a, TCGOpcode opc) =20 void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a) { + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); + if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) { TCGv_vec t =3D tcg_const_ones_vec_matching(r); tcg_gen_xor_vec(0, r, a, t); tcg_temp_free_vec(t); } + tcg_swap_vecop_list(hold_list); } =20 void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a) --=20 2.17.1