From nobody Sun May 19 06:04:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1562165873; cv=none; d=zoho.com; s=zohoarc; b=dld2vfplGSmfplkvtDbpYfqew+cIC+JdvM+aubNtlaqwY36zgKCb3iubtblc43vN1PmlOCSC91n88ac4Va9VuBbuGkP35dtc+mKNyI7nwAVg404q6WWQIQeVTOmux9STChn+NLnI4CStAX44R/RpLvYGzq8ufenr2CKQinl6rW8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562165873; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To:ARC-Authentication-Results; bh=S4GLaGF27xwxf453XEY/HO48Tcqe+Cu+6xjACrErnQg=; b=ZSWziwtM9hRs3w4E05SwVb/k11K8zUWMfAUrradVNwoW6/QFW33qadgQUIv9IArKuNm3oXEOrywTSn0V5MbyS7D4mY70hWkuszSdkx9/ZdexUHbrA1riG9bmTTZos66uPYGCedoYoA3AVKyIZ9qaZyY+r3qZ3pLm/875QwbBfi0= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562165873689913.6851238862084; Wed, 3 Jul 2019 07:57:53 -0700 (PDT) Received: from localhost ([::1]:36604 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1highg-0003Es-2O for importer@patchew.org; Wed, 03 Jul 2019 10:57:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54850) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1higDj-0002j6-KK for qemu-devel@nongnu.org; Wed, 03 Jul 2019 10:26:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1higDh-0004AC-MH for qemu-devel@nongnu.org; Wed, 03 Jul 2019 10:26:51 -0400 Received: from serv1.kernkonzept.com ([2a01:4f8:1c1c:b490::2]:59405 helo=mx.kernkonzept.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1higDf-00043R-MS; Wed, 03 Jul 2019 10:26:49 -0400 Received: from [95.90.166.246] (helo=tweek.dd1.int.kernkonzept.com) by mx.kernkonzept.com with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) id 1higDU-0003do-OA; Wed, 03 Jul 2019 16:26:36 +0200 From: Georg Kotheimer To: qemu-devel@nongnu.org Date: Wed, 3 Jul 2019 16:26:17 +0200 Message-Id: <20190703142617.21073-1-georg.kotheimer@kernkonzept.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a01:4f8:1c1c:b490::2 X-Mailman-Approved-At: Wed, 03 Jul 2019 10:56:11 -0400 Subject: [Qemu-devel] [PATCH] RISC-V: Select FPU gdb xml file based on the supported extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, Georg Kotheimer Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The size of the FPU registers depends solely on the floating point extensions supported by the target architecture. However, in the previous implementation the floating point register size was derived from whether the target architecture is 32-bit or 64-bit. Signed-off-by: Georg Kotheimer --- configure | 4 ++-- gdb-xml/{riscv-64bit-fpu.xml =3D> riscv-fpu-d.xml} | 0 gdb-xml/{riscv-32bit-fpu.xml =3D> riscv-fpu-f.xml} | 0 target/riscv/gdbstub.c | 15 +++++++-------- 4 files changed, 9 insertions(+), 10 deletions(-) rename gdb-xml/{riscv-64bit-fpu.xml =3D> riscv-fpu-d.xml} (100%) rename gdb-xml/{riscv-32bit-fpu.xml =3D> riscv-fpu-f.xml} (100%) diff --git a/configure b/configure index f2cb9f3c66..462c5a4f1a 100755 --- a/configure +++ b/configure @@ -7581,14 +7581,14 @@ case "$target_name" in TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv mttcg=3Dyes - gdb_xml_files=3D"riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-c= sr.xml" + gdb_xml_files=3D"riscv-32bit-cpu.xml riscv-fpu-f.xml riscv-fpu-d.xml r= iscv-32bit-csr.xml" target_compiler=3D$cross_cc_riscv32 ;; riscv64) TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv mttcg=3Dyes - gdb_xml_files=3D"riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-c= sr.xml" + gdb_xml_files=3D"riscv-64bit-cpu.xml riscv-fpu-f.xml riscv-fpu-d.xml r= iscv-64bit-csr.xml" target_compiler=3D$cross_cc_riscv64 ;; sh4|sh4eb) diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-fpu-d.xml similarity index 100% rename from gdb-xml/riscv-64bit-fpu.xml rename to gdb-xml/riscv-fpu-d.xml diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-fpu-f.xml similarity index 100% rename from gdb-xml/riscv-32bit-fpu.xml rename to gdb-xml/riscv-fpu-f.xml diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 27be93279b..29fa468b28 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -375,20 +375,19 @@ void riscv_cpu_register_gdb_regs_for_features(CPUStat= e *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; -#if defined(TARGET_RISCV32) - if (env->misa & RVF) { + + if (env->misa & RVD) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 36, "riscv-32bit-fpu.xml", 0); + 36, "riscv-fpu-d.xml", 0); + } else if (env->misa & RVF) { + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, + 36, "riscv-fpu-f.xml", 0); } =20 +#if defined(TARGET_RISCV32) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 4096, "riscv-32bit-csr.xml", 0); #elif defined(TARGET_RISCV64) - if (env->misa & RVF) { - gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 36, "riscv-64bit-fpu.xml", 0); - } - gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 4096, "riscv-64bit-csr.xml", 0); #endif --=20 2.19.1