From nobody Mon Feb 9 22:59:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1562037234; cv=none; d=zoho.com; s=zohoarc; b=abXaGxhu0yafDTXHNzj4bGm9AafQAMIoH/Px9dz4eJjymt/Ib3qP+5IQ3VHlu3y3ZZZaXyX26Oqb2LVaxfoxEPbGA8NSSUp7ju/QgZDrM5a4rl3LEYSOO2y2phM/kUdpdUPu0/YOLCy12suQsylsqt+7ngY4qp9/ov285ka/aP4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562037234; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=oHLCG5MMdGrDxZZA+nB0FI6ToWrEbgwYYMLYEbqQAnk=; b=SS5eSCJ6FGATC2Q511c/wkosdYHGPl/zZEubYOi3tjhaE+zr7k+FCtFj6ztfYfbkFFOt7bPJTS5GjzSJQ/TFBH0ZTBkiR6DDYTiN/q/kBhohyYyvspM7NmZTLwEvQznIsrd32zPimWo/YPeh+yzVwISbOJBd142CS6cQHwXX9QM= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562037234409552.5003649468591; Mon, 1 Jul 2019 20:13:54 -0700 (PDT) Received: from localhost ([::1]:47840 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi9Es-0002qU-MY for importer@patchew.org; Mon, 01 Jul 2019 23:13:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34744) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi7Ad-00034E-27 for qemu-devel@nongnu.org; Mon, 01 Jul 2019 21:01:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi79n-0001iy-H0 for qemu-devel@nongnu.org; Mon, 01 Jul 2019 21:00:48 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59196) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hi79J-0001GA-Iy; Mon, 01 Jul 2019 20:59:58 -0400 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 46825307CDF2; Tue, 2 Jul 2019 00:59:51 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-21.brq.redhat.com [10.40.204.21]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 6EC941001B33; Tue, 2 Jul 2019 00:59:45 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 21:58:51 -0300 Message-Id: <20190702005912.15905-7-philmd@redhat.com> In-Reply-To: <20190702005912.15905-1-philmd@redhat.com> References: <20190702005912.15905-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.49]); Tue, 02 Jul 2019 00:59:51 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 06/27] hw/block/pflash_cfi02: Add helpers to manipulate the status bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Laurent Vivier , Thomas Huth , Stephen Checkoway , qemu-block@nongnu.org, Max Reitz , Alistair Francis , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Pull out all of the code to modify the status into simple helper functions. Status handling becomes more complex once multiple chips are interleaved to produce a single device. No change in functionality is intended with this commit. Signed-off-by: Stephen Checkoway Message-Id: <20190426162624.55977-3-stephen.checkoway@oberlin.edu> Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 [PMD: Extracted from bigger patch] Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/pflash_cfi02.c | 40 ++++++++++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 303d225f23..e9eea0ec08 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -101,6 +101,31 @@ struct PFlashCFI02 { void *storage; }; =20 +/* + * Toggle status bit DQ7. + */ +static inline void toggle_dq7(PFlashCFI02 *pfl) +{ + pfl->status ^=3D 0x80; +} + +/* + * Set status bit DQ7 to bit 7 of value. + */ +static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value) +{ + pfl->status &=3D 0x7F; + pfl->status |=3D value & 0x80; +} + +/* + * Toggle status bit DQ6. + */ +static inline void toggle_dq6(PFlashCFI02 *pfl) +{ + pfl->status ^=3D 0x40; +} + /* * Set up replicated mappings of the same region. */ @@ -130,7 +155,7 @@ static void pflash_timer (void *opaque) =20 trace_pflash_timer_expired(pfl->cmd); /* Reset flash */ - pfl->status ^=3D 0x80; + toggle_dq7(pfl); if (pfl->bypass) { pfl->wcycle =3D 2; } else { @@ -229,8 +254,7 @@ static uint32_t pflash_read(PFlashCFI02 *pfl, hwaddr of= fset, /* Status register read */ ret =3D pfl->status; DPRINTF("%s: status %" PRIx32 "\n", __func__, ret); - /* Toggle bit 6 */ - pfl->status ^=3D 0x40; + toggle_dq6(pfl); break; case 0x98: /* CFI query mode */ @@ -374,7 +398,11 @@ static void pflash_write(PFlashCFI02 *pfl, hwaddr offs= et, break; } } - pfl->status =3D 0x00 | ~(value & 0x80); + /* + * While programming, status bit DQ7 should hold the opposite + * value from how it was programmed. + */ + set_dq7(pfl, ~value); /* Let's pretend write is immediate */ if (pfl->bypass) goto do_bypass; @@ -422,7 +450,7 @@ static void pflash_write(PFlashCFI02 *pfl, hwaddr offse= t, memset(pfl->storage, 0xFF, pfl->chip_len); pflash_update(pfl, 0, pfl->chip_len); } - pfl->status =3D 0x00; + set_dq7(pfl, 0x00); /* Let's wait 5 seconds before chip erase is done */ timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (NANOSECONDS_PER_SECOND * 5)); @@ -437,7 +465,7 @@ static void pflash_write(PFlashCFI02 *pfl, hwaddr offse= t, memset(p + offset, 0xFF, pfl->sector_len); pflash_update(pfl, offset, pfl->sector_len); } - pfl->status =3D 0x00; + set_dq7(pfl, 0x00); /* Let's wait 1/2 second before sector erase is done */ timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (NANOSECONDS_PER_SECOND / 2)); --=20 2.20.1