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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.52 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Sy0WFm2MPPX0JE4Sw4IHzF1G+za7ZNoZ8lYBMqWvoGQ=; b=XfDfqNBQrt3zosQ62oDrLackWZ5LGomx+UIqBao3FyccDQqlOYg/KkMNfwM4EPRDHt C45Ls4D6df1CUsmqsaqdMYLRf7jihyD2mfB1ijn/QixfJo9+yktX1756XivbPvtzl5+B +KOagQzU9nhq3RbhuXo4aLTPPWa7b/7UETD8CqDsr3zzWNMT7Mfn9MZCefeyWLwL77XH +rQ8ZdlngHQT4Vs0/UuFPuYDLBsxXgvuhv8LfmwqM2DNo4yYmz7y4a1qOjYKPkyfveyn 0Z4pGaHS4INoBtfgJQwzuCiLhuYrZD2+6SLQ/bNIt7wJYBR0da8ywVWPrveUmAWhZ696 5rkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Sy0WFm2MPPX0JE4Sw4IHzF1G+za7ZNoZ8lYBMqWvoGQ=; b=JZC6N4oCRhSqS2Zg4NMH4pK4E6pfsoV76GOsVpuXZJwNhQqotdjWtnq3dxG+TFAvcP vjDLRlnN674iNeRsJjVCf7+xXwz5eVzPDlQ+9yatfAV7VnSUZ3jqdQnIcaB1zdnKoOOy aCyhIvvjSyLXd6iuQQ5V2CUumsxJkXvKcP6+GJpCG6T8toJhmIfwUaSCkMaTvj311eZa nsPxrSRJVoNr8BZL1hyRzZb5UOYhXA5cqEIYra/AcUT9eqx6sPLRHEoLHU29Wv55NkCe H9X+rXjH9MWNSe5d0io9Za3A0yfyqS6BZaiYXcqxae432YJwwmbAS02GQ+ce7eYxh1v3 z2Ug== X-Gm-Message-State: APjAAAVc854ccGGSlwgBNXmQuc5YiuXlsO7vvOttgp01+9tQReIK+k/e Opsz7cwDvBgzs3Bzn4lR+gfP52RCG9yvzA== X-Google-Smtp-Source: APXvYqwxv60h2OSGZFEwplw032D4NjKucCAlotWWw8hyQnxMEgpVnQDzVYr+Rfle97GV7fR7V55a6g== X-Received: by 2002:adf:df0f:: with SMTP id y15mr13262612wrl.155.1561999193176; Mon, 01 Jul 2019 09:39:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:05 +0100 Message-Id: <20190701163943.22313-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.66 Subject: [Qemu-devel] [PULL 08/46] i.mx7d: pci: Update PCI IRQ mapping to match HW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Andrey Smirnov Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches that of i.MX6: * INTD/MSI 122 * INTC 123 * INTB 124 * INTA 125 Fix all of the relevant code to reflect that fact. Needed by latest Linux kernels. (Reference: Linux kernel commit 538d6e9d597584e80 from an NXP employee confirming that the datasheet is incorrect and with a report of a test against hardware.) Signed-off-by: Andrey Smirnov Cc: Peter Maydell Cc: Michael S. Tsirkin Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Reviewed-by: Peter Maydell [PMM: added ref to kernel commit confirming the datasheet error] Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx7.h | 8 ++++---- hw/pci-host/designware.c | 6 ++++-- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 09f4f33f6e5..8003d45d1e5 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -213,10 +213,10 @@ enum FslIMX7IRQs { FSL_IMX7_USB2_IRQ =3D 42, FSL_IMX7_USB3_IRQ =3D 40, =20 - FSL_IMX7_PCI_INTA_IRQ =3D 122, - FSL_IMX7_PCI_INTB_IRQ =3D 123, - FSL_IMX7_PCI_INTC_IRQ =3D 124, - FSL_IMX7_PCI_INTD_IRQ =3D 125, + FSL_IMX7_PCI_INTA_IRQ =3D 125, + FSL_IMX7_PCI_INTB_IRQ =3D 124, + FSL_IMX7_PCI_INTC_IRQ =3D 123, + FSL_IMX7_PCI_INTD_IRQ =3D 122, =20 FSL_IMX7_UART7_IRQ =3D 126, =20 diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 931cd954e87..9ae8c0deb75 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -51,6 +51,8 @@ #define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff) #define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C =20 +#define DESIGNWARE_PCIE_IRQ_MSI 3 + static DesignwarePCIEHost * designware_pcie_root_to_host(DesignwarePCIERoot *root) { @@ -67,7 +69,7 @@ static void designware_pcie_root_msi_write(void *opaque, = hwaddr addr, root->msi.intr[0].status |=3D BIT(val) & root->msi.intr[0].enable; =20 if (root->msi.intr[0].status & ~root->msi.intr[0].mask) { - qemu_set_irq(host->pci.irqs[0], 1); + qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1); } } =20 @@ -311,7 +313,7 @@ static void designware_pcie_root_config_write(PCIDevice= *d, uint32_t address, case DESIGNWARE_PCIE_MSI_INTR0_STATUS: root->msi.intr[0].status ^=3D val; if (!root->msi.intr[0].status) { - qemu_set_irq(host->pci.irqs[0], 0); + qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0); } break; =20 --=20 2.20.1