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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.53 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=50Y0/N9FaT3fyCQ4ei1ieOLigwzHJFfKxUOH5AH37Qc=; b=ezgFOIiWaFsiUjakxR9OQHxbQNOMixXYVZeEodLQJN5vpKqxAB8kFLM/vhEu47wliy sd/2c0X0Emo/JV5VP9T2PmZ7YQuf3UnHVHm/+5BtSkrD+K1P1XSPEW5J8CouPchsoY9I 16AXu8zYA/sdYkZy63aGRi3ew2j/HknjjjljmSgKR1GJSHbEfTI8cJsHaUpU8EtjGP5Y AbWZg/oLBxoyJ3lsAbZz3H6Gw4OMTj29RBmmGbBvaAxJK152xQVAVF4OamauZVj6Xgll 1wWTsCrpZf0NZgSvHyDa8VY1sKDfOdp9eWoxhPeMvWUstpMhIsFZPoa1eptkuCoioRUb /01A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=50Y0/N9FaT3fyCQ4ei1ieOLigwzHJFfKxUOH5AH37Qc=; b=aUAYg0G7lOHdZNxEObSMwcCgcnh/3KT3h6/XvLRKbgF3bjnUf5miV9WpsZa1/MBBMg ZuVgyo2gaF4g+sWckDJLIxbQPjICewDSt3Uk9suf580+oMU774dojeSH+7eM5gGb/rx1 PaZteTxsCA4yiPSJX+Y9H0Rs6SN+DG1HubmigjwOeS9yoM9Qmdf42nJSUSt1LewC2Tdk dbiBNDIQbUwlEkGEgCkxBhMAwpxUcR638YV+SINIvibqBDgXbnfEo6EklnbQ7LjQPQVC L65dlDRIBETgusO8EIA6lPMAHMPNXVWsUbJuJc0IULd2JKpbrmCN3TLEydSn0HROvsXM Trkw== X-Gm-Message-State: APjAAAXkoata509dBd3aJQj5enlEpI1t0N1oAHwSzu0iGTqxfy//sbzj zLLRR5GVml53zf74nkjis3gMNGk2aIaTGQ== X-Google-Smtp-Source: APXvYqw9xqSnzzF7WTUSd/okUTna5coC6wYiAfv4/BFwwjDMIflrb5K7K5wQMm1eunYgF+uFOd9OCQ== X-Received: by 2002:adf:fc52:: with SMTP id e18mr18897260wrs.14.1561999194144; Mon, 01 Jul 2019 09:39:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:06 +0100 Message-Id: <20190701163943.22313-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.52 Subject: [Qemu-devel] [PULL 09/46] aspeed: add a per SoC mapping for the interrupt space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: C=C3=A9dric Le Goater This will simplify the definition of new SoCs, like the AST2600 which should use a different CPU and a different IRQ number layout. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Joel Stanley Message-id: 20190618165311.27066-2-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 36 +++++++++++++++++++++++ hw/arm/aspeed_soc.c | 57 +++++++++++++++++++++++++++++++------ 2 files changed, 85 insertions(+), 8 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 836b2ba8bf1..963abecb724 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -56,6 +56,7 @@ typedef struct AspeedSoCInfo { const char *fmc_typename; const char **spi_typename; int wdts_num; + const int *irqmap; } AspeedSoCInfo; =20 typedef struct AspeedSoCClass { @@ -68,4 +69,39 @@ typedef struct AspeedSoCClass { #define ASPEED_SOC_GET_CLASS(obj) \ OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC) =20 +enum { + ASPEED_IOMEM, + ASPEED_UART1, + ASPEED_UART2, + ASPEED_UART3, + ASPEED_UART4, + ASPEED_UART5, + ASPEED_VUART, + ASPEED_FMC, + ASPEED_SPI1, + ASPEED_SPI2, + ASPEED_VIC, + ASPEED_SDMC, + ASPEED_SCU, + ASPEED_ADC, + ASPEED_SRAM, + ASPEED_GPIO, + ASPEED_RTC, + ASPEED_TIMER1, + ASPEED_TIMER2, + ASPEED_TIMER3, + ASPEED_TIMER4, + ASPEED_TIMER5, + ASPEED_TIMER6, + ASPEED_TIMER7, + ASPEED_TIMER8, + ASPEED_WDT, + ASPEED_PWM, + ASPEED_LPC, + ASPEED_IBT, + ASPEED_I2C, + ASPEED_ETH1, + ASPEED_ETH2, +}; + #endif /* ASPEED_SOC_H */ diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index a2ea8c74844..de75bf04027 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -38,12 +38,42 @@ #define ASPEED_SOC_ETH1_BASE 0x1E660000 #define ASPEED_SOC_ETH2_BASE 0x1E680000 =20 -static const int uart_irqs[] =3D { 9, 32, 33, 34, 10 }; -static const int timer_irqs[] =3D { 16, 17, 18, 35, 36, 37, 38, 39, }; +static const int aspeed_soc_ast2400_irqmap[] =3D { + [ASPEED_UART1] =3D 9, + [ASPEED_UART2] =3D 32, + [ASPEED_UART3] =3D 33, + [ASPEED_UART4] =3D 34, + [ASPEED_UART5] =3D 10, + [ASPEED_VUART] =3D 8, + [ASPEED_FMC] =3D 19, + [ASPEED_SDMC] =3D 0, + [ASPEED_SCU] =3D 21, + [ASPEED_ADC] =3D 31, + [ASPEED_GPIO] =3D 20, + [ASPEED_RTC] =3D 22, + [ASPEED_TIMER1] =3D 16, + [ASPEED_TIMER2] =3D 17, + [ASPEED_TIMER3] =3D 18, + [ASPEED_TIMER4] =3D 35, + [ASPEED_TIMER5] =3D 36, + [ASPEED_TIMER6] =3D 37, + [ASPEED_TIMER7] =3D 38, + [ASPEED_TIMER8] =3D 39, + [ASPEED_WDT] =3D 27, + [ASPEED_PWM] =3D 28, + [ASPEED_LPC] =3D 8, + [ASPEED_IBT] =3D 8, /* LPC */ + [ASPEED_I2C] =3D 12, + [ASPEED_ETH1] =3D 2, + [ASPEED_ETH2] =3D 3, +}; =20 #define AST2400_SDRAM_BASE 0x40000000 #define AST2500_SDRAM_BASE 0x80000000 =20 +/* AST2500 uses the same IRQs as the AST2400 */ +#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap + static const hwaddr aspeed_soc_ast2400_spi_bases[] =3D { ASPEED_SOC_SPI_BA= SE }; static const char *aspeed_soc_ast2400_typenames[] =3D { "aspeed.smc.spi" }; =20 @@ -64,6 +94,7 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .fmc_typename =3D "aspeed.smc.fmc", .spi_typename =3D aspeed_soc_ast2400_typenames, .wdts_num =3D 2, + .irqmap =3D aspeed_soc_ast2400_irqmap, }, { .name =3D "ast2400-a1", .cpu_type =3D ARM_CPU_TYPE_NAME("arm926"), @@ -75,6 +106,7 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .fmc_typename =3D "aspeed.smc.fmc", .spi_typename =3D aspeed_soc_ast2400_typenames, .wdts_num =3D 2, + .irqmap =3D aspeed_soc_ast2400_irqmap, }, { .name =3D "ast2400", .cpu_type =3D ARM_CPU_TYPE_NAME("arm926"), @@ -86,6 +118,7 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .fmc_typename =3D "aspeed.smc.fmc", .spi_typename =3D aspeed_soc_ast2400_typenames, .wdts_num =3D 2, + .irqmap =3D aspeed_soc_ast2400_irqmap, }, { .name =3D "ast2500-a1", .cpu_type =3D ARM_CPU_TYPE_NAME("arm1176"), @@ -97,9 +130,17 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .fmc_typename =3D "aspeed.smc.ast2500-fmc", .spi_typename =3D aspeed_soc_ast2500_typenames, .wdts_num =3D 3, + .irqmap =3D aspeed_soc_ast2500_irqmap, }, }; =20 +static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) +{ + AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + + return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]); +} + static void aspeed_soc_init(Object *obj) { AspeedSoCState *s =3D ASPEED_SOC(obj); @@ -216,14 +257,14 @@ static void aspeed_soc_realize(DeviceState *dev, Erro= r **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BAS= E); - for (i =3D 0; i < ARRAY_SIZE(timer_irqs); i++) { - qemu_irq irq =3D qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]); + for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { + qemu_irq irq =3D aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); } =20 /* UART - attach an 8250 to the IO space as our UART5 */ if (serial_hd(0)) { - qemu_irq uart5 =3D qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]); + qemu_irq uart5 =3D aspeed_soc_get_irq(s, ASPEED_UART5); serial_mm_init(get_system_memory(), ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2, uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); @@ -237,7 +278,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE); sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, - qdev_get_gpio_in(DEVICE(&s->vic), 12)); + aspeed_soc_get_irq(s, ASPEED_I2C)); =20 /* FMC, The number of CS is set at the board level */ object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); @@ -249,7 +290,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, s->fmc.ctrl->flash_window_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, - qdev_get_gpio_in(DEVICE(&s->vic), 19)); + aspeed_soc_get_irq(s, ASPEED_FMC)); =20 /* SPI */ for (i =3D 0; i < sc->info->spis_num; i++) { @@ -297,7 +338,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE= ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0, - qdev_get_gpio_in(DEVICE(&s->vic), 2)); + aspeed_soc_get_irq(s, ASPEED_ETH1)); } =20 static void aspeed_soc_class_init(ObjectClass *oc, void *data) --=20 2.20.1