From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562015934; cv=none; d=zoho.com; s=zohoarc; b=lH7dr94VoKqGabuUHfqD9RIuMSTWPSaZ0NBTGwZ50WvUItL9RW+wl4548G/En9995nmr4XoN9UyK8RRwR/dmQ9PaZESTsOYC1L1424g1vovEDp0aCTxWJ01/Dvw3jN+S3PTKW6EW1RU9PzwkXEGXHB1olC8ErmAPMGVmze88ywQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562015934; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=+7unfHKTxn3c2hGaVv4Q2qP6l53QsTHsGlRUyP5LU9c=; b=L58AuRVOf9mSQeZ74E3mWkRq76YgEmqDoaOgNkC4x15kFL9mQLwuhPpvr1LpL/IhyvSjRmsoh/z5NFBohSifS85Hc9XsbxIIqrjw48UWAur3MepjX0I++VCi41AuWpqSxnkOxKjiiccSqJrFTnpi3Q3FHuXw+KKqMVRR7iqyRDM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562015934357160.72377864882094; Mon, 1 Jul 2019 14:18:54 -0700 (PDT) Received: from localhost ([::1]:45610 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3hN-0005j9-9Z for importer@patchew.org; Mon, 01 Jul 2019 17:18:53 -0400 Received: from eggs.gnu.org ([209.51.188.92]:45833) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3FR-0002RV-N0 for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:50:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3FN-0002HZ-Jy for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:49:59 -0400 Received: from mail-wm1-f51.google.com ([209.85.128.51]:50956) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3FN-0002Cr-BY for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:49:57 -0400 Received: by mail-wm1-f51.google.com with SMTP id n9so838463wmi.0 for ; Mon, 01 Jul 2019 13:49:46 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.45 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+7unfHKTxn3c2hGaVv4Q2qP6l53QsTHsGlRUyP5LU9c=; b=JNkzR0iGBGjjf6e8ygg+wjGKfO3n3XNjfWA//2X/iZj9L5xnYBe1q1WxphqrM2moCO kWYIoKVj0Uu8YRIINd4nC0uIpyiadDK7D0BYgIMHiSQRMNm3rQHZ9Nrpdq+yan3lBaPa ENuW/sPBQD6X3N8xiSY285kt2ZERkf3D6NEOhTG4iLvMe5Q80TKkRWmZxAupb5Ck+hUF IzmvvNzfxHLQnPpyK6SGDlpMsnOZ3NF1P0HnXF3w9LSuaUgGJ29oKnYqri2cw47oouQU hobZ9pssvW+V4RxKSNKTLbCZuw+ksB2+Qvpog2BU34rr5a4vP3gWm/f8BlnVWMaZmcqs 9aXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+7unfHKTxn3c2hGaVv4Q2qP6l53QsTHsGlRUyP5LU9c=; b=CXjHFuwWEA2c2uNPpAgI66NwpNYETy7518+n+c3EOMBlDdN9S0/j4l4QWyaCXWl0/N DXDNd6YTXyEFJ8sR8MjsAZyvMzo1jZ9wHteuIq4dyVxxz3GC1a/30o1Cg3ENwqvMD0KW ToT8IPMkGn3vuOwExkNjSv8n0bcaBkjIVmnKaDxLMyiUwmdFuSTINiMIQYq7zIBmpJXp k9dEQ2Mlj+6J5aPQPmraJOphsf86z4JNXkQB7pE+iSP93FYlYIjjwS07TOdXiPGk/1nA aiy4ovkqNZf1pZVNOxlYc4BzJWdMciWJLMoAoMMKH7d4IO8wFXL+Ya/6aVCLRndreWHP n0cg== X-Gm-Message-State: APjAAAUFWMMad0FlpJxwYEOKMkeq52UXtVofzOeREJBOrdIrBmiTsQn8 GvPVCw4LP8CiKs8LLCmxV/RnnexNizm3AQ== X-Google-Smtp-Source: APXvYqyNf3bw12HSw7FLP1cc3DdxCj3oA68IVlM4Lcq9TZNifUN/kk8GU3FWIa45RScAnWZ7bKOjEw== X-Received: by 2002:a1c:1f06:: with SMTP id f6mr145598wmf.60.1561999186444; Mon, 01 Jul 2019 09:39:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:38:58 +0100 Message-Id: <20190701163943.22313-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.51 Subject: [Qemu-devel] [PULL 01/46] hw/arm/boot: fix direct kernel boot with initrd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Andrew Jones Fix the condition used to check whether the initrd fits into RAM; in some cases if an initrd was also passed on the command line we would get an error stating that it was too big to fit into RAM after the kernel. Despite the error the loader continued anyway, though, so also add an exit(1) when the initrd is actually too big. Fixes: 852dc64d665f ("hw/arm/boot: Diagnose layouts that put initrd or DTB off the end of RAM") Signed-off-by: Andrew Jones Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190618125844.4863-1-drjones@redhat.com Signed-off-by: Peter Maydell --- hw/arm/boot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index b2f93f6beff..1fb24fbef27 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -1109,10 +1109,11 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cp= u, info->initrd_filename); exit(1); } - if (info->initrd_start + initrd_size > info->ram_size) { + if (info->initrd_start + initrd_size > ram_end) { error_report("could not load initrd '%s': " "too big to fit into RAM after the kernel", info->initrd_filename); + exit(1); } } else { initrd_size =3D 0; --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562031395; cv=none; d=zoho.com; s=zohoarc; b=ck8THyUFNnlsO8BTC0YDsfUGnCyaFgjk9L6FnTqoJfH9j00SH5HxI2wtoIQ4e29iYWZjgQz+z9giRdMMt1i20rtlLri9Db9a0gXM4yiv3t3lGuAiVS2ywIO6GD3sxiNXUJsdFVEvnJdmWLv8qvpBEJPEYoUkGONsUNofXWqSYUY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562031395; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=sudBZzt6fCQJ8cQwNMK19XbmjoKhOxFTcvcuBuImuhY=; b=YKMriU62gh9kbpAUT64rZm7FruNyxSChurowSEId1uc3RyHo+u9qN4FW8D7TiQ/l33JYA2aeEAnSTrvPeuD/iuzw+lOLGzjuBMw4UcE+7DQdJNWA7v01WTRmxg2egnaBH9O2RfbFXBsq5yuAy/SMlCjVn9CoRz9t+AuUiPeEv8g= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562031395180796.5275904055854; Mon, 1 Jul 2019 18:36:35 -0700 (PDT) Received: from localhost ([::1]:46912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi7if-0006nP-8u for importer@patchew.org; Mon, 01 Jul 2019 21:36:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46704) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3wd-00089P-BT for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:34:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3wb-0001wb-HE for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:34:38 -0400 Received: from mail-wr1-f44.google.com ([209.85.221.44]:45290) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3wZ-0001hR-EU for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:34:36 -0400 Received: by mail-wr1-f44.google.com with SMTP id f9so15332764wre.12 for ; Mon, 01 Jul 2019 14:33:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.46 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sudBZzt6fCQJ8cQwNMK19XbmjoKhOxFTcvcuBuImuhY=; b=sgrqr4xI0PlW1BJh2TX9dQ3LR9+J6c6sCrB9Lr8rp4MfRV0yOypHdy+fkNxJD9g7ZR mLAcNFodJ1temny1x38kcVxvXvEN/vzm2Xk3J5/oIzegowOE8noDuZ8YXtAcxS93ItUU D405K1j1Y1P5M16lciJ4SqVjIo8+bifhPhgpFyrnqF39I+xUoiNIp1OtLmRpLw5VA7vW FC/3EgYPnBmo8DCl4R/EXpMWsqQ8HiZSRD5VzEhKWATRImxZQyhC+fnGFl34oEjiTsLc 8XCdIGGMvTIxL71cM8qUlozc6Xc/zf2QPuTY1q7/wNIKYAt7ceiRrBcoqrWCrvQCiZXA nj5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sudBZzt6fCQJ8cQwNMK19XbmjoKhOxFTcvcuBuImuhY=; b=hTOqRZegKMRDA+2JeAF6DkJVJC+o8ahk9U0pSk7xEZQj502dsgI5pdwz8WmeMsgeVW u0Q7ccacJ57RGQd9EnJ9a6gNLW61cwxPKA7mX7f5KoQqo6r0z6uMkI2TnaO9jigo2hui VyPWRfxDvloQHBWFIwsvNjyz0TvnQuOXMVU/jGwezMB3Iu8q0ZjeSJ2vO2nLmcaD7x6h f8bOyuZFMZo6Y08e9dupA98VwZqJ05njV0ca3Fj42MM6LS/YwQG6YDVMLmbRIj5g8gOH 2FXXRGjs9KVxR+IVjy5dL2b2GsicOV1Uz543AXZNJ2JxcdVYgKXZA2QgWpvnmMJJ/VeL DyLQ== X-Gm-Message-State: APjAAAVJksdIrgJkcCLydENaZ6UbyIV5zoi8KILM+OFAqxSNn1zMzl4p TbgXYI8/KDejt8Y2JNvgzjajVFgc0SuFQg== X-Google-Smtp-Source: APXvYqwH6x9DwXKcyIsoA/fOdzUSaJ7+QluDE2uy9psM+F7wMX7v+AuVXPNSI84rCbXPcTYFuHduLg== X-Received: by 2002:a5d:4941:: with SMTP id r1mr19002429wrs.225.1561999187548; Mon, 01 Jul 2019 09:39:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:38:59 +0100 Message-Id: <20190701163943.22313-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.44 Subject: [Qemu-devel] [PULL 02/46] hw/arm/msf2-som: Exit when the cpu is not the expected one X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 This machine correctly defines its default_cpu_type to cortex-m3 and report an error if the user requested another cpu_type, however it does not exit, and this can confuse users trying to use another core: $ qemu-system-arm -M emcraft-sf2 -cpu cortex-m4 -kernel test-m4.elf qemu-system-arm: This board can only be used with CPU cortex-m3-arm-cpu [output related to M3 core ...] The CPU is indeed a M3 core: (qemu) info qom-tree /machine (emcraft-sf2-machine) /unattached (container) /device[0] (msf2-soc) /armv7m (armv7m) /cpu (cortex-m3-arm-cpu) Add the missing exit() call to return to the shell. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Eduardo Habkost Message-id: 20190617160136.29930-1-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/arm/msf2-som.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 8c550a8bddc..2c9984bb3b8 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -53,6 +53,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { error_report("This board can only be used with CPU %s", mc->default_cpu_type); + exit(1); } =20 memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE, --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562030809; cv=none; d=zoho.com; s=zohoarc; b=kH6JgpOrYkxqbj2jTb9U/MyFl+OcHo963ObkGl8oXK283/he2bhnricG0cNpc6/iHMUcdhUAiC6xbHRUosK1h1A8Ucxe3RgQ7e+NyTzJzX5synFWU2HybiRKF71KuEc4mXjcAsSzrX+t86l7eLf/O5sdulZCLwHp+WwvpI8cB24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562030809; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=5CvhAR9JL3XvS1viNpt8Z+O+QAfXPREE5z2qgUjmg2c=; b=IDmCHyIYnp5SnGAMT9Lp+OVwgC9SZTzPQ9hn3MF1rY9PlfQliQ9axclPTmdR+DrlBH0G7gMahwGnMbGsL37GWi206uSDwJNBUJVwkLC/yFi1xWHFXjl9sMqz97bmoOaKRRxjOD7oeQ6yRT48/ZNgChU0kI5OC+eERSwyZy7oNTc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562030809219910.1361808541582; Mon, 1 Jul 2019 18:26:49 -0700 (PDT) Received: from localhost ([::1]:46820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi7ZG-0004nT-8e for importer@patchew.org; Mon, 01 Jul 2019 21:26:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52660) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4CN-0006hw-HO for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:50:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi4CM-0004n2-HI for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:50:55 -0400 Received: from mail-wm1-f53.google.com ([209.85.128.53]:52118) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi4CM-0004mY-6A for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:50:54 -0400 Received: by mail-wm1-f53.google.com with SMTP id 207so948891wma.1 for ; Mon, 01 Jul 2019 14:50:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.47 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5CvhAR9JL3XvS1viNpt8Z+O+QAfXPREE5z2qgUjmg2c=; b=yvNFfoLsjCGbWdM+B6GYebsDQUlcOtkTMbxyZqRnMYiJV5tJZo+s9JtnP1QVutl1Dn YDc66fO6n2+uEEyBr4xYwc+HXUWjJ5s4nfGbBkIoAyy9FNhqf01YncAHUYo0lzUi9qKC skhcsPTRRJ+KgHHlE8BRl7UQCkKUUsD4YxgtlGvj9cF/nuuXIQqT4a6fvFKL3SfWIpbv nEzoldofboalAYt32QkZMwVj1Ik16euRq7nR3Bwb29aOYMLmv5Dgh4wepp/HU/cmhDYL Hglz8OTR8Ip5NBhVtP/YilHaNGFLy3IwvD8Q1ULKtJQ9onORpKkNuxDBkonjHWO7bdRO 7bcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5CvhAR9JL3XvS1viNpt8Z+O+QAfXPREE5z2qgUjmg2c=; b=TfYVFnEEBMq0kZRzUv2kstbcc0MTs/bG29G7pL0GiQWRw2NXk0CwPM5EeQIkdvq8YP PZuGvHQqs+KAHaOCRaiERCFk4wGd48woGBG8tj10Hy9djMAh6R4UVPqLKfaq0a4URtiW VXuUttK9XUySGvinKZtM0lbayIW6G5UcOFAStS6yLumkdM0KqOYM+T5AuCv5EcUJy1cO /HsV4eCAxGeUIN72qnHnqPxaH/VRKD9hLW3nPDtgQ3/Exn29iSd7UKqZPFvcgKexQhSD ofAF7gQdUhEp1OOidK2Z3zJSJfDUTWEdqY0ATEZ7UKDVoUhd/H7qSOEaQr2D6wy3JHlZ J/lw== X-Gm-Message-State: APjAAAVhbLAYyU4ZBeYbVb1DWTi/IWHE73xVXVYN6IREYZkcwEowoTs6 /1F1IYlitHSV//GI+pLB9aMOlJqWVipHsQ== X-Google-Smtp-Source: APXvYqxGZJIjcK0maWtnOqNPFfxP51OnvFqKm6vC5UwPt6g31XITmyc0rlVTDP/XB3J3A8i1hy3f7g== X-Received: by 2002:a1c:e108:: with SMTP id y8mr112360wmg.65.1561999188397; Mon, 01 Jul 2019 09:39:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:00 +0100 Message-Id: <20190701163943.22313-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.53 Subject: [Qemu-devel] [PULL 03/46] hw/arm/virt: Add support for Cortex-A7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Jan Kiszka Allow cortex-a7 to be used with the virt board; it supports the v7VE features and there is no reason to deny this type. Signed-off-by: Jan Kiszka Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: fc5404f7-4d1d-c28f-6e48-d8799c82acc0@web.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 431e2900fd2..ed009fa447c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -176,6 +176,7 @@ static const int a15irqmap[] =3D { }; =20 static const char *valid_cpus[] =3D { + ARM_CPU_TYPE_NAME("cortex-a7"), ARM_CPU_TYPE_NAME("cortex-a15"), ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562032717; cv=none; d=zoho.com; s=zohoarc; b=Z2WkG4mRK1H+NWIN1I3MoFTXsVK1UP/8wtw5WiTQYYd0FKFuR2LvNOH/SSmY82HN0eaDJy0Hc+ryLbIYwu9Bc03tAfpG0aYbsX0B7z58pd6hz4f/M7decxTBoUVPwoM70eh621mgT+XIDM6ZBTfmZZCyb22PXWvH69JUCDVTbfY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562032717; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=hD++A+b60c+NWWs//dc/hO0mhFB2lXMUgW0Rk7HhCUs=; b=dDNO+t8JMenNxOrVLel8Plk3hVamKkbp9LTZ4xh/+RE0r8yhE/eKXk8wAFP4LyWCeuTnM6hvlbDPQtmNSgLxT8uftrrSlkIaZrC1Cy8lyb2xNHITPW3x9jDJ4AVnC6i+LrLAuvzpy5LXl76WWgTBAn8j6WDjnImexKfrNoV4q+A= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562032717080365.0903078858378; Mon, 1 Jul 2019 18:58:37 -0700 (PDT) Received: from localhost ([::1]:47070 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi841-0004ir-UI for importer@patchew.org; Mon, 01 Jul 2019 21:58:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53552) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4GO-00084x-MY for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:55:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi4GN-0006Mp-HX for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:55:04 -0400 Received: from mail-wm1-f52.google.com ([209.85.128.52]:52596) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi4GN-0006Ld-9n for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:55:03 -0400 Received: by mail-wm1-f52.google.com with SMTP id s3so951591wms.2 for ; Mon, 01 Jul 2019 14:54:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.48 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hD++A+b60c+NWWs//dc/hO0mhFB2lXMUgW0Rk7HhCUs=; b=ThIts78IEayGhVVTq3zLoFOLx0+Cor7bh+IkeOmhrKfVqUJtsAE5VUlL8+sNUK3+mV /Xl07I7yPiKE9Us6zgB8M3d4tSKUMKNqqqwFrLAASgkvMAJuOVYLAhMcAdoU782m+stJ CMG16B7V6gmL0Q6RktSpuzAoVuf6W2n1UJEshE71tfn/HmNJVRgc1cknOzZFK/43pr08 Dy4Xiu6nhxcZSNpb3a7gL+D9kB0sOtJfnJxSvSERxYM8qay8fsLdSqeKwwyqh35y54Uv 2Zkm0+ZHRi+9EzYtyTBpRK/o9MDnt8ge6mNpDtL89oCwvyU2ZqrpaQP8M3z+DTQ1jct8 qbcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hD++A+b60c+NWWs//dc/hO0mhFB2lXMUgW0Rk7HhCUs=; b=ixFL69ma4f0OkQbuWe3UYuVIpYqMn5c/bhMLEHZPRFx5uYF5htqHMq85pYxbohd2JV 2h2gb/PAOoWati86o7Pb+W6Gjf0fqHDdpmPRsGAR/nJB7NKpppe2KShwQIQ9cQObR1cU YGjB3VHSpgLVOB2vKcIwngv5BmCG2g7jJ59uMdvo6vWXBFw23AiWIwdsP9Mrj/flAwya hlrpEeJrMz4d0WwcoZNrmjgLvYjL3Squuk+QKiZ1v3uosEuRrlIGxyE9mQb8lmCmT8aq ZASZQC4dJAfgW0kPPFEDnVh8Iix+4+Fwg6Lc74CeGMPub+1cvVxldMLwlm0JtMNW5xvy snHA== X-Gm-Message-State: APjAAAUCkcs+arSd47Bp4T+t1fzS0VNYFlAT1tkOLdFJHqbOiaTnPC43 30mhH7g+bTbOi+7wuya8iv5lPLUcie69wA== X-Google-Smtp-Source: APXvYqyVY+8sHA+iP8Dd2z8NDXsIhjO48baZz3w3DKfBgJUz7lNvyAoQcwJHxukdp2W6oCnPL++qZg== X-Received: by 2002:a1c:c545:: with SMTP id v66mr122796wmf.51.1561999189206; Mon, 01 Jul 2019 09:39:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:01 +0100 Message-Id: <20190701163943.22313-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.52 Subject: [Qemu-devel] [PULL 04/46] i.mx7d: Add no-op/unimplemented APBH DMA module X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Andrey Smirnov Instantiate no-op APBH DMA module. Needed to boot latest Linux kernel. Signed-off-by: Andrey Smirnov Cc: Peter Maydell Cc: Michael S. Tsirkin Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- include/hw/arm/fsl-imx7.h | 3 +++ hw/arm/fsl-imx7.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 4101f80251e..dcd73603c33 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -179,6 +179,9 @@ enum FslIMX7MemoryMap { FSL_IMX7_PCIE_REG_SIZE =3D 16 * 1024, =20 FSL_IMX7_GPR_ADDR =3D 0x30340000, + + FSL_IMX7_DMA_APBH_ADDR =3D 0x33000000, + FSL_IMX7_DMA_APBH_SIZE =3D 0x2000, }; =20 enum FslIMX7IRQs { diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index b7e3526b4f3..803fe94c034 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -526,6 +526,12 @@ static void fsl_imx7_realize(DeviceState *dev, Error *= *errp) */ create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR, FSL_IMX7_LCDIF_SIZE); + + /* + * DMA APBH + */ + create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR, + FSL_IMX7_DMA_APBH_SIZE); } =20 static void fsl_imx7_class_init(ObjectClass *oc, void *data) --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562033794; cv=none; d=zoho.com; s=zohoarc; b=XnkzKVzW4ePg12yOe2IlBzU7w80GeoxhkmpzXkUF8gJx/J4JBRtV3LgU5LKHkFf4a1ltX8USnCyAJMie9jLL2CkiTFv9UNWvLZsuH/4JMtVTuC8oWB5EEbW7HgDGIg4ipY8NkVAN3k5UKU7PD7LRM+epf0+7ayljlBeo4hKVlMo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562033794; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=FU2Y0liu1lAY21ffJv7mbpvtLv+zwcB4gkTn/owodzc=; b=hptSKSH1Y96wbxDnOrD8M1quNouX+jHQG/n3SVJ7vLcQL0EIttH3DuIc6p3RZFtgWlkgIhHHTU/oZYKJ1hx5OHymApPK1EIc9oIRxCdKHYDLoKIawL8HyF4jY3auaq1PNr186pLsK05Cdqu5h1NvJadPu5nmbh/eoJTSrUnPu8M= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 156203379423473.15564449887711; Mon, 1 Jul 2019 19:16:34 -0700 (PDT) Received: from localhost ([::1]:47154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi8LJ-0003FF-5u for importer@patchew.org; Mon, 01 Jul 2019 22:16:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55415) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4MF-0004EF-9J for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:01:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi4MD-00007B-Ir for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:01:07 -0400 Received: from mail-wm1-f44.google.com ([209.85.128.44]:40145) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi4MD-00005C-9E for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:01:05 -0400 Received: by mail-wm1-f44.google.com with SMTP id v19so1068524wmj.5 for ; Mon, 01 Jul 2019 15:01:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.49 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FU2Y0liu1lAY21ffJv7mbpvtLv+zwcB4gkTn/owodzc=; b=dTYZuzRqznkL1JWXiXhXsfzH6vrFZSAfYuUAxXz14yzh+XhdihHx+yiIemFyuvKftu /uXJx/Bzq2Aa1hr+hFIUDh9KNXSqu7R/0BpJrXB1uVLAR+Xmr3DO2KJ3b9GA3b/s7cjY kczeZT2svdsUWUs9wN8b0rmT8u5sJ5N3f0Z4zMXK37F81BT8u/wglyW/9Gjv/AUF8u08 zhWmISA25oWJ5HLtleVC+Tlr+Eyxy7neAOgzVlSiRRemVuB14zLotZFBL075zLv3Q/hZ YQj6fjBu4YUiZbi5Yj7CAWb/HlPQ1Hz3TTFAt1WCzF1SVktUC7ayCcyPBtaVZzE4xj5b bYgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FU2Y0liu1lAY21ffJv7mbpvtLv+zwcB4gkTn/owodzc=; b=DQiZhyQo5bZy5V4Tmp8jnKv1Mr8LY18BFr9tYhRVQKFIEZ8iTpHVjsmaav40XfA9ao L+/oLoZtg5kFKK+IXA4z2JGh46sgQZyi1qtjyuhHlJNgfYrHRRdnkrZuVvMmiruXEXf1 JTpCk7hjA7PmlaUJyHZxRc1bGseaJaskF32x6uuXgrFPN936XnZc7oSV6dyPUWQKPCGs fbixyLYISpueKKLFn5abeXnerjFz6MkPkaB9EhW8e4b8i+rhwM8fY8/QkrDyoDqRiZSE ufAc7mHBGE70CFJZfq7Qn1lj/HKEqAROD6Q7c8fxoyeV8zTUBCmMXutGD6y6yTfC2mx5 228w== X-Gm-Message-State: APjAAAU8cYJd9dskPsH1P8WcKtnMAc+WZHGQ0GWv8Ff8z6yehKzGPGii T5ImJscxw3ocZH+5Fbi0ngksn8fwT/kAoA== X-Google-Smtp-Source: APXvYqxqJE48jegwRpLdka4IArNOqs/boilwqQAw4ipEBofAAVhLQw5EesHmbTfm9PPKm/rVSqDkCA== X-Received: by 2002:a1c:700b:: with SMTP id l11mr132471wmc.106.1561999189993; Mon, 01 Jul 2019 09:39:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:02 +0100 Message-Id: <20190701163943.22313-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.44 Subject: [Qemu-devel] [PULL 05/46] i.mx7d: Add no-op/unimplemented PCIE PHY IP block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Andrey Smirnov Add no-op/unimplemented PCIE PHY IP block. Needed by new kernels to use PCIE. Signed-off-by: Andrey Smirnov Cc: Peter Maydell Cc: Michael S. Tsirkin Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx7.h | 3 +++ hw/arm/fsl-imx7.c | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index dcd73603c33..09f4f33f6e5 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -125,6 +125,9 @@ enum FslIMX7MemoryMap { FSL_IMX7_ADC2_ADDR =3D 0x30620000, FSL_IMX7_ADCn_SIZE =3D 0x1000, =20 + FSL_IMX7_PCIE_PHY_ADDR =3D 0x306D0000, + FSL_IMX7_PCIE_PHY_SIZE =3D 0x10000, + FSL_IMX7_GPC_ADDR =3D 0x303A0000, =20 FSL_IMX7_I2C1_ADDR =3D 0x30A20000, diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 803fe94c034..2eddf3f25c6 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -532,6 +532,11 @@ static void fsl_imx7_realize(DeviceState *dev, Error *= *errp) */ create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR, FSL_IMX7_DMA_APBH_SIZE); + /* + * PCIe PHY + */ + create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, + FSL_IMX7_PCIE_PHY_SIZE); } =20 static void fsl_imx7_class_init(ObjectClass *oc, void *data) --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562029958; cv=none; d=zoho.com; s=zohoarc; b=Vv0IPMBn+VwsAl4bES0acIGebuTKBWSaVf/jCRZur6UgBH0KmcB59HkJWuktgjhGDmjoWQp+FnCdHSPcBWPxSVKn8hnxVhMPGimsyCdJn0J0q5vpldMNeb8o8ODlyw1JYXBBVUa2M074kgnBXTLdTCeZ4Nge6zDpMrvSmOqwD/w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562029958; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=rnHrhKlg4rPjTPEn7YeLUI7OUdliTbLuOiEfOpcbWYc=; b=IFlmdvxQEVLTU69CO/RZjWEX6nEU6U+/CMzh6svFba2tB+JymX4ICi3v2CAHwKhuemDhS9zoJUBgAmovCJoXjkAgCT7uDqqOgK8gk+B0Z3Sf/nk2/SXLhvjUMerw5PlXV0m9ckTGFLqf210M11b7VvGuNsb5Zz5I4mOljPjJYZI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156202995886780.51796775885498; Mon, 1 Jul 2019 18:12:38 -0700 (PDT) Received: from localhost ([::1]:46700 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi768-0000Qu-SG for importer@patchew.org; Mon, 01 Jul 2019 20:56:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48855) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi42m-0006kp-Rd for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:41:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi42l-0004on-Pf for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:41:00 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:43714) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi42l-0004nU-Id for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:40:59 -0400 Received: by mail-wr1-f66.google.com with SMTP id p13so15363850wru.10 for ; Mon, 01 Jul 2019 14:40:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.50 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rnHrhKlg4rPjTPEn7YeLUI7OUdliTbLuOiEfOpcbWYc=; b=t5zliwsZ5Hwp0hVTa/zzs3QODp6L6rpRk23Kf6qKZb61KucKyX/GI43dj18RRcwGBx L3B69Gp87ycvZq9Uhi/5B6t6KXlfEhrCYPeN/B8xlUO6GWSdYjo7IRSCyITpPmVMBXcx s/2FMSY4zo8tAWNsLD9P5a6woiggfO2So2y/EOwzTp1N7FYL8W0quimlhiXJYFppqLbt B0yjGhmwCoRUJMVknYNctLYGMm0b1LxCeulJxcuMeQLxQ/Cq/AhEombVyN6w+dUy41/c bowumHeP7mDPT1gEyRg7N2pwn1qD/Eyjo0gUhrJjiSlTq7NORcnMO5gjfD3TeFh3tS9W I7fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rnHrhKlg4rPjTPEn7YeLUI7OUdliTbLuOiEfOpcbWYc=; b=WkbYA1aCj2rwGOap46NWJmmTB3rbUarARw5AS7q2ZQ0BNedgQCoEmi9s6eUSQzSK5g ejQmiF2rJBmnW4g7c/+1nhD1m3Gd43OiixJJ/w7QPBjzkuB5wh19gbMS+q4HJxbl4zVq QXXDwiAD7ulrBh3DRiHkv/0+WXX7cjsJyPsgAtWgBhCn1GwyYNBJs/ZFN5p74pmwfDA4 +SqRzpQ7yPFVMtP3EX8mS/1LmnFMQLsyYx6EMBzwp6ADmLq3TSGyFCEDbciLpvbWHUcM bEgjzski6eMfdoRZZBxSyAiLyVCrfrF0AxMhaaCFg0/sFTAvBwaiNJg7A6IzaOdHqeAJ C95A== X-Gm-Message-State: APjAAAVDRG2+9XUIhzBq6SciFc59Zdo0U1HHYoxFu2pH6+977EkTVS77 K0OptQCCh859tl/U1ao3kKD7v3X+NXj8xA== X-Google-Smtp-Source: APXvYqzSnavuc+sA/3DP4G5/6vuE2nV96qOE/ItV/ZSfDLX8NXq0J5edWyx2UEhIis/aDfYkizou+w== X-Received: by 2002:adf:f042:: with SMTP id t2mr6306647wro.299.1561999190855; Mon, 01 Jul 2019 09:39:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:03 +0100 Message-Id: <20190701163943.22313-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.66 Subject: [Qemu-devel] [PULL 06/46] pci: designware: Update MSI mapping unconditionally X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Andrey Smirnov Expression to calculate update_msi_mapping in code handling writes to DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should be: !!root->msi.intr[0].enable ^ !!val; so that MSI mapping is updated when enabled transitions from either "none" -> "any" or "any" -> "none". Since that register shouldn't be written to very often, change the code to update MSI mapping unconditionally instead of trying to fix the update_msi_mapping logic. Signed-off-by: Andrey Smirnov Cc: Peter Maydell Cc: Michael S. Tsirkin Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Acked-by: Michael S. Tsirkin Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/pci-host/designware.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 0fdfff57848..ec697c8f9df 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -297,16 +297,10 @@ static void designware_pcie_root_config_write(PCIDevi= ce *d, uint32_t address, root->msi.base |=3D (uint64_t)val << 32; break; =20 - case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: { - const bool update_msi_mapping =3D !root->msi.intr[0].enable ^ !!va= l; - + case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: root->msi.intr[0].enable =3D val; - - if (update_msi_mapping) { - designware_pcie_root_update_msi_mapping(root); - } + designware_pcie_root_update_msi_mapping(root); break; - } =20 case DESIGNWARE_PCIE_MSI_INTR0_MASK: root->msi.intr[0].mask =3D val; --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562031058; cv=none; d=zoho.com; s=zohoarc; b=I9OCQyuLv5jfB9j2u25CedEFiDX9EyVz5+jdrGKXWDxXKluxbWvghq25TYs+79r9wpZZ1YZghiTRFOxOjKxYN6GnGUJ3H3vIpPpN9zVYbixJGPonfz64GW3E/3OGBBpMiderhpNE0/A6HRoPGLcZg14Ywmh66kwjNIKyWvtgPTM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562031058; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=KkUQSWRyDo7N3gMjPFgWAFIufs62qiUnuMkPV6Fsbp4=; b=CHGtPFwBP6L3XMbWHFFmjFwL4mffTuM1prayxjWme9XwHS/3LR1mJrEJMgCJ8IyfWaXGHrigNU5qogUzP889ftMmOt4OAitkKkmfacUBxgELq1F/qFBajJldIvft3fk8r44P2Hew5uT+lqXnNVjXsPgMw+79bHg2xRJYHPKIXXA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562031058123513.4517086225189; Mon, 1 Jul 2019 18:30:58 -0700 (PDT) Received: from localhost ([::1]:46866 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi7dE-0001CL-0F for importer@patchew.org; Mon, 01 Jul 2019 21:30:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55938) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4Na-0005Ft-Ll for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:02:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi4NY-0000a6-L6 for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:02:30 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:41572) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi4NV-0000Ts-GO for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:02:26 -0400 Received: by mail-wr1-f67.google.com with SMTP id c2so15441571wrm.8 for ; Mon, 01 Jul 2019 15:02:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.50 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KkUQSWRyDo7N3gMjPFgWAFIufs62qiUnuMkPV6Fsbp4=; b=eSUm5Pht6gJL8SzhSmxiPQULQJzBY0cI1Q3x7OssvcCHel0w6maC1/oSV00SeY+mNE 8VZRlirc9S5A9t3kbYe9DONj7hwVro5koBmKvSSkP2QtNRvsldq5aSaXanaqrpcS+dJA i9hKFixCEVTX4S2f300g2A7FLiRhDTkUMy4EnejnUcQmm0DVL3eDc7U8u0Mvsje2MXOx G32NAhHC2CrJVEHh6GJUjf7qPe33hzxWgul1PhERAM2+eCl0O6XczVSZeTmgeeYVf9Zz 094Zd3+uerm+ugLO6uDhjVFtduCY+cg24fBIkB8MXtpKRfanMN+rurh9PaK0cQ/ANYYf Zi7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KkUQSWRyDo7N3gMjPFgWAFIufs62qiUnuMkPV6Fsbp4=; b=fIc0vcLs3AbzMjutZ8Ucaba+Wb0aw39XC1+6YLxALJH6nzuoFJE2155sgGqZPuZYJi EgAxE1fet11qBA/p+ylJ+0160DaGljugGpaQRqnWIa9MVq/IqrRvetKWfAqD/3VwELX6 HU90BWqfKgrIpH5NAG/3NWdDN1Y0n6oG/nIVA2sbwH/5R7lBT/3oCFdhZQWYKFDTGMal OgYemvitR7+T7/xKwbCBbU4tD0Pb7qRa3Oy4skrqAqf/j0beOGyjxDNQhza8yI+KUkCv n9RNz+cTAnWsRJIBiI9kDKxAGxUfQ3BTBkRl7ZgBLb2+F90NHQs28ecyW1KMa41wY97f kvYg== X-Gm-Message-State: APjAAAVnqDN3QiNvYffC7IOfVpgvxycBBpKKJK5d0bjdEb8Ed1y0CR/9 sJLWvdRpwjufPGgE6X7b+7qgZt9LcNz/ag== X-Google-Smtp-Source: APXvYqyEeY51OM8LgNBMbG1hjRPU4+p7Z1PjSrZ9DifrGkNIeT8Yswg4PjQNbADUNvXPK1zDZWGJEQ== X-Received: by 2002:adf:e947:: with SMTP id m7mr8960339wrn.123.1561999192071; Mon, 01 Jul 2019 09:39:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:04 +0100 Message-Id: <20190701163943.22313-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.67 Subject: [Qemu-devel] [PULL 07/46] pci: designware: Update MSI mapping when MSI address changes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Andrey Smirnov MSI mapping needs to be update when MSI address changes, so add the code to do so. Signed-off-by: Andrey Smirnov Cc: Peter Maydell Cc: Michael S. Tsirkin Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Acked-by: Michael S. Tsirkin Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/pci-host/designware.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index ec697c8f9df..931cd954e87 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -290,11 +290,13 @@ static void designware_pcie_root_config_write(PCIDevi= ce *d, uint32_t address, case DESIGNWARE_PCIE_MSI_ADDR_LO: root->msi.base &=3D 0xFFFFFFFF00000000ULL; root->msi.base |=3D val; + designware_pcie_root_update_msi_mapping(root); break; =20 case DESIGNWARE_PCIE_MSI_ADDR_HI: root->msi.base &=3D 0x00000000FFFFFFFFULL; root->msi.base |=3D (uint64_t)val << 32; + designware_pcie_root_update_msi_mapping(root); break; =20 case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562016567; cv=none; d=zoho.com; s=zohoarc; b=W6exjeG4gadjSTyWFT6Fbllx03lDsSiALJBE6K9Q2qZfA0jKa9r/5Zs1M0e2GCLqotfpSu3A4S7+F9e5tQ9FrwsjJDuYjqMUBkFqa+UO0R85IN3D0C53IR37ESAAMicp1m5chj2heRURfV2uvfx8KCTHeWqc/0UlEIJK7dEwcIg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562016567; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Sy0WFm2MPPX0JE4Sw4IHzF1G+za7ZNoZ8lYBMqWvoGQ=; b=ONRRC6BG0l1ZJ1Ech2tu79yRKCyz7oDVQzvR8XZBf2JNNYQ3CUWhON1kYMo/LqVk33xtgpAmDLXhOe25U5+ngGNYBOR7rU4dZK7oeewf/NZ2YN2NboJwUstiJZ0TB/zyXLzWo4SKCZJ3Y/iL4APjhuQqtqXjHwo7UHksN/8EP2o= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562016567540304.5401067713283; Mon, 1 Jul 2019 14:29:27 -0700 (PDT) Received: from localhost ([::1]:45676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3ra-0004Fs-A8 for importer@patchew.org; Mon, 01 Jul 2019 17:29:26 -0400 Received: from eggs.gnu.org ([209.51.188.92]:46539) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3Gi-0003Gg-RJ for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:51:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3Gf-0002mq-Mv for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:51:18 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:36165) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3Gf-0002m2-Fp for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:51:17 -0400 Received: by mail-wr1-f66.google.com with SMTP id n4so15301187wrs.3 for ; Mon, 01 Jul 2019 13:51:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.52 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Sy0WFm2MPPX0JE4Sw4IHzF1G+za7ZNoZ8lYBMqWvoGQ=; b=XfDfqNBQrt3zosQ62oDrLackWZ5LGomx+UIqBao3FyccDQqlOYg/KkMNfwM4EPRDHt C45Ls4D6df1CUsmqsaqdMYLRf7jihyD2mfB1ijn/QixfJo9+yktX1756XivbPvtzl5+B +KOagQzU9nhq3RbhuXo4aLTPPWa7b/7UETD8CqDsr3zzWNMT7Mfn9MZCefeyWLwL77XH +rQ8ZdlngHQT4Vs0/UuFPuYDLBsxXgvuhv8LfmwqM2DNo4yYmz7y4a1qOjYKPkyfveyn 0Z4pGaHS4INoBtfgJQwzuCiLhuYrZD2+6SLQ/bNIt7wJYBR0da8ywVWPrveUmAWhZ696 5rkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Sy0WFm2MPPX0JE4Sw4IHzF1G+za7ZNoZ8lYBMqWvoGQ=; b=JZC6N4oCRhSqS2Zg4NMH4pK4E6pfsoV76GOsVpuXZJwNhQqotdjWtnq3dxG+TFAvcP vjDLRlnN674iNeRsJjVCf7+xXwz5eVzPDlQ+9yatfAV7VnSUZ3jqdQnIcaB1zdnKoOOy aCyhIvvjSyLXd6iuQQ5V2CUumsxJkXvKcP6+GJpCG6T8toJhmIfwUaSCkMaTvj311eZa nsPxrSRJVoNr8BZL1hyRzZb5UOYhXA5cqEIYra/AcUT9eqx6sPLRHEoLHU29Wv55NkCe H9X+rXjH9MWNSe5d0io9Za3A0yfyqS6BZaiYXcqxae432YJwwmbAS02GQ+ce7eYxh1v3 z2Ug== X-Gm-Message-State: APjAAAVc854ccGGSlwgBNXmQuc5YiuXlsO7vvOttgp01+9tQReIK+k/e Opsz7cwDvBgzs3Bzn4lR+gfP52RCG9yvzA== X-Google-Smtp-Source: APXvYqwxv60h2OSGZFEwplw032D4NjKucCAlotWWw8hyQnxMEgpVnQDzVYr+Rfle97GV7fR7V55a6g== X-Received: by 2002:adf:df0f:: with SMTP id y15mr13262612wrl.155.1561999193176; Mon, 01 Jul 2019 09:39:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:05 +0100 Message-Id: <20190701163943.22313-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.66 Subject: [Qemu-devel] [PULL 08/46] i.mx7d: pci: Update PCI IRQ mapping to match HW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Andrey Smirnov Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches that of i.MX6: * INTD/MSI 122 * INTC 123 * INTB 124 * INTA 125 Fix all of the relevant code to reflect that fact. Needed by latest Linux kernels. (Reference: Linux kernel commit 538d6e9d597584e80 from an NXP employee confirming that the datasheet is incorrect and with a report of a test against hardware.) Signed-off-by: Andrey Smirnov Cc: Peter Maydell Cc: Michael S. Tsirkin Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Reviewed-by: Peter Maydell [PMM: added ref to kernel commit confirming the datasheet error] Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx7.h | 8 ++++---- hw/pci-host/designware.c | 6 ++++-- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 09f4f33f6e5..8003d45d1e5 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -213,10 +213,10 @@ enum FslIMX7IRQs { FSL_IMX7_USB2_IRQ =3D 42, FSL_IMX7_USB3_IRQ =3D 40, =20 - FSL_IMX7_PCI_INTA_IRQ =3D 122, - FSL_IMX7_PCI_INTB_IRQ =3D 123, - FSL_IMX7_PCI_INTC_IRQ =3D 124, - FSL_IMX7_PCI_INTD_IRQ =3D 125, + FSL_IMX7_PCI_INTA_IRQ =3D 125, + FSL_IMX7_PCI_INTB_IRQ =3D 124, + FSL_IMX7_PCI_INTC_IRQ =3D 123, + FSL_IMX7_PCI_INTD_IRQ =3D 122, =20 FSL_IMX7_UART7_IRQ =3D 126, =20 diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 931cd954e87..9ae8c0deb75 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -51,6 +51,8 @@ #define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff) #define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C =20 +#define DESIGNWARE_PCIE_IRQ_MSI 3 + static DesignwarePCIEHost * designware_pcie_root_to_host(DesignwarePCIERoot *root) { @@ -67,7 +69,7 @@ static void designware_pcie_root_msi_write(void *opaque, = hwaddr addr, root->msi.intr[0].status |=3D BIT(val) & root->msi.intr[0].enable; =20 if (root->msi.intr[0].status & ~root->msi.intr[0].mask) { - qemu_set_irq(host->pci.irqs[0], 1); + qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1); } } =20 @@ -311,7 +313,7 @@ static void designware_pcie_root_config_write(PCIDevice= *d, uint32_t address, case DESIGNWARE_PCIE_MSI_INTR0_STATUS: root->msi.intr[0].status ^=3D val; if (!root->msi.intr[0].status) { - qemu_set_irq(host->pci.irqs[0], 0); + qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0); } break; =20 --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562018362; cv=none; d=zoho.com; s=zohoarc; b=lRav3jFwtOzkHRwdwzVzA2G4kksp+1d3rFoHgJnhFnMThVIO0MY9KiOBrTA9AZbQGaL4w5PNK+7+csgZs985Uc1dNyStFGjjgdsPJzlrjpeCw22c2cWvEv1c78xHbHHovnrmwoa72ix8JGyAlOCEqqMO3Pw4xf7Ved8AoxCmejU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562018362; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=50Y0/N9FaT3fyCQ4ei1ieOLigwzHJFfKxUOH5AH37Qc=; b=c9ofWizHWktywrVCyYGSVdlBphFqeuM+ZT1Igb8dNwrm4mja7rRl++uA9Bg0Mkjm+PFcqQH822j6XpBMl03jamwGi51lzTa4uAD89hJyK4jQGY4tDWHMtPgzXj2YhnyDvJQhbEuGeBKlHS7wb7y95vhuIpUghZxKJG4Dc8E4IRk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562018362614103.3199775642696; Mon, 1 Jul 2019 14:59:22 -0700 (PDT) Received: from localhost ([::1]:45866 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4KW-0002Kb-KT for importer@patchew.org; Mon, 01 Jul 2019 17:59:20 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48919) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3MK-0007XT-7M for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:57:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3MG-000535-Cn for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:57:06 -0400 Received: from mail-wr1-f52.google.com ([209.85.221.52]:37908) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3MG-0004xA-1V for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:57:04 -0400 Received: by mail-wr1-f52.google.com with SMTP id p11so4087544wro.5 for ; Mon, 01 Jul 2019 13:56:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.53 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=50Y0/N9FaT3fyCQ4ei1ieOLigwzHJFfKxUOH5AH37Qc=; b=ezgFOIiWaFsiUjakxR9OQHxbQNOMixXYVZeEodLQJN5vpKqxAB8kFLM/vhEu47wliy sd/2c0X0Emo/JV5VP9T2PmZ7YQuf3UnHVHm/+5BtSkrD+K1P1XSPEW5J8CouPchsoY9I 16AXu8zYA/sdYkZy63aGRi3ew2j/HknjjjljmSgKR1GJSHbEfTI8cJsHaUpU8EtjGP5Y AbWZg/oLBxoyJ3lsAbZz3H6Gw4OMTj29RBmmGbBvaAxJK152xQVAVF4OamauZVj6Xgll 1wWTsCrpZf0NZgSvHyDa8VY1sKDfOdp9eWoxhPeMvWUstpMhIsFZPoa1eptkuCoioRUb /01A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=50Y0/N9FaT3fyCQ4ei1ieOLigwzHJFfKxUOH5AH37Qc=; b=aUAYg0G7lOHdZNxEObSMwcCgcnh/3KT3h6/XvLRKbgF3bjnUf5miV9WpsZa1/MBBMg ZuVgyo2gaF4g+sWckDJLIxbQPjICewDSt3Uk9suf580+oMU774dojeSH+7eM5gGb/rx1 PaZteTxsCA4yiPSJX+Y9H0Rs6SN+DG1HubmigjwOeS9yoM9Qmdf42nJSUSt1LewC2Tdk dbiBNDIQbUwlEkGEgCkxBhMAwpxUcR638YV+SINIvibqBDgXbnfEo6EklnbQ7LjQPQVC L65dlDRIBETgusO8EIA6lPMAHMPNXVWsUbJuJc0IULd2JKpbrmCN3TLEydSn0HROvsXM Trkw== X-Gm-Message-State: APjAAAXkoata509dBd3aJQj5enlEpI1t0N1oAHwSzu0iGTqxfy//sbzj zLLRR5GVml53zf74nkjis3gMNGk2aIaTGQ== X-Google-Smtp-Source: APXvYqw9xqSnzzF7WTUSd/okUTna5coC6wYiAfv4/BFwwjDMIflrb5K7K5wQMm1eunYgF+uFOd9OCQ== X-Received: by 2002:adf:fc52:: with SMTP id e18mr18897260wrs.14.1561999194144; Mon, 01 Jul 2019 09:39:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:06 +0100 Message-Id: <20190701163943.22313-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.52 Subject: [Qemu-devel] [PULL 09/46] aspeed: add a per SoC mapping for the interrupt space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: C=C3=A9dric Le Goater This will simplify the definition of new SoCs, like the AST2600 which should use a different CPU and a different IRQ number layout. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Joel Stanley Message-id: 20190618165311.27066-2-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 36 +++++++++++++++++++++++ hw/arm/aspeed_soc.c | 57 +++++++++++++++++++++++++++++++------ 2 files changed, 85 insertions(+), 8 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 836b2ba8bf1..963abecb724 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -56,6 +56,7 @@ typedef struct AspeedSoCInfo { const char *fmc_typename; const char **spi_typename; int wdts_num; + const int *irqmap; } AspeedSoCInfo; =20 typedef struct AspeedSoCClass { @@ -68,4 +69,39 @@ typedef struct AspeedSoCClass { #define ASPEED_SOC_GET_CLASS(obj) \ OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC) =20 +enum { + ASPEED_IOMEM, + ASPEED_UART1, + ASPEED_UART2, + ASPEED_UART3, + ASPEED_UART4, + ASPEED_UART5, + ASPEED_VUART, + ASPEED_FMC, + ASPEED_SPI1, + ASPEED_SPI2, + ASPEED_VIC, + ASPEED_SDMC, + ASPEED_SCU, + ASPEED_ADC, + ASPEED_SRAM, + ASPEED_GPIO, + ASPEED_RTC, + ASPEED_TIMER1, + ASPEED_TIMER2, + ASPEED_TIMER3, + ASPEED_TIMER4, + ASPEED_TIMER5, + ASPEED_TIMER6, + ASPEED_TIMER7, + ASPEED_TIMER8, + ASPEED_WDT, + ASPEED_PWM, + ASPEED_LPC, + ASPEED_IBT, + ASPEED_I2C, + ASPEED_ETH1, + ASPEED_ETH2, +}; + #endif /* ASPEED_SOC_H */ diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index a2ea8c74844..de75bf04027 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -38,12 +38,42 @@ #define ASPEED_SOC_ETH1_BASE 0x1E660000 #define ASPEED_SOC_ETH2_BASE 0x1E680000 =20 -static const int uart_irqs[] =3D { 9, 32, 33, 34, 10 }; -static const int timer_irqs[] =3D { 16, 17, 18, 35, 36, 37, 38, 39, }; +static const int aspeed_soc_ast2400_irqmap[] =3D { + [ASPEED_UART1] =3D 9, + [ASPEED_UART2] =3D 32, + [ASPEED_UART3] =3D 33, + [ASPEED_UART4] =3D 34, + [ASPEED_UART5] =3D 10, + [ASPEED_VUART] =3D 8, + [ASPEED_FMC] =3D 19, + [ASPEED_SDMC] =3D 0, + [ASPEED_SCU] =3D 21, + [ASPEED_ADC] =3D 31, + [ASPEED_GPIO] =3D 20, + [ASPEED_RTC] =3D 22, + [ASPEED_TIMER1] =3D 16, + [ASPEED_TIMER2] =3D 17, + [ASPEED_TIMER3] =3D 18, + [ASPEED_TIMER4] =3D 35, + [ASPEED_TIMER5] =3D 36, + [ASPEED_TIMER6] =3D 37, + [ASPEED_TIMER7] =3D 38, + [ASPEED_TIMER8] =3D 39, + [ASPEED_WDT] =3D 27, + [ASPEED_PWM] =3D 28, + [ASPEED_LPC] =3D 8, + [ASPEED_IBT] =3D 8, /* LPC */ + [ASPEED_I2C] =3D 12, + [ASPEED_ETH1] =3D 2, + [ASPEED_ETH2] =3D 3, +}; =20 #define AST2400_SDRAM_BASE 0x40000000 #define AST2500_SDRAM_BASE 0x80000000 =20 +/* AST2500 uses the same IRQs as the AST2400 */ +#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap + static const hwaddr aspeed_soc_ast2400_spi_bases[] =3D { ASPEED_SOC_SPI_BA= SE }; static const char *aspeed_soc_ast2400_typenames[] =3D { "aspeed.smc.spi" }; =20 @@ -64,6 +94,7 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .fmc_typename =3D "aspeed.smc.fmc", .spi_typename =3D aspeed_soc_ast2400_typenames, .wdts_num =3D 2, + .irqmap =3D aspeed_soc_ast2400_irqmap, }, { .name =3D "ast2400-a1", .cpu_type =3D ARM_CPU_TYPE_NAME("arm926"), @@ -75,6 +106,7 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .fmc_typename =3D "aspeed.smc.fmc", .spi_typename =3D aspeed_soc_ast2400_typenames, .wdts_num =3D 2, + .irqmap =3D aspeed_soc_ast2400_irqmap, }, { .name =3D "ast2400", .cpu_type =3D ARM_CPU_TYPE_NAME("arm926"), @@ -86,6 +118,7 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .fmc_typename =3D "aspeed.smc.fmc", .spi_typename =3D aspeed_soc_ast2400_typenames, .wdts_num =3D 2, + .irqmap =3D aspeed_soc_ast2400_irqmap, }, { .name =3D "ast2500-a1", .cpu_type =3D ARM_CPU_TYPE_NAME("arm1176"), @@ -97,9 +130,17 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .fmc_typename =3D "aspeed.smc.ast2500-fmc", .spi_typename =3D aspeed_soc_ast2500_typenames, .wdts_num =3D 3, + .irqmap =3D aspeed_soc_ast2500_irqmap, }, }; =20 +static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) +{ + AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + + return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]); +} + static void aspeed_soc_init(Object *obj) { AspeedSoCState *s =3D ASPEED_SOC(obj); @@ -216,14 +257,14 @@ static void aspeed_soc_realize(DeviceState *dev, Erro= r **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BAS= E); - for (i =3D 0; i < ARRAY_SIZE(timer_irqs); i++) { - qemu_irq irq =3D qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]); + for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { + qemu_irq irq =3D aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); } =20 /* UART - attach an 8250 to the IO space as our UART5 */ if (serial_hd(0)) { - qemu_irq uart5 =3D qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]); + qemu_irq uart5 =3D aspeed_soc_get_irq(s, ASPEED_UART5); serial_mm_init(get_system_memory(), ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2, uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); @@ -237,7 +278,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE); sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, - qdev_get_gpio_in(DEVICE(&s->vic), 12)); + aspeed_soc_get_irq(s, ASPEED_I2C)); =20 /* FMC, The number of CS is set at the board level */ object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); @@ -249,7 +290,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, s->fmc.ctrl->flash_window_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, - qdev_get_gpio_in(DEVICE(&s->vic), 19)); + aspeed_soc_get_irq(s, ASPEED_FMC)); =20 /* SPI */ for (i =3D 0; i < sc->info->spis_num; i++) { @@ -297,7 +338,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE= ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0, - qdev_get_gpio_in(DEVICE(&s->vic), 2)); + aspeed_soc_get_irq(s, ASPEED_ETH1)); } =20 static void aspeed_soc_class_init(ObjectClass *oc, void *data) --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562034732; cv=none; d=zoho.com; s=zohoarc; b=F2tHF9eAvdoqEwR3WBglKwKVxnlQZwLdi3ygsjN8vcbS7AKwvM1xd86aK9DkvGcFDmQhswVl1Bm7BuTLbz8NYO/EqHcbcL7ASc59ubLJhh6MQ8OLV07ZwG+0B+WgPx4zcPHM5JRLRh4H9XoD956Xf+p2q6iBVdVaUyIT2IiCRVs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562034732; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.54 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=woHhYY92L1yVEaV0N+VO3jRl6CsEGrwlmOo1GH6Xz6Y=; b=kkgm2x9Ow0TvGYJ3izolYt1XjvB4yciYNNDmJcdu7GqkdLQsg0L7Zg3OXtlUU9juOm jZ+SjcF3bzvO5rZzwFGC5FGg7P/zUKRANqorEy2e+m5g55r02CTWB+fBg4m9MsTowXDX 9QbG74gmi6Kw2Dlnqt9exxy4/sPLlYvY8CUmMSAA9xskiMcRD3tnvqwpJNFfyvasiLom omXW+WNrRgmgJmlStRFKN9SchLFzN4SgDw+FE5m8YUya0EI2oWCj0FVYpiqyYZr/P55+ DwGkUqjlSZ6rmZ172Ie5JAZywEs3hleba/pXyaABep6kWpvVgDq2pfEQnZ0SfVNMSq30 Fu4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=woHhYY92L1yVEaV0N+VO3jRl6CsEGrwlmOo1GH6Xz6Y=; b=tYwPI+6/PSLNFQUshkOp5Mm+Gq9TiJLJGKx9Ei3GWzzo2aH85ZlkQy47DnNXNq/3O3 /qU9IV09i8AVWkiU9OKVEbxn1vPOd3XzOyg2bexISmm4QgN1yz9Wn0NbwH4tCtBhM28C 3iqSt3i+i2IX2LtbjxVSqBjUfed23QXkTwR/LYy2VZbqpYIdrH0tFiA+syyRwpPl8q+3 HZZAwxNNGDR8R9MTcO1PXHPBAS667MCNJuj6cmF1nlbFWkFHyDSxTf8yuZAD1escS+E2 ADGk7ouderuIwh6Jes6gAKavFbmPI64oWLSX9aquT1ARIHYSM+fDIoOkbS2dzHQJqlqH /uTA== X-Gm-Message-State: APjAAAX9LCCBcUGJaHlfHYc2HfWPbZyNJL4++TgriV8zxkR502nrNAE/ 1GB+2NCz320v96J3RQCE5ujkKLz4i1r/xQ== X-Google-Smtp-Source: APXvYqymEIq/pGxSpBCl/Hf4Th/d6t9XtT4NP+zU40VyzAN7tXqew7B2W6GfP6WgVefUvw9xuoil/g== X-Received: by 2002:a5d:4309:: with SMTP id h9mr6164162wrq.221.1561999195154; Mon, 01 Jul 2019 09:39:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:07 +0100 Message-Id: <20190701163943.22313-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.48 Subject: [Qemu-devel] [PULL 10/46] aspeed: add a per SoC mapping for the memory space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: C=C3=A9dric Le Goater This will simplify the definition of new SoCs, like the AST2600 which should use a slightly different address space and have a different set of controllers. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Joel Stanley Message-id: 20190618165311.27066-3-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 4 +- hw/arm/aspeed.c | 8 +-- hw/arm/aspeed_soc.c | 117 ++++++++++++++++++++++-------------- 3 files changed, 78 insertions(+), 51 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 963abecb724..88b901d5dfa 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -49,14 +49,13 @@ typedef struct AspeedSoCInfo { const char *name; const char *cpu_type; uint32_t silicon_rev; - hwaddr sdram_base; uint64_t sram_size; int spis_num; - const hwaddr *spi_bases; const char *fmc_typename; const char **spi_typename; int wdts_num; const int *irqmap; + const hwaddr *memmap; } AspeedSoCInfo; =20 typedef struct AspeedSoCClass { @@ -102,6 +101,7 @@ enum { ASPEED_I2C, ASPEED_ETH1, ASPEED_ETH2, + ASPEED_SDRAM, }; =20 #endif /* ASPEED_SOC_H */ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index d2ad2da24b5..c692ca1dba9 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -191,8 +191,8 @@ static void aspeed_board_init(MachineState *machine, &error_abort); =20 memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); - memory_region_add_subregion(get_system_memory(), sc->info->sdram_base, - &bmc->ram); + memory_region_add_subregion(get_system_memory(), + sc->info->memmap[ASPEED_SDRAM], &bmc->ram); object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->= ram), &error_abort); =20 @@ -201,7 +201,7 @@ static void aspeed_board_init(MachineState *machine, memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, "max_ram", max_ram_size - ram_size); memory_region_add_subregion(get_system_memory(), - sc->info->sdram_base + ram_size, + sc->info->memmap[ASPEED_SDRAM] + ram_size, &bmc->max_ram); =20 aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort); @@ -229,7 +229,7 @@ static void aspeed_board_init(MachineState *machine, aspeed_board_binfo.initrd_filename =3D machine->initrd_filename; aspeed_board_binfo.kernel_cmdline =3D machine->kernel_cmdline; aspeed_board_binfo.ram_size =3D ram_size; - aspeed_board_binfo.loader_start =3D sc->info->sdram_base; + aspeed_board_binfo.loader_start =3D sc->info->memmap[ASPEED_SDRAM]; =20 if (cfg->i2c_init) { cfg->i2c_init(bmc); diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index de75bf04027..1cc98b9f404 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -22,21 +22,58 @@ #include "hw/i2c/aspeed_i2c.h" #include "net/net.h" =20 -#define ASPEED_SOC_UART_5_BASE 0x00184000 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 -#define ASPEED_SOC_IOMEM_BASE 0x1E600000 -#define ASPEED_SOC_FMC_BASE 0x1E620000 -#define ASPEED_SOC_SPI_BASE 0x1E630000 -#define ASPEED_SOC_SPI2_BASE 0x1E631000 -#define ASPEED_SOC_VIC_BASE 0x1E6C0000 -#define ASPEED_SOC_SDMC_BASE 0x1E6E0000 -#define ASPEED_SOC_SCU_BASE 0x1E6E2000 -#define ASPEED_SOC_SRAM_BASE 0x1E720000 -#define ASPEED_SOC_TIMER_BASE 0x1E782000 -#define ASPEED_SOC_WDT_BASE 0x1E785000 -#define ASPEED_SOC_I2C_BASE 0x1E78A000 -#define ASPEED_SOC_ETH1_BASE 0x1E660000 -#define ASPEED_SOC_ETH2_BASE 0x1E680000 + +static const hwaddr aspeed_soc_ast2400_memmap[] =3D { + [ASPEED_IOMEM] =3D 0x1E600000, + [ASPEED_FMC] =3D 0x1E620000, + [ASPEED_SPI1] =3D 0x1E630000, + [ASPEED_VIC] =3D 0x1E6C0000, + [ASPEED_SDMC] =3D 0x1E6E0000, + [ASPEED_SCU] =3D 0x1E6E2000, + [ASPEED_ADC] =3D 0x1E6E9000, + [ASPEED_SRAM] =3D 0x1E720000, + [ASPEED_GPIO] =3D 0x1E780000, + [ASPEED_RTC] =3D 0x1E781000, + [ASPEED_TIMER1] =3D 0x1E782000, + [ASPEED_WDT] =3D 0x1E785000, + [ASPEED_PWM] =3D 0x1E786000, + [ASPEED_LPC] =3D 0x1E789000, + [ASPEED_IBT] =3D 0x1E789140, + [ASPEED_I2C] =3D 0x1E78A000, + [ASPEED_ETH1] =3D 0x1E660000, + [ASPEED_ETH2] =3D 0x1E680000, + [ASPEED_UART1] =3D 0x1E783000, + [ASPEED_UART5] =3D 0x1E784000, + [ASPEED_VUART] =3D 0x1E787000, + [ASPEED_SDRAM] =3D 0x40000000, +}; + +static const hwaddr aspeed_soc_ast2500_memmap[] =3D { + [ASPEED_IOMEM] =3D 0x1E600000, + [ASPEED_FMC] =3D 0x1E620000, + [ASPEED_SPI1] =3D 0x1E630000, + [ASPEED_SPI2] =3D 0x1E631000, + [ASPEED_VIC] =3D 0x1E6C0000, + [ASPEED_SDMC] =3D 0x1E6E0000, + [ASPEED_SCU] =3D 0x1E6E2000, + [ASPEED_ADC] =3D 0x1E6E9000, + [ASPEED_SRAM] =3D 0x1E720000, + [ASPEED_GPIO] =3D 0x1E780000, + [ASPEED_RTC] =3D 0x1E781000, + [ASPEED_TIMER1] =3D 0x1E782000, + [ASPEED_WDT] =3D 0x1E785000, + [ASPEED_PWM] =3D 0x1E786000, + [ASPEED_LPC] =3D 0x1E789000, + [ASPEED_IBT] =3D 0x1E789140, + [ASPEED_I2C] =3D 0x1E78A000, + [ASPEED_ETH1] =3D 0x1E660000, + [ASPEED_ETH2] =3D 0x1E680000, + [ASPEED_UART1] =3D 0x1E783000, + [ASPEED_UART5] =3D 0x1E784000, + [ASPEED_VUART] =3D 0x1E787000, + [ASPEED_SDRAM] =3D 0x80000000, +}; =20 static const int aspeed_soc_ast2400_irqmap[] =3D { [ASPEED_UART1] =3D 9, @@ -68,17 +105,9 @@ static const int aspeed_soc_ast2400_irqmap[] =3D { [ASPEED_ETH2] =3D 3, }; =20 -#define AST2400_SDRAM_BASE 0x40000000 -#define AST2500_SDRAM_BASE 0x80000000 - -/* AST2500 uses the same IRQs as the AST2400 */ #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap =20 -static const hwaddr aspeed_soc_ast2400_spi_bases[] =3D { ASPEED_SOC_SPI_BA= SE }; static const char *aspeed_soc_ast2400_typenames[] =3D { "aspeed.smc.spi" }; - -static const hwaddr aspeed_soc_ast2500_spi_bases[] =3D { ASPEED_SOC_SPI_BA= SE, - ASPEED_SOC_SPI2_BAS= E}; static const char *aspeed_soc_ast2500_typenames[] =3D { "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" }; =20 @@ -87,50 +116,46 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .name =3D "ast2400-a0", .cpu_type =3D ARM_CPU_TYPE_NAME("arm926"), .silicon_rev =3D AST2400_A0_SILICON_REV, - .sdram_base =3D AST2400_SDRAM_BASE, .sram_size =3D 0x8000, .spis_num =3D 1, - .spi_bases =3D aspeed_soc_ast2400_spi_bases, .fmc_typename =3D "aspeed.smc.fmc", .spi_typename =3D aspeed_soc_ast2400_typenames, .wdts_num =3D 2, .irqmap =3D aspeed_soc_ast2400_irqmap, + .memmap =3D aspeed_soc_ast2400_memmap, }, { .name =3D "ast2400-a1", .cpu_type =3D ARM_CPU_TYPE_NAME("arm926"), .silicon_rev =3D AST2400_A1_SILICON_REV, - .sdram_base =3D AST2400_SDRAM_BASE, .sram_size =3D 0x8000, .spis_num =3D 1, - .spi_bases =3D aspeed_soc_ast2400_spi_bases, .fmc_typename =3D "aspeed.smc.fmc", .spi_typename =3D aspeed_soc_ast2400_typenames, .wdts_num =3D 2, .irqmap =3D aspeed_soc_ast2400_irqmap, + .memmap =3D aspeed_soc_ast2400_memmap, }, { .name =3D "ast2400", .cpu_type =3D ARM_CPU_TYPE_NAME("arm926"), .silicon_rev =3D AST2400_A0_SILICON_REV, - .sdram_base =3D AST2400_SDRAM_BASE, .sram_size =3D 0x8000, .spis_num =3D 1, - .spi_bases =3D aspeed_soc_ast2400_spi_bases, .fmc_typename =3D "aspeed.smc.fmc", .spi_typename =3D aspeed_soc_ast2400_typenames, .wdts_num =3D 2, .irqmap =3D aspeed_soc_ast2400_irqmap, + .memmap =3D aspeed_soc_ast2400_memmap, }, { .name =3D "ast2500-a1", .cpu_type =3D ARM_CPU_TYPE_NAME("arm1176"), .silicon_rev =3D AST2500_A1_SILICON_REV, - .sdram_base =3D AST2500_SDRAM_BASE, .sram_size =3D 0x9000, .spis_num =3D 2, - .spi_bases =3D aspeed_soc_ast2500_spi_bases, .fmc_typename =3D "aspeed.smc.ast2500-fmc", .spi_typename =3D aspeed_soc_ast2500_typenames, .wdts_num =3D 3, .irqmap =3D aspeed_soc_ast2500_irqmap, + .memmap =3D aspeed_soc_ast2500_memmap, }, }; =20 @@ -210,8 +235,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) Error *err =3D NULL, *local_err =3D NULL; =20 /* IO space */ - create_unimplemented_device("aspeed_soc.io", - ASPEED_SOC_IOMEM_BASE, ASPEED_SOC_IOMEM_SI= ZE); + create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_I= OMEM], + ASPEED_SOC_IOMEM_SIZE); =20 /* CPU */ object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); @@ -227,8 +252,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) error_propagate(errp, err); return; } - memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE, - &s->sram); + memory_region_add_subregion(get_system_memory(), + sc->info->memmap[ASPEED_SRAM], &s->sram); =20 /* SCU */ object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); @@ -236,7 +261,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) error_propagate(errp, err); return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->info->memmap[ASPEED_SC= U]); =20 /* VIC */ object_property_set_bool(OBJECT(&s->vic), true, "realized", &err); @@ -244,7 +269,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) error_propagate(errp, err); return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->info->memmap[ASPEED_VI= C]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, @@ -256,7 +281,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) error_propagate(errp, err); return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BAS= E); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, + sc->info->memmap[ASPEED_TIMER1]); for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { qemu_irq irq =3D aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); @@ -265,8 +291,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) /* UART - attach an 8250 to the IO space as our UART5 */ if (serial_hd(0)) { qemu_irq uart5 =3D aspeed_soc_get_irq(s, ASPEED_UART5); - serial_mm_init(get_system_memory(), - ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2, + serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5]= , 2, uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); } =20 @@ -276,7 +301,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) error_propagate(errp, err); return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->info->memmap[ASPEED_I2= C]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, aspeed_soc_get_irq(s, ASPEED_I2C)); =20 @@ -286,7 +311,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) error_propagate(errp, err); return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->info->memmap[ASPEED_FM= C]); sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, s->fmc.ctrl->flash_window_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, @@ -302,7 +327,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) error_propagate(errp, err); return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases= [i]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, + sc->info->memmap[ASPEED_SPI1 + i]); sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, s->spi[i].ctrl->flash_window_base); } @@ -313,7 +339,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) error_propagate(errp, err); return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->info->memmap[ASPEED_S= DMC]); =20 /* Watch dog */ for (i =3D 0; i < sc->info->wdts_num; i++) { @@ -323,7 +349,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, - ASPEED_SOC_WDT_BASE + i * 0x20); + sc->info->memmap[ASPEED_WDT] + i * 0x20); } =20 /* Net */ @@ -336,7 +362,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) error_propagate(errp, err); return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE= ); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, + sc->info->memmap[ASPEED_ETH1]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0, aspeed_soc_get_irq(s, ASPEED_ETH1)); } --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.55 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CYfx37JxnssAjr/tG+kyQQOiehR3Iv+2f3PQj31KL1k=; b=xhqioRQGf568ofeu8XUsiPc5H6X+8w7tPd/JWgRWPF2jmOGsjlJZJaSJOn1khDEUmW FKsIosXhewecqkYCjwiETXkI5D12ElqX2vRrddlYk5Pa9IXQ9pl6O+gYLb/kKDH0gvpt uU/Pmy3hdqEnxQGvZitM6KqkSj1vCgIMa+wkxpuVy7BYqHSwIKZVdYF3hCagY/cCWrpk 1BPcR/b1D9okWKM5OINFtIH3z6qaWuLYos7xvPLQXASCq2ac2+BduDZioNgHrl8601Q3 hNBZojTFKVeAWa1hfIRx8SennqeNX9Ni5OJm/dxCR5IHqv8tfBCzsvQ53cYeZ1R2wv4f F3fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CYfx37JxnssAjr/tG+kyQQOiehR3Iv+2f3PQj31KL1k=; b=rCf9d7lwlv4DmysHqN+CwU5j49dasQGUPhFB6eOzwyH3ZLvey2HId0ee6k87ozA83n VlMiAuxS1d1p0Yfvn7IKsPkh4ied/fQ0CAp8GstfTcgY2J/PeFc0leYfpWFTnh1sbusy HlNPPkUBEDElM+skNk9To1f/CjTk1U99K7RQtPskvn3gLxgld13DVYLA3YZLC1NVRrIw GdIAHyJLdPJdOINqkUyE2bPD7do6F4gQHQtByhz33z7N7JT1qGnU5V51koxIJsW+ByU6 jinXTafTQS9SjcqIm5KHEqAcp6AjXf4m2fcrkuorBJCUX5lJjm+2l3X0eehRTascgkaC IdqA== X-Gm-Message-State: APjAAAXXSKRuhCQ18VM4alVwVNglnyXP69VVbZsthR2sTX2gcttp4u50 GW3w9d0IDonqeqsbisnr3w/rofQ/HoYWuA== X-Google-Smtp-Source: APXvYqzEIY0+ruDueHoQm9lAIXvoBFoTGZDQ2j7XzszLVSpqtsSzJ6jYgJyVIf8Aug9VIqOl1NuJiQ== X-Received: by 2002:adf:900e:: with SMTP id h14mr5757364wrh.58.1561999196156; Mon, 01 Jul 2019 09:39:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:08 +0100 Message-Id: <20190701163943.22313-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.49 Subject: [Qemu-devel] [PULL 11/46] hw: timer: Add ASPEED RTC device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Joel Stanley The RTC is modeled to provide time and date functionality. It is initialised at zero to match the hardware. There is no modelling of the alarm functionality, which includes the IRQ line. As there is no guest code to exercise this function that is acceptable for now. Signed-off-by: Joel Stanley Reviewed-by: Peter Maydell Message-id: 20190618165311.27066-4-clg@kaod.org Signed-off-by: Peter Maydell --- hw/timer/Makefile.objs | 2 +- include/hw/timer/aspeed_rtc.h | 31 ++++++ hw/timer/aspeed_rtc.c | 180 ++++++++++++++++++++++++++++++++++ hw/timer/trace-events | 4 + 4 files changed, 216 insertions(+), 1 deletion(-) create mode 100644 include/hw/timer/aspeed_rtc.h create mode 100644 hw/timer/aspeed_rtc.c diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index 0e9a4530f84..123d92c9692 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -41,7 +41,7 @@ obj-$(CONFIG_MC146818RTC) +=3D mc146818rtc.o obj-$(CONFIG_ALLWINNER_A10_PIT) +=3D allwinner-a10-pit.o =20 common-obj-$(CONFIG_STM32F2XX_TIMER) +=3D stm32f2xx_timer.o -common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_timer.o +common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_timer.o aspeed_rtc.o =20 common-obj-$(CONFIG_SUN4V_RTC) +=3D sun4v-rtc.o common-obj-$(CONFIG_CMSDK_APB_TIMER) +=3D cmsdk-apb-timer.o diff --git a/include/hw/timer/aspeed_rtc.h b/include/hw/timer/aspeed_rtc.h new file mode 100644 index 00000000000..1f1155a676c --- /dev/null +++ b/include/hw/timer/aspeed_rtc.h @@ -0,0 +1,31 @@ +/* + * ASPEED Real Time Clock + * Joel Stanley + * + * Copyright 2019 IBM Corp + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ASPEED_RTC_H +#define ASPEED_RTC_H + +#include + +#include "hw/hw.h" +#include "hw/irq.h" +#include "hw/sysbus.h" + +typedef struct AspeedRtcState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + + uint32_t reg[0x18]; + int offset; + +} AspeedRtcState; + +#define TYPE_ASPEED_RTC "aspeed.rtc" +#define ASPEED_RTC(obj) OBJECT_CHECK(AspeedRtcState, (obj), TYPE_ASPEED_RT= C) + +#endif /* ASPEED_RTC_H */ diff --git a/hw/timer/aspeed_rtc.c b/hw/timer/aspeed_rtc.c new file mode 100644 index 00000000000..19f061c846e --- /dev/null +++ b/hw/timer/aspeed_rtc.c @@ -0,0 +1,180 @@ +/* + * ASPEED Real Time Clock + * Joel Stanley + * + * Copyright 2019 IBM Corp + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "hw/timer/aspeed_rtc.h" +#include "qemu/log.h" +#include "qemu/timer.h" + +#include "trace.h" + +#define COUNTER1 (0x00 / 4) +#define COUNTER2 (0x04 / 4) +#define ALARM (0x08 / 4) +#define CONTROL (0x10 / 4) +#define ALARM_STATUS (0x14 / 4) + +#define RTC_UNLOCKED BIT(1) +#define RTC_ENABLED BIT(0) + +static void aspeed_rtc_calc_offset(AspeedRtcState *rtc) +{ + struct tm tm; + uint32_t year, cent; + uint32_t reg1 =3D rtc->reg[COUNTER1]; + uint32_t reg2 =3D rtc->reg[COUNTER2]; + + tm.tm_mday =3D (reg1 >> 24) & 0x1f; + tm.tm_hour =3D (reg1 >> 16) & 0x1f; + tm.tm_min =3D (reg1 >> 8) & 0x3f; + tm.tm_sec =3D (reg1 >> 0) & 0x3f; + + cent =3D (reg2 >> 16) & 0x1f; + year =3D (reg2 >> 8) & 0x7f; + tm.tm_mon =3D ((reg2 >> 0) & 0x0f) - 1; + tm.tm_year =3D year + (cent * 100) - 1900; + + rtc->offset =3D qemu_timedate_diff(&tm); +} + +static uint32_t aspeed_rtc_get_counter(AspeedRtcState *rtc, int r) +{ + uint32_t year, cent; + struct tm now; + + qemu_get_timedate(&now, rtc->offset); + + switch (r) { + case COUNTER1: + return (now.tm_mday << 24) | (now.tm_hour << 16) | + (now.tm_min << 8) | now.tm_sec; + case COUNTER2: + cent =3D (now.tm_year + 1900) / 100; + year =3D now.tm_year % 100; + return ((cent & 0x1f) << 16) | ((year & 0x7f) << 8) | + ((now.tm_mon + 1) & 0xf); + default: + g_assert_not_reached(); + } +} + +static uint64_t aspeed_rtc_read(void *opaque, hwaddr addr, + unsigned size) +{ + AspeedRtcState *rtc =3D opaque; + uint64_t val; + uint32_t r =3D addr >> 2; + + switch (r) { + case COUNTER1: + case COUNTER2: + if (rtc->reg[CONTROL] & RTC_ENABLED) { + rtc->reg[r] =3D aspeed_rtc_get_counter(rtc, r); + } + /* fall through */ + case CONTROL: + val =3D rtc->reg[r]; + break; + case ALARM: + case ALARM_STATUS: + default: + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx "\n", __func__, add= r); + return 0; + } + + trace_aspeed_rtc_read(addr, val); + + return val; +} + +static void aspeed_rtc_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + AspeedRtcState *rtc =3D opaque; + uint32_t r =3D addr >> 2; + + switch (r) { + case COUNTER1: + case COUNTER2: + if (!(rtc->reg[CONTROL] & RTC_UNLOCKED)) { + break; + } + /* fall through */ + case CONTROL: + rtc->reg[r] =3D val; + aspeed_rtc_calc_offset(rtc); + break; + case ALARM: + case ALARM_STATUS: + default: + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx "\n", __func__, add= r); + break; + } + trace_aspeed_rtc_write(addr, val); +} + +static void aspeed_rtc_reset(DeviceState *d) +{ + AspeedRtcState *rtc =3D ASPEED_RTC(d); + + rtc->offset =3D 0; + memset(rtc->reg, 0, sizeof(rtc->reg)); +} + +static const MemoryRegionOps aspeed_rtc_ops =3D { + .read =3D aspeed_rtc_read, + .write =3D aspeed_rtc_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static const VMStateDescription vmstate_aspeed_rtc =3D { + .name =3D TYPE_ASPEED_RTC, + .version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18), + VMSTATE_INT32(offset, AspeedRtcState), + VMSTATE_INT32(offset, AspeedRtcState), + VMSTATE_END_OF_LIST() + } +}; + +static void aspeed_rtc_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + AspeedRtcState *s =3D ASPEED_RTC(dev); + + sysbus_init_irq(sbd, &s->irq); + + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_rtc_ops, s, + "aspeed-rtc", 0x18ULL); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void aspeed_rtc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D aspeed_rtc_realize; + dc->vmsd =3D &vmstate_aspeed_rtc; + dc->reset =3D aspeed_rtc_reset; +} + +static const TypeInfo aspeed_rtc_info =3D { + .name =3D TYPE_ASPEED_RTC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedRtcState), + .class_init =3D aspeed_rtc_class_init, +}; + +static void aspeed_rtc_register_types(void) +{ + type_register_static(&aspeed_rtc_info); +} + +type_init(aspeed_rtc_register_types) diff --git a/hw/timer/trace-events b/hw/timer/trace-events index dcaf3d6da6c..db02a9142cd 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -66,6 +66,10 @@ cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data,= unsigned size) "CMSDK A cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "= CMSDK APB dualtimer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset" =20 +# hw/timer/aspeed-rtc.c +aspeed_rtc_read(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value= 0x%08" PRIx64 +aspeed_rtc_write(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " valu= e 0x%08" PRIx64 + # sun4v-rtc.c sun4v_rtc_read(uint64_t addr, uint64_t value) "read: addr 0x%" PRIx64 " va= lue 0x%" PRIx64 sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " = value 0x%" PRIx64 --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.56 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=j+8CvV6xVOR9giO4NQvCrXsJxw5VIv1X7DZKMX4Y4WU=; b=qyWU7bY0HECSPd1xHpHsFE5FEPm/XHyAq7jD7+alKGSSbN6DaXK1KbBmrfY21MnTzI xXnuAU3zdLRlWRVwzIKoePY2FoqUWeelY+dp/wBVvj91LEaW7296IlRv26a2xwoys8+K jtM89qTkU8lZCY/UNqJQ8I2GEhtWvE2q5HxovYKXl9RfRUWkWi2qptqSvWa58JFxPfwj r5HrJitDTzAsaneP20tAvy938fsfq39eTm40//ogLjERXMCCSdoSgwqVfD9dy379gyQN ollrMHmINcEMZsd6iw8N4kyyAmyWjfC45Sq9/WXCjxQF7fkFd/dJjLubyQbSWhfpEeQV Ivxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j+8CvV6xVOR9giO4NQvCrXsJxw5VIv1X7DZKMX4Y4WU=; b=g5i9mpsGwG5uDdokBwCq4xjQ3b+d1fNutUiMetj4n54cLjOF9r0vdEpvbdGXoRnc2u LLp4Pu964FCU5a1bSzak3FhMkBK8A43eJZeR+pvxylFvm9eIw7tLo+sVmSQDLohQaSMT FQkvk6KUu13OafpX/+GfQK85afRfiAlPRuOUIL0TkOoWNUoF6Cb0QOcEt9nY8B6VORBd ttJhq5i6rzkpOyIyiZozpw4+knh9cfzS7K5Cdfnrc3KEPNXaTGygA+eSaLLVlG/n9SxT p7qrGdnCmKbdr+Clj2zXPMcEUs6vZluzYmtmKEfXEKDvFCHbjif+viu3qlqOc+MPs3zX R3ww== X-Gm-Message-State: APjAAAW7H+fKxwMCDgAplXKMMfS3ujefQI8CfjI+7mhvegj/EZr872iW NzOh2jZRAli4GhbbVH/eR22YN60IDMHVnQ== X-Google-Smtp-Source: APXvYqyreM1V3fx9LjgFNxgju3wCWCeWZ1ah+AKjH3WJxZOjfbdZs+0m6glmG7Vo1au72l5uuIyKgw== X-Received: by 2002:a5d:4941:: with SMTP id r1mr19002855wrs.225.1561999198558; Mon, 01 Jul 2019 09:39:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:09 +0100 Message-Id: <20190701163943.22313-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.44 Subject: [Qemu-devel] [PULL 12/46] hw/arm/aspeed: Add RTC to SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Joel Stanley All systems have an RTC. The IRQ is hooked up but the model does not use it at this stage. There is no guest code that uses it, so this limitation is acceptable. Signed-off-by: Joel Stanley Reviewed-by: Peter Maydell Message-id: 20190618165311.27066-5-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 2 ++ hw/arm/aspeed_soc.c | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 88b901d5dfa..fa0ba957a61 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -16,6 +16,7 @@ #include "hw/misc/aspeed_scu.h" #include "hw/misc/aspeed_sdmc.h" #include "hw/timer/aspeed_timer.h" +#include "hw/timer/aspeed_rtc.h" #include "hw/i2c/aspeed_i2c.h" #include "hw/ssi/aspeed_smc.h" #include "hw/watchdog/wdt_aspeed.h" @@ -32,6 +33,7 @@ typedef struct AspeedSoCState { ARMCPU cpu; MemoryRegion sram; AspeedVICState vic; + AspeedRtcState rtc; AspeedTimerCtrlState timerctrl; AspeedI2CState i2c; AspeedSCUState scu; diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 1cc98b9f404..5faa78d81fd 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -189,6 +189,9 @@ static void aspeed_soc_init(Object *obj) sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic), TYPE_ASPEED_VIC); =20 + sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc), + TYPE_ASPEED_RTC); + sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), sizeof(s->timerctrl), TYPE_ASPEED_TIMER); object_property_add_const_link(OBJECT(&s->timerctrl), "scu", @@ -275,6 +278,16 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); =20 + /* RTC */ + object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->info->memmap[ASPEED_RT= C]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, + aspeed_soc_get_irq(s, ASPEED_RTC)); + /* Timer */ object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err= ); if (err) { --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562031844; cv=none; d=zoho.com; s=zohoarc; b=MQBCNe/jcckCbkRik3PgYj/8THyVWEieAiMwcOKJ7+gjetZ5Se8G+ayIiYrF1Ag5Lx5k6M6f/LMA/RtnWqdp6CHiF2lh2tZbAFQ+MO002QNehgHPp65GlR4MFY+sgX3Id8hKHMUGFKyYolQ2pNZj6Sf8DCjQbrXY5E3QSLFr5e0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562031844; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=1E06iM3g2rGIpvDkSZRxcV4cH98QgZLgZ77VISOvPlc=; b=QyePNhy4JLarTuEOaQEv7aR13Msv0cYNuJIwSTRGm3JXLwQNWNthhSMu1rJ+s/4atKOv4s8zkCPmtUhcVxoOWyAl1yp4fQfutueUjcx/bCr7Y1wcdlJ/IKvmnFaToKRXsWQ4inYZgm6PlshuUCovfGOAbFT519XPDL49jzjwP+c= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562031844098753.4544580314011; Mon, 1 Jul 2019 18:44:04 -0700 (PDT) Received: from localhost ([::1]:46996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi7pw-0006PF-UJ for importer@patchew.org; Mon, 01 Jul 2019 21:44:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55574) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4Md-00053I-9r for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:01:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi4Mb-0000HU-Li for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:01:31 -0400 Received: from mail-wr1-f52.google.com ([209.85.221.52]:43829) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi4Mb-0000HI-EW for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:01:29 -0400 Received: by mail-wr1-f52.google.com with SMTP id p13so15406507wru.10 for ; Mon, 01 Jul 2019 15:01:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.58 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1E06iM3g2rGIpvDkSZRxcV4cH98QgZLgZ77VISOvPlc=; b=rrC9IS53HJ9tl6cCe3/PhPlonva0bhClgGXrn4M88ljUCJkYgfpUmgKOFbYAFP1UO3 JtwowsCbRmFCnU4TOU4QsFLVVm1QZdj5YKRVhc8v3x/6yb87zABKu3FecdoV/gLiFRUI /oQAeRbDI0CzITZuZnC+FVrl4+iCuhZ9shzBj/6NSBcVWntiXq9mtdcOHamZZlaZm1MF FodNHQEirXGsDtdNibMeYVWvUvspMZ5xYXsEsUbe8oZCgAl9bCbI6FFS+1BQ1TJ8/l/t Z4QDl1bn+jLWFcm6PSXdOuDSygXo4RND5+iZe8CuxjFrnGFQS2b6d4ZYqyzqIy8/xnft wJvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1E06iM3g2rGIpvDkSZRxcV4cH98QgZLgZ77VISOvPlc=; b=JHNQ2yMt6EwaW2umRQXxu48mczVA63MfdYy49rzN5/5ZbE9x/sCcwWRzax6+T5TZpm 8fIt5Zz8G6Nhp/M4PyPBi+7oALE/Pje55JGpL2TvhftKpSQnFokToVu6kvLLlBanA5cD 0Ch4gZXGUuck/1pKj94cAMxBdPMq2qPuRRLR2i2mGbM5SLu+s94mOlyhqO5RLoZtX29D kHPsCfKDEMsOLnn/PzNKGmwrjcZIbsMwXyiTswWfWxiiaJPXuzmvfogixuDNub0t2ZcD +4BhHAjdiM17/55ZG7oI2dTYuADsiYCKLdHSgZJtQfRzdoPVETsAp4GPtNod4M5KzdcG 9kWw== X-Gm-Message-State: APjAAAU7/qkpR/ioVCYBqBqxhCI+sUrcq8JhBr8eUGmG0DZeBCUiioDW SJVz//3SHsz0zTSqJdvLyZG/AErzHXi9ng== X-Google-Smtp-Source: APXvYqw5SRtS0ySqCxCgThkkGdeBtzB/0lcnmjHJLS6wniI76wAY2PLjxDFWdU/5nGnJkOxSNjiP+A== X-Received: by 2002:adf:e84d:: with SMTP id d13mr15984958wrn.88.1561999199485; Mon, 01 Jul 2019 09:39:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:10 +0100 Message-Id: <20190701163943.22313-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.52 Subject: [Qemu-devel] [PULL 13/46] aspeed: introduce a configurable number of CPU per machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: C=C3=A9dric Le Goater The current models of the Aspeed SoCs only have one CPU but future ones will support SMP. Introduce a new num_cpus field at the SoC class level to define the number of available CPUs per SoC and also introduce a 'num-cpus' property to activate the CPUs configured for the machine. The max_cpus limit of the machine should depend on the SoC definition but, unfortunately, these values are not available when the machine class is initialized. This is the reason why we add a check on num_cpus in the AspeedSoC realize handler. SMP support will be activated when models for such SoCs are implemented. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Message-id: 20190618165311.27066-6-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 5 ++++- hw/arm/aspeed.c | 7 +++++-- hw/arm/aspeed_soc.c | 33 +++++++++++++++++++++++++++------ 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index fa0ba957a61..b613b00600f 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -24,13 +24,15 @@ =20 #define ASPEED_SPIS_NUM 2 #define ASPEED_WDTS_NUM 3 +#define ASPEED_CPUS_NUM 2 =20 typedef struct AspeedSoCState { /*< private >*/ DeviceState parent; =20 /*< public >*/ - ARMCPU cpu; + ARMCPU cpu[ASPEED_CPUS_NUM]; + uint32_t num_cpus; MemoryRegion sram; AspeedVICState vic; AspeedRtcState rtc; @@ -58,6 +60,7 @@ typedef struct AspeedSoCInfo { int wdts_num; const int *irqmap; const hwaddr *memmap; + uint32_t num_cpus; } AspeedSoCInfo; =20 typedef struct AspeedSoCClass { diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index c692ca1dba9..96de4f5c2a8 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -22,13 +22,13 @@ #include "hw/misc/tmp105.h" #include "qemu/log.h" #include "sysemu/block-backend.h" +#include "sysemu/sysemu.h" #include "hw/loader.h" #include "qemu/error-report.h" #include "qemu/units.h" =20 static struct arm_boot_info aspeed_board_binfo =3D { .board_id =3D -1, /* device-tree-only board */ - .nb_cpus =3D 1, }; =20 struct AspeedBoardState { @@ -171,6 +171,8 @@ static void aspeed_board_init(MachineState *machine, &error_abort); object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs", &error_abort); + object_property_set_int(OBJECT(&bmc->soc), smp_cpus, "num-cpus", + &error_abort); if (machine->kernel_filename) { /* * When booting with a -kernel command line there is no u-boot @@ -230,6 +232,7 @@ static void aspeed_board_init(MachineState *machine, aspeed_board_binfo.kernel_cmdline =3D machine->kernel_cmdline; aspeed_board_binfo.ram_size =3D ram_size; aspeed_board_binfo.loader_start =3D sc->info->memmap[ASPEED_SDRAM]; + aspeed_board_binfo.nb_cpus =3D bmc->soc.num_cpus; =20 if (cfg->i2c_init) { cfg->i2c_init(bmc); @@ -326,7 +329,7 @@ static void aspeed_machine_class_init(ObjectClass *oc, = void *data) =20 mc->desc =3D board->desc; mc->init =3D aspeed_machine_init; - mc->max_cpus =3D 1; + mc->max_cpus =3D ASPEED_CPUS_NUM; mc->no_sdcard =3D 1; mc->no_floppy =3D 1; mc->no_cdrom =3D 1; diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 5faa78d81fd..d38fb0aaa0f 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -19,6 +19,7 @@ #include "hw/char/serial.h" #include "qemu/log.h" #include "qemu/module.h" +#include "qemu/error-report.h" #include "hw/i2c/aspeed_i2c.h" #include "net/net.h" =20 @@ -123,6 +124,7 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .wdts_num =3D 2, .irqmap =3D aspeed_soc_ast2400_irqmap, .memmap =3D aspeed_soc_ast2400_memmap, + .num_cpus =3D 1, }, { .name =3D "ast2400-a1", .cpu_type =3D ARM_CPU_TYPE_NAME("arm926"), @@ -134,6 +136,7 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .wdts_num =3D 2, .irqmap =3D aspeed_soc_ast2400_irqmap, .memmap =3D aspeed_soc_ast2400_memmap, + .num_cpus =3D 1, }, { .name =3D "ast2400", .cpu_type =3D ARM_CPU_TYPE_NAME("arm926"), @@ -145,6 +148,7 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .wdts_num =3D 2, .irqmap =3D aspeed_soc_ast2400_irqmap, .memmap =3D aspeed_soc_ast2400_memmap, + .num_cpus =3D 1, }, { .name =3D "ast2500-a1", .cpu_type =3D ARM_CPU_TYPE_NAME("arm1176"), @@ -156,6 +160,7 @@ static const AspeedSoCInfo aspeed_socs[] =3D { .wdts_num =3D 3, .irqmap =3D aspeed_soc_ast2500_irqmap, .memmap =3D aspeed_soc_ast2500_memmap, + .num_cpus =3D 1, }, }; =20 @@ -172,8 +177,11 @@ static void aspeed_soc_init(Object *obj) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); int i; =20 - object_initialize_child(obj, "cpu", OBJECT(&s->cpu), sizeof(s->cpu), - sc->info->cpu_type, &error_abort, NULL); + for (i =3D 0; i < sc->info->num_cpus; i++) { + object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), + sizeof(s->cpu[i]), sc->info->cpu_type, + &error_abort, NULL); + } =20 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), TYPE_ASPEED_SCU); @@ -241,11 +249,19 @@ static void aspeed_soc_realize(DeviceState *dev, Erro= r **errp) create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_I= OMEM], ASPEED_SOC_IOMEM_SIZE); =20 + if (s->num_cpus > sc->info->num_cpus) { + warn_report("%s: invalid number of CPUs %d, using default %d", + sc->info->name, s->num_cpus, sc->info->num_cpus); + s->num_cpus =3D sc->info->num_cpus; + } + /* CPU */ - object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; + for (i =3D 0; i < s->num_cpus; i++) { + object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &er= r); + if (err) { + error_propagate(errp, err); + return; + } } =20 /* SRAM */ @@ -380,6 +396,10 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0, aspeed_soc_get_irq(s, ASPEED_ETH1)); } +static Property aspeed_soc_properties[] =3D { + DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0), + DEFINE_PROP_END_OF_LIST(), +}; =20 static void aspeed_soc_class_init(ObjectClass *oc, void *data) { @@ -390,6 +410,7 @@ static void aspeed_soc_class_init(ObjectClass *oc, void= *data) dc->realize =3D aspeed_soc_realize; /* Reason: Uses serial_hds and nd_table in realize() directly */ dc->user_creatable =3D false; + dc->props =3D aspeed_soc_properties; } =20 static const TypeInfo aspeed_soc_type_info =3D { --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.39.59 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:39:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xLXG4Nv6yEmVw9kkMxGxEVuFArgBP+Xz+Oi4X8SxX1A=; b=xvjUEJUg+ZWVyqYduXllUqk1KcQofIY+0jtnEDDmxSSjUNgJc1WttJY8OgQX/G3/58 L3z/2NQi4rcDvq2VhLH5YSAu1IztT3qbt7wNfiBO9s9LwslApxWUyrid9d9ZYCB/ldB1 sx14sohFPT6YCgt1yb3+i84XuhaMMLUBszeiCTakJqyTqmd0mowjc/6cn+HxQfzbCEI7 efjGqbpxSt0c+xRdFV9wg95JOkdfpouCv/qQyUBy636PggJcNYe6rnO2YUK6U2jc3fwj 2bKCKlFEgSU5KlOjhpNFxPuBinS3zDNc+uZvDvSMZoMEOMI0IXhgKzFWjnOu9UX1P2Z6 c4Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xLXG4Nv6yEmVw9kkMxGxEVuFArgBP+Xz+Oi4X8SxX1A=; b=kZG8A137EBvFCzd5YwJcYaPEcDwCHz19EBDos/A+ZGpQEuixAalIsXN+t/mnG2N87e dirPVANMYry1h2uOpD9QAqSsf+m2mjnLplk9PYFZ0vUIc1VS18/9pbTzSGf7O6UBdUyL GLrJPX811HHYYGs3C0TDdNxf2KnWjZpEZNCwV6UXXF2X+9Rx/a4QYB/H5xJeQUzEgGG2 2ODLAnMVnF9iwXpav1S1zOJPfiTDGcDY4O8B2b5s5ClJp2XAohHgr6+SfCbs78IOxLfm UjDAEEH4jcFmqXVN6XEmuNBaLzQcMb6hV7T+7n2kziEQ6MDrt067QNvxUrcOqRiJjXdJ A+2Q== X-Gm-Message-State: APjAAAXCnfRUtDPM/FW7GP0TRCusvELyMyyy5wxnwHSEAdFRaMhPpC7X tgCPhlwDd+BkYBYLXbSjowv2VUWkcf90mw== X-Google-Smtp-Source: APXvYqxxP09lzpvQqNtXgAdPcYOHDYks8o7ByFGa7jDuUH2ba1Ai+21qSE2QmLngXEOmjneUd5dHZQ== X-Received: by 2002:adf:e28a:: with SMTP id v10mr1424716wri.178.1561999200375; Mon, 01 Jul 2019 09:40:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:11 +0100 Message-Id: <20190701163943.22313-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.49 Subject: [Qemu-devel] [PULL 14/46] aspeed: add support for multiple NICs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: C=C3=A9dric Le Goater The Aspeed SoCs have two MACs. Extend the Aspeed model to support a second NIC. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Message-id: 20190618165311.27066-7-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 3 ++- hw/arm/aspeed_soc.c | 33 +++++++++++++++++++-------------- 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index b613b00600f..75b557060b9 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -25,6 +25,7 @@ #define ASPEED_SPIS_NUM 2 #define ASPEED_WDTS_NUM 3 #define ASPEED_CPUS_NUM 2 +#define ASPEED_MACS_NUM 2 =20 typedef struct AspeedSoCState { /*< private >*/ @@ -43,7 +44,7 @@ typedef struct AspeedSoCState { AspeedSMCState spi[ASPEED_SPIS_NUM]; AspeedSDMCState sdmc; AspeedWDTState wdt[ASPEED_WDTS_NUM]; - FTGMAC100State ftgmac100; + FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; } AspeedSoCState; =20 #define TYPE_ASPEED_SOC "aspeed-soc" diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index d38fb0aaa0f..736e52366a6 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -234,8 +234,10 @@ static void aspeed_soc_init(Object *obj) sc->info->silicon_rev); } =20 - sysbus_init_child_obj(obj, "ftgmac100", OBJECT(&s->ftgmac100), - sizeof(s->ftgmac100), TYPE_FTGMAC100); + for (i =3D 0; i < ASPEED_MACS_NUM; i++) { + sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]= ), + sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); + } } =20 static void aspeed_soc_realize(DeviceState *dev, Error **errp) @@ -382,19 +384,22 @@ static void aspeed_soc_realize(DeviceState *dev, Erro= r **errp) } =20 /* Net */ - qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]); - object_property_set_bool(OBJECT(&s->ftgmac100), true, "aspeed", &err); - object_property_set_bool(OBJECT(&s->ftgmac100), true, "realized", - &local_err); - error_propagate(&err, local_err); - if (err) { - error_propagate(errp, err); - return; + for (i =3D 0; i < nb_nics; i++) { + qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]); + object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", + &err); + object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized= ", + &local_err); + error_propagate(&err, local_err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, + sc->info->memmap[ASPEED_ETH1 + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, + aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, - sc->info->memmap[ASPEED_ETH1]); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0, - aspeed_soc_get_irq(s, ASPEED_ETH1)); } static Property aspeed_soc_properties[] =3D { DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0), --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.00 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wbaK2lk4yZHP52j/5+PW5BzsdFPHnkuejkFeyT9B6iY=; b=fKNZZew5Oh02CcxlKp2lEV04XxxkatzL6oCiuE3zqI6/RoSINksSra+/JteNGuKeE2 Fv5edWUc/wL7d6Asf1HM/ldpFU2nGJB9r37hnOPyw1nB8aipJJb5zAqkzGK1LdCdFoEI tlTdH7dAQLRI3Ouz47bjXeTZ2j03anFT/OVT8gURDvaT24WJimi57OuqakybGLElo34i +kMBNXcC5bPsBwLiVBe6nps42etI2oY9mwF2kaTXj/KegjoUSNPqOJNu/Y5JpYYg3lLC E6SYxx0Q3BwOjdyxznW2c9IZSLqMwzDUWifR1IUZ+58+MeuItkjd3j6SMXoFmlEUG7B1 JfYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wbaK2lk4yZHP52j/5+PW5BzsdFPHnkuejkFeyT9B6iY=; b=fQoC7Ccwc1rt1nGLuhd1Ix14bzQxffcDNe2ClqwGkWTV0+bU/2WXJ6jk/n9mTCc1Kj oXrJCCkXgbhqTt33G475qy21EQCc0fTO5VmmS6UHeH7H7o7cmKBXxYw8m6H5jsg7JcDt +GdcKvRYD9YiHLQyebVeEuLhgsHLES0W1vN1mIQP9TrFXNuy5xj3CUp9tX++Ft402p9C No5qVUgHnqrZXgH9utFMDUE5Om9WJhiPnRipFBC2MVIeg7TqN9I5q7a8INHfpe/Aru+U NvA7OjbuysEYFDnXhPi1njUvFrl7XZQPJOrI8etvZDP62OEkvHpVlxYNZaEojTAZmJTr xaSg== X-Gm-Message-State: APjAAAXqDmO5b/JSOAmbCXbvrVCXhbbqwBI7S7QYumI0cq/gdrCA8iir CZX6w9bxh6LUrwk/tgDmaKvI23xr2VbWlg== X-Google-Smtp-Source: APXvYqyntrThvsXnDgmb3Jvc2F4qwOVxFWJlUiUGcjNnuo+nYw6R91DADJ8zyoqesNcI/ywnEdy9hQ== X-Received: by 2002:a5d:5386:: with SMTP id d6mr11726003wrv.207.1561999201868; Mon, 01 Jul 2019 09:40:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:12 +0100 Message-Id: <20190701163943.22313-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.44 Subject: [Qemu-devel] [PULL 15/46] aspeed/timer: Fix behaviour running Linux X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Joel Stanley The Linux kernel driver was updated in commit 4451d3f59f2a ("clocksource/drivers/fttmr010: Fix set_next_event handler) to fix an issue observed on hardware: > RELOAD register is loaded into COUNT register when the aspeed timer > is enabled, which means the next event may be delayed because timer > interrupt won't be generated until <0xFFFFFFFF - current_count + > cycles>. When running under Qemu, the system appeared "laggy". The guest is now scheduling timer events too regularly, starving the host of CPU time. This patch modifies the timer model to attempt to schedule the timer expiry as the guest requests, but if we have missed the deadline we re interrupt and try again, which allows the guest to catch up. Provides expected behaviour with old and new guest code. Fixes: c04bd47db6b9 ("hw/timer: Add ASPEED timer device model") Signed-off-by: Joel Stanley Signed-off-by: C=C3=A9dric Le Goater Message-id: 20190618165311.27066-8-clg@kaod.org [clg: - merged a fix from Andrew Jeffery "Fire interrupt on failure to meet deadline" https://lists.ozlabs.org/pipermail/openbmc/2019-January/014641.html - adapted commit log - checkpatch fixes ] Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: Peter Maydell --- hw/timer/aspeed_timer.c | 57 ++++++++++++++++++++++------------------- 1 file changed, 30 insertions(+), 27 deletions(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 2c3a4d0fe77..537f072cf87 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -109,37 +109,40 @@ static inline uint64_t calculate_time(struct AspeedTi= mer *t, uint32_t ticks) =20 static uint64_t calculate_next(struct AspeedTimer *t) { - uint64_t next =3D 0; - uint32_t rate =3D calculate_rate(t); + uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint64_t next; =20 - while (!next) { - /* We don't know the relationship between the values in the match - * registers, so sort using MAX/MIN/zero. We sort in that order as= the - * timer counts down to zero. */ - uint64_t seq[] =3D { - calculate_time(t, MAX(t->match[0], t->match[1])), - calculate_time(t, MIN(t->match[0], t->match[1])), - calculate_time(t, 0), - }; - uint64_t reload_ns; - uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + /* + * We don't know the relationship between the values in the match + * registers, so sort using MAX/MIN/zero. We sort in that order as + * the timer counts down to zero. + */ =20 - if (now < seq[0]) { - next =3D seq[0]; - } else if (now < seq[1]) { - next =3D seq[1]; - } else if (now < seq[2]) { - next =3D seq[2]; - } else if (t->reload) { - reload_ns =3D muldiv64(t->reload, NANOSECONDS_PER_SECOND, rate= ); - t->start =3D now - ((now - t->start) % reload_ns); - } else { - /* no reload value, return 0 */ - break; - } + next =3D calculate_time(t, MAX(t->match[0], t->match[1])); + if (now < next) { + return next; } =20 - return next; + next =3D calculate_time(t, MIN(t->match[0], t->match[1])); + if (now < next) { + return next; + } + + next =3D calculate_time(t, 0); + if (now < next) { + return next; + } + + /* We've missed all deadlines, fire interrupt and try again */ + timer_del(&t->timer); + + if (timer_overflow_interrupt(t)) { + t->level =3D !t->level; + qemu_set_irq(t->irq, t->level); + } + + t->start =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + return calculate_time(t, MAX(MAX(t->match[0], t->match[1]), 0)); } =20 static void aspeed_timer_mod(AspeedTimer *t) --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562014475; cv=none; d=zoho.com; s=zohoarc; b=Q7wHFsis5VlWq+82GmDxNEgar6afUVQrJlBsT6ooX3dtBSt0CZAlpfRRxpaIUeS0LHydehAqafBW8mFwYikg+jLIznJJqqLf9+ks9/eg/GNPtXHLi5vKZCX73v+ox3H2YHCAvqA933KZ/EcwHmbhtCt4GYEy/z3+wRERKRhAY8w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562014475; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=mZ6UaTHJQ/2uqJDbG+FXLikrSjiMTyAKTGAbvzcGyPU=; b=lLBkcgTd/MUfS2CpzMqCSwpo+++KBKrxkDotdNVXA7xqm40uk5533M6NQ6YrNSRlKKNeDie85pCPZBKiYvDp9hKFyfNHDY1dNJHOzFNwmVwZsLnHn4Gb/AozYN9Ibtz4hMgAB9itmiGNopAaIopMFB66/8QlEZRiSTCaYuCtFtc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562014475774684.6022702132223; Mon, 1 Jul 2019 13:54:35 -0700 (PDT) Received: from localhost ([::1]:45444 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3Jo-0005Wo-OM for importer@patchew.org; Mon, 01 Jul 2019 16:54:32 -0400 Received: from eggs.gnu.org ([209.51.188.92]:43903) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3CN-0000P0-Ue for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:46:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3CJ-0000ai-QC for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:46:49 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:42169) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3CD-0000WX-Qw for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:46:43 -0400 Received: by mail-wr1-f67.google.com with SMTP id x17so15244614wrl.9 for ; Mon, 01 Jul 2019 13:46:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.01 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mZ6UaTHJQ/2uqJDbG+FXLikrSjiMTyAKTGAbvzcGyPU=; b=h7t6IQeAD2YH1nRXEGZwMsApACnrIidZ2SNCxC0shTAl4sTs6gdpS+r7NkRkaRIfV/ Rlvk0jiHGAR5FiLDCO/3oc5JDg1y674JUuBGLMq1R5Di/DEoUL/X2uWcMlt4JIeZ7l2u HUwU9CgIQlJQqWiEH6YcS1Qp9yof+tC+SeNTW80q5E81OUb+8zGvcEzFVntYHB1xLbLZ O5XYV+JfNe9O8JwuVhpaOBTxhBWcnsq7dEV6FIyRMRUVZtwhdu0V1VtTCxjcdO1eXIxc do1uvvKP3yPmA4D07WboTXi7smFG+a2ZxS0j66976BGNGkjnqz8yh30OntMnnZbKz/oZ Oq2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mZ6UaTHJQ/2uqJDbG+FXLikrSjiMTyAKTGAbvzcGyPU=; b=tBBukOcQZgigUFBzPgTd/7sB6lCsctP0w/FFQhPmBijS3J7+BPt/zGJc8dVWjmHzhf QrbxPWGqmyh1jIp9+hJXb+1I6srn633zKpfqwwauZ7sYoXQMJOXdfRfxoDnoY6Fqs+sa MGMwAKfFEj4t6fkmIlQ+6f9NSXu1KXlCluqEezEj42u85LP1OGt6cD8IzrNwfRUjHaaw Z/EIhIBmN/epz5sjyR+jGvojndHab1BMP1frpQ17Aoq16rPWDC/nb2u/KcSVFY3m7sYK d+u10Q7xUn5FKtBlhgCt6+sPB10R1RchNTEmgTM+HBs+dnxrosvsVWLVRshzvIa6lWiW P5NQ== X-Gm-Message-State: APjAAAVY9pvDZdBwBKgIS2Yvn9kAER6+m0b+D3EaEM/tFRLIgAUd67Ma Que4970N1t/f+gEh2SySdd5SoQURuKQXuA== X-Google-Smtp-Source: APXvYqzrPHZuKwQLUqEUxTV/KIuOkrhKrBReEj7+ui6PfON5bX4YPDIer2IfRkQqWfxdfU+vRFyrkg== X-Received: by 2002:adf:f589:: with SMTP id f9mr20206113wro.90.1561999202886; Mon, 01 Jul 2019 09:40:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:13 +0100 Message-Id: <20190701163943.22313-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.67 Subject: [Qemu-devel] [PULL 16/46] aspeed/timer: Status register contains reload for stopped timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Andrew Jeffery From the datasheet: This register stores the current status of counter #N. When timer enable bit TMC30[N * b] is disabled, the reload register will be loaded into this counter. When timer bit TMC30[N * b] is set, the counter will start to decrement. CPU can update this register value when enable bit is set. Signed-off-by: Andrew Jeffery Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Message-id: 20190618165311.27066-9-clg@kaod.org Signed-off-by: Peter Maydell --- hw/timer/aspeed_timer.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 537f072cf87..8d6266b0fd8 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -187,7 +187,11 @@ static uint64_t aspeed_timer_get_value(AspeedTimer *t,= int reg) =20 switch (reg) { case TIMER_REG_STATUS: - value =3D calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)= ); + if (timer_enabled(t)) { + value =3D calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRT= UAL)); + } else { + value =3D t->reload; + } break; case TIMER_REG_RELOAD: value =3D t->reload; --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562017594; cv=none; d=zoho.com; s=zohoarc; b=CNA1s7JyePhCWKwvSgOfUfuqn4fb4i9HyO2sf1tTFRRbug3lOOPLHDz5u/TFTh+Ra+hYkpQbu0dm8Tls37nmq5QHzQY+V6IyV8W5ENfv8Aph+BAcoMW6zo3Uxg+WGLmHzneb//HOTeN8fdHgIXjFbMWEusQ59EZwARyxKHJ8oRM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562017594; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=NSiFpefnwqGsQxlF73UeZNcosVDLd7kx/8RbZQ5Fgqc=; b=L3K/dhLlH9TtbmSimN+2N9mwn4342qV5ALFXMRhS05qTixePfYP3NC0VQt9qtTEJekoC0WHeZoGx8QvHwrVnvNG6N8LAnUFFnxgryRuX3zGNykh1DVFNGpebh59rIUP30qQQLgZR+hMTpEZw+k8Q17uas6iZ0JwwIRNjEJRoBi4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 15620175943951016.025296436033; Mon, 1 Jul 2019 14:46:34 -0700 (PDT) Received: from localhost ([::1]:45770 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi484-0003BX-ED for importer@patchew.org; Mon, 01 Jul 2019 17:46:28 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47217) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3IH-0004xW-WF for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:53:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3IE-0003Wo-7S for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:52:55 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:41095) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3ID-0003Vg-Vp for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:52:54 -0400 Received: by mail-wr1-f66.google.com with SMTP id c2so15282646wrm.8 for ; Mon, 01 Jul 2019 13:52:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.02 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NSiFpefnwqGsQxlF73UeZNcosVDLd7kx/8RbZQ5Fgqc=; b=HgF/WC6Bw8ZLbR9X7Nj9iRL3HglUY/qrNUFOVkI68FaWm/vsch/wSfYuTYTgxJgF0O pR3VwgU1ka3sFuhSOqkRDrKxHnWnQaTgefbL10uZZbLXcPtgBBNrkv1g9YEn5diKYSBj 2DKuzitpKABxqh2KvBV0oLbGKX0iMfpf9jNplE90+RWWP3yXbdto7jWPMMrKsPo3jGrd FS1hFhTpboYRo9daOb5F/JpQJwCo/+jwQU+YDOOhZqdsLbiCO3Tzq/nYG7cKWI3/n9hK IawESfUdRwhKBYgAZAFwlwf+G/dQDzbHhpUBypqo2O2N/uvQl6gGx4bgiePIb9arz+0U AIRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NSiFpefnwqGsQxlF73UeZNcosVDLd7kx/8RbZQ5Fgqc=; b=R1HFU/FsofmNoAcd1hbl0NPb6AsNHJ7e0gSnyXdk3I0XsllUoMNYd9hHjAyoFmsLl2 D7i5vuKUrNp2SqhrmiS3J0sgat0c6m5gR/g/kgWa2R7UaCUKEqvo1wqpynELUNovfhP7 fT6zqeCi4y76ZhMUQOiWGq8GEurRLq90nMH7/2t9qX2QOQBQmNCkIFYzvkUQK1opGf1X P1BBS+QI5LMqAUkOU+xG3Ytde38ODwMKogyClgbfVSqe6+opIrfOJDEZ0O7ROYWp6On0 /1i+9/9szNC+XEztkk30rCPUiMmlWOPxgiGD1trMvNiHTsYuUgwbGmxRmuKHHO1QWdMB EIUQ== X-Gm-Message-State: APjAAAWUEnGlRq47dw3WIxfTk65Du/i3SEJ1kADWA+ja+5CtNNGba8hN hjaqTZ2lKcNu/FATIKuy1KgCX+A723oL/Q== X-Google-Smtp-Source: APXvYqxEX7KgYha/GjNe+vKR+nSMnYUX/6du1q2Ng3NgZa8NLbMSqF+1I1I5wAY8MQva2HeOLj54Xw== X-Received: by 2002:a5d:42c5:: with SMTP id t5mr18845683wrr.5.1561999203905; Mon, 01 Jul 2019 09:40:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:14 +0100 Message-Id: <20190701163943.22313-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.66 Subject: [Qemu-devel] [PULL 17/46] aspeed/timer: Fix match calculations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Andrew Jeffery If the match value exceeds reload then we don't want to include it in calculations for the next event. Signed-off-by: Andrew Jeffery Signed-off-by: C=C3=A9dric Le Goater Message-id: 20190618165311.27066-10-clg@kaod.org Signed-off-by: Peter Maydell --- hw/timer/aspeed_timer.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 8d6266b0fd8..745eb8608b5 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -107,6 +107,11 @@ static inline uint64_t calculate_time(struct AspeedTim= er *t, uint32_t ticks) return t->start + delta_ns; } =20 +static inline uint32_t calculate_match(struct AspeedTimer *t, int i) +{ + return t->match[i] < t->reload ? t->match[i] : 0; +} + static uint64_t calculate_next(struct AspeedTimer *t) { uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -118,12 +123,12 @@ static uint64_t calculate_next(struct AspeedTimer *t) * the timer counts down to zero. */ =20 - next =3D calculate_time(t, MAX(t->match[0], t->match[1])); + next =3D calculate_time(t, MAX(calculate_match(t, 0), calculate_match(= t, 1))); if (now < next) { return next; } =20 - next =3D calculate_time(t, MIN(t->match[0], t->match[1])); + next =3D calculate_time(t, MIN(calculate_match(t, 0), calculate_match(= t, 1))); if (now < next) { return next; } @@ -141,8 +146,10 @@ static uint64_t calculate_next(struct AspeedTimer *t) qemu_set_irq(t->irq, t->level); } =20 + next =3D MAX(MAX(calculate_match(t, 0), calculate_match(t, 1)), 0); t->start =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - return calculate_time(t, MAX(MAX(t->match[0], t->match[1]), 0)); + + return calculate_time(t, next); } =20 static void aspeed_timer_mod(AspeedTimer *t) --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562034448; cv=none; d=zoho.com; s=zohoarc; b=W5ef9SCQATfc2EImgYY2vgNBUsSr3ZjiN1GMOSXHxt5ugEE2ErhAkJuiC0BEnZv2Gm4BEJ6mv4PdNl/29rm9Z+5tKeG5CxFWaCmwvZ3P9Jo3TdsUdLKFqEOsG3LRjQo/zN0ACwBnHraMbnrg7l+ZLNNrYodrJsWGE9MZj9scR+s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562034448; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=SM8mY+R0SiuBOfCMBxDLwmP2jvWXg+rVriH+MW5T7NQ=; b=n0UoUL/ivbW9Wh5M2YqMGc/JYXTk8o+eP0BkTN0hTLYQwutfY5hQaMc6Na2AcgzqChZBKm3JJXIfLuHAnXelPLuptpElsJLtk+KFYNiZp3f/mxmFvxYduMU659oQU20aYX9QX66/UzWO4pWnnGeV/ZY9Nf8YOVPcy8Xy7gXpuPs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562034448162879.6134051657734; Mon, 1 Jul 2019 19:27:28 -0700 (PDT) Received: from localhost ([::1]:47264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi8Vz-00059u-5m for importer@patchew.org; Mon, 01 Jul 2019 22:27:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58855) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4Z1-00058v-8U for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:14:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi4Z0-0003mR-74 for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:14:19 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:41720) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi4Z0-0003m0-0P for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:14:18 -0400 Received: by mail-wr1-f66.google.com with SMTP id c2so15466177wrm.8 for ; Mon, 01 Jul 2019 15:14:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.03 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=SM8mY+R0SiuBOfCMBxDLwmP2jvWXg+rVriH+MW5T7NQ=; b=BcKv3pdK6VP3YAvICZ3IjFWl8q1SUNfgZVufEMve5wV23Y9aKngp7BhjFG3Lfwflji vXaGU0aO3uJnFcAWRygMdhXJ2ZePDe53efT/3XN0Gyh7T8rx8CrV0auXxalGzoJBw4/A c65cRGaNitO2d9kW75cz8dkPys7TAN6z8VE1OMAqSUs3x/wPrnp/a/q7JVd9T+zJ5PFi jmi86rSre0NHaa2KEhF9dPRNvMwxDsM9WjptMZA2SCkSE0UgeS1xGz/O/vUV2V6dOXPQ j0dpacPdzSyBERnahO2v4ZVbmXGnG0hQzm6s6ZtqwNJY8p7GR3pFkhYoDV4Yn2TnmlUP VXSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SM8mY+R0SiuBOfCMBxDLwmP2jvWXg+rVriH+MW5T7NQ=; b=C8eP99jhMev0rUeJzXjc2IV2LbLpnKoqer7wdYe7Zy57+PHXaVAEbgSg8tzhiMGPB0 0kldTxoIw3jORbNq52wLdxUvzgsP39BfENolcsqKvznyLUeSdG42EHcT6rkXdoX5rKon FRsSMAyrQrqhfu7oyqmVFEwamjdFlJCmNl4xI8vmOTX4m8l7XyZvjZOKcC7Ar2vXvsUG FAExM3ZzaRDmgBU9ZIvin/4AtpOn4kX8zNzsLHv5khmrpi7C3f5V/tJeNVwPBmNX9fUY 08ddBes0usyUttWZIB8IWZtrbXKErHWVCrwTfvRYoDI5/LmDqPIriToObCsxVCGkjAW2 G/Fg== X-Gm-Message-State: APjAAAWrxXxKui2m54gR2Q5r+pEgwkLrI9lj1r2sPnXLGBXCRDGt0S+V uimN+HyVhw4aNqhiU9a14yK34PpPDwjBzA== X-Google-Smtp-Source: APXvYqxKgF3m5Olw4flHXvWP4Bn+sryjaKJzfiMfXIOtoIT+qhRcBaYZhuPwFrzbfEsEiq/7UC+pzA== X-Received: by 2002:adf:dc09:: with SMTP id t9mr1952549wri.69.1561999204945; Mon, 01 Jul 2019 09:40:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:15 +0100 Message-Id: <20190701163943.22313-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.66 Subject: [Qemu-devel] [PULL 18/46] aspeed/timer: Ensure positive muldiv delta X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Christian Svensson If the host decrements the counter register that results in a negative delta. This is then passed to muldiv64 which only handles unsigned numbers resulting in bogus results. This fix ensures the delta being operated on is positive. Test case: kexec a kernel using aspeed_timer and it will freeze on the second bootup when the kernel initializes the timer. With this patch that no longer happens and the timer appears to run OK. Signed-off-by: Christian Svensson Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Reviewed-by: Andrew Jeffery Message-id: 20190618165311.27066-12-clg@kaod.org Signed-off-by: Peter Maydell --- hw/timer/aspeed_timer.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 745eb8608b5..29cc5e80708 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -275,7 +275,11 @@ static void aspeed_timer_set_value(AspeedTimerCtrlStat= e *s, int timer, int reg, int64_t delta =3D (int64_t) value - (int64_t) calculate_ticks(= t, now); uint32_t rate =3D calculate_rate(t); =20 - t->start +=3D muldiv64(delta, NANOSECONDS_PER_SECOND, rate); + if (delta >=3D 0) { + t->start +=3D muldiv64(delta, NANOSECONDS_PER_SECOND, rate= ); + } else { + t->start -=3D muldiv64(-delta, NANOSECONDS_PER_SECOND, rat= e); + } aspeed_timer_mod(t); } break; --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562018049; cv=none; d=zoho.com; s=zohoarc; b=WddTKQV9KSgq52EOic6d1hvF8s+TKgn/do+JYzpkxrr4E6Wk/Mr2jnIDImvAP9a0iZlrNLMdGm26f3VpuvROMDT89n/zEUQYOPdmacmRTytVc3jZmTE+25G4RvTVxLr9f+8DlDAc1nT3Sevm1xiI/hL9iyx8eA5DkKsqxo24iRs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562018049; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=O0qux12GpX3gODzOI2UowV8fi9llKB8go8fG3JIr+S8=; b=d3T/O2FYyiFfX3yYWJqEUBNx+R5zQOEFSoDpunKL8kzUO7/vcV7v3WYMPOXeFkNKPR7r60jbiyWNKHYhZ7xv0J1FoZNV7Ly2XwFlK58LpU+114cg8Pj4/6faUWbXNUh8RCNi6CRqCNAprCh20N1E7Rm+xdgF33rMSzQd+KpuW3o= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562018049539754.806114577077; Mon, 1 Jul 2019 14:54:09 -0700 (PDT) Received: from localhost ([::1]:45804 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4FP-0006Vd-FM for importer@patchew.org; Mon, 01 Jul 2019 17:54:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54904) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3WK-0006qa-Sp for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:07:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3WH-0005e5-Jt for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:07:27 -0400 Received: from mail-wm1-f53.google.com ([209.85.128.53]:55422) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3WH-0005cz-BV for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:07:25 -0400 Received: by mail-wm1-f53.google.com with SMTP id a15so843347wmj.5 for ; Mon, 01 Jul 2019 14:07:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.04 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=O0qux12GpX3gODzOI2UowV8fi9llKB8go8fG3JIr+S8=; b=WrtLyyntmoC4ZuLUeUCgEuzq/5QpinYuVKuaXzq/FLGL5WBS5BTpDgrZ6b/7H9YocE YxYFtqTpK2hf88InI9tg3fxGXFsL6EHAhTQw1oDfgbbkc85tQjjszhVp9Ge5s0TxmsXa cM3QNc5009w7vYHi/+6wFfhuXZfKNjoZiK6wtvhdFp7TKf8Q9SXGVYPzz35E9oPZdMrw oCcaC+18Qsy6pl3RApboc76jsXhzDXL2/0Wjl52IaQKty9imG/lwR6MpxIQOskFGt1ff 1ZNEyA8VqePYF96yYH0li/GeW43YKfuEjVfIbyLH5xqVC3f1ihiv7hVl8U8xbM1QCeld 583Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O0qux12GpX3gODzOI2UowV8fi9llKB8go8fG3JIr+S8=; b=F5lFrs7cZRmzTZs/QRybvnugSaz1ft0jbAzB9BMsgQqDDeKoHPFGbiihgZerMM1+ac +m0osFVeXzaKOOgVMd2skltkKmo59nyb1SzpqC7Yinvlq39AgIn91yH11v5bf+NF3XTQ T2fbNfKOT5LO3uXpssCvJk4a8ojdH+TfCZs4JcyPTlAs3ggeGSDQrGzooPTsMtPAPpWk BmcjcPRfim3+J9zfW6Dh8gjgWhZVn/a+lzfoV58HrP1KcqrDbW+2x/YM7SS8TDfZepsc +JdMWOG7FRUkMlRzG4Q+V/Z0uEuzOOAEAmRM51s3pYlnZoLrfNeIK576v+H5OrE+4b4x 9Xmg== X-Gm-Message-State: APjAAAWk8MP6mNq3p9oXSZ3mPJyXED6SMshXCsUNofDF6fWL/VABI1op WpJzgibxbFFkriuzieN8OSfxJ/8TRRGtJw== X-Google-Smtp-Source: APXvYqwHo1LY6zFx8HWkozeobRgA0Ah6oOAEFTOPy7YZAv4fXNURX4Bg9AwJpdUfzIOkCHnGo19wfg== X-Received: by 2002:a1c:63d7:: with SMTP id x206mr122570wmb.19.1561999205891; Mon, 01 Jul 2019 09:40:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:16 +0100 Message-Id: <20190701163943.22313-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.53 Subject: [Qemu-devel] [PULL 19/46] aspeed: remove the "ram" link X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: C=C3=A9dric Le Goater It has never been used as far as I can tell from the git history. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Message-id: 20190618165311.27066-13-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 96de4f5c2a8..5d73267da16 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -195,8 +195,6 @@ static void aspeed_board_init(MachineState *machine, memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); memory_region_add_subregion(get_system_memory(), sc->info->memmap[ASPEED_SDRAM], &bmc->ram); - object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->= ram), - &error_abort); =20 max_ram_size =3D object_property_get_uint(OBJECT(&bmc->soc), "max-ram-= size", &error_abort); --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562019791; cv=none; d=zoho.com; s=zohoarc; b=kv+5ehTdB2Qe4uQNb8iTTmBUz3oA1/RXIDqRlE9W2qj9UPUrO8Xs2ck8XGR20YudzosVxZ7R5SMXEJvImHsemSvDODxSNMcnFn7JiF9qced6KAIf30VaFKylKH5KqjhtJZRijPYKEyIiypDd6/p0cCcPx/r6CAqLv6RX5RxJjDQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562019791; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ehjkWhdt19qHAzsl/X1nqYdNDUK2w3SB8ITjOfQ+4TI=; b=SVwyxfuEtF7HcKfzpHJYQi06Yr1Q+Ti33wVMyVG4fxmkTL+INeD7KaIFTFv4z9ZpS2jO0jnQpI8IJdiALVJEvphI/Wj7JszB9y2OelS1NcDZBPlmZYE96/eCV2NyAPkxJtnvQKPWBh9LrOu9NX9BH6dh/hzidB+/RWygBx3dcMg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562019791512765.8440514889353; Mon, 1 Jul 2019 15:23:11 -0700 (PDT) Received: from localhost ([::1]:46038 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4hS-0001ke-8F for importer@patchew.org; Mon, 01 Jul 2019 18:23:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56639) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3Xp-0008KS-SE for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:09:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3Xm-0006aA-Bg for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:09:01 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:32804) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3Xm-0006XT-39 for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:08:58 -0400 Received: by mail-wr1-f65.google.com with SMTP id n9so15367038wru.0 for ; Mon, 01 Jul 2019 14:08:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.05 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ehjkWhdt19qHAzsl/X1nqYdNDUK2w3SB8ITjOfQ+4TI=; b=KMINlJErVZ7iKNRZ2mGI6agJBxPZ5UynPiAegrlvS+4aFfDW8o0FtGInDe6SF0CBki ZQPVCCikM5C2JGisHOb48SJO1HAoam0gnTjtq6yrgmli6Pso7Ur7mHNJKFo9zzWseSSh UMXS1xxDohNFbhxWdlq8RgLz+1/EqhdngSUQk7wwEtrt/NkvLphuqrEsxj5Inky6Ijc4 lC4HyzdbdBHaVxh6Moc1oNO0IKJ7H/IIWuOS6SSUOJbCHD+rrjmyuYpJLQbUwecLQJ0m uO+5ZOzBnESU8QnMlHp8gZ5pBxf9R9enZ56nKr7zF/4hgppj3kQy4gBBVtc5wlHUfOi0 sw/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ehjkWhdt19qHAzsl/X1nqYdNDUK2w3SB8ITjOfQ+4TI=; b=VMV3T2W4oWZJU92cq1to5fbvE8MMSeSpOg303d4fNZ4+mRKBknKwgRPcTKXWaRnQNH EsGYZok2KBCP8Fm4PnKY4fPzk2Xfg/BrN1XnEwBEcVKWrZQV5hl4egR3tZ6JtZTrs2wm 0hX95nIilyB3gOatIZwLyEMJSW/K1Hi3IeYjwuf5EfV3ZWbJ8RpYlpbfLJsChA1WBPIy sWYbe/Yf4+1+7Zm2lKyNkfWEJi/BYyqPHLgzhIBx5CTELepWiiYxfyE+/R4N7w1++FxD yqIY5MYJ5qNw3+1PVIcnVwWibujqJi42I4DxotPK537T02NszNd+5+HQDUcxPa4fdzqY wDWQ== X-Gm-Message-State: APjAAAXNG7A/iCQ7FtWLok3EOkkFdW96ky3rVoaNXmVfPCVF3hfMzYmL j+r7kjxY8VEI7WL9XcSNyYFE5INNI84hxg== X-Google-Smtp-Source: APXvYqwgw42ETSsGk1LeD/uFWz5EaZ8D1CEOUaAm881AhiceVCqQ6nn9XTr7OlnlhxQ6tX9GCaQhcA== X-Received: by 2002:adf:e84d:: with SMTP id d13mr15985309wrn.88.1561999206838; Mon, 01 Jul 2019 09:40:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:17 +0100 Message-Id: <20190701163943.22313-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.65 Subject: [Qemu-devel] [PULL 20/46] aspeed: add a RAM memory region container X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: C=C3=A9dric Le Goater The RAM memory region is defined after the SoC is realized when the SDMC controller has checked that the defined RAM size for the machine is correct. This is problematic for controller models requiring a link on the RAM region, for DMA support in the SMC controller for instance. Introduce a container memory region for the RAM that we can link into the controllers early, before the SoC is realized. It will be populated with the RAM region after the checks have be done. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Message-id: 20190618165311.27066-14-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 5d73267da16..7f01df1b61d 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -33,6 +33,7 @@ static struct arm_boot_info aspeed_board_binfo =3D { =20 struct AspeedBoardState { AspeedSoCState soc; + MemoryRegion ram_container; MemoryRegion ram; MemoryRegion max_ram; }; @@ -159,6 +160,10 @@ static void aspeed_board_init(MachineState *machine, ram_addr_t max_ram_size; =20 bmc =3D g_new0(AspeedBoardState, 1); + + memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", + UINT32_MAX); + object_initialize_child(OBJECT(machine), "soc", &bmc->soc, (sizeof(bmc->soc)), cfg->soc_name, &error_abor= t, NULL); @@ -193,16 +198,16 @@ static void aspeed_board_init(MachineState *machine, &error_abort); =20 memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); + memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram); memory_region_add_subregion(get_system_memory(), - sc->info->memmap[ASPEED_SDRAM], &bmc->ram); + sc->info->memmap[ASPEED_SDRAM], + &bmc->ram_container); =20 max_ram_size =3D object_property_get_uint(OBJECT(&bmc->soc), "max-ram-= size", &error_abort); memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, "max_ram", max_ram_size - ram_size); - memory_region_add_subregion(get_system_memory(), - sc->info->memmap[ASPEED_SDRAM] + ram_size, - &bmc->max_ram); + memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_r= am); =20 aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort); aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abo= rt); --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562027411; cv=none; d=zoho.com; s=zohoarc; b=KBjxvKoRxwFk1/tReY94j9dyPMoqNh82Q1f73jaWx2iLZqR17PpV5OIePhFa0dg3DKpSnV1ktKKr4l88rmeKYAOy1ok4V6y+dyCmmgsDY1IQ3NXFFn9ZrO6fPZVHn6cdd2qs8gDiQCnYQzEsDOonF9t43LR4BEIVn9M470Uj8n8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562027411; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=pigEtb5VD7XCWgXu8Dli8Jr+xIcMfHiGbTXOqk3Rhsw=; b=NqfE021vO23FHi/5wqZagSP+BjiC1dVBbgYhgmgGItgKIFhp9mRqhUxKY7NOp5IGo+ZIodrkmWjX5mEmux2jB3KLnIlN32L9WKM4ZMy2U3GD8eGM4+bXSShunbSvlYRgeNOUGxFAigGlqunfm8JFcnGgCUfagYmkiBsiN7nVXJ8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15620274110671011.5233839794249; Mon, 1 Jul 2019 17:30:11 -0700 (PDT) Received: from localhost ([::1]:46412 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi6gQ-0003Ks-0k for importer@patchew.org; Mon, 01 Jul 2019 20:30:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51717) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi49X-00055t-Ac for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:48:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi49V-0007tU-0D for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:47:59 -0400 Received: from mail-wm1-f53.google.com ([209.85.128.53]:35496) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi49U-0007p1-KF for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:47:56 -0400 Received: by mail-wm1-f53.google.com with SMTP id c6so1081770wml.0 for ; Mon, 01 Jul 2019 14:47:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.06 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pigEtb5VD7XCWgXu8Dli8Jr+xIcMfHiGbTXOqk3Rhsw=; b=vPUIPgOjkGlkRG6lx/rCNLO7Iw+3S0ripCG9sc1xsogG9PgBE9Rpd+1Xk2cGvaKWyI eWt+CGyTi5aSrZv1FrS5xRN5Eo3f85N7RdRFDjFdYqB/5UcFDbKL7PewScczaRWGf+X1 iiRZTWGYd1uf9ypmgyEGcZFibYLTEPCZSvJ2wamf+QSknfFbR0N4LscAjrm62tMFSRNP clMzD2nGAJJlKHh4vRrjyMIeZ4dpjbUgrlEy/944+UPDrHDylj37Vv7XYKqQ6DHtfpw5 B4HNSxKrP6J24hUGneYWGTHGYVRbUW7bXm21ROWY41yeCrWnasXryOnrcX1GceypVSl3 r+NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pigEtb5VD7XCWgXu8Dli8Jr+xIcMfHiGbTXOqk3Rhsw=; b=WIRe65lcFHhTt1VyC05dRptvo+L2jRfdvGukOIV86fZ6JXptC5vssN9UsBUF8zX8Ru nEr3Un6IBckY3PHfU9bfCOsq50koy5uNN9vYSjsFKk1PhvS/aRIwdwnVmCKBoyeKMmj2 dLzyP4M0QA8bWLxm96e2k2QBkzFldBCysQTZse475HwRhRpbrB0i/pDAtjL5Bu5QmHoW pd+Prq9QX5k+/pPwzxBdqjKRzbDMJVpRHwzXHsJdhMpqFSuYYcl5vPM5WwzOihUYpNgk WYZQdrrO72M8G5PgziLCIZB0YiEI+GxlrP+dOqqRdM/oRGKzk0FDziCwRDC1muH1R9lR l1rg== X-Gm-Message-State: APjAAAUy96ntKiwvvkG36yHedmiVCoLioBopQOTuPoUdMtmSDz8I597d 6wE7+55o68Fa+hVAGmMcfGfpVHuMl7eIGQ== X-Google-Smtp-Source: APXvYqwprTbJML91UkqV0ad/rE4aw0+YEOZyt4g6w5IZAm8A2LCqc1pQGgRpuY8E6AMHKjWi4B2V/A== X-Received: by 2002:a1c:c109:: with SMTP id r9mr106069wmf.143.1561999207940; Mon, 01 Jul 2019 09:40:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:18 +0100 Message-Id: <20190701163943.22313-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.53 Subject: [Qemu-devel] [PULL 21/46] aspeed/smc: add a 'sdram_base' property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: C=C3=A9dric Le Goater The DRAM address of a DMA transaction depends on the DRAM base address of the SoC. Inform the SMC controller model with this value. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190618165311.27066-15-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/ssi/aspeed_smc.h | 3 +++ hw/arm/aspeed_soc.c | 6 ++++++ hw/ssi/aspeed_smc.c | 1 + 3 files changed, 10 insertions(+) diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 3b1e7fce6c8..591279ba1f4 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -97,6 +97,9 @@ typedef struct AspeedSMCState { uint8_t r_timings; uint8_t conf_enable_w0; =20 + /* for DMA support */ + uint64_t sdram_base; + AspeedSMCFlash *flashes; =20 uint8_t snoop_index; diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 736e52366a6..02feb4361ba 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -337,6 +337,12 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) aspeed_soc_get_irq(s, ASPEED_I2C)); =20 /* FMC, The number of CS is set at the board level */ + object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM= ], + "sdram-base", &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 9eda0d720be..81f2fb7f707 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -913,6 +913,7 @@ static const VMStateDescription vmstate_aspeed_smc =3D { =20 static Property aspeed_smc_properties[] =3D { DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1), + DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562018367; cv=none; d=zoho.com; s=zohoarc; b=mjGqELB1R6RnFald1YUXsUWfkvCP0mMo+qQ19ryDvVnzohhKMSNbjaKDse9QBs/NKVl6cEKCSUId7qASCP1rngne1HYxvAX/uxsnp84+43xt9UOo/d0tVP4xr0OzPk+jF18cIOd/rfIb0ZVI75lFgsZulELnX+rSoZe2157t6EA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562018367; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=0fHjbhgF7m8C4s1QBD+xWxolDP9qtqhdoa9wWejRTJA=; b=NCHK8ibfnJpSLJYNW4b1G6/JsXkBdFAkD9V3PzsZmP2+lg1NRebgPml/9oXlYVW86hplnllZyY04PSsTQCIW0QRUoO5e5qJDAc0Vz62sF1CAmm4Q4ru2K9p63qfQVRsl3pmCvrLDlj9wuQXFR6OkGhyYjFgixuUMK5enpShQZ4g= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562018367567265.475246103023; Mon, 1 Jul 2019 14:59:27 -0700 (PDT) Received: from localhost ([::1]:45868 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4Kc-0002Y5-ED for importer@patchew.org; Mon, 01 Jul 2019 17:59:26 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47997) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3Jo-0006RE-TW for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:54:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3Jl-00043u-PS for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:54:30 -0400 Received: from mail-wm1-f47.google.com ([209.85.128.47]:51201) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3Jl-00041L-Bn for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:54:29 -0400 Received: by mail-wm1-f47.google.com with SMTP id 207so838509wma.1 for ; Mon, 01 Jul 2019 13:54:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.07 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0fHjbhgF7m8C4s1QBD+xWxolDP9qtqhdoa9wWejRTJA=; b=ffnshPO8F/gurxfmTl1kJFxAqyRnRzz3GJazOnwDBI3AmryIGS9I9yENWcLuF0nJc1 no0AhXfjbx5JPDoVxUYm2BaBnQOkO9NEcD8HFn0u0IlUT4WlTfcQwhxjzj/trL55l20v wov3NW7eavYFMQH2GxvNUxvwP2UVTHZu5j+Zp+wQDDI9AukQ22ZwKWPXn0DiuWNmo1e3 6XrzAUMWBEFtuEjThWUOTR8u94djcRLwcDIJ80k2svEHLMX662QjH3tJKy49uyVryZ1a 23WnB2+xYDiqgr99H0JwvRsClJjNCTrf8ih37Vi9Mc7h2iUhwR1/DK1fG+iIP1+im+SE hxbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0fHjbhgF7m8C4s1QBD+xWxolDP9qtqhdoa9wWejRTJA=; b=C+c1jz5/a3jfGkj/K5xpr+akiWLD9LZ+j7IkT6aruuI1FHEtqhAniZTz3NExbiKsKB +RO9gYcyQz95fDNyB31NkOIpdtgZFn/BXw6jguCNsxKChseglS6CZ0G9RxmxoIlqVcLF 8+bt5vRsVgMAH0N4BJmdaLtYyxGA5Wr8hQ6jdxRyrXAK1FZjXL/3TXB6HEuLS9+prdAB 7S3osVUk04zpFHVqeTmB2grGUmtHYecpU2AL7A07cp+x27Uo7aHoz8abRcDx3a+cQJ8G qVe/kWdrQckpUYhyMwiTdcjgjuEsZ3fmraL5Nr6PQVKPxVHvzp6ksRvEWUkb0DoJm8Vv kwPw== X-Gm-Message-State: APjAAAUv8q6lNiHU5Zy19l0RiXCLFK/pTuerDNq+wb2rdy9G6MgYvAav pxuOxQhaGA14J/sm3DesWpe0XFGHawgRQw== X-Google-Smtp-Source: APXvYqzhSNB/XZzcsmHGl/Rjv0Gce7PDiOczjrTi/qq/3XA4KW3S2DX40+lV9DSp5XEAOoH5S6fE3g== X-Received: by 2002:a1c:9c8a:: with SMTP id f132mr119087wme.29.1561999208877; Mon, 01 Jul 2019 09:40:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:19 +0100 Message-Id: <20190701163943.22313-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.47 Subject: [Qemu-devel] [PULL 22/46] aspeed: Add support for the swift-bmc board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Adriana Kobylak The Swift board is an OpenPOWER system hosting POWER processors. Add support for their BMC including the I2C devices as found on HW. Signed-off-by: Adriana Kobylak Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Message-id: 20190618165311.27066-20-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 7f01df1b61d..8b6d304247c 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -73,6 +73,17 @@ struct AspeedBoardState { SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) =20 +/* Swift hardware value: 0xF11AD206 */ +#define SWIFT_BMC_HW_STRAP1 ( \ + AST2500_HW_STRAP1_DEFAULTS | \ + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ + SCU_AST2500_HW_STRAP_UART_DEBUG | \ + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ + SCU_H_PLL_BYPASS_EN | \ + SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) + /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 =20 @@ -292,6 +303,35 @@ static void romulus_bmc_i2c_init(AspeedBoardState *bmc) i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", = 0x32); } =20 +static void swift_bmc_i2c_init(AspeedBoardState *bmc) +{ + AspeedSoCState *soc =3D &bmc->soc; + + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", = 0x60); + + /* The swift board expects a TMP275 but a TMP105 is compatible */ + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0= x48); + /* The swift board expects a pca9551 but a pca9552 is compatible */ + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "pca9552", = 0x60); + + /* The swift board expects an Epson RX8900 RTC but a ds1338 is compati= ble */ + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "ds1338", 0= x32); + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", = 0x60); + + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp423", 0= x4c); + /* The swift board expects a pca9539 but a pca9552 is compatible */ + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "pca9552", = 0x74); + + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "tmp423", = 0x4c); + /* The swift board expects a pca9539 but a pca9552 is compatible */ + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "pca9552", + 0x74); + + /* The swift board expects a TMP275 but a TMP105 is compatible */ + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", = 0x48); + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", = 0x4a); +} + static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) { AspeedSoCState *soc =3D &bmc->soc; @@ -382,6 +422,16 @@ static const AspeedBoardConfig aspeed_boards[] =3D { .num_cs =3D 2, .i2c_init =3D romulus_bmc_i2c_init, .ram =3D 512 * MiB, + }, { + .name =3D MACHINE_TYPE_NAME("swift-bmc"), + .desc =3D "OpenPOWER Swift BMC (ARM1176)", + .soc_name =3D "ast2500-a1", + .hw_strap1 =3D SWIFT_BMC_HW_STRAP1, + .fmc_model =3D "mx66l1g45g", + .spi_model =3D "mx66l1g45g", + .num_cs =3D 2, + .i2c_init =3D swift_bmc_i2c_init, + .ram =3D 512 * MiB, }, { .name =3D MACHINE_TYPE_NAME("witherspoon-bmc"), .desc =3D "OpenPOWER Witherspoon BMC (ARM1176)", --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.08 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jtDC6+RlmBJHfbCA1udB+lS55G6A49jnV1UvKe11c8o=; b=doeo1Nlk9UaOOivObZ7YmoEfYJpnB8L15MbfPltri3VZNmaI/yFn2bdXSmDpobWfUK BzYdubxf+lpG+O9MT0kqOwlzD63FQHpKuWTgYmZl+UxRyPonTPKerRFwNEROrgrWhEyq KCNCg/CpZ3RxhQxPIKEFl8HpjmJrP1hn2DokrjWOVZmrp8AZd0x+vUj+jJy4NYiaJNoU i7m7ZxMw4KGpOazY/9je8T9C2i/AA5Xk/rLZeb6isi6yjxyfZNjDm4CC86kSL9tze9Jw yRx/TYsRQuqPaNP+FngKyXKe8Bo6nPa7btWTM/OtcVdtXXKEFB4NiHBqFlIERyqOT57z UYOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jtDC6+RlmBJHfbCA1udB+lS55G6A49jnV1UvKe11c8o=; b=gRZpIWG8zQM4SYagAgb5qyQQ+o7qFpEV3NP6cVgIO10E0WReb+3V6vZL2X2x8bZW1G W++YBFswJ8O6PUqLteY4DfsUMLco23/bYpqe8aIIKniXb2rxQjs51lXxpUbkvvlU6g2H 6B7SZjxr0KTbz7DOtAku44BLUQ45NO4kLO1ccJ5vNLavbMnvvwbq7pAtII2nr6PPeYdI qc4oY9JtdqFEZ0yDTObv6A3GJOHcHfFGBYEzOLshL+ai8o5LCFgZoiOECV/9Dm3KRgqh xXPC43ZrBZ/MHX6dSdvlbcXAEQUjZ/Dproai58AwkD6AtaSw0ODKjxXsohb6hotYdSFQ t/BA== X-Gm-Message-State: APjAAAW3cAJ5Xe/U/l3MENX55+NlEGU03NI3crJfLJsF8Wv3yMC79V1m xV/NdUyNgopzx8swqcJ8jb2lMfy5sit6+Q== X-Google-Smtp-Source: APXvYqzX+/TeEcc+Of6b1LkyyJVbXhenRakwWEbBHU+SQEJkZP9GUzm4wYXu/8Svpq3OJ4ukweNZKg== X-Received: by 2002:a1c:f001:: with SMTP id a1mr139071wmb.130.1561999209936; Mon, 01 Jul 2019 09:40:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:20 +0100 Message-Id: <20190701163943.22313-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.51 Subject: [Qemu-devel] [PULL 23/46] hw/misc/aspeed_xdma: New device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Eddie James The XDMA engine embedded in the Aspeed SOCs performs PCI DMA operations between the SOC (acting as a BMC) and a host processor in a server. The XDMA engine exists on the AST2400, AST2500, and AST2600 SOCs, so enable it for all of those. Add trace events on the important register writes in the XDMA engine. Signed-off-by: Eddie James Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: C=C3=A9dric Le Goater Message-id: 20190618165311.27066-21-clg@kaod.org [clg: - changed title ] Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: Peter Maydell --- hw/misc/Makefile.objs | 1 + include/hw/arm/aspeed_soc.h | 3 + include/hw/misc/aspeed_xdma.h | 30 +++++++ hw/arm/aspeed_soc.c | 17 ++++ hw/misc/aspeed_xdma.c | 165 ++++++++++++++++++++++++++++++++++ hw/misc/trace-events | 3 + 6 files changed, 219 insertions(+) create mode 100644 include/hw/misc/aspeed_xdma.h create mode 100644 hw/misc/aspeed_xdma.c diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 77b9df9796e..e9aab519a1a 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -74,6 +74,7 @@ obj-$(CONFIG_ARMSSE_MHU) +=3D armsse-mhu.o =20 obj-$(CONFIG_PVPANIC) +=3D pvpanic.o obj-$(CONFIG_AUX) +=3D auxbus.o +obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_xdma.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o obj-$(CONFIG_MSF2) +=3D msf2-sysreg.o obj-$(CONFIG_NRF51_SOC) +=3D nrf51_rng.o diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 75b557060b9..cef605ad6bd 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -15,6 +15,7 @@ #include "hw/intc/aspeed_vic.h" #include "hw/misc/aspeed_scu.h" #include "hw/misc/aspeed_sdmc.h" +#include "hw/misc/aspeed_xdma.h" #include "hw/timer/aspeed_timer.h" #include "hw/timer/aspeed_rtc.h" #include "hw/i2c/aspeed_i2c.h" @@ -40,6 +41,7 @@ typedef struct AspeedSoCState { AspeedTimerCtrlState timerctrl; AspeedI2CState i2c; AspeedSCUState scu; + AspeedXDMAState xdma; AspeedSMCState fmc; AspeedSMCState spi[ASPEED_SPIS_NUM]; AspeedSDMCState sdmc; @@ -108,6 +110,7 @@ enum { ASPEED_ETH1, ASPEED_ETH2, ASPEED_SDRAM, + ASPEED_XDMA, }; =20 #endif /* ASPEED_SOC_H */ diff --git a/include/hw/misc/aspeed_xdma.h b/include/hw/misc/aspeed_xdma.h new file mode 100644 index 00000000000..00b45d931f8 --- /dev/null +++ b/include/hw/misc/aspeed_xdma.h @@ -0,0 +1,30 @@ +/* + * ASPEED XDMA Controller + * Eddie James + * + * Copyright (C) 2019 IBM Corp. + * SPDX-License-Identifer: GPL-2.0-or-later + */ + +#ifndef ASPEED_XDMA_H +#define ASPEED_XDMA_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_XDMA "aspeed.xdma" +#define ASPEED_XDMA(obj) OBJECT_CHECK(AspeedXDMAState, (obj), TYPE_ASPEED_= XDMA) + +#define ASPEED_XDMA_NUM_REGS (ASPEED_XDMA_REG_SIZE / sizeof(uint32_t)) +#define ASPEED_XDMA_REG_SIZE 0x7C + +typedef struct AspeedXDMAState { + SysBusDevice parent; + + MemoryRegion iomem; + qemu_irq irq; + + char bmc_cmdq_readp_set; + uint32_t regs[ASPEED_XDMA_NUM_REGS]; +} AspeedXDMAState; + +#endif /* ASPEED_XDMA_H */ diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 02feb4361ba..443e4c49f21 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -32,6 +32,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] =3D { [ASPEED_VIC] =3D 0x1E6C0000, [ASPEED_SDMC] =3D 0x1E6E0000, [ASPEED_SCU] =3D 0x1E6E2000, + [ASPEED_XDMA] =3D 0x1E6E7000, [ASPEED_ADC] =3D 0x1E6E9000, [ASPEED_SRAM] =3D 0x1E720000, [ASPEED_GPIO] =3D 0x1E780000, @@ -58,6 +59,7 @@ static const hwaddr aspeed_soc_ast2500_memmap[] =3D { [ASPEED_VIC] =3D 0x1E6C0000, [ASPEED_SDMC] =3D 0x1E6E0000, [ASPEED_SCU] =3D 0x1E6E2000, + [ASPEED_XDMA] =3D 0x1E6E7000, [ASPEED_ADC] =3D 0x1E6E9000, [ASPEED_SRAM] =3D 0x1E720000, [ASPEED_GPIO] =3D 0x1E780000, @@ -104,6 +106,7 @@ static const int aspeed_soc_ast2400_irqmap[] =3D { [ASPEED_I2C] =3D 12, [ASPEED_ETH1] =3D 2, [ASPEED_ETH2] =3D 3, + [ASPEED_XDMA] =3D 6, }; =20 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap @@ -238,6 +241,9 @@ static void aspeed_soc_init(Object *obj) sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]= ), sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); } + + sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), + TYPE_ASPEED_XDMA); } =20 static void aspeed_soc_realize(DeviceState *dev, Error **errp) @@ -406,6 +412,17 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); } + + /* XDMA */ + object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, + sc->info->memmap[ASPEED_XDMA]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, + aspeed_soc_get_irq(s, ASPEED_XDMA)); } static Property aspeed_soc_properties[] =3D { DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0), diff --git a/hw/misc/aspeed_xdma.c b/hw/misc/aspeed_xdma.c new file mode 100644 index 00000000000..eebd4ad540a --- /dev/null +++ b/hw/misc/aspeed_xdma.c @@ -0,0 +1,165 @@ +/* + * ASPEED XDMA Controller + * Eddie James + * + * Copyright (C) 2019 IBM Corp + * SPDX-License-Identifer: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "hw/misc/aspeed_xdma.h" +#include "qapi/error.h" + +#include "trace.h" + +#define XDMA_BMC_CMDQ_ADDR 0x10 +#define XDMA_BMC_CMDQ_ENDP 0x14 +#define XDMA_BMC_CMDQ_WRP 0x18 +#define XDMA_BMC_CMDQ_W_MASK 0x0003FFFF +#define XDMA_BMC_CMDQ_RDP 0x1C +#define XDMA_BMC_CMDQ_RDP_MAGIC 0xEE882266 +#define XDMA_IRQ_ENG_CTRL 0x20 +#define XDMA_IRQ_ENG_CTRL_US_COMP BIT(4) +#define XDMA_IRQ_ENG_CTRL_DS_COMP BIT(5) +#define XDMA_IRQ_ENG_CTRL_W_MASK 0xBFEFF07F +#define XDMA_IRQ_ENG_STAT 0x24 +#define XDMA_IRQ_ENG_STAT_US_COMP BIT(4) +#define XDMA_IRQ_ENG_STAT_DS_COMP BIT(5) +#define XDMA_IRQ_ENG_STAT_RESET 0xF8000000 +#define XDMA_MEM_SIZE 0x1000 + +#define TO_REG(addr) ((addr) / sizeof(uint32_t)) + +static uint64_t aspeed_xdma_read(void *opaque, hwaddr addr, unsigned int s= ize) +{ + uint32_t val =3D 0; + AspeedXDMAState *xdma =3D opaque; + + if (addr < ASPEED_XDMA_REG_SIZE) { + val =3D xdma->regs[TO_REG(addr)]; + } + + return (uint64_t)val; +} + +static void aspeed_xdma_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + unsigned int idx; + uint32_t val32 =3D (uint32_t)val; + AspeedXDMAState *xdma =3D opaque; + + if (addr >=3D ASPEED_XDMA_REG_SIZE) { + return; + } + + switch (addr) { + case XDMA_BMC_CMDQ_ENDP: + xdma->regs[TO_REG(addr)] =3D val32 & XDMA_BMC_CMDQ_W_MASK; + break; + case XDMA_BMC_CMDQ_WRP: + idx =3D TO_REG(addr); + xdma->regs[idx] =3D val32 & XDMA_BMC_CMDQ_W_MASK; + xdma->regs[TO_REG(XDMA_BMC_CMDQ_RDP)] =3D xdma->regs[idx]; + + trace_aspeed_xdma_write(addr, val); + + if (xdma->bmc_cmdq_readp_set) { + xdma->bmc_cmdq_readp_set =3D 0; + } else { + xdma->regs[TO_REG(XDMA_IRQ_ENG_STAT)] |=3D + XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP; + + if (xdma->regs[TO_REG(XDMA_IRQ_ENG_CTRL)] & + (XDMA_IRQ_ENG_CTRL_US_COMP | XDMA_IRQ_ENG_CTRL_DS_COMP)) + qemu_irq_raise(xdma->irq); + } + break; + case XDMA_BMC_CMDQ_RDP: + trace_aspeed_xdma_write(addr, val); + + if (val32 =3D=3D XDMA_BMC_CMDQ_RDP_MAGIC) { + xdma->bmc_cmdq_readp_set =3D 1; + } + break; + case XDMA_IRQ_ENG_CTRL: + xdma->regs[TO_REG(addr)] =3D val32 & XDMA_IRQ_ENG_CTRL_W_MASK; + break; + case XDMA_IRQ_ENG_STAT: + trace_aspeed_xdma_write(addr, val); + + idx =3D TO_REG(addr); + if (val32 & (XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP= )) { + xdma->regs[idx] &=3D + ~(XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP); + qemu_irq_lower(xdma->irq); + } + break; + default: + xdma->regs[TO_REG(addr)] =3D val32; + break; + } +} + +static const MemoryRegionOps aspeed_xdma_ops =3D { + .read =3D aspeed_xdma_read, + .write =3D aspeed_xdma_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static void aspeed_xdma_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + AspeedXDMAState *xdma =3D ASPEED_XDMA(dev); + + sysbus_init_irq(sbd, &xdma->irq); + memory_region_init_io(&xdma->iomem, OBJECT(xdma), &aspeed_xdma_ops, xd= ma, + TYPE_ASPEED_XDMA, XDMA_MEM_SIZE); + sysbus_init_mmio(sbd, &xdma->iomem); +} + +static void aspeed_xdma_reset(DeviceState *dev) +{ + AspeedXDMAState *xdma =3D ASPEED_XDMA(dev); + + xdma->bmc_cmdq_readp_set =3D 0; + memset(xdma->regs, 0, ASPEED_XDMA_REG_SIZE); + xdma->regs[TO_REG(XDMA_IRQ_ENG_STAT)] =3D XDMA_IRQ_ENG_STAT_RESET; + + qemu_irq_lower(xdma->irq); +} + +static const VMStateDescription aspeed_xdma_vmstate =3D { + .name =3D TYPE_ASPEED_XDMA, + .version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AspeedXDMAState, ASPEED_XDMA_NUM_REGS), + VMSTATE_END_OF_LIST(), + }, +}; + +static void aspeed_xdma_class_init(ObjectClass *classp, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(classp); + + dc->realize =3D aspeed_xdma_realize; + dc->reset =3D aspeed_xdma_reset; + dc->vmsd =3D &aspeed_xdma_vmstate; +} + +static const TypeInfo aspeed_xdma_info =3D { + .name =3D TYPE_ASPEED_XDMA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedXDMAState), + .class_init =3D aspeed_xdma_class_init, +}; + +static void aspeed_xdma_register_type(void) +{ + type_register_static(&aspeed_xdma_info); +} +type_init(aspeed_xdma_register_type); diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 47e1bccf71d..c1ea1aa4376 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -140,3 +140,6 @@ armsse_cpuid_write(uint64_t offset, uint64_t data, unsi= gned size) "SSE-200 CPU_I # armsse-mhu.c armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MH= U read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 M= HU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" + +# aspeed_xdma.c +aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%"= PRIx64 " data 0x%" PRIx64 --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.10 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5GuL1wde7cGfVlpJxuRJAQdP3IMbXq3IqGGP+UBMbD4=; b=C2olxWY4u4LzEd0U8iTgCmdCSrkRUhX7sYoDyorstGXOUPseIQKqaOhrlRM61CGifZ Lk5b/8E4JF3LTRVcsvjHVHaUC18hTHFGqqal7ZjuD0EOWDTqrrakTIFJ1gpET+SP4seO QrihmhP0TeywuTw/asHcpjU3C2BqvlABoisq4y8BkgRQFx9hLHbgxblmnFRdFT2aY2u8 zm5WylSqryZDOY4O4aYeT0pRXdVaN+P+2IQKPws2rBu29yn51d6H3JSkLmEzjm04SHca s9t4RSlLZpvVy9WnP0FGyzFNWj9uiaV7jcqhVJKdL4J/D3+KsLXVirXbEeb5lquYdh1E 5vng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5GuL1wde7cGfVlpJxuRJAQdP3IMbXq3IqGGP+UBMbD4=; b=oEBx1sB2ukPfrUto7BaxOrvpV+WclBFIIyqvNuzX1fdtrI+1tEEYyQvuew68qr0ta1 0ojuKiCzm3xdZlW/YZF6Ny+D2iQBHP4+fXN2Cly0MYcinvoTlXRbuOKVEiVHT81thNbp 7IPWdxQ6vJdRvrhPLXfmC3S8StHH4tcK2bo3S6h6bMoHP1s0K+FLR9qJDxyYhQV9iSVl Wij1cnCqrtChTUZWbwJ8DT3LU1qqc8SyiKL1M+hXuBk3d14sEIwJae2JfEckxwbxPngd azZiXcmn+4w0t/0xQfgAkiJfJPH/JCmY+qrJGRl2J3f2n5x9xvz1npSlGVWSvP6C1EJt x/Wg== X-Gm-Message-State: APjAAAXLYu494BhXjLRv8X404maA6zQIShjanXeIIHR6GSDNammOFHw2 xRbynwlYL0ed9T86wY9UFWYL4IOecynS8Q== X-Google-Smtp-Source: APXvYqwipFEgNV3Tx5O9q5iQaCc0ixaJqgA9uPxGkkijlYvLGxk0r0zWUJTwSR5r32YEjnzI1LWIAw== X-Received: by 2002:a1c:751a:: with SMTP id o26mr118393wmc.13.1561999210984; Mon, 01 Jul 2019 09:40:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:21 +0100 Message-Id: <20190701163943.22313-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.46 Subject: [Qemu-devel] [PULL 24/46] aspeed: vic: Add support for legacy register interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Andrew Jeffery The legacy interface only supported up to 32 IRQs, which became restrictive around the AST2400 generation. QEMU support for the SoCs started with the AST2400 along with an effort to reimplement and upstream drivers for Linux, so up until this point the consumers of the QEMU ASPEED support only required the 64 IRQ register interface. In an effort to support older BMC firmware, add support for the 32 IRQ interface. Signed-off-by: Andrew Jeffery Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Message-id: 20190618165311.27066-22-clg@kaod.org Signed-off-by: Peter Maydell --- hw/intc/aspeed_vic.c | 105 ++++++++++++++++++++++++++----------------- 1 file changed, 63 insertions(+), 42 deletions(-) diff --git a/hw/intc/aspeed_vic.c b/hw/intc/aspeed_vic.c index 927638d5322..266a309f3b4 100644 --- a/hw/intc/aspeed_vic.c +++ b/hw/intc/aspeed_vic.c @@ -104,54 +104,63 @@ static void aspeed_vic_set_irq(void *opaque, int irq,= int level) =20 static uint64_t aspeed_vic_read(void *opaque, hwaddr offset, unsigned size) { - uint64_t val; - const bool high =3D !!(offset & 0x4); - hwaddr n_offset =3D (offset & ~0x4); AspeedVICState *s =3D (AspeedVICState *)opaque; + hwaddr n_offset; + uint64_t val; + bool high; =20 if (offset < AVIC_NEW_BASE_OFFSET) { - qemu_log_mask(LOG_UNIMP, "%s: Ignoring read from legacy registers " - "at 0x%" HWADDR_PRIx "[%u]\n", __func__, offset, siz= e); - return 0; + high =3D false; + n_offset =3D offset; + } else { + high =3D !!(offset & 0x4); + n_offset =3D (offset & ~0x4); } =20 - n_offset -=3D AVIC_NEW_BASE_OFFSET; - switch (n_offset) { - case 0x0: /* IRQ Status */ + case 0x80: /* IRQ Status */ + case 0x00: val =3D s->raw & ~s->select & s->enable; break; - case 0x08: /* FIQ Status */ + case 0x88: /* FIQ Status */ + case 0x04: val =3D s->raw & s->select & s->enable; break; - case 0x10: /* Raw Interrupt Status */ + case 0x90: /* Raw Interrupt Status */ + case 0x08: val =3D s->raw; break; - case 0x18: /* Interrupt Selection */ + case 0x98: /* Interrupt Selection */ + case 0x0c: val =3D s->select; break; - case 0x20: /* Interrupt Enable */ + case 0xa0: /* Interrupt Enable */ + case 0x10: val =3D s->enable; break; - case 0x30: /* Software Interrupt */ + case 0xb0: /* Software Interrupt */ + case 0x18: val =3D s->trigger; break; - case 0x40: /* Interrupt Sensitivity */ + case 0xc0: /* Interrupt Sensitivity */ + case 0x24: val =3D s->sense; break; - case 0x48: /* Interrupt Both Edge Trigger Control */ + case 0xc8: /* Interrupt Both Edge Trigger Control */ + case 0x28: val =3D s->dual_edge; break; - case 0x50: /* Interrupt Event */ + case 0xd0: /* Interrupt Event */ + case 0x2c: val =3D s->event; break; - case 0x60: /* Edge Triggered Interrupt Status */ + case 0xe0: /* Edge Triggered Interrupt Status */ val =3D s->raw & ~s->sense; break; /* Illegal */ - case 0x28: /* Interrupt Enable Clear */ - case 0x38: /* Software Interrupt Clear */ - case 0x58: /* Edge Triggered Interrupt Clear */ + case 0xa8: /* Interrupt Enable Clear */ + case 0xb8: /* Software Interrupt Clear */ + case 0xd8: /* Edge Triggered Interrupt Clear */ qemu_log_mask(LOG_GUEST_ERROR, "%s: Read of write-only register with offset 0x%" HWADDR_PRIx "\n", __func__, offset); @@ -166,6 +175,8 @@ static uint64_t aspeed_vic_read(void *opaque, hwaddr of= fset, unsigned size) } if (high) { val =3D extract64(val, 32, 19); + } else { + val =3D extract64(val, 0, 32); } trace_aspeed_vic_read(offset, size, val); return val; @@ -174,19 +185,18 @@ static uint64_t aspeed_vic_read(void *opaque, hwaddr = offset, unsigned size) static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data, unsigned size) { - const bool high =3D !!(offset & 0x4); - hwaddr n_offset =3D (offset & ~0x4); AspeedVICState *s =3D (AspeedVICState *)opaque; + hwaddr n_offset; + bool high; =20 if (offset < AVIC_NEW_BASE_OFFSET) { - qemu_log_mask(LOG_UNIMP, - "%s: Ignoring write to legacy registers at 0x%" - HWADDR_PRIx "[%u] <- 0x%" PRIx64 "\n", __func__, off= set, - size, data); - return; + high =3D false; + n_offset =3D offset; + } else { + high =3D !!(offset & 0x4); + n_offset =3D (offset & ~0x4); } =20 - n_offset -=3D AVIC_NEW_BASE_OFFSET; trace_aspeed_vic_write(offset, size, data); =20 /* Given we have members using separate enable/clear registers, deposi= t64() @@ -201,7 +211,8 @@ static void aspeed_vic_write(void *opaque, hwaddr offse= t, uint64_t data, } =20 switch (n_offset) { - case 0x18: /* Interrupt Selection */ + case 0x98: /* Interrupt Selection */ + case 0x0c: /* Register has deposit64() semantics - overwrite requested 32 bit= s */ if (high) { s->select &=3D AVIC_L_MASK; @@ -210,21 +221,25 @@ static void aspeed_vic_write(void *opaque, hwaddr off= set, uint64_t data, } s->select |=3D data; break; - case 0x20: /* Interrupt Enable */ + case 0xa0: /* Interrupt Enable */ + case 0x10: s->enable |=3D data; break; - case 0x28: /* Interrupt Enable Clear */ + case 0xa8: /* Interrupt Enable Clear */ + case 0x14: s->enable &=3D ~data; break; - case 0x30: /* Software Interrupt */ + case 0xb0: /* Software Interrupt */ + case 0x18: qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. " "IRQs requested: 0x%016" PRIx64 "\n", __func__, data= ); break; - case 0x38: /* Software Interrupt Clear */ + case 0xb8: /* Software Interrupt Clear */ + case 0x1c: qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. " "IRQs to be cleared: 0x%016" PRIx64 "\n", __func__, = data); break; - case 0x50: /* Interrupt Event */ + case 0xd0: /* Interrupt Event */ /* Register has deposit64() semantics - overwrite the top four val= id * IRQ bits, as only the top four IRQs (GPIOs) can change their ev= ent * type */ @@ -236,15 +251,21 @@ static void aspeed_vic_write(void *opaque, hwaddr off= set, uint64_t data, "Ignoring invalid write to interrupt event regis= ter"); } break; - case 0x58: /* Edge Triggered Interrupt Clear */ + case 0xd8: /* Edge Triggered Interrupt Clear */ + case 0x38: s->raw &=3D ~(data & ~s->sense); break; - case 0x00: /* IRQ Status */ - case 0x08: /* FIQ Status */ - case 0x10: /* Raw Interrupt Status */ - case 0x40: /* Interrupt Sensitivity */ - case 0x48: /* Interrupt Both Edge Trigger Control */ - case 0x60: /* Edge Triggered Interrupt Status */ + case 0x80: /* IRQ Status */ + case 0x00: + case 0x88: /* FIQ Status */ + case 0x04: + case 0x90: /* Raw Interrupt Status */ + case 0x08: + case 0xc0: /* Interrupt Sensitivity */ + case 0x24: + case 0xc8: /* Interrupt Both Edge Trigger Control */ + case 0x28: + case 0xe0: /* Edge Triggered Interrupt Status */ qemu_log_mask(LOG_GUEST_ERROR, "%s: Write of read-only register with offset 0x%" HWADDR_PRIx "\n", __func__, offset); --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562034175; cv=none; d=zoho.com; s=zohoarc; b=kZVtihCZuc/obEIjScmfgTf7pqRETpmHFL6ojSN5p/EECNxiuzrPeO8jo39g8vY8FzGFp8IJR4f4x4YjcUmxEr4PSJa63ysGu3pSuKEcl1mj/bukT098ivdqKjWmZStQrBF49oiFMDs6SHDUv0DGIcdp55gcfyklJKigRs1ZNVM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562034175; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=xbk2+L8i1dH/Jdn/9lZBOUO8xsAaRhCxthSSE1bfYCw=; b=JPkNnIkyp9QG41Xniy3wsRtm+9Yy52yaqj1M/Dq4PDpvC5oE2POaEJ5kthq0OPUaI9kSkwyO1vFTe8tJLHI8nlncKLDgwzUAJnoyRM3ImrJQX98hFFKn2MmPgdw4HQkoyPcpIGv/GKZQMN75+EvE8kJHFaeTjaZXiU7WDMfftMA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562034175873656.9925323973065; Mon, 1 Jul 2019 19:22:55 -0700 (PDT) Received: from localhost ([::1]:47202 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi8RW-00008h-QZ for importer@patchew.org; Mon, 01 Jul 2019 22:22:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58204) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4We-0003GZ-Qi for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:11:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi4Wb-00037o-Ig for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:11:51 -0400 Received: from mail-wm1-f46.google.com ([209.85.128.46]:52660) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi4WY-00032R-H1 for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:11:47 -0400 Received: by mail-wm1-f46.google.com with SMTP id s3so981094wms.2 for ; Mon, 01 Jul 2019 15:11:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.11 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xbk2+L8i1dH/Jdn/9lZBOUO8xsAaRhCxthSSE1bfYCw=; b=P9bqeS87YK3ujDL5fg/rcLxtJ0BE/g7M20Lz1gOn4ateb+R0lRC+ed4Qk0YHY0DRJU gmiNDyn+e/R6WapZ7RKivjCxJMZucK8loZr2CriToyNqsIntC9pm3TQ7A6vGqK3lFhFu 5cBgIryhS62NdxIiHqefcR6gKmMae2Aqp0gvmgKyftMTjYfww7uVHYw1+L+T2/9SvDA4 kuaTqsCX7D6aUl56MjkqeG5Jj4s3vaWc4dxtHf+gBTcrLOHctnnmoQTiwYNKKD4rf2Sl a0O8U6gVUr+zrf/6rZxYh05yee7vRyIFQqd39SRcGtEkMzq6aQauSrCnpalxJMaOftl+ 6dDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xbk2+L8i1dH/Jdn/9lZBOUO8xsAaRhCxthSSE1bfYCw=; b=bDYlD2K15LT/8BwjAV/MadNOQR53Xuf1tcNOHFzpJyeWqmX/kaE1VWVTbtBy3eHaT3 S4UPF3VzUHnol4twBE5fbAlAq4F4j1Dda4W7pl7dVQ2X29PCowl0RQxj3j9kqMmdBULs 5m+hTtHKM8OkqeD7+li1XdSzz2WdyrL+ds3JKFiV82hv//dshAD3jK+Hel4PAOiRfEC0 ZVRzzYfkHqok2LlsvjFUJsB2bZdpuOJZfZka6Abw8DXfe7QKuESjvbpc/eBufEY7cFuK eALNTKGQeHi4b1p07pfU5gZEWH3hBh6YncaK6AnhtdsCrERH8Mztw64l23AHZHw6qFv/ MKLg== X-Gm-Message-State: APjAAAV6DIjV2UDM9SciT7kzFPS39h4WZC52GL6TMeEqIt+D5ZSjFNtC Pxs2au/1/8+H3wPaecd1cQjvqHzqZQ+5pg== X-Google-Smtp-Source: APXvYqymY/shN1UstWvOFuFKi9V+Li53LO2QxHj+AgiRps3PLmg/jCviO1xZ5EF1FfjY9wQQoELYcA== X-Received: by 2002:a1c:c747:: with SMTP id x68mr131327wmf.138.1561999212006; Mon, 01 Jul 2019 09:40:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:22 +0100 Message-Id: <20190701163943.22313-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.46 Subject: [Qemu-devel] [PULL 25/46] aspeed: Link SCU to the watchdog X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Joel Stanley The ast2500 uses the watchdog to reset the SDRAM controller. This operation is usually performed by u-boot's memory training procedure, and it is enabled by setting a bit in the SCU and then causing the watchdog to expire. Therefore, we need the watchdog to be able to access the SCU's register space. This causes the watchdog to not perform a system reset when the bit is set. In the future it could perform a reset of the SDMC model. Signed-off-by: Joel Stanley Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190621065242.32535-1-joel@jms.id.au Signed-off-by: Peter Maydell --- include/hw/watchdog/wdt_aspeed.h | 1 + hw/arm/aspeed_soc.c | 2 ++ hw/watchdog/wdt_aspeed.c | 20 ++++++++++++++++++++ 3 files changed, 23 insertions(+) diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_asp= eed.h index 88d8be4f78d..daef0c0e230 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -27,6 +27,7 @@ typedef struct AspeedWDTState { MemoryRegion iomem; uint32_t regs[ASPEED_WDT_REGS_MAX]; =20 + AspeedSCUState *scu; uint32_t pclk_freq; uint32_t silicon_rev; uint32_t ext_pulse_width_mask; diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 443e4c49f21..c6fb3700f27 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -235,6 +235,8 @@ static void aspeed_soc_init(Object *obj) sizeof(s->wdt[i]), TYPE_ASPEED_WDT); qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev", sc->info->silicon_rev); + object_property_add_const_link(OBJECT(&s->wdt[i]), "scu", + OBJECT(&s->scu), &error_abort); } =20 for (i =3D 0; i < ASPEED_MACS_NUM; i++) { diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index 4a8409f0daf..57fe24ae6b1 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -44,6 +44,9 @@ =20 #define WDT_RESTART_MAGIC 0x4755 =20 +#define SCU_RESET_CONTROL1 (0x04 / 4) +#define SCU_RESET_SDRAM BIT(0) + static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) { return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; @@ -222,6 +225,13 @@ static void aspeed_wdt_timer_expired(void *dev) { AspeedWDTState *s =3D ASPEED_WDT(dev); =20 + /* Do not reset on SDRAM controller reset */ + if (s->scu->regs[SCU_RESET_CONTROL1] & SCU_RESET_SDRAM) { + timer_del(s->timer); + s->regs[WDT_CTRL] =3D 0; + return; + } + qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n"); watchdog_perform_action(); timer_del(s->timer); @@ -233,6 +243,16 @@ static void aspeed_wdt_realize(DeviceState *dev, Error= **errp) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); AspeedWDTState *s =3D ASPEED_WDT(dev); + Error *err =3D NULL; + Object *obj; + + obj =3D object_property_get_link(OBJECT(dev), "scu", &err); + if (!obj) { + error_propagate(errp, err); + error_prepend(errp, "required link 'scu' not found: "); + return; + } + s->scu =3D ASPEED_SCU(obj); =20 if (!is_supported_silicon_rev(s->silicon_rev)) { error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.12 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YreNQHlm+doIoZhj84WwaRq/l3PPbbq8nMhtQ4YKDMQ=; b=IZDSSWEtGbhGJUG7oVffLANDiMjIWTrtMt8zpbg5F60w38RFwTCsvZsqbmBcf3nV8S stDA/5xOx5Y8xVs0CDbtcV4/zo9A4NNM5PcHRgpaDvEiScTJ8r3m4UkHI1IozT7Oj1tW dfNBc0RkdNZnNSMdGPVBJkGppYuh7ch793nTtD+IJAi5TMSqzJjXVYenOoXp3gZLeYSD Hsce237cfTb9oY9ikyKhhz67YabxrcyysFeiETUF3cLzNCI0wk6I/ZneR37cxP6lw0Ya LpiXiDtigu+JMu+jtnildX/D0jn4PStwd0c/O7MrYG1Ztyv2YVv570ZSKqoPArkcDgnh NVqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YreNQHlm+doIoZhj84WwaRq/l3PPbbq8nMhtQ4YKDMQ=; b=PxWBlwGNERZrcA916ZzKufVopy9E0ABsYkBrd8PvB05piOPG1ZuTLijqQGZrsQ2qcT 3gy8QNCVVjiN1D35x2CECngfqmNk8Dm+6MwMkt3KqniqLQKxGiX1yfBpbVyOuyMM9Cw+ 3F3YSC/kgcBBwjAOjhF5r8ncOq8D/hy9RB7Msan3gmj+F+RDqwfgHZfUbiPo3ANir8h5 rNXKbfUjW9u1bOEHHeTnT5GpiebUDKaK5iqTiTgLVeax3yD3EoEKLIOE1/IjSZSlHbdL BLk0A7H/RHmYsyhMKlv3DVCRB27Mmo7HLu3o2ovxhkMwEvOOztE8rkNO2qWql6Haf3/2 rh7g== X-Gm-Message-State: APjAAAXnrvn4KgD73W84cLZmux5UdgUw2g8cSheuOK47afb7NGTim3V/ G7bjCOdF0qvfUekSmz7RCFlJvRr6BIerxw== X-Google-Smtp-Source: APXvYqx18mwzL1PZziFNq6r3eSfQCHh9TMXSEdkkUrDTiGMtA5WBpN/m2+ADeVcao/GHDE8Mdy1xkA== X-Received: by 2002:a1c:c109:: with SMTP id r9mr106312wmf.143.1561999213481; Mon, 01 Jul 2019 09:40:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:23 +0100 Message-Id: <20190701163943.22313-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.51 Subject: [Qemu-devel] [PULL 26/46] hw/arm: Add arm SBSA reference machine, skeleton part X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Hongbo Zhang For AArch64, the existing "virt" machine is primarily meant to run on KVM and execute virtualization workloads, but we need an environment as faithful as possible to physical hardware, for supporting firmware and OS development for physical Aarch64 machines. This patch introduces new machine type 'sbsa-ref' with main features: - Based on 'virt' machine type. - A new memory map. - CPU type cortex-a57. - EL2 and EL3 are enabled. - GIC version 3. - System bus AHCI controller. - System bus EHCI controller. - CDROM and hard disc on AHCI bus. - E1000E ethernet card on PCIE bus. - VGA display adaptor on PCIE bus. - No virtio devices. - No fw_cfg device. - No ACPI table supplied. - Only minimal device tree nodes. Arm Trusted Firmware and UEFI porting to this are done accordingly, and the firmware should supply ACPI tables to the guest OS. The minimal device tree nodes supplied by QEMU for this platform are only to pass the dynamic info reflecting command line input to firmware, not for loading the guest OS. To make the review easier, this task is split into two patches, the fundamental skeleton part and the peripheral devices part; this patch is the first part. Signed-off-by: Hongbo Zhang Message-id: 1561890034-15921-2-git-send-email-hongbo.zhang@linaro.org [PMM: commit message tweaks; moved some bits between patch 1 and 2 to ensure patch 1 builds cleanly; removed unneeded lines from Kconfig stanza; only provide board for qemu-system-aarch64, not qemu-system-arm; added MAINTAINERS entry] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/Makefile.objs | 1 + hw/arm/sbsa-ref.c | 271 ++++++++++++++++++++++++++++ MAINTAINERS | 8 + default-configs/aarch64-softmmu.mak | 1 + hw/arm/Kconfig | 14 ++ 5 files changed, 295 insertions(+) create mode 100644 hw/arm/sbsa-ref.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 994e67dd0da..43ce8d5b19f 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -19,6 +19,7 @@ obj-$(CONFIG_SPITZ) +=3D spitz.o obj-$(CONFIG_TOSA) +=3D tosa.o obj-$(CONFIG_Z2) +=3D z2.o obj-$(CONFIG_REALVIEW) +=3D realview.o +obj-$(CONFIG_SBSA_REF) +=3D sbsa-ref.o obj-$(CONFIG_STELLARIS) +=3D stellaris.o obj-$(CONFIG_COLLIE) +=3D collie.o obj-$(CONFIG_VERSATILE) +=3D versatilepb.o diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c new file mode 100644 index 00000000000..b2e7d10bada --- /dev/null +++ b/hw/arm/sbsa-ref.c @@ -0,0 +1,271 @@ +/* + * ARM SBSA Reference Platform emulation + * + * Copyright (c) 2018 Linaro Limited + * Written by Hongbo Zhang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/units.h" +#include "sysemu/numa.h" +#include "sysemu/sysemu.h" +#include "exec/address-spaces.h" +#include "exec/hwaddr.h" +#include "kvm_arm.h" +#include "hw/arm/boot.h" +#include "hw/boards.h" +#include "hw/intc/arm_gicv3_common.h" + +#define RAMLIMIT_GB 8192 +#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) + +enum { + SBSA_FLASH, + SBSA_MEM, + SBSA_CPUPERIPHS, + SBSA_GIC_DIST, + SBSA_GIC_REDIST, + SBSA_SMMU, + SBSA_UART, + SBSA_RTC, + SBSA_PCIE, + SBSA_PCIE_MMIO, + SBSA_PCIE_MMIO_HIGH, + SBSA_PCIE_PIO, + SBSA_PCIE_ECAM, + SBSA_GPIO, + SBSA_SECURE_UART, + SBSA_SECURE_UART_MM, + SBSA_SECURE_MEM, + SBSA_AHCI, + SBSA_EHCI, +}; + +typedef struct MemMapEntry { + hwaddr base; + hwaddr size; +} MemMapEntry; + +typedef struct { + MachineState parent; + struct arm_boot_info bootinfo; + int smp_cpus; + void *fdt; + int fdt_size; + int psci_conduit; +} SBSAMachineState; + +#define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") +#define SBSA_MACHINE(obj) \ + OBJECT_CHECK(SBSAMachineState, (obj), TYPE_SBSA_MACHINE) + +static const MemMapEntry sbsa_ref_memmap[] =3D { + /* 512M boot ROM */ + [SBSA_FLASH] =3D { 0, 0x20000000 }, + /* 512M secure memory */ + [SBSA_SECURE_MEM] =3D { 0x20000000, 0x20000000 }, + /* Space reserved for CPU peripheral devices */ + [SBSA_CPUPERIPHS] =3D { 0x40000000, 0x00040000 }, + [SBSA_GIC_DIST] =3D { 0x40060000, 0x00010000 }, + [SBSA_GIC_REDIST] =3D { 0x40080000, 0x04000000 }, + [SBSA_UART] =3D { 0x60000000, 0x00001000 }, + [SBSA_RTC] =3D { 0x60010000, 0x00001000 }, + [SBSA_GPIO] =3D { 0x60020000, 0x00001000 }, + [SBSA_SECURE_UART] =3D { 0x60030000, 0x00001000 }, + [SBSA_SECURE_UART_MM] =3D { 0x60040000, 0x00001000 }, + [SBSA_SMMU] =3D { 0x60050000, 0x00020000 }, + /* Space here reserved for more SMMUs */ + [SBSA_AHCI] =3D { 0x60100000, 0x00010000 }, + [SBSA_EHCI] =3D { 0x60110000, 0x00010000 }, + /* Space here reserved for other devices */ + [SBSA_PCIE_PIO] =3D { 0x7fff0000, 0x00010000 }, + /* 32-bit address PCIE MMIO space */ + [SBSA_PCIE_MMIO] =3D { 0x80000000, 0x70000000 }, + /* 256M PCIE ECAM space */ + [SBSA_PCIE_ECAM] =3D { 0xf0000000, 0x10000000 }, + /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ + [SBSA_PCIE_MMIO_HIGH] =3D { 0x100000000ULL, 0xFF00000000ULL }, + [SBSA_MEM] =3D { 0x10000000000ULL, RAMLIMIT_BYTES }, +}; + +static void sbsa_ref_init(MachineState *machine) +{ + SBSAMachineState *sms =3D SBSA_MACHINE(machine); + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + MemoryRegion *sysmem =3D get_system_memory(); + MemoryRegion *secure_sysmem =3D NULL; + MemoryRegion *ram =3D g_new(MemoryRegion, 1); + const CPUArchIdList *possible_cpus; + int n, sbsa_max_cpus; + + if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { + error_report("sbsa-ref: CPU type other than the built-in " + "cortex-a57 not supported"); + exit(1); + } + + if (kvm_enabled()) { + error_report("sbsa-ref: KVM is not supported for this machine"); + exit(1); + } + + /* + * This machine has EL3 enabled, external firmware should supply PSCI + * implementation, so the QEMU's internal PSCI is disabled. + */ + sms->psci_conduit =3D QEMU_PSCI_CONDUIT_DISABLED; + + sbsa_max_cpus =3D sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST= _SIZE; + + if (max_cpus > sbsa_max_cpus) { + error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " + "supported by machine 'sbsa-ref' (%d)", + max_cpus, sbsa_max_cpus); + exit(1); + } + + sms->smp_cpus =3D smp_cpus; + + if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { + error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT= _GB); + exit(1); + } + + possible_cpus =3D mc->possible_cpu_arch_ids(machine); + for (n =3D 0; n < possible_cpus->len; n++) { + Object *cpuobj; + CPUState *cs; + + if (n >=3D smp_cpus) { + break; + } + + cpuobj =3D object_new(possible_cpus->cpus[n].type); + object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, + "mp-affinity", NULL); + + cs =3D CPU(cpuobj); + cs->cpu_index =3D n; + + numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuo= bj), + &error_fatal); + + if (object_property_find(cpuobj, "reset-cbar", NULL)) { + object_property_set_int(cpuobj, + sbsa_ref_memmap[SBSA_CPUPERIPHS].base, + "reset-cbar", &error_abort); + } + + object_property_set_link(cpuobj, OBJECT(sysmem), "memory", + &error_abort); + + object_property_set_link(cpuobj, OBJECT(secure_sysmem), + "secure-memory", &error_abort); + + object_property_set_bool(cpuobj, true, "realized", &error_fatal); + object_unref(cpuobj); + } + + memory_region_allocate_system_memory(ram, NULL, "sbsa-ref.ram", + machine->ram_size); + memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ra= m); + + sms->bootinfo.ram_size =3D machine->ram_size; + sms->bootinfo.kernel_filename =3D machine->kernel_filename; + sms->bootinfo.nb_cpus =3D smp_cpus; + sms->bootinfo.board_id =3D -1; + sms->bootinfo.loader_start =3D sbsa_ref_memmap[SBSA_MEM].base; + arm_load_kernel(ARM_CPU(first_cpu), &sms->bootinfo); +} + +static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) +{ + uint8_t clustersz =3D ARM_DEFAULT_CPUS_PER_CLUSTER; + return arm_cpu_mp_affinity(idx, clustersz); +} + +static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *m= s) +{ + SBSAMachineState *sms =3D SBSA_MACHINE(ms); + int n; + + if (ms->possible_cpus) { + assert(ms->possible_cpus->len =3D=3D max_cpus); + return ms->possible_cpus; + } + + ms->possible_cpus =3D g_malloc0(sizeof(CPUArchIdList) + + sizeof(CPUArchId) * max_cpus); + ms->possible_cpus->len =3D max_cpus; + for (n =3D 0; n < ms->possible_cpus->len; n++) { + ms->possible_cpus->cpus[n].type =3D ms->cpu_type; + ms->possible_cpus->cpus[n].arch_id =3D + sbsa_ref_cpu_mp_affinity(sms, n); + ms->possible_cpus->cpus[n].props.has_thread_id =3D true; + ms->possible_cpus->cpus[n].props.thread_id =3D n; + } + return ms->possible_cpus; +} + +static CpuInstanceProperties +sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + const CPUArchIdList *possible_cpus =3D mc->possible_cpu_arch_ids(ms); + + assert(cpu_index < possible_cpus->len); + return possible_cpus->cpus[cpu_index].props; +} + +static int64_t +sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) +{ + return idx % nb_numa_nodes; +} + +static void sbsa_ref_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->init =3D sbsa_ref_init; + mc->desc =3D "QEMU 'SBSA Reference' ARM Virtual Machine"; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a57"); + mc->max_cpus =3D 512; + mc->pci_allow_0_address =3D true; + mc->minimum_page_bits =3D 12; + mc->block_default_type =3D IF_IDE; + mc->no_cdrom =3D 1; + mc->default_ram_size =3D 1 * GiB; + mc->default_cpus =3D 4; + mc->possible_cpu_arch_ids =3D sbsa_ref_possible_cpu_arch_ids; + mc->cpu_index_to_instance_props =3D sbsa_ref_cpu_index_to_props; + mc->get_default_cpu_node_id =3D sbsa_ref_get_default_cpu_node_id; +} + +static const TypeInfo sbsa_ref_info =3D { + .name =3D TYPE_SBSA_MACHINE, + .parent =3D TYPE_MACHINE, + .class_init =3D sbsa_ref_class_init, + .instance_size =3D sizeof(SBSAMachineState), +}; + +static void sbsa_ref_machine_init(void) +{ + type_register_static(&sbsa_ref_info); +} + +type_init(sbsa_ref_machine_init); diff --git a/MAINTAINERS b/MAINTAINERS index cad58b94879..a875868e8ae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -728,6 +728,14 @@ F: include/hw/arm/fsl-imx6.h F: include/hw/misc/imx6_*.h F: include/hw/ssi/imx_spi.h =20 +SBSA-REF +M: Radoslaw Biernacki +M: Peter Maydell +R: Leif Lindholm +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/sbsa-ref.c + Sharp SL-5500 (Collie) PDA M: Peter Maydell L: qemu-arm@nongnu.org diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-= softmmu.mak index 49ff415ee4c..958b1e08e40 100644 --- a/default-configs/aarch64-softmmu.mak +++ b/default-configs/aarch64-softmmu.mak @@ -5,3 +5,4 @@ include arm-softmmu.mak =20 CONFIG_XLNX_ZYNQMP_ARM=3Dy CONFIG_XLNX_VERSAL=3Dy +CONFIG_SBSA_REF=3Dy diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 9aced9d54de..ab65ecd2169 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -184,6 +184,20 @@ config REALVIEW select DS1338 # I2C RTC+NVRAM select USB_OHCI =20 +config SBSA_REF + bool + imply PCI_DEVICES + select AHCI + select ARM_SMMUV3 + select GPIO_KEY + select PCI_EXPRESS + select PCI_EXPRESS_GENERIC_BRIDGE + select PFLASH_CFI01 + select PL011 # UART + select PL031 # RTC + select PL061 # GPIO + select USB_EHCI_SYSBUS + config SABRELITE bool select FSL_IMX6 --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.13 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7cHyzKWTMk+EfqfdyyVgXHSXcfCS9HBaHC85sQxQKUE=; b=G10KQaUYqhxA+TOUnShX1mu5zWwAZAuqZ4X9juE6Zw8c3/BRNTQMg9AlNITDzQP48r cVrHurkN+izAMxEpXc6vW3f7Fpp1UDSJF3Qj0t2cbpe9m18JQNu6EYH8wjsmD5xaP2Wd 04DViZw055f/99jDGYjpwVjl5JsrSqJ9ou669cFPzLmRuPPMuDFXXQS624L3a03XWlDr tCYwXPyjT8akA1mt6MwaDxHcTGhmL1H/Kf7xrYN3x/5werxjOAjrm9VHnpz97D1KqAAN YVvVXCSkabD+vXUnjlP6Jnb0HeZzEC8x1dJy3dO5UAOU2FOfjuQguVP3RSoKCSTmHOKO P3Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7cHyzKWTMk+EfqfdyyVgXHSXcfCS9HBaHC85sQxQKUE=; b=aBYT0k39RJXkUxb2AkXHf7A1WFEfyHbpikzo+JohtnBaI9KlZbBRq/GbB+2lkYupah ZY2w4rvb38kqv0arDFxvOO5FPyUuRRgBwCQZctctbqBkn1o6P39B6VWzGS7VJLv2uw+r UST1QdHCENZHB6UocI3Ire+STxdahHmAB27g3AB/2bSqVksj1W5LfxGRJSaVlSwikWGu c7pjdhpt5iLWIcqCEz+n1IJqabM1NqSXBbkso12ZAIkXs6sqUejRVUuobfXsEDq2R/NB C5j/plbN82gJQpraqahjXKbInNXwBLJec3pjjOA6ww4wEtMlTTYEXXISX08rXBkxO+0g 09Sw== X-Gm-Message-State: APjAAAUwf7fcL9oXXkTfFqioB1GylX564Cn1/q3n9XcrENrt8lSL7Dsc o3Kws7q4uU1R3NgBC0gh/7I3qwgFfVg//g== X-Google-Smtp-Source: APXvYqwC1h5+LDI28izfhAGyB0Nxl4ZO80EcswqMszPy/L5A3cch92vWfxa8iIj1ByugupLiVp9dOA== X-Received: by 2002:a1c:1f06:: with SMTP id f6mr146835wmf.60.1561999214862; Mon, 01 Jul 2019 09:40:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:24 +0100 Message-Id: <20190701163943.22313-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.44 Subject: [Qemu-devel] [PULL 27/46] hw/arm: Add arm SBSA reference machine, devices part X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Hongbo Zhang Following the previous patch, this patch adds peripheral devices to the newly introduced SBSA-ref machine. Signed-off-by: Hongbo Zhang Message-id: 1561890034-15921-3-git-send-email-hongbo.zhang@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 535 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 535 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index b2e7d10bada..ee53f0ff60d 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -18,21 +18,41 @@ */ =20 #include "qemu/osdep.h" +#include "qemu-common.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/units.h" +#include "sysemu/device_tree.h" #include "sysemu/numa.h" #include "sysemu/sysemu.h" #include "exec/address-spaces.h" #include "exec/hwaddr.h" #include "kvm_arm.h" #include "hw/arm/boot.h" +#include "hw/block/flash.h" #include "hw/boards.h" +#include "hw/ide/internal.h" +#include "hw/ide/ahci_internal.h" #include "hw/intc/arm_gicv3_common.h" +#include "hw/loader.h" +#include "hw/pci-host/gpex.h" +#include "hw/usb.h" +#include "net/net.h" =20 #define RAMLIMIT_GB 8192 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) =20 +#define NUM_IRQS 256 +#define NUM_SMMU_IRQS 4 +#define NUM_SATA_PORTS 6 + +#define VIRTUAL_PMU_IRQ 7 +#define ARCH_GIC_MAINT_IRQ 9 +#define ARCH_TIMER_VIRT_IRQ 11 +#define ARCH_TIMER_S_EL1_IRQ 13 +#define ARCH_TIMER_NS_EL1_IRQ 14 +#define ARCH_TIMER_NS_EL2_IRQ 10 + enum { SBSA_FLASH, SBSA_MEM, @@ -67,6 +87,7 @@ typedef struct { void *fdt; int fdt_size; int psci_conduit; + PFlashCFI01 *flash[2]; } SBSAMachineState; =20 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") @@ -102,6 +123,466 @@ static const MemMapEntry sbsa_ref_memmap[] =3D { [SBSA_MEM] =3D { 0x10000000000ULL, RAMLIMIT_BYTES }, }; =20 +static const int sbsa_ref_irqmap[] =3D { + [SBSA_UART] =3D 1, + [SBSA_RTC] =3D 2, + [SBSA_PCIE] =3D 3, /* ... to 6 */ + [SBSA_GPIO] =3D 7, + [SBSA_SECURE_UART] =3D 8, + [SBSA_SECURE_UART_MM] =3D 9, + [SBSA_AHCI] =3D 10, + [SBSA_EHCI] =3D 11, +}; + +/* + * Firmware on this machine only uses ACPI table to load OS, these limited + * device tree nodes are just to let firmware know the info which varies f= rom + * command line parameters, so it is not necessary to be fully compatible + * with the kernel CPU and NUMA binding rules. + */ +static void create_fdt(SBSAMachineState *sms) +{ + void *fdt =3D create_device_tree(&sms->fdt_size); + const MachineState *ms =3D MACHINE(sms); + int cpu; + + if (!fdt) { + error_report("create_device_tree() failed"); + exit(1); + } + + sms->fdt =3D fdt; + + qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); + qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); + + if (have_numa_distance) { + int size =3D nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); + uint32_t *matrix =3D g_malloc0(size); + int idx, i, j; + + for (i =3D 0; i < nb_numa_nodes; i++) { + for (j =3D 0; j < nb_numa_nodes; j++) { + idx =3D (i * nb_numa_nodes + j) * 3; + matrix[idx + 0] =3D cpu_to_be32(i); + matrix[idx + 1] =3D cpu_to_be32(j); + matrix[idx + 2] =3D cpu_to_be32(numa_info[i].distance[j]); + } + } + + qemu_fdt_add_subnode(fdt, "/distance-map"); + qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", + matrix, size); + g_free(matrix); + } + + qemu_fdt_add_subnode(sms->fdt, "/cpus"); + + for (cpu =3D sms->smp_cpus - 1; cpu >=3D 0; cpu--) { + char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); + CPUState *cs =3D CPU(armcpu); + + qemu_fdt_add_subnode(sms->fdt, nodename); + + if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { + qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", + ms->possible_cpus->cpus[cs->cpu_index].props.node_id); + } + + g_free(nodename); + } +} + +#define SBSA_FLASH_SECTOR_SIZE (256 * KiB) + +static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, + const char *name, + const char *alias_prop_name) +{ + /* + * Create a single flash device. We use the same parameters as + * the flash devices on the Versatile Express board. + */ + DeviceState *dev =3D qdev_create(NULL, TYPE_PFLASH_CFI01); + + qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); + qdev_prop_set_uint8(dev, "width", 4); + qdev_prop_set_uint8(dev, "device-width", 2); + qdev_prop_set_bit(dev, "big-endian", false); + qdev_prop_set_uint16(dev, "id0", 0x89); + qdev_prop_set_uint16(dev, "id1", 0x18); + qdev_prop_set_uint16(dev, "id2", 0x00); + qdev_prop_set_uint16(dev, "id3", 0x00); + qdev_prop_set_string(dev, "name", name); + object_property_add_child(OBJECT(sms), name, OBJECT(dev), + &error_abort); + object_property_add_alias(OBJECT(sms), alias_prop_name, + OBJECT(dev), "drive", &error_abort); + return PFLASH_CFI01(dev); +} + +static void sbsa_flash_create(SBSAMachineState *sms) +{ + sms->flash[0] =3D sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); + sms->flash[1] =3D sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); +} + +static void sbsa_flash_map1(PFlashCFI01 *flash, + hwaddr base, hwaddr size, + MemoryRegion *sysmem) +{ + DeviceState *dev =3D DEVICE(flash); + + assert(size % SBSA_FLASH_SECTOR_SIZE =3D=3D 0); + assert(size / SBSA_FLASH_SECTOR_SIZE <=3D UINT32_MAX); + qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); + qdev_init_nofail(dev); + + memory_region_add_subregion(sysmem, base, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), + 0)); +} + +static void sbsa_flash_map(SBSAMachineState *sms, + MemoryRegion *sysmem, + MemoryRegion *secure_sysmem) +{ + /* + * Map two flash devices to fill the SBSA_FLASH space in the memmap. + * sysmem is the system memory space. secure_sysmem is the secure view + * of the system, and the first flash device should be made visible on= ly + * there. The second flash device is visible to both secure and nonsec= ure. + * If sysmem =3D=3D secure_sysmem this means there is no separate Secu= re + * address space and both flash devices are generally visible. + */ + hwaddr flashsize =3D sbsa_ref_memmap[SBSA_FLASH].size / 2; + hwaddr flashbase =3D sbsa_ref_memmap[SBSA_FLASH].base; + + sbsa_flash_map1(sms->flash[0], flashbase, flashsize, + secure_sysmem); + sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, + sysmem); +} + +static bool sbsa_firmware_init(SBSAMachineState *sms, + MemoryRegion *sysmem, + MemoryRegion *secure_sysmem) +{ + int i; + BlockBackend *pflash_blk0; + + /* Map legacy -drive if=3Dpflash to machine properties */ + for (i =3D 0; i < ARRAY_SIZE(sms->flash); i++) { + pflash_cfi01_legacy_drive(sms->flash[i], + drive_get(IF_PFLASH, 0, i)); + } + + sbsa_flash_map(sms, sysmem, secure_sysmem); + + pflash_blk0 =3D pflash_cfi01_get_blk(sms->flash[0]); + + if (bios_name) { + char *fname; + MemoryRegion *mr; + int image_size; + + if (pflash_blk0) { + error_report("The contents of the first flash device may be " + "specified with -bios or with -drive if=3Dpflash.= .. " + "but you cannot use both options at once"); + exit(1); + } + + /* Fall back to -bios */ + + fname =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + if (!fname) { + error_report("Could not find ROM image '%s'", bios_name); + exit(1); + } + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); + image_size =3D load_image_mr(fname, mr); + g_free(fname); + if (image_size < 0) { + error_report("Could not load ROM image '%s'", bios_name); + exit(1); + } + } + + return pflash_blk0 || bios_name; +} + +static void create_secure_ram(SBSAMachineState *sms, + MemoryRegion *secure_sysmem) +{ + MemoryRegion *secram =3D g_new(MemoryRegion, 1); + hwaddr base =3D sbsa_ref_memmap[SBSA_SECURE_MEM].base; + hwaddr size =3D sbsa_ref_memmap[SBSA_SECURE_MEM].size; + + memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, + &error_fatal); + memory_region_add_subregion(secure_sysmem, base, secram); +} + +static void create_gic(SBSAMachineState *sms, qemu_irq *pic) +{ + DeviceState *gicdev; + SysBusDevice *gicbusdev; + const char *gictype; + uint32_t redist0_capacity, redist0_count; + int i; + + gictype =3D gicv3_class_name(); + + gicdev =3D qdev_create(NULL, gictype); + qdev_prop_set_uint32(gicdev, "revision", 3); + qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); + /* + * Note that the num-irq property counts both internal and external + * interrupts; there are always 32 of the former (mandated by GIC spec= ). + */ + qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); + qdev_prop_set_bit(gicdev, "has-security-extensions", true); + + redist0_capacity =3D + sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; + redist0_count =3D MIN(smp_cpus, redist0_capacity); + + qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); + qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); + + qdev_init_nofail(gicdev); + gicbusdev =3D SYS_BUS_DEVICE(gicdev); + sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); + sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); + + /* + * Wire the outputs from each CPU's generic timer and the GICv3 + * maintenance interrupt signal to the appropriate GIC PPI inputs, + * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inpu= ts. + */ + for (i =3D 0; i < smp_cpus; i++) { + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); + int ppibase =3D NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; + int irq; + /* + * Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs used for this board. + */ + const int timer_irq[] =3D { + [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, + }; + + for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { + qdev_connect_gpio_out(cpudev, irq, + qdev_get_gpio_in(gicdev, + ppibase + timer_irq[irq= ])); + } + + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",= 0, + qdev_get_gpio_in(gicdev, ppibase + + ARCH_GIC_MAINT_IRQ)= ); + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, + qdev_get_gpio_in(gicdev, ppibase + + VIRTUAL_PMU_IRQ)); + + sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); + sysbus_connect_irq(gicbusdev, i + smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + } + + for (i =3D 0; i < NUM_IRQS; i++) { + pic[i] =3D qdev_get_gpio_in(gicdev, i); + } +} + +static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int ua= rt, + MemoryRegion *mem, Chardev *chr) +{ + hwaddr base =3D sbsa_ref_memmap[uart].base; + int irq =3D sbsa_ref_irqmap[uart]; + DeviceState *dev =3D qdev_create(NULL, "pl011"); + SysBusDevice *s =3D SYS_BUS_DEVICE(dev); + + qdev_prop_set_chr(dev, "chardev", chr); + qdev_init_nofail(dev); + memory_region_add_subregion(mem, base, + sysbus_mmio_get_region(s, 0)); + sysbus_connect_irq(s, 0, pic[irq]); +} + +static void create_rtc(const SBSAMachineState *sms, qemu_irq *pic) +{ + hwaddr base =3D sbsa_ref_memmap[SBSA_RTC].base; + int irq =3D sbsa_ref_irqmap[SBSA_RTC]; + + sysbus_create_simple("pl031", base, pic[irq]); +} + +static DeviceState *gpio_key_dev; +static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) +{ + /* use gpio Pin 3 for power button event */ + qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); +} + +static Notifier sbsa_ref_powerdown_notifier =3D { + .notify =3D sbsa_ref_powerdown_req +}; + +static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic) +{ + DeviceState *pl061_dev; + hwaddr base =3D sbsa_ref_memmap[SBSA_GPIO].base; + int irq =3D sbsa_ref_irqmap[SBSA_GPIO]; + + pl061_dev =3D sysbus_create_simple("pl061", base, pic[irq]); + + gpio_key_dev =3D sysbus_create_simple("gpio-key", -1, + qdev_get_gpio_in(pl061_dev, 3)); + + /* connect powerdown request */ + qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); +} + +static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic) +{ + hwaddr base =3D sbsa_ref_memmap[SBSA_AHCI].base; + int irq =3D sbsa_ref_irqmap[SBSA_AHCI]; + DeviceState *dev; + DriveInfo *hd[NUM_SATA_PORTS]; + SysbusAHCIState *sysahci; + AHCIState *ahci; + int i; + + dev =3D qdev_create(NULL, "sysbus-ahci"); + qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]); + + sysahci =3D SYSBUS_AHCI(dev); + ahci =3D &sysahci->ahci; + ide_drive_get(hd, ARRAY_SIZE(hd)); + for (i =3D 0; i < ahci->ports; i++) { + if (hd[i] =3D=3D NULL) { + continue; + } + ide_create_drive(&ahci->dev[i].port, 0, hd[i]); + } +} + +static void create_ehci(const SBSAMachineState *sms, qemu_irq *pic) +{ + hwaddr base =3D sbsa_ref_memmap[SBSA_EHCI].base; + int irq =3D sbsa_ref_irqmap[SBSA_EHCI]; + + sysbus_create_simple("platform-ehci-usb", base, pic[irq]); +} + +static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic, + PCIBus *bus) +{ + hwaddr base =3D sbsa_ref_memmap[SBSA_SMMU].base; + int irq =3D sbsa_ref_irqmap[SBSA_SMMU]; + DeviceState *dev; + int i; + + dev =3D qdev_create(NULL, "arm-smmuv3"); + + object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", + &error_abort); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + for (i =3D 0; i < NUM_SMMU_IRQS; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + } +} + +static void create_pcie(SBSAMachineState *sms, qemu_irq *pic) +{ + hwaddr base_ecam =3D sbsa_ref_memmap[SBSA_PCIE_ECAM].base; + hwaddr size_ecam =3D sbsa_ref_memmap[SBSA_PCIE_ECAM].size; + hwaddr base_mmio =3D sbsa_ref_memmap[SBSA_PCIE_MMIO].base; + hwaddr size_mmio =3D sbsa_ref_memmap[SBSA_PCIE_MMIO].size; + hwaddr base_mmio_high =3D sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; + hwaddr size_mmio_high =3D sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; + hwaddr base_pio =3D sbsa_ref_memmap[SBSA_PCIE_PIO].base; + int irq =3D sbsa_ref_irqmap[SBSA_PCIE]; + MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; + MemoryRegion *ecam_alias, *ecam_reg; + DeviceState *dev; + PCIHostState *pci; + int i; + + dev =3D qdev_create(NULL, TYPE_GPEX_HOST); + qdev_init_nofail(dev); + + /* Map ECAM space */ + ecam_alias =3D g_new0(MemoryRegion, 1); + ecam_reg =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", + ecam_reg, 0, size_ecam); + memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias= ); + + /* Map the MMIO space */ + mmio_alias =3D g_new0(MemoryRegion, 1); + mmio_reg =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", + mmio_reg, base_mmio, size_mmio); + memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias= ); + + /* Map the MMIO_HIGH space */ + mmio_alias_high =3D g_new0(MemoryRegion, 1); + memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high= ", + mmio_reg, base_mmio_high, size_mmio_high); + memory_region_add_subregion(get_system_memory(), base_mmio_high, + mmio_alias_high); + + /* Map IO port space */ + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); + + for (i =3D 0; i < GPEX_NUM_IRQS; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); + } + + pci =3D PCI_HOST_BRIDGE(dev); + if (pci->bus) { + for (i =3D 0; i < nb_nics; i++) { + NICInfo *nd =3D &nd_table[i]; + + if (!nd->model) { + nd->model =3D g_strdup("e1000e"); + } + + pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); + } + } + + pci_create_simple(pci->bus, -1, "VGA"); + + create_smmu(sms, pic, pci->bus); +} + +static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) +{ + const SBSAMachineState *board =3D container_of(binfo, SBSAMachineState, + bootinfo); + + *fdt_size =3D board->fdt_size; + return board->fdt; +} + static void sbsa_ref_init(MachineState *machine) { SBSAMachineState *sms =3D SBSA_MACHINE(machine); @@ -109,8 +590,10 @@ static void sbsa_ref_init(MachineState *machine) MemoryRegion *sysmem =3D get_system_memory(); MemoryRegion *secure_sysmem =3D NULL; MemoryRegion *ram =3D g_new(MemoryRegion, 1); + bool firmware_loaded; const CPUArchIdList *possible_cpus; int n, sbsa_max_cpus; + qemu_irq pic[NUM_IRQS]; =20 if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { error_report("sbsa-ref: CPU type other than the built-in " @@ -123,6 +606,27 @@ static void sbsa_ref_init(MachineState *machine) exit(1); } =20 + /* + * The Secure view of the world is the same as the NonSecure, + * but with a few extra devices. Create it as a container region + * containing the system memory at low priority; any secure-only + * devices go in at higher priority and take precedence. + */ + secure_sysmem =3D g_new(MemoryRegion, 1); + memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", + UINT64_MAX); + memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); + + firmware_loaded =3D sbsa_firmware_init(sms, sysmem, + secure_sysmem ?: sysmem); + + if (machine->kernel_filename && firmware_loaded) { + error_report("sbsa-ref: No fw_cfg device on this machine, " + "so -kernel option is not supported when firmware loa= ded, " + "please load OS from hard disk instead"); + exit(1); + } + /* * This machine has EL3 enabled, external firmware should supply PSCI * implementation, so the QEMU's internal PSCI is disabled. @@ -184,11 +688,34 @@ static void sbsa_ref_init(MachineState *machine) machine->ram_size); memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ra= m); =20 + create_fdt(sms); + + create_secure_ram(sms, secure_sysmem); + + create_gic(sms, pic); + + create_uart(sms, pic, SBSA_UART, sysmem, serial_hd(0)); + create_uart(sms, pic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); + /* Second secure UART for RAS and MM from EL0 */ + create_uart(sms, pic, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)= ); + + create_rtc(sms, pic); + + create_gpio(sms, pic); + + create_ahci(sms, pic); + + create_ehci(sms, pic); + + create_pcie(sms, pic); + sms->bootinfo.ram_size =3D machine->ram_size; sms->bootinfo.kernel_filename =3D machine->kernel_filename; sms->bootinfo.nb_cpus =3D smp_cpus; sms->bootinfo.board_id =3D -1; sms->bootinfo.loader_start =3D sbsa_ref_memmap[SBSA_MEM].base; + sms->bootinfo.get_dtb =3D sbsa_ref_dtb; + sms->bootinfo.firmware_loaded =3D firmware_loaded; arm_load_kernel(ARM_CPU(first_cpu), &sms->bootinfo); } =20 @@ -237,6 +764,13 @@ sbsa_ref_get_default_cpu_node_id(const MachineState *m= s, int idx) return idx % nb_numa_nodes; } =20 +static void sbsa_ref_instance_init(Object *obj) +{ + SBSAMachineState *sms =3D SBSA_MACHINE(obj); + + sbsa_flash_create(sms); +} + static void sbsa_ref_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -259,6 +793,7 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *= data) static const TypeInfo sbsa_ref_info =3D { .name =3D TYPE_SBSA_MACHINE, .parent =3D TYPE_MACHINE, + .instance_init =3D sbsa_ref_instance_init, .class_init =3D sbsa_ref_class_init, .instance_size =3D sizeof(SBSAMachineState), }; --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.14 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vI8UZn5YgvLXUBbGW41e3aj469sfNMLp6oyJ3oBawnQ=; b=W8f+V00unL4RCehArWvfE8qiiSJ+d4wqsZTiKW6cKnSUhOpXoqIsCJEJHulltqZA8n o2aXkZDsY3W0g4sjFy0b+Q/oN+WcpcE5NDBSXTZeSGlbWVxAQi/Z4hsBUb8/PRLMMop/ 8fEoajmFUXJdomE3YZAKoiQCv94k9F0zsgaV2b58X1SQ2GaVN6+3Wx5zTEiI14yecrxU O+fZ4OH8YzifrOd90QjHDNVSR0K+XvV0T4r2WWsGLowI3o/i5EuNzfoIsSewoT2HYbB4 T1QfGw0qT+jWKAuUpde1Tp5zJufL9n21cI3s/pfyMEkOpYNAGIaZEzyZKdt9bSFWg0ah modw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vI8UZn5YgvLXUBbGW41e3aj469sfNMLp6oyJ3oBawnQ=; b=hEwXCxDw4+1JPV6chayJG45pXEDlzIdaaYdD6syGuQHD7KbAYh7SiEVwbPCTNtcPki ryTd/hJyO6txIsOhVi5+gTiS9PYRWvdrSVeVk9p7073TRGCz64f36/f3IDbJ7pFLwmv9 05ryJ77fskD55pkqK9Ob5reIFoXOQKVPDUuW486Z1Tx9ROVKGn/l8UAKc0az11QaszWn tCC3uENOJi7k7kBVA6xiyjPGMb+/MOWHXUYYkHJzYpAsFRM+1fODa7afcZZphkzHCROM KVDYVZHZ4AgWDSXndlIDU50aan6My3SqMUbXPR2DNdMNCQExPWPIg5qVDg+lYhW0fAya 6AWg== X-Gm-Message-State: APjAAAX5iYvWmh99rjcykfHDhLsU/9VG9Clhqs4LT3ahvNvB8bvCUq19 LSCjJLfb2wUCxPGryKj0euCxR8nMGh/rsw== X-Google-Smtp-Source: APXvYqwYy2lZl+DwG0N4YokSPQ4JLYdcVzaf+iODcPG3PEj+vqoQQ750lmjGv5hfB8nxtTWZoLpy5Q== X-Received: by 2002:a1c:b707:: with SMTP id h7mr114963wmf.45.1561999216099; Mon, 01 Jul 2019 09:40:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:25 +0100 Message-Id: <20190701163943.22313-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.43 Subject: [Qemu-devel] [PULL 28/46] target/arm: Makefile cleanup (Aarch64) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Group Aarch64 rules together, TCG related ones at the bottom. This will help when restricting TCG-only objects. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-2-philmd@redhat.com Signed-off-by: Peter Maydell --- target/arm/Makefile.objs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index dfa736a3752..7c31fa01c1c 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -7,8 +7,7 @@ obj-$(call lnot,$(CONFIG_KVM)) +=3D kvm-stub.o obj-y +=3D translate.o op_helper.o helper.o cpu.o obj-y +=3D neon_helper.o iwmmxt_helper.o vec_helper.o vfp_helper.o obj-y +=3D gdbstub.o -obj-$(TARGET_AARCH64) +=3D cpu64.o translate-a64.o helper-a64.o gdbstub64.o -obj-$(TARGET_AARCH64) +=3D pauth_helper.o +obj-$(TARGET_AARCH64) +=3D cpu64.o gdbstub64.o obj-y +=3D crypto_helper.o obj-$(CONFIG_SOFTMMU) +=3D arm-powerctl.o =20 @@ -33,4 +32,6 @@ target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c =20 +obj-$(TARGET_AARCH64) +=3D translate-a64.o helper-a64.o obj-$(TARGET_AARCH64) +=3D translate-sve.o sve_helper.o +obj-$(TARGET_AARCH64) +=3D pauth_helper.o --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562033347; cv=none; d=zoho.com; s=zohoarc; b=O5b0ji+XzuizlCBU3b5oaX4S5odXJ7U0LpPUbCukH6/6d8LH4tom9qHoEI02RxUeVbIY6mpLySSJD0bzYuykDgBW2QOhvXMlF439/wU4s67kIiaQH0JdfyVuu/dssLIYeA+Jq+jPrcDhNlrWcIxcJCadbMxLZrjLyVMB0ghw9+0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562033347; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=KqpLKfjrgSvCjVcmL96LXqXG75GeUM+DNTc46s318rE=; b=Tm7YoALgJcIfsxOw0+dCmEVjj4T59ukv3A+dTWkEqrrGvSfR9fMQLgODFoLlYmgueCkzWRuyPd9ba9jr76XubYIhQO6qiPM8MgJGFljo+yVHgnsTs8H7l4ac+g5rsuJ9niUHoRAz6SdjE2WsX73d9ue4QjQ+BGwnX8OwwmWbqBk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562033347065860.5420710278096; Mon, 1 Jul 2019 19:09:07 -0700 (PDT) Received: from localhost ([::1]:47120 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi8Dr-00088S-Eb for importer@patchew.org; Mon, 01 Jul 2019 22:08:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55291) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4Lm-000469-3a for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:00:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi4Lj-0008SR-P4 for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:00:37 -0400 Received: from mail-wr1-f50.google.com ([209.85.221.50]:43745) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi4Lh-0008NC-PN for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:00:35 -0400 Received: by mail-wr1-f50.google.com with SMTP id p13so15404184wru.10 for ; Mon, 01 Jul 2019 15:00:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.16 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KqpLKfjrgSvCjVcmL96LXqXG75GeUM+DNTc46s318rE=; b=VK/Q8/0LfvU8fmYJ/2BejcaK4j0cH1dTfnksW+UfwmBnzBLcfpnb4KEZIy/kWNGt/n MEqjRVx2I4L95cHfCzDzzY8kgn08le5J31I8ga31GuzbLIT77K3n/xi1/eezySQQMjEM 0cfo9mWV2N8ORsZOmGeA2cn7Z6+IPJeYVYfzCy8+KnHnjKcGq9VGG974WySZuKAq+UF4 qCeFwVkCRM5FIu5QoQVxBVzprTb8rKP46lMXUMhyi8JyiH+gIp+eru0dEtc276UKncn6 5yWNIJN0YvjEOypRiBBEvBK1PrE9rcXANj/GLl4zYmIe8vZuQwzw6lOTyw0MDECAm9w5 qCEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KqpLKfjrgSvCjVcmL96LXqXG75GeUM+DNTc46s318rE=; b=N3DCs5354X2lamCKazJ8O3xQjJjbQtbqytSh7QVs+oeRkUYFtZAVTWLogayusNU9Ve BM2XWnCkM1tbyd1yCKDTGFJT3TMEkmcNvmVRium719Zync+wTyOtVrtbCAG1KFXTiDtY ETEj4aNU/MOUfZQcyZZFwoWGUT27CbxyGKdLVbYLgKfTn2eENYFdou6bg71k6gz/nCed s0l1t49YG/IK+4T9kuHcUIoVwstO2cUonxTfrP7lGaaeUrWt2KWE6gBkNAPNsnSRvWSx iHzKbUy2uw4ZAxhP9nxjyGuTTWpJanB6rb5cg5cG8upCOj5+fy7/527YnuRTqv4FtdoS Oqlg== X-Gm-Message-State: APjAAAV4w2hbwIYltCNGGT4qdUw3PhxRldHdWho35MlAQY8yEk5JqdDh m5D1yK3ssnytKXAj6upArHwE6ti7nn8mUw== X-Google-Smtp-Source: APXvYqx/VqneEvFcfzcF966LizdY7zagZ3Aj4lH3Ayvgb+07cEcN9PcqJEjvu8s6G3Z2nMgROySyEg== X-Received: by 2002:a5d:42c5:: with SMTP id t5mr18846199wrr.5.1561999217125; Mon, 01 Jul 2019 09:40:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:26 +0100 Message-Id: <20190701163943.22313-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.50 Subject: [Qemu-devel] [PULL 29/46] target/arm: Makefile cleanup (ARM) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Group ARM objects together, TCG related ones at the bottom. This will help when restricting TCG-only objects. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-3-philmd@redhat.com Signed-off-by: Peter Maydell --- target/arm/Makefile.objs | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 7c31fa01c1c..1cbe7cfdb47 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -4,11 +4,9 @@ obj-$(CONFIG_KVM) +=3D kvm.o obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) +=3D kvm32.o obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) +=3D kvm64.o obj-$(call lnot,$(CONFIG_KVM)) +=3D kvm-stub.o -obj-y +=3D translate.o op_helper.o helper.o cpu.o -obj-y +=3D neon_helper.o iwmmxt_helper.o vec_helper.o vfp_helper.o -obj-y +=3D gdbstub.o +obj-y +=3D helper.o vfp_helper.o +obj-y +=3D cpu.o gdbstub.o obj-$(TARGET_AARCH64) +=3D cpu64.o gdbstub64.o -obj-y +=3D crypto_helper.o obj-$(CONFIG_SOFTMMU) +=3D arm-powerctl.o =20 DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py @@ -32,6 +30,10 @@ target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c =20 +obj-y +=3D translate.o op_helper.o +obj-y +=3D crypto_helper.o +obj-y +=3D iwmmxt_helper.o vec_helper.o neon_helper.o + obj-$(TARGET_AARCH64) +=3D translate-a64.o helper-a64.o obj-$(TARGET_AARCH64) +=3D translate-sve.o sve_helper.o obj-$(TARGET_AARCH64) +=3D pauth_helper.o --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562016566; cv=none; d=zoho.com; s=zohoarc; b=GCDUaLfZ4WFuaiT5DY/mLk5VgLuto+II92B3fMvBymIqwjZLaw3Y0KAteS0rEfqp6qDLQ3Dd2aK6Sfcb+1qFvRnFe7+r0Slw1yySQMR9drkhOYDLisgKypkfgkYkHHmH2KVtbsWE7Wrm8DJdYetAfW8GcyPg5q6oa1YsZFOCSCM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562016566; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=XIpbYiZf2SRJuij2NyCsmVITR8aYraN06NwGun1+UKo=; b=CS+WI8dyHzb080ZisSxJFbIcp/SOkhqvy2Hm2+FPzlebq1j9TaX+weL3ZmVp3L4/rot8PGY8KEPIA/587XA9D8xC/ALXrEEAOIi5x86WHDdx5T8nGiZWZTwBD59tz7eLdCg2ygc7HcNi6Xfv+xG1h9soYleHFHoNDL1flX5uFLo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156201656672996.81115750685535; Mon, 1 Jul 2019 14:29:26 -0700 (PDT) Received: from localhost ([::1]:45674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3rZ-0004FX-O7 for importer@patchew.org; Mon, 01 Jul 2019 17:29:25 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44952) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3Dn-0001bX-Md for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:48:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3Dj-0001Op-2h for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:48:17 -0400 Received: from mail-wm1-f54.google.com ([209.85.128.54]:36982) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3Di-0001LX-QP for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:48:14 -0400 Received: by mail-wm1-f54.google.com with SMTP id f17so936146wme.2 for ; Mon, 01 Jul 2019 13:48:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.17 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XIpbYiZf2SRJuij2NyCsmVITR8aYraN06NwGun1+UKo=; b=rksDEHIWsnZsCPPLqt8XHpd3gmarGdae5onUU9ETDy4RPkd8vUqTPXbdxP5wW/rMbJ uiUWQP4iCitqIiJLcgy/D4T6EbnGlM1px38NJbfgcCPiWCAjRJRkxII6vdR0StREMKx1 /9XO5rW6eGLvBAsqpnwgeTx7C1mYiXzTqnQkS2U9fBFsbkyA6TSxUz/WAhXpCzt1w2Pb WrNmf1ko7DL/Vi/q7mlIm4cMyKpfQKx0FaE2C8lYVzC6QBv0u9QTLnwYC+i7FitsDJQk FhYubxNZ/pasL4Zkd0uMp5iWglfDU6TtU2QoepXJf1gr1ciJv9WhPK5mi2HBMqe+zBST WApQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XIpbYiZf2SRJuij2NyCsmVITR8aYraN06NwGun1+UKo=; b=Cp45jhGtfopzaO8O43aNyXSiumAyQ62iMxAZtwfNj/t1J5mgPLNXqMwaFx8B+792E8 z/1k0M+iyr1wAlcElSPaTgVm5rzH8/HbEEt2tE5MkWBj/+QWBXp8q4zV0oE+zPfevShb qjJoHSTCgifWTmkux6VqCgSHNNRi1AXSOAsyDxjTVwbfkQudcE+z4dUoc99B4I6CW765 1L37/2DmTIe6pQJ1bW9xd3sUiYXODI7/4u/4C8qaWjsXFwD8NxQcIiLiCma/dRb+LZ+L FqxWSJVMxwqyL7I9KQHIc0ezzBQLc3rr5FVstHQ/2Jw8cWNGR+sg+6oGcho2p0nHOadi ZcgQ== X-Gm-Message-State: APjAAAUacXOTOZcrnV59HUiXSOwS130BEebmCH822p8mAc1GauRn1RcE XjIyxghO1PEbNzAE+bH0E4XXZj+TyGgK/Q== X-Google-Smtp-Source: APXvYqyrPYsbaLDj5jp+xvGqUuKn1fZoQ+ZFL3Qpt3+SbIFwFb8xkrHW65jaFZdzMGBeNv3N5F29LQ== X-Received: by 2002:a1c:6555:: with SMTP id z82mr97753wmb.129.1561999217998; Mon, 01 Jul 2019 09:40:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:27 +0100 Message-Id: <20190701163943.22313-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.54 Subject: [Qemu-devel] [PULL 30/46] target/arm: Makefile cleanup (KVM) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Group KVM rules together. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-4-philmd@redhat.com Signed-off-by: Peter Maydell --- target/arm/Makefile.objs | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 1cbe7cfdb47..7a933eebc75 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -1,14 +1,15 @@ obj-y +=3D arm-semi.o obj-$(CONFIG_SOFTMMU) +=3D machine.o psci.o arch_dump.o monitor.o -obj-$(CONFIG_KVM) +=3D kvm.o -obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) +=3D kvm32.o -obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) +=3D kvm64.o -obj-$(call lnot,$(CONFIG_KVM)) +=3D kvm-stub.o obj-y +=3D helper.o vfp_helper.o obj-y +=3D cpu.o gdbstub.o obj-$(TARGET_AARCH64) +=3D cpu64.o gdbstub64.o obj-$(CONFIG_SOFTMMU) +=3D arm-powerctl.o =20 +obj-$(CONFIG_KVM) +=3D kvm.o +obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) +=3D kvm32.o +obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) +=3D kvm64.o +obj-$(call lnot,$(CONFIG_KVM)) +=3D kvm-stub.o + DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py =20 target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETRE= E) --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562035244; cv=none; d=zoho.com; s=zohoarc; b=e6VR50tQAg/Nz9ig8lb4W+e3+fN1GcrlkpmnLBRZu//3ot6C8wBDN2SJGePi2k9V2+jb0LnilrmCebtmoIOZQlG6tqehH48Zhu99MhIMo3uIzPxvOc3JnZuyERZitzmgy9DvwqYTM+nfUqwZkI9kT8w8lozzlGZv6wUXbQ+aI2E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562035244; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=jCabYHM40d2+5uj/C4fh8Q0u8TCASTWJ9SXGpNj41KI=; b=Bn9Ea7dUGD3beSOxqpzIDtRu84o/8Cl8BrlEjf+jqfPQI+2V0HrpUZAHkCuxcABvRGOs+OcPKhDleFRBBlyhsfyV9KYOP/FCpLShfrt51L/307rncQKpi4RJrGvI323WmUOrheXQQXpwS43MNfy02d8gAXdv4J8/GK8+zshpBPM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562035244039410.3224305475601; Mon, 1 Jul 2019 19:40:44 -0700 (PDT) Received: from localhost ([::1]:47436 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi8ii-0004hg-Oo for importer@patchew.org; Mon, 01 Jul 2019 22:40:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34206) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4pm-0005VG-5o for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:32:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi4pa-0000Z3-Gt for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:31:32 -0400 Received: from mail-wm1-f48.google.com ([209.85.128.48]:35322) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi4pN-0000Rm-2w for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:31:19 -0400 Received: by mail-wm1-f48.google.com with SMTP id c6so1160659wml.0 for ; Mon, 01 Jul 2019 15:31:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.18 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jCabYHM40d2+5uj/C4fh8Q0u8TCASTWJ9SXGpNj41KI=; b=XXsFSncZWydLgSkofGymPCmNeXpPb+XzojABwfhJM4s3nP8u796rxY33Ax/z+gC2YC +OtokLgh0WJBZtpDOmx/itDw+leHGTqQU3wyfztKVImLlFQ4/aQe5u7oV7L54kNGVJ0w neqCuU4QTMAWXRpj0zraPoy3nNsZVsa6vTzpLniehytLiNuf33AGk5z084fM5Y/YwPIw 7Qap1Id3u9UJMMnWPAJQ9FzaCiDGy0yVCpph3tOGifMgS5F8nMZoEfM4HDFYVG+dQ0Ek LKnNxctda6jF2KJpKJ/iqFDHGoyiVyPmZHy6nXKZ0/bZk50pwd13KuQA5FAZ7YRFHcqA a/3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jCabYHM40d2+5uj/C4fh8Q0u8TCASTWJ9SXGpNj41KI=; b=GaY9ZTk5sySvzx9F3nt8wuwWPDkqcSBIKMq5oyiQAuZG2Z4QcNuZOWam1Y1TwW0c51 4Mjg+yc1PXUe8lAlZz6pLyAn0jenGGjh1313MDPV/qzfmBy2CIldt9WiKmn5xP+h4zyu vyfeRvF+7KLcgYZqZEpIGP3rR1BcTX0tdJXMIOkQUDMSYqn0is/IR25cBrgmeb9iA6tm waUTmFOuNFo5Ke4PVgUnsckez51FIWrbuvOnO3B2nfozrW90in2JqMSkc82lPMBROvTI ir9JqckhboHPEm9smozzlF4hFGtTH3NX4DvzVDe2K8hKVNNOXdgQs8An/WHzLTIKE6hK c8aQ== X-Gm-Message-State: APjAAAW10RLkXkjebMe/9vLgYpSqTtYbKWiT64ErlOeJ4t19iKStpEMd 8B96ek4ok3mHJPbuV72ZC3YWtD+rz4BFkA== X-Google-Smtp-Source: APXvYqyPKBj4F1RrnDKe5X9nBlRcEUF+wdx8NZ8XaCHNez70k2oT9rOTBfGAuDMvsSYwiPfwZiij6g== X-Received: by 2002:a1c:700b:: with SMTP id l11mr133605wmc.106.1561999218880; Mon, 01 Jul 2019 09:40:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:28 +0100 Message-Id: <20190701163943.22313-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.48 Subject: [Qemu-devel] [PULL 31/46] target/arm: Makefile cleanup (softmmu) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Group SOFTMMU objects together. Since PSCI is TCG specific, keep it separate. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-5-philmd@redhat.com Signed-off-by: Peter Maydell --- target/arm/Makefile.objs | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 7a933eebc75..3fcda66132a 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -1,8 +1,9 @@ obj-y +=3D arm-semi.o -obj-$(CONFIG_SOFTMMU) +=3D machine.o psci.o arch_dump.o monitor.o obj-y +=3D helper.o vfp_helper.o obj-y +=3D cpu.o gdbstub.o obj-$(TARGET_AARCH64) +=3D cpu64.o gdbstub64.o + +obj-$(CONFIG_SOFTMMU) +=3D machine.o arch_dump.o monitor.o obj-$(CONFIG_SOFTMMU) +=3D arm-powerctl.o =20 obj-$(CONFIG_KVM) +=3D kvm.o @@ -35,6 +36,8 @@ obj-y +=3D translate.o op_helper.o obj-y +=3D crypto_helper.o obj-y +=3D iwmmxt_helper.o vec_helper.o neon_helper.o =20 +obj-$(CONFIG_SOFTMMU) +=3D psci.o + obj-$(TARGET_AARCH64) +=3D translate-a64.o helper-a64.o obj-$(TARGET_AARCH64) +=3D translate-sve.o sve_helper.o obj-$(TARGET_AARCH64) +=3D pauth_helper.o --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562018754; cv=none; d=zoho.com; s=zohoarc; b=EWvJG6gaCppFp0824OslXB1b414iXbS6sjajQdl9u376TItSxNkCSzcsrvdHrqioVkxXCrevGmt9nhRhOcql1eaa8uUWcujw5USpXIbvJ07CCMTw7s1I0Rn1W4Z47WmjFRpEEcvgQu6Wa4bPk7f6+EwMI39jAN7OOpS0iMUGxHg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562018754; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=sgWf2P2ycpWcgSXDYsWUTZ5BfbzfW6NVgQcaK6lwObA=; b=WK2yC5BSSzJL7frjTQZo0tsF9JU2ktaASDmwD8nSoiQtC7FP3WU4Fc9DLFORl7k/BLq2Cha85J05y7UKImsHfcCNANQ23JoJhNUX9HWfYKumg49yZMAmNJlYYFuShZ9K7hycQBU6E7zCxlxkBn2vp2aBIIL0VrevyeH6GXSMUzs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562018754426356.2339490451567; Mon, 1 Jul 2019 15:05:54 -0700 (PDT) Received: from localhost ([::1]:45918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4Qq-0007FN-6G for importer@patchew.org; Mon, 01 Jul 2019 18:05:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53001) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3UC-0005Ny-R8 for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:05:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3UB-0004OG-Ug for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:05:16 -0400 Received: from mail-wm1-f50.google.com ([209.85.128.50]:37472) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3UB-0004MU-Dh for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:05:15 -0400 Received: by mail-wm1-f50.google.com with SMTP id f17so976004wme.2 for ; Mon, 01 Jul 2019 14:05:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.18 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sgWf2P2ycpWcgSXDYsWUTZ5BfbzfW6NVgQcaK6lwObA=; b=mSO8z0/N9e+5E7XIA7S/ESajHceWVQS3SOEuGdXq0LyRfeKepCcDkfMzws8pOmgYWz 7UCtMQ3exyS3a82tHOaxx6/NqvPkar+9LedhJa1+mkBA2xRCvFTltdZPhq2z/jHHsVNy usuG9bSYMZhfmDUmvA7gVAEt/bL6bg1MMThQP7R92Cu2J3D2Fksd+CeeEoRBXN3uhJ/z 2jnS0cR4A3OepuPLh9tO9WJN98tXKD0G9LQXBgJ4TYYzdK3VM9V+BcwdskhzK78UAh1H G2U+CkQNqxGOSvOU4J0T/+xemoZtXtuAKIwWo5drZxFf9W0hs11USIVnXHyRdrJ4EvyP RVuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sgWf2P2ycpWcgSXDYsWUTZ5BfbzfW6NVgQcaK6lwObA=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.50 Subject: [Qemu-devel] [PULL 32/46] target/arm: Add copyright boilerplate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Robert Bradford Reviewed-by: Samuel Ortiz Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-6-philmd@redhat.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index df4276f5f6c..d3f3cb57d5f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1,3 +1,10 @@ +/* + * ARM generic helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ #include "qemu/osdep.h" #include "qemu/units.h" #include "target/arm/idau.h" --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.19 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=o6tJonaWbPJQHk+WHfPFs3EZy62SAe8H5ByWEfMlaXA=; b=tblbu+7+WjY/sWIznRy9L6qiQm6ggh5fhapgt8YDfHwMnH89VrGcDX4D8SE3DuoOFr +UZS/YcLYBUlIf+XRIycQs8GrOny6kbT1LxeSUw2ttMB4lXMGYvZW9ewHdZyPflsxcP5 rqNCbjx/ZKraKqNclNzjji1wvE08Nmh6Qi3gH7qz7zjkWqBxytwViXQUl/pqZCtUHrSI uCPTS/Rz7McuQjXJP+VMlc3wOIsi/0Z7IRvBygE91NqNcTHPuc2vZqy12anBhxvZW520 fAOv7y7nH/9boG6DoQLBjx2uyJnxxQN03xNdJW+h5d8RM3FtWzD2OaUOSdZIRLBX+Qet XBtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o6tJonaWbPJQHk+WHfPFs3EZy62SAe8H5ByWEfMlaXA=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.42 Subject: [Qemu-devel] [PULL 33/46] target/arm/helper: Remove unused include X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-7-philmd@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d3f3cb57d5f..ca4d4a57bff 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -14,7 +14,6 @@ #include "exec/gdbstub.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" -#include "sysemu/arch_init.h" #include "sysemu/sysemu.h" #include "qemu/bitops.h" #include "qemu/crc32c.h" @@ -26,7 +25,6 @@ #include "hw/semihosting/semihost.h" #include "sysemu/cpus.h" #include "sysemu/kvm.h" -#include "fpu/softfloat.h" #include "qemu/range.h" #include "qapi/qapi-commands-target.h" #include "qapi/error.h" --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.20 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=EwpRBNeUrGyzlCkkPaR10FtxiEGV5Xvub4EowqMp0/c=; b=UZTdz0qgfUu0a2r5cnT4GQ/uoB9D5I2VurOppwjO+LrjKSx1qYTAqz3UygnVi6AGnS xJQipK1QFo1yblDX9YOElKegQ1gskvDGj5ViQZrIL/WaXPzaFzTvXZ46HWcVqRcHIoiM sSTxt5pXT1iBtBhzu3LD8Fgh7taGfOu5jprzFGlBtbxUkiu1Zxl188yyVh8jb2b+K8qs eo4IIuJ5lBHF0QdBG+KVf3bitZg3OExW7vh/kGORM9Wr3JSX77bBBM6J2wWuFEI4kQN1 Db9kujupu4ivk5GezXeVvzmWn/0ee2WMCViD3LqFylxJRjosskBkDDllFMHe7JIvYUOs hTGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EwpRBNeUrGyzlCkkPaR10FtxiEGV5Xvub4EowqMp0/c=; b=lnXqzSObH0UzAWAM/P/SrIp+h/lF7Cd9SlLZCzT0CS+rd+FxYBaeVnmwGz+bRA82f7 wlfwRkN5327huoFViql7KUepI6nmc3IU/j69ricwXtzE7yeZcixYlCv10atAANCJ1Zfd toeOiwuZE2f7i+3YtMHYJChO1BK82Y5897gyQXwgigoKJX6GIkBk/luytRx64BMwak6g 2PnmtHO72Kxm+jXNzW5AKAdVg4GVI7mpgZgPXzAjNgGEXuP3j3LsEWsf6p8orwATHyRd Etp65KmWmR/mCPqJPmInf8dElygB5yz9QCXPWwQ/BPs5dbQms+I/ro8oBUWNf6fTIqHl dxYg== X-Gm-Message-State: APjAAAXdLlP5u8omMjhqTwSXD0oUaj0E7ie90OUC0TRrSfCX5asCtTYF WyeUbrUYBp9g5KVqmHHCftpT7A358OeGag== X-Google-Smtp-Source: APXvYqwxWCRaYv42GOwxZX6sP0W6vUJEfKFHw3zV3T7cwnwpQ2KoySz0HaHwUCdSv3TtCJc08nZo0A== X-Received: by 2002:a5d:6583:: with SMTP id q3mr21504891wru.184.1561999223589; Mon, 01 Jul 2019 09:40:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:31 +0100 Message-Id: <20190701163943.22313-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.46 Subject: [Qemu-devel] [PULL 34/46] target/arm: Fix multiline comment syntax X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Since commit 8c06fbdf36b checkpatch.pl enforce a new multiline comment syntax. Since we'll move this code around, fix its style first. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-8-philmd@redhat.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 237 ++++++++++++++++++++++++++-------------- target/arm/op_helper.c | 54 ++++++--- target/arm/vfp_helper.c | 3 +- 3 files changed, 196 insertions(+), 98 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ca4d4a57bff..c77ed852155 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7529,7 +7529,8 @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fpt= r) =20 uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) { - /* The TT instructions can be used by unprivileged code, but in + /* + * The TT instructions can be used by unprivileged code, but in * user-only emulation we don't have the MPU. * Luckily since we know we are NonSecure unprivileged (and that in * turn means that the A flag wasn't specified), all the bits in the @@ -7801,7 +7802,8 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t add= r, uint32_t value, return true; =20 pend_fault: - /* By pending the exception at this point we are making + /* + * By pending the exception at this point we are making * the IMPDEF choice "overridden exceptions pended" (see the * MergeExcInfo() pseudocode). The other choice would be to not * pend them now and then make a choice about which to throw away @@ -7876,7 +7878,8 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *des= t, uint32_t addr, return true; =20 pend_fault: - /* By pending the exception at this point we are making + /* + * By pending the exception at this point we are making * the IMPDEF choice "overridden exceptions pended" (see the * MergeExcInfo() pseudocode). The other choice would be to not * pend them now and then make a choice about which to throw away @@ -7977,7 +7980,8 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env) */ } =20 -/* Write to v7M CONTROL.SPSEL bit for the specified security bank. +/* + * Write to v7M CONTROL.SPSEL bit for the specified security bank. * This may change the current stack pointer between Main and Process * stack pointers if it is done for the CONTROL register for the current * security state. @@ -8005,7 +8009,8 @@ static void write_v7m_control_spsel_for_secstate(CPUA= RMState *env, } } =20 -/* Write to v7M CONTROL.SPSEL bit. This may change the current +/* + * Write to v7M CONTROL.SPSEL bit. This may change the current * stack pointer between Main and Process stack pointers. */ static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel) @@ -8015,7 +8020,8 @@ static void write_v7m_control_spsel(CPUARMState *env,= bool new_spsel) =20 void write_v7m_exception(CPUARMState *env, uint32_t new_exc) { - /* Write a new value to v7m.exception, thus transitioning into or out + /* + * Write a new value to v7m.exception, thus transitioning into or out * of Handler mode; this may result in a change of active stack pointe= r. */ bool new_is_psp, old_is_psp =3D v7m_using_psp(env); @@ -8041,7 +8047,8 @@ static void switch_v7m_security_state(CPUARMState *en= v, bool new_secstate) return; } =20 - /* All the banked state is accessed by looking at env->v7m.secure + /* + * All the banked state is accessed by looking at env->v7m.secure * except for the stack pointer; rearrange the SP appropriately. */ new_ss_msp =3D env->v7m.other_ss_msp; @@ -8068,7 +8075,8 @@ static void switch_v7m_security_state(CPUARMState *en= v, bool new_secstate) =20 void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) { - /* Handle v7M BXNS: + /* + * Handle v7M BXNS: * - if the return value is a magic value, do exception return (like = BX) * - otherwise bit 0 of the return value is the target security state */ @@ -8083,7 +8091,8 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) } =20 if (dest >=3D min_magic) { - /* This is an exception return magic value; put it where + /* + * This is an exception return magic value; put it where * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT. * Note that if we ever add gen_ss_advance() singlestep support to * M profile this should count as an "instruction execution comple= te" @@ -8108,7 +8117,8 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) =20 void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) { - /* Handle v7M BLXNS: + /* + * Handle v7M BLXNS: * - bit 0 of the destination address is the target security state */ =20 @@ -8121,7 +8131,8 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t des= t) assert(env->v7m.secure); =20 if (dest & 1) { - /* target is Secure, so this is just a normal BLX, + /* + * Target is Secure, so this is just a normal BLX, * except that the low bit doesn't indicate Thumb/not. */ env->regs[14] =3D nextinst; @@ -8152,7 +8163,8 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t des= t) env->regs[13] =3D sp; env->regs[14] =3D 0xfeffffff; if (arm_v7m_is_handler_mode(env)) { - /* Write a dummy value to IPSR, to avoid leaking the current secure + /* + * Write a dummy value to IPSR, to avoid leaking the current secure * exception number to non-secure code. This is guaranteed not * to cause write_v7m_exception() to actually change stacks. */ @@ -8167,7 +8179,8 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t des= t) static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool thread= mode, bool spsel) { - /* Return a pointer to the location where we currently store the + /* + * Return a pointer to the location where we currently store the * stack pointer for the requested security state and thread mode. * This pointer will become invalid if the CPU state is updated * such that the stack pointers are switched around (eg changing @@ -8213,7 +8226,8 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc,= bool targets_secure, =20 mmu_idx =3D arm_v7m_mmu_idx_for_secstate_and_priv(env, targets_secure,= true); =20 - /* We don't do a get_phys_addr() here because the rules for vector + /* + * We don't do a get_phys_addr() here because the rules for vector * loads are special: they always use the default memory map, and * the default memory map permits reads from all addresses. * Since there's no easy way to pass through to pmsav8_mpu_lookup() @@ -8244,7 +8258,8 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc,= bool targets_secure, return true; =20 load_fail: - /* All vector table fetch fails are reported as HardFault, with + /* + * All vector table fetch fails are reported as HardFault, with * HFSR.VECTTBL and .FORCED set. (FORCED is set because * technically the underlying exception is a MemManage or BusFault * that is escalated to HardFault.) This is a terminal exception, @@ -8276,7 +8291,8 @@ static uint32_t v7m_integrity_sig(CPUARMState *env, u= int32_t lr) static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailcha= in, bool ignore_faults) { - /* For v8M, push the callee-saves register part of the stack frame. + /* + * For v8M, push the callee-saves register part of the stack frame. * Compare the v8M pseudocode PushCalleeStack(). * In the tailchaining case this may not be the current stack. */ @@ -8327,7 +8343,8 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32= _t lr, bool dotailchain, return true; } =20 - /* Write as much of the stack frame as we can. A write failure may + /* + * Write as much of the stack frame as we can. A write failure may * cause us to pend a derived exception. */ sig =3D v7m_integrity_sig(env, lr); @@ -8351,7 +8368,8 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32= _t lr, bool dotailchain, static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, bool ignore_stackfaults) { - /* Do the "take the exception" parts of exception entry, + /* + * Do the "take the exception" parts of exception entry, * but not the pushing of state to the stack. This is * similar to the pseudocode ExceptionTaken() function. */ @@ -8376,13 +8394,15 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32= _t lr, bool dotailchain, if (arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_M_SECURITY) && (lr & R_V7M_EXCRET_S_MASK)) { - /* The background code (the owner of the registers in the + /* + * The background code (the owner of the registers in the * exception frame) is Secure. This means it may either already * have or now needs to push callee-saves registers. */ if (targets_secure) { if (dotailchain && !(lr & R_V7M_EXCRET_ES_MASK)) { - /* We took an exception from Secure to NonSecure + /* + * We took an exception from Secure to NonSecure * (which means the callee-saved registers got stacked) * and are now tailchaining to a Secure exception. * Clear DCRS so eventual return from this Secure @@ -8391,7 +8411,8 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t= lr, bool dotailchain, lr &=3D ~R_V7M_EXCRET_DCRS_MASK; } } else { - /* We're going to a non-secure exception; push the + /* + * We're going to a non-secure exception; push the * callee-saves registers to the stack now, if they're * not already saved. */ @@ -8413,14 +8434,16 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32= _t lr, bool dotailchain, lr |=3D R_V7M_EXCRET_SPSEL_MASK; } =20 - /* Clear registers if necessary to prevent non-secure exception + /* + * Clear registers if necessary to prevent non-secure exception * code being able to see register values from secure code. * Where register values become architecturally UNKNOWN we leave * them with their previous values. */ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { if (!targets_secure) { - /* Always clear the caller-saved registers (they have been + /* + * Always clear the caller-saved registers (they have been * pushed to the stack earlier in v7m_push_stack()). * Clear callee-saved registers if the background code is * Secure (in which case these regs were saved in @@ -8441,7 +8464,8 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t= lr, bool dotailchain, } =20 if (push_failed && !ignore_stackfaults) { - /* Derived exception on callee-saves register stacking: + /* + * Derived exception on callee-saves register stacking: * we might now want to take a different exception which * targets a different security state, so try again from the top. */ @@ -8458,7 +8482,8 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t= lr, bool dotailchain, return; } =20 - /* Now we've done everything that might cause a derived exception + /* + * Now we've done everything that might cause a derived exception * we can go ahead and activate whichever exception we're going to * take (which might now be the derived exception). */ @@ -8661,7 +8686,8 @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fpt= r) =20 static bool v7m_push_stack(ARMCPU *cpu) { - /* Do the "set up stack frame" part of exception entry, + /* + * Do the "set up stack frame" part of exception entry, * similar to pseudocode PushStack(). * Return true if we generate a derived exception (and so * should ignore further stack faults trying to process @@ -8729,7 +8755,8 @@ static bool v7m_push_stack(ARMCPU *cpu) } } =20 - /* Write as much of the stack frame as we can. If we fail a stack + /* + * Write as much of the stack frame as we can. If we fail a stack * write this will result in a derived exception being pended * (which may be taken in preference to the one we started with * if it has higher priority). @@ -8846,7 +8873,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) bool ftype; bool restore_s16_s31; =20 - /* If we're not in Handler mode then jumps to magic exception-exit + /* + * If we're not in Handler mode then jumps to magic exception-exit * addresses don't have magic behaviour. However for the v8M * security extensions the magic secure-function-return has to * work in thread mode too, so to avoid doing an extra check in @@ -8860,7 +8888,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) return; } =20 - /* In the spec pseudocode ExceptionReturn() is called directly + /* + * In the spec pseudocode ExceptionReturn() is called directly * from BXWritePC() and gets the full target PC value including * bit zero. In QEMU's implementation we treat it as a normal * jump-to-register (which is then caught later on), and so split @@ -8893,7 +8922,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } =20 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - /* EXC_RETURN.ES validation check (R_SMFL). We must do this before + /* + * EXC_RETURN.ES validation check (R_SMFL). We must do this before * we pick which FAULTMASK to clear. */ if (!env->v7m.secure && @@ -8907,7 +8937,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } =20 if (env->v7m.exception !=3D ARMV7M_EXCP_NMI) { - /* Auto-clear FAULTMASK on return from other than NMI. + /* + * Auto-clear FAULTMASK on return from other than NMI. * If the security extension is implemented then this only * happens if the raw execution priority is >=3D 0; the * value of the ES bit in the exception return value indicates @@ -8932,7 +8963,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* still an irq active now */ break; case 1: - /* we returned to base exception level, no nesting. + /* + * We returned to base exception level, no nesting. * (In the pseudocode this is written using "NestedActivation !=3D= 1" * where we have 'rettobase =3D=3D false'.) */ @@ -8949,7 +8981,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) =20 if (arm_feature(env, ARM_FEATURE_V8)) { if (!arm_feature(env, ARM_FEATURE_M_SECURITY)) { - /* UNPREDICTABLE if S =3D=3D 1 or DCRS =3D=3D 0 or ES =3D=3D 1= (R_XLCP); + /* + * UNPREDICTABLE if S =3D=3D 1 or DCRS =3D=3D 0 or ES =3D=3D 1= (R_XLCP); * we choose to take the UsageFault. */ if ((excret & R_V7M_EXCRET_S_MASK) || @@ -8968,7 +9001,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) break; case 13: /* Return to Thread using Process stack */ case 9: /* Return to Thread using Main stack */ - /* We only need to check NONBASETHRDENA for v7M, because in + /* + * We only need to check NONBASETHRDENA for v7M, because in * v8M this bit does not exist (it is RES1). */ if (!rettobase && @@ -9026,7 +9060,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } =20 if (ufault) { - /* Bad exception return: instead of popping the exception + /* + * Bad exception return: instead of popping the exception * stack, directly take a usage fault on the current stack. */ env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; @@ -9056,7 +9091,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) switch_v7m_security_state(env, return_to_secure); =20 { - /* The stack pointer we should be reading the exception frame from + /* + * The stack pointer we should be reading the exception frame from * depends on bits in the magic exception return type value (and * for v8M isn't necessarily the stack pointer we will eventually * end up resuming execution with). Get a pointer to the location @@ -9129,7 +9165,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) v7m_stack_read(cpu, &xpsr, frameptr + 0x1c, mmu_idx); =20 if (!pop_ok) { - /* v7m_stack_read() pended a fault, so take it (as a tail + /* + * v7m_stack_read() pended a fault, so take it (as a tail * chained exception on the same stack frame) */ qemu_log_mask(CPU_LOG_INT, "...derived exception on unstacking= \n"); @@ -9137,7 +9174,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) return; } =20 - /* Returning from an exception with a PC with bit 0 set is defined + /* + * Returning from an exception with a PC with bit 0 set is defined * behaviour on v8M (bit 0 is ignored), but for v7M it was specifi= ed * to be UNPREDICTABLE. In practice actual v7M hardware seems to i= gnore * the lsbit, and there are several RTOSes out there which incorre= ctly @@ -9155,13 +9193,15 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } =20 if (arm_feature(env, ARM_FEATURE_V8)) { - /* For v8M we have to check whether the xPSR exception field + /* + * For v8M we have to check whether the xPSR exception field * matches the EXCRET value for return to handler/thread * before we commit to changing the SP and xPSR. */ bool will_be_handler =3D (xpsr & XPSR_EXCP) !=3D 0; if (return_to_handler !=3D will_be_handler) { - /* Take an INVPC UsageFault on the current stack. + /* + * Take an INVPC UsageFault on the current stack. * By this point we will have switched to the security sta= te * for the background state, so this UsageFault will target * that state. @@ -9276,7 +9316,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) frameptr +=3D 0x40; } } - /* Undo stack alignment (the SPREALIGN bit indicates that the orig= inal + /* + * Undo stack alignment (the SPREALIGN bit indicates that the orig= inal * pre-exception SP was not 8-aligned and we added a padding word = to * align it, so we undo this by ORing in the bit that increases it * from the current 8-aligned value to the 8-unaligned value. (Add= ing 4 @@ -9302,13 +9343,15 @@ static void do_v7m_exception_exit(ARMCPU *cpu) V7M_CONTROL, SFPA, sfpa); } =20 - /* The restored xPSR exception field will be zero if we're + /* + * The restored xPSR exception field will be zero if we're * resuming in Thread mode. If that doesn't match what the * exception return excret specified then this is a UsageFault. * v7M requires we make this check here; v8M did it earlier. */ if (return_to_handler !=3D arm_v7m_is_handler_mode(env)) { - /* Take an INVPC UsageFault by pushing the stack again; + /* + * Take an INVPC UsageFault by pushing the stack again; * we know we're v7M so this is never a Secure UsageFault. */ bool ignore_stackfaults; @@ -9330,7 +9373,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) =20 static bool do_v7m_function_return(ARMCPU *cpu) { - /* v8M security extensions magic function return. + /* + * v8M security extensions magic function return. * We may either: * (1) throw an exception (longjump) * (2) return true if we successfully handled the function return @@ -9360,7 +9404,8 @@ static bool do_v7m_function_return(ARMCPU *cpu) frame_sp_p =3D get_v7m_sp_ptr(env, true, threadmode, spsel); frameptr =3D *frame_sp_p; =20 - /* These loads may throw an exception (for MPU faults). We want to + /* + * These loads may throw an exception (for MPU faults). We want to * do them as secure, so work out what MMU index that is. */ mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, true); @@ -9441,7 +9486,8 @@ static void arm_log_exception(int idx) static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, uint32_t addr, uint16_t *insn) { - /* Load a 16-bit portion of a v7M instruction, returning true on succe= ss, + /* + * Load a 16-bit portion of a v7M instruction, returning true on succe= ss, * or false on failure (in which case we will have pended the appropri= ate * exception). * We need to do the instruction fetch's MPU and SAU checks @@ -9464,7 +9510,8 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, =20 v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs); if (!sattrs.nsc || sattrs.ns) { - /* This must be the second half of the insn, and it straddles a + /* + * This must be the second half of the insn, and it straddles a * region boundary with the second half not being S&NSC. */ env->v7m.sfsr |=3D R_V7M_SFSR_INVEP_MASK; @@ -9494,7 +9541,8 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, =20 static bool v7m_handle_execute_nsc(ARMCPU *cpu) { - /* Check whether this attempt to execute code in a Secure & NS-Callable + /* + * Check whether this attempt to execute code in a Secure & NS-Callable * memory region is for an SG instruction; if so, then emulate the * effect of the SG instruction and return true. Otherwise pend * the correct kind of exception and return false. @@ -9503,7 +9551,8 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) ARMMMUIdx mmu_idx; uint16_t insn; =20 - /* We should never get here unless get_phys_addr_pmsav8() caused + /* + * We should never get here unless get_phys_addr_pmsav8() caused * an exception for NS executing in S&NSC memory. */ assert(!env->v7m.secure); @@ -9521,7 +9570,8 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) } =20 if (insn !=3D 0xe97f) { - /* Not an SG instruction first half (we choose the IMPDEF + /* + * Not an SG instruction first half (we choose the IMPDEF * early-SG-check option). */ goto gen_invep; @@ -9532,13 +9582,15 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) } =20 if (insn !=3D 0xe97f) { - /* Not an SG instruction second half (yes, both halves of the SG + /* + * Not an SG instruction second half (yes, both halves of the SG * insn have the same hex value) */ goto gen_invep; } =20 - /* OK, we have confirmed that we really have an SG instruction. + /* + * OK, we have confirmed that we really have an SG instruction. * We know we're NS in S memory so don't need to repeat those checks. */ qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx= 32 @@ -9567,8 +9619,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) =20 arm_log_exception(cs->exception_index); =20 - /* For exceptions we just mark as pending on the NVIC, and let that - handle it. */ + /* + * For exceptions we just mark as pending on the NVIC, and let that + * handle it. + */ switch (cs->exception_index) { case EXCP_UDEF: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); @@ -9614,13 +9668,15 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* Note that for M profile we don't have a guest facing FSR, but + /* + * Note that for M profile we don't have a guest facing FSR, but * the env->exception.fsr will be populated by the code that * raises the fault, in the A profile short-descriptor format. */ switch (env->exception.fsr & 0xf) { case M_FAKE_FSR_NSC_EXEC: - /* Exception generated when we try to execute code at an addre= ss + /* + * Exception generated when we try to execute code at an addre= ss * which is marked as Secure & Non-Secure Callable and the CPU * is in the Non-Secure state. The only instruction which can * be executed like this is SG (and that only if both halves of @@ -9633,7 +9689,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) } break; case M_FAKE_FSR_SFAULT: - /* Various flavours of SecureFault for attempts to execute or + /* + * Various flavours of SecureFault for attempts to execute or * access data in the wrong security state. */ switch (cs->exception_index) { @@ -9675,7 +9732,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); break; default: - /* All other FSR values are either MPU faults or "can't happen + /* + * All other FSR values are either MPU faults or "can't happen * for M profile" cases. */ switch (cs->exception_index) { @@ -9741,7 +9799,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) if (arm_feature(env, ARM_FEATURE_V8)) { lr =3D R_V7M_EXCRET_RES1_MASK | R_V7M_EXCRET_DCRS_MASK; - /* The S bit indicates whether we should return to Secure + /* + * The S bit indicates whether we should return to Secure * or NonSecure (ie our current state). * The ES bit indicates whether we're taking this exception * to Secure or NonSecure (ie our target state). We set it @@ -9776,7 +9835,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) v7m_exception_taken(cpu, lr, false, ignore_stackfaults); } =20 -/* Function used to synchronize QEMU's AArch64 register set with AArch32 +/* + * Function used to synchronize QEMU's AArch64 register set with AArch32 * register set. This is necessary when switching between AArch32 and AAr= ch64 * execution state. */ @@ -9790,7 +9850,8 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[i] =3D env->regs[i]; } =20 - /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r= 12. + /* + * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r= 12. * Otherwise, they come from the banked user regs. */ if (mode =3D=3D ARM_CPU_MODE_FIQ) { @@ -9803,7 +9864,8 @@ void aarch64_sync_32_to_64(CPUARMState *env) } } =20 - /* Registers x13-x23 are the various mode SP and FP registers. Registe= rs + /* + * Registers x13-x23 are the various mode SP and FP registers. Registe= rs * r13 and r14 are only copied if we are in that mode, otherwise we co= py * from the mode banked register. */ @@ -9858,7 +9920,8 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[23] =3D env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; } =20 - /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in F= IQ + /* + * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in F= IQ * mode, then we can copy from r8-r14. Otherwise, we copy from the * FIQ bank for r8-r14. */ @@ -9877,7 +9940,8 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->pc =3D env->regs[15]; } =20 -/* Function used to synchronize QEMU's AArch32 register set with AArch64 +/* + * Function used to synchronize QEMU's AArch32 register set with AArch64 * register set. This is necessary when switching between AArch32 and AAr= ch64 * execution state. */ @@ -9891,7 +9955,8 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[i] =3D env->xregs[i]; } =20 - /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x= 12. + /* + * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x= 12. * Otherwise, we copy x8-x12 into the banked user regs. */ if (mode =3D=3D ARM_CPU_MODE_FIQ) { @@ -9904,7 +9969,8 @@ void aarch64_sync_64_to_32(CPUARMState *env) } } =20 - /* Registers r13 & r14 depend on the current mode. + /* + * Registers r13 & r14 depend on the current mode. * If we are in a given mode, we copy the corresponding x registers to= r13 * and r14. Otherwise, we copy the x register to the banked r13 and r= 14 * for the mode. @@ -9915,7 +9981,8 @@ void aarch64_sync_64_to_32(CPUARMState *env) } else { env->banked_r13[bank_number(ARM_CPU_MODE_USR)] =3D env->xregs[13]; =20 - /* HYP is an exception in that it does not have its own banked r14= but + /* + * HYP is an exception in that it does not have its own banked r14= but * shares the USR r14 */ if (mode =3D=3D ARM_CPU_MODE_HYP) { @@ -12758,7 +12825,8 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t= reg) return value; } case 0x94: /* CONTROL_NS */ - /* We have to handle this here because unprivileged Secure code + /* + * We have to handle this here because unprivileged Secure code * can read the NS CONTROL register. */ if (!env->v7m.secure) { @@ -12811,7 +12879,8 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t= reg) return env->v7m.faultmask[M_REG_NS]; case 0x98: /* SP_NS */ { - /* This gives the non-secure SP selected based on whether we're + /* + * This gives the non-secure SP selected based on whether we're * currently in handler mode or not, using the NS CONTROL.SPSE= L. */ bool spsel =3D env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSE= L_MASK; @@ -12862,7 +12931,8 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t= reg) =20 void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) { - /* We're passed bits [11..0] of the instruction; extract + /* + * We're passed bits [11..0] of the instruction; extract * SYSm and the mask bits. * Invalid combinations of SYSm and mask are UNPREDICTABLE; * we choose to treat them as if the mask bits were valid. @@ -12948,7 +13018,8 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t mas= kreg, uint32_t val) return; case 0x98: /* SP_NS */ { - /* This gives the non-secure SP selected based on whether we're + /* + * This gives the non-secure SP selected based on whether we're * currently in handler mode or not, using the NS CONTROL.SPSE= L. */ bool spsel =3D env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSE= L_MASK; @@ -13109,7 +13180,8 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t = addr, uint32_t op) bool targetsec =3D env->v7m.secure; bool is_subpage; =20 - /* Work out what the security state and privilege level we're + /* + * Work out what the security state and privilege level we're * interested in is... */ if (alt) { @@ -13126,12 +13198,14 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_= t addr, uint32_t op) /* ...and then figure out which MMU index this is */ mmu_idx =3D arm_v7m_mmu_idx_for_secstate_and_priv(env, targetsec, targ= etpriv); =20 - /* We know that the MPU and SAU don't care about the access type + /* + * We know that the MPU and SAU don't care about the access type * for our purposes beyond that we don't want to claim to be * an insn fetch, so we arbitrarily call this a read. */ =20 - /* MPU region info only available for privileged or if + /* + * MPU region info only available for privileged or if * inspecting the other MPU state. */ if (arm_current_el(env) !=3D 0 || alt) { @@ -13236,7 +13310,8 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, =20 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) { - /* Implement DC ZVA, which zeroes a fixed-length block of memory. + /* + * Implement DC ZVA, which zeroes a fixed-length block of memory. * Note that we do not implement the (architecturally mandated) * alignment fault for attempts to use this on Device memory * (which matches the usual QEMU behaviour of not implementing either @@ -13249,7 +13324,8 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vadd= r_in) =20 #ifndef CONFIG_USER_ONLY { - /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than + /* + * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than * the block size so we might have to do more than one TLB lookup. * We know that in fact for any v8 CPU the page size is at least 4K * and the block size must be 2K or less, but TARGET_PAGE_SIZE is = only @@ -13276,7 +13352,8 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vadd= r_in) } } if (i =3D=3D maxidx) { - /* If it's all in the TLB it's fair game for just writing = to; + /* + * If it's all in the TLB it's fair game for just writing = to; * we know we don't need to update dirty status, etc. */ for (i =3D 0; i < maxidx - 1; i++) { @@ -13285,7 +13362,8 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vadd= r_in) memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); return; } - /* OK, try a store and see if we can populate the tlb. This + /* + * OK, try a store and see if we can populate the tlb. This * might cause an exception if the memory isn't writable, * in which case we will longjmp out of here. We must for * this purpose use the actual register value passed to us @@ -13301,7 +13379,8 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vadd= r_in) } } =20 - /* Slow path (probably attempt to do this to an I/O device or + /* + * Slow path (probably attempt to do this to an I/O device or * similar, or clearing of a block of code we have translations * cached for). Just do a series of byte writes as the architecture * demands. It's not worth trying to use a cpu_physical_memory_map= (), diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 4db254876dd..b1952486c61 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -97,7 +97,8 @@ static inline uint32_t merge_syn_data_abort(uint32_t temp= late_syn, { uint32_t syn; =20 - /* ISV is only set for data aborts routed to EL2 and + /* + * ISV is only set for data aborts routed to EL2 and * never for stage-1 page table walks faulting on stage 2. * * Furthermore, ISV is only set for certain kinds of load/stores. @@ -112,7 +113,8 @@ static inline uint32_t merge_syn_data_abort(uint32_t te= mplate_syn, syn =3D syn_data_abort_no_iss(same_el, ea, 0, s1ptw, is_write, fsc); } else { - /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template + /* + * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template * syndrome created at translation time. * Now we create the runtime syndrome with the remaining fields. */ @@ -144,14 +146,16 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAc= cessType access_type, =20 if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el) || arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { - /* LPAE format fault status register : bottom 6 bits are + /* + * LPAE format fault status register : bottom 6 bits are * status code in the same form as needed for syndrome */ fsr =3D arm_fi_to_lfsc(fi); fsc =3D extract32(fsr, 0, 6); } else { fsr =3D arm_fi_to_sfsc(fi); - /* Short format FSR : this fault will never actually be reported + /* + * Short format FSR : this fault will never actually be reported * to an EL that uses a syndrome register. Use a (currently) * reserved FSR code in case the constructed syndrome does leak * into the guest somehow. @@ -194,7 +198,8 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr va= ddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } =20 -/* arm_cpu_do_transaction_failed: handle a memory system error response +/* + * arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort * exception */ @@ -970,7 +975,8 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) int bt; uint32_t contextidr; =20 - /* Links to unimplemented or non-context aware breakpoints are + /* + * Links to unimplemented or non-context aware breakpoints are * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or * as if linked to an UNKNOWN context-aware breakpoint (in which * case DBGWCR_EL1.LBN must indicate that breakpoint). @@ -989,7 +995,8 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) =20 bt =3D extract64(bcr, 20, 4); =20 - /* We match the whole register even if this is AArch32 using the + /* + * We match the whole register even if this is AArch32 using the * short descriptor format (in which case it holds both PROCID and ASI= D), * since we don't implement the optional v7 context ID masking. */ @@ -1006,7 +1013,8 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) case 9: /* linked VMID match (reserved if no EL2) */ case 11: /* linked context ID and VMID match (reserved if no EL2) */ default: - /* Links to Unlinked context breakpoints must generate no + /* + * Links to Unlinked context breakpoints must generate no * events; we choose to do the same for reserved values too. */ return false; @@ -1020,7 +1028,8 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is= _wp) CPUARMState *env =3D &cpu->env; uint64_t cr; int pac, hmc, ssc, wt, lbn; - /* Note that for watchpoints the check is against the CPU security + /* + * Note that for watchpoints the check is against the CPU security * state, not the S/NS attribute on the offending data access. */ bool is_secure =3D arm_is_secure(env); @@ -1034,7 +1043,8 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is= _wp) } cr =3D env->cp15.dbgwcr[n]; if (wp->hitattrs.user) { - /* The LDRT/STRT/LDT/STT "unprivileged access" instructions sh= ould + /* + * The LDRT/STRT/LDT/STT "unprivileged access" instructions sh= ould * match watchpoints as if they were accesses done at EL0, eve= n if * the CPU is at EL1 or higher. */ @@ -1048,7 +1058,8 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is= _wp) } cr =3D env->cp15.dbgbcr[n]; } - /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is + /* + * The WATCHPOINT_HIT flag guarantees us that the watchpoint is * enabled and that the address and access type match; for breakpoints * we know the address matched; check the remaining fields, including * linked breakpoints. We rely on WCR and BCR having the same layout @@ -1116,7 +1127,8 @@ static bool check_watchpoints(ARMCPU *cpu) CPUARMState *env =3D &cpu->env; int n; =20 - /* If watchpoints are disabled globally or we can't take debug + /* + * If watchpoints are disabled globally or we can't take debug * exceptions here then watchpoint firings are ignored. */ if (extract32(env->cp15.mdscr_el1, 15, 1) =3D=3D 0 @@ -1137,7 +1149,8 @@ static bool check_breakpoints(ARMCPU *cpu) CPUARMState *env =3D &cpu->env; int n; =20 - /* If breakpoints are disabled globally or we can't take debug + /* + * If breakpoints are disabled globally or we can't take debug * exceptions here then breakpoint firings are ignored. */ if (extract32(env->cp15.mdscr_el1, 15, 1) =3D=3D 0 @@ -1164,7 +1177,8 @@ void HELPER(check_breakpoints)(CPUARMState *env) =20 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) { - /* Called by core code when a CPU watchpoint fires; need to check if t= his + /* + * Called by core code when a CPU watchpoint fires; need to check if t= his * is also an architectural watchpoint match. */ ARMCPU *cpu =3D ARM_CPU(cs); @@ -1177,7 +1191,8 @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vad= dr addr, int len) ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; =20 - /* In BE32 system mode, target memory is stored byteswapped (on a + /* + * In BE32 system mode, target memory is stored byteswapped (on a * little-endian host system), and by the time we reach here (via an * opcode helper) the addresses of subword accesses have been adjusted * to account for that, which means that watchpoints will not match. @@ -1196,7 +1211,8 @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vad= dr addr, int len) =20 void arm_debug_excp_handler(CPUState *cs) { - /* Called by core code when a watchpoint or breakpoint fires; + /* + * Called by core code when a watchpoint or breakpoint fires; * need to check which one and raise the appropriate exception. */ ARMCPU *cpu =3D ARM_CPU(cs); @@ -1220,7 +1236,8 @@ void arm_debug_excp_handler(CPUState *cs) uint64_t pc =3D is_a64(env) ? env->pc : env->regs[15]; bool same_el =3D (arm_debug_target_el(env) =3D=3D arm_current_el(e= nv)); =20 - /* (1) GDB breakpoints should be handled first. + /* + * (1) GDB breakpoints should be handled first. * (2) Do not raise a CPU exception if no CPU breakpoint has fired, * since singlestep is also done by generating a debug internal * exception. @@ -1231,7 +1248,8 @@ void arm_debug_excp_handler(CPUState *cs) } =20 env->exception.fsr =3D arm_debug_exception_fsr(env); - /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing + /* + * FAR is UNKNOWN: clear vaddress to avoid potentially exposing * values to the guest that it shouldn't be able to see at its * exception/security level. */ diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index d3e83b627b7..7ece78e987b 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -170,7 +170,8 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t v= al) set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16); } =20 - /* The exception flags are ORed together when we read fpscr so we + /* + * The exception flags are ORed together when we read fpscr so we * only need to preserve the current state in one of our * float_status values. */ --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562033864; cv=none; d=zoho.com; s=zohoarc; b=GAU66a0OP8DGhO/u0yT373cTskhin0SUO4KbWqtgWOQJq0nnyYin0HGkW6XYyIzz1p+oGF4mOVHYVeiK6DJFN8wRPXXjUTdYofrNI7wQTCPrTgC/SJOA6hSeweoqTPS/W3gNiQOIjXnvJZxiG9I9zOwKoYsH4Edyv6+9T7/a5J4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562033864; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=kvmRawPGPmElWaZn3Ee6CrEYDJliNT9WQgA2cgByzq0=; b=nluT/ijUJhmN/K+8bfwztDHyZQW2JqLkfXNzimxnP1lBTBIR1elBsbzjmdDdUpfKRSxUsF+A531yEWHZTDVLKIrw85sV0daQxxpPsO+6J41k1PsilvvBTDPWK/TQpWdU6dmTyM4zzFxllLAjhHJK39aRYnELPH4Bn+clD/5KPAs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562033864194356.677032275167; Mon, 1 Jul 2019 19:17:44 -0700 (PDT) Received: from localhost ([::1]:47167 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi8MZ-0004pK-7h for importer@patchew.org; Mon, 01 Jul 2019 22:17:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57246) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4Sn-00015d-KQ for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:07:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi4Se-000270-7V for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:07:47 -0400 Received: from mail-wr1-f54.google.com ([209.85.221.54]:41336) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi4Sc-000264-7e for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:07:44 -0400 Received: by mail-wr1-f54.google.com with SMTP id c2so15453590wrm.8 for ; Mon, 01 Jul 2019 15:07:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.23 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kvmRawPGPmElWaZn3Ee6CrEYDJliNT9WQgA2cgByzq0=; b=RgyXmKF1Azn3zawAGqyGiQQVgYJ2nV1x8DwVmPZGcQU/NtEQcKVATbRFkMVWbjQ4Ke asSYAnGDisiZoaGDhI7K75WNJiXTWcghdKTUapfB3AnzJxxWjyNNnfbo841iTn3rbNDk JOjtuFCj3BN0g++slmnAsemuYS4oQVW7hztq98cQNZV9/P5Uj1+N5fxfA8C+bnon5zHk kf+aifEaF7XR4bxQiuhvX2QWKJJnJDtOcJFjiInI63rkZv4vcOf9PumaoZTX8iNuywn7 4oOd7LqeJHeTvFD9q0UsJ3Yk4Z6HK1VIoxSzb6NGr4UwfwDA3kHeZTDE8BJ/92iac876 1F2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kvmRawPGPmElWaZn3Ee6CrEYDJliNT9WQgA2cgByzq0=; b=dCHAGdesC3hmFbozMuTpDGuI6/Xv6Iqgi2CbMBlu8Y6SZ+Q8ekuTPzOFGJ0pwroo4Q a3A86ly1Lkz8KBqHuHDnOE4p+QOzqrnTg8PzJi1ZUC7XptmkllvKzJR24dBjmmQ3/d9v 88UEp00PPtCgNapKhce/WIT5wYpYrXGrpJWgRhw+O5SrzBPYqptRUm5fe5sHbHWFXbvQ 4TjutSj/I1ZaXOgFuXRorWi/Q8XcRBiqR393hvHGISJ6DSWbeb+lnCVACoARq898dVjB I3RailzIIV2RY43zpVefMlLnVpGQDth4KKU/edm1MfO89bPcloAjTYQ/JxX7SVcEqMDa fZNQ== X-Gm-Message-State: APjAAAVB9Da2RvbGRoh37nwWLGJWxt4s+3y+ChHuIGZ8TW8I4JpEaISQ U4cFJJp7lVJHYQ5ZyT0M2chf8CY9TczDrA== X-Google-Smtp-Source: APXvYqwr/B6FgjDNoshZoyySt8Den7g3/hNz1yPFuglMZP3rA7hb9o/KwMze3Acuka/zSRy9laPZnA== X-Received: by 2002:a5d:5752:: with SMTP id q18mr14428598wrw.337.1561999224904; Mon, 01 Jul 2019 09:40:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:32 +0100 Message-Id: <20190701163943.22313-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.54 Subject: [Qemu-devel] [PULL 35/46] target/arm: Fix coding style issues X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Since we'll move this code around, fix its style first. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-9-philmd@redhat.com Signed-off-by: Peter Maydell --- target/arm/translate.c | 11 ++++++----- target/arm/vfp_helper.c | 36 ++++++++++++++++++++++++------------ 2 files changed, 30 insertions(+), 17 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4750b9fa1bb..c6bdf026b45 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9109,7 +9109,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) loaded_base =3D 0; loaded_var =3D NULL; n =3D 0; - for(i=3D0;i<16;i++) { + for (i =3D 0; i < 16; i++) { if (insn & (1 << i)) n++; } @@ -9132,7 +9132,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) } } j =3D 0; - for(i=3D0;i<16;i++) { + for (i =3D 0; i < 16; i++) { if (insn & (1 << i)) { if (is_load) { /* load */ @@ -12353,12 +12353,13 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, in= t flags) return; } =20 - for(i=3D0;i<16;i++) { + for (i =3D 0; i < 16; i++) { qemu_fprintf(f, "R%02d=3D%08x", i, env->regs[i]); - if ((i % 4) =3D=3D 3) + if ((i % 4) =3D=3D 3) { qemu_fprintf(f, "\n"); - else + } else { qemu_fprintf(f, " "); + } } =20 if (arm_feature(env, ARM_FEATURE_M)) { diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 7ece78e987b..121bdbd3aff 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -34,18 +34,24 @@ static inline int vfp_exceptbits_from_host(int host_bit= s) { int target_bits =3D 0; =20 - if (host_bits & float_flag_invalid) + if (host_bits & float_flag_invalid) { target_bits |=3D 1; - if (host_bits & float_flag_divbyzero) + } + if (host_bits & float_flag_divbyzero) { target_bits |=3D 2; - if (host_bits & float_flag_overflow) + } + if (host_bits & float_flag_overflow) { target_bits |=3D 4; - if (host_bits & (float_flag_underflow | float_flag_output_denormal)) + } + if (host_bits & (float_flag_underflow | float_flag_output_denormal)) { target_bits |=3D 8; - if (host_bits & float_flag_inexact) + } + if (host_bits & float_flag_inexact) { target_bits |=3D 0x10; - if (host_bits & float_flag_input_denormal) + } + if (host_bits & float_flag_input_denormal) { target_bits |=3D 0x80; + } return target_bits; } =20 @@ -80,18 +86,24 @@ static inline int vfp_exceptbits_to_host(int target_bit= s) { int host_bits =3D 0; =20 - if (target_bits & 1) + if (target_bits & 1) { host_bits |=3D float_flag_invalid; - if (target_bits & 2) + } + if (target_bits & 2) { host_bits |=3D float_flag_divbyzero; - if (target_bits & 4) + } + if (target_bits & 4) { host_bits |=3D float_flag_overflow; - if (target_bits & 8) + } + if (target_bits & 8) { host_bits |=3D float_flag_underflow; - if (target_bits & 0x10) + } + if (target_bits & 0x10) { host_bits |=3D float_flag_inexact; - if (target_bits & 0x80) + } + if (target_bits & 0x80) { host_bits |=3D float_flag_input_denormal; + } return host_bits; } =20 --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.24 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fdrDNbvOacI/5pnc14JmN0WEOnjbN8Mg7gxzfagzIQY=; b=fRoZJvYvB+ATgw/uLzWGE4PWwt48VIceP5oOGHYf/8DDXzReAmIrzjaH9pEsG1AjTD pGDMzcm7gYYK2xFOdD4oivjm6NQyjKAUMb8WCXLBsIX2M/7FgTywHympwB5ipAGmo5i+ 7zXRcc1fpsItpgHuZSjnA1BrRACMsTFfI1bYejJpfBU8RRy3SG1KR5aMVliPOWRmgfFs YFji1XFxQuiGhFgyWvuBwTNiLrQXFAb8ajtyUpVKn2Urn582nJ5h3vqQ42PrJXXCd/Fr wmY0REwUlLLmwHMnVL1pHPXzxPzJe3qw16C8GUrE3Rv6cGrcj8I0ImrCYcXeqcWyOD1t wavg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fdrDNbvOacI/5pnc14JmN0WEOnjbN8Mg7gxzfagzIQY=; b=mUYgXJTqkhFMnsRDBA9BgxoGGAUBqXb6+pKivzdo35ve7beTIf069VIsjP3rg+7Zc/ DOZNya7YUxNPMpRGuYdn6JkpX/mZecBDx2Teb3g3hvRAf0dK2Tz9ixvcFHpoDpNsMl1R f/XhO4kfUDfPRsuNBjXZgvNkbVp5WHXXaAtmRqtZGHb4bj9rMv7UiVGYm/ExfAbQiwtx ZNHpBvy2SEGiVK3zxy91ZtDyRNsBVpQsgaji4gIb9nl2UkO0FwAPdh629jW8hy6SL2fQ 5vlOwDa3sKNj+ebgcHca7JPJiY2pcV5WRgehzh6O/k4bd+4oNSByLskQbbjRlOFl2jE4 RDPw== X-Gm-Message-State: APjAAAVEr8O2yNER7yahT2e+YnVzm/o1PhvC1HU68nUJH0HT5ywxgbRr h9LkxnevzA0vay8EywQFgVNwfSe044mCPw== X-Google-Smtp-Source: APXvYqzDu2FYDg68HafCIoQYRaLHpX9MoHNCUDiTLEzlf1Kl6QWaZ+ELVAqJUkUg4BPZEgsPxz//qA== X-Received: by 2002:adf:e947:: with SMTP id m7mr8961791wrn.123.1561999225981; Mon, 01 Jul 2019 09:40:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:33 +0100 Message-Id: <20190701163943.22313-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.53 Subject: [Qemu-devel] [PULL 36/46] target/arm: Move the DC ZVA helper into op_helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Samuel Ortiz Those helpers are a software implementation of the ARM v8 memory zeroing op code. They should be moved to the op helper file, which is going to eventually be built only when TCG is enabled. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Robert Bradford Signed-off-by: Samuel Ortiz Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-10-philmd@redhat.com [PMD: Rebased] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 92 ----------------------------------------- target/arm/op_helper.c | 93 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 93 insertions(+), 92 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c77ed852155..a87fda91914 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13308,98 +13308,6 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, #endif } =20 -void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) -{ - /* - * Implement DC ZVA, which zeroes a fixed-length block of memory. - * Note that we do not implement the (architecturally mandated) - * alignment fault for attempts to use this on Device memory - * (which matches the usual QEMU behaviour of not implementing either - * alignment faults or any memory attribute handling). - */ - - ARMCPU *cpu =3D env_archcpu(env); - uint64_t blocklen =3D 4 << cpu->dcz_blocksize; - uint64_t vaddr =3D vaddr_in & ~(blocklen - 1); - -#ifndef CONFIG_USER_ONLY - { - /* - * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than - * the block size so we might have to do more than one TLB lookup. - * We know that in fact for any v8 CPU the page size is at least 4K - * and the block size must be 2K or less, but TARGET_PAGE_SIZE is = only - * 1K as an artefact of legacy v5 subpage support being present in= the - * same QEMU executable. So in practice the hostaddr[] array has - * two entries, given the current setting of TARGET_PAGE_BITS_MIN. - */ - int maxidx =3D DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); - void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)]; - int try, i; - unsigned mmu_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); - - assert(maxidx <=3D ARRAY_SIZE(hostaddr)); - - for (try =3D 0; try < 2; try++) { - - for (i =3D 0; i < maxidx; i++) { - hostaddr[i] =3D tlb_vaddr_to_host(env, - vaddr + TARGET_PAGE_SIZE *= i, - 1, mmu_idx); - if (!hostaddr[i]) { - break; - } - } - if (i =3D=3D maxidx) { - /* - * If it's all in the TLB it's fair game for just writing = to; - * we know we don't need to update dirty status, etc. - */ - for (i =3D 0; i < maxidx - 1; i++) { - memset(hostaddr[i], 0, TARGET_PAGE_SIZE); - } - memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); - return; - } - /* - * OK, try a store and see if we can populate the tlb. This - * might cause an exception if the memory isn't writable, - * in which case we will longjmp out of here. We must for - * this purpose use the actual register value passed to us - * so that we get the fault address right. - */ - helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); - /* Now we can populate the other TLB entries, if any */ - for (i =3D 0; i < maxidx; i++) { - uint64_t va =3D vaddr + TARGET_PAGE_SIZE * i; - if (va !=3D (vaddr_in & TARGET_PAGE_MASK)) { - helper_ret_stb_mmu(env, va, 0, oi, GETPC()); - } - } - } - - /* - * Slow path (probably attempt to do this to an I/O device or - * similar, or clearing of a block of code we have translations - * cached for). Just do a series of byte writes as the architecture - * demands. It's not worth trying to use a cpu_physical_memory_map= (), - * memset(), unmap() sequence here because: - * + we'd need to account for the blocksize being larger than a p= age - * + the direct-RAM access case is almost always going to be dealt - * with in the fastpath code above, so there's no speed benefit - * + we would have to deal with the map returning NULL because the - * bounce buffer was in use - */ - for (i =3D 0; i < blocklen; i++) { - helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); - } - } -#else - memset(g2h(vaddr), 0, blocklen); -#endif -} - /* Note that signed overflow is undefined in C. The following routines are careful to use unsigned types where modulo arithmetic is required. Failure to do so _will_ break on newer gcc. */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index b1952486c61..7c835d3ce77 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -17,6 +17,7 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" @@ -1325,3 +1326,95 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x= , uint32_t i) return ((uint32_t)x >> shift) | (x << (32 - shift)); } } + +void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) +{ + /* + * Implement DC ZVA, which zeroes a fixed-length block of memory. + * Note that we do not implement the (architecturally mandated) + * alignment fault for attempts to use this on Device memory + * (which matches the usual QEMU behaviour of not implementing either + * alignment faults or any memory attribute handling). + */ + + ARMCPU *cpu =3D env_archcpu(env); + uint64_t blocklen =3D 4 << cpu->dcz_blocksize; + uint64_t vaddr =3D vaddr_in & ~(blocklen - 1); + +#ifndef CONFIG_USER_ONLY + { + /* + * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than + * the block size so we might have to do more than one TLB lookup. + * We know that in fact for any v8 CPU the page size is at least 4K + * and the block size must be 2K or less, but TARGET_PAGE_SIZE is = only + * 1K as an artefact of legacy v5 subpage support being present in= the + * same QEMU executable. So in practice the hostaddr[] array has + * two entries, given the current setting of TARGET_PAGE_BITS_MIN. + */ + int maxidx =3D DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); + void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)]; + int try, i; + unsigned mmu_idx =3D cpu_mmu_index(env, false); + TCGMemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + + assert(maxidx <=3D ARRAY_SIZE(hostaddr)); + + for (try =3D 0; try < 2; try++) { + + for (i =3D 0; i < maxidx; i++) { + hostaddr[i] =3D tlb_vaddr_to_host(env, + vaddr + TARGET_PAGE_SIZE *= i, + 1, mmu_idx); + if (!hostaddr[i]) { + break; + } + } + if (i =3D=3D maxidx) { + /* + * If it's all in the TLB it's fair game for just writing = to; + * we know we don't need to update dirty status, etc. + */ + for (i =3D 0; i < maxidx - 1; i++) { + memset(hostaddr[i], 0, TARGET_PAGE_SIZE); + } + memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); + return; + } + /* + * OK, try a store and see if we can populate the tlb. This + * might cause an exception if the memory isn't writable, + * in which case we will longjmp out of here. We must for + * this purpose use the actual register value passed to us + * so that we get the fault address right. + */ + helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); + /* Now we can populate the other TLB entries, if any */ + for (i =3D 0; i < maxidx; i++) { + uint64_t va =3D vaddr + TARGET_PAGE_SIZE * i; + if (va !=3D (vaddr_in & TARGET_PAGE_MASK)) { + helper_ret_stb_mmu(env, va, 0, oi, GETPC()); + } + } + } + + /* + * Slow path (probably attempt to do this to an I/O device or + * similar, or clearing of a block of code we have translations + * cached for). Just do a series of byte writes as the architecture + * demands. It's not worth trying to use a cpu_physical_memory_map= (), + * memset(), unmap() sequence here because: + * + we'd need to account for the blocksize being larger than a p= age + * + the direct-RAM access case is almost always going to be dealt + * with in the fastpath code above, so there's no speed benefit + * + we would have to deal with the map returning NULL because the + * bounce buffer was in use + */ + for (i =3D 0; i < blocklen; i++) { + helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); + } + } +#else + memset(g2h(vaddr), 0, blocklen); +#endif +} --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562026907; cv=none; d=zoho.com; s=zohoarc; b=hNcuZd1qV1S1zdiILGbz26jS4DkaHZZ+ylhK6JpltNzwSJ9aVukwzcd8Ty2xl6sKXexyCp2ORHVCvjq6vdmE+ZZUaB9/IE+qAVEss7b8sAS3RhPr7Exocd2lYWi7mjJPX/Tz6LVsGkHCKbWf+M03XUXPtD7YP1ZfAhE1yBGjeo0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562026907; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=QjlnPd48sl1+3JCPnbga36CM99PsIZY1yldEsKZ9V/s=; b=g/QKpKq20jTQrh3aCvbS70w8zsxrAldDw86ISboe8M+c95iqU9xo/M1Hie7nUw8/BHAzUadwa6bQZgAkNgBewImxjCHA0P3tJJ8SaUL2GOdwfbxftKfGqJPLJ1w/yPeoW/SuAA2W+oOrCDDPMU2L4yqWGobp4Oo2TIabfj+0li4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562026907699399.27035694435745; Mon, 1 Jul 2019 17:21:47 -0700 (PDT) Received: from localhost ([::1]:46406 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi6YK-0002Ug-EB for importer@patchew.org; Mon, 01 Jul 2019 20:21:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47733) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3zt-00020G-Pr for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:38:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3zr-0003Ai-Pq for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:38:01 -0400 Received: from mail-wr1-f54.google.com ([209.85.221.54]:33123) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3zn-00033o-1I for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:37:55 -0400 Received: by mail-wr1-f54.google.com with SMTP id n9so15432818wru.0 for ; Mon, 01 Jul 2019 14:37:38 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.26 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QjlnPd48sl1+3JCPnbga36CM99PsIZY1yldEsKZ9V/s=; b=qLA9/CUUaOTb1wH5mfGLt9H6r4N3oWvUJBOMCPBv4cSMAZgMfdDFI246E1lj3bg4qi LzzuUmQbZ9VUPsTh/EHPwJ6lCaZhYVkPEK3amu0WlUQ8JykxCY8ZMfuvWF4JgCX6D7GD ZPAv+CmVPTD37JkyL/JT6AWrME1jsqVvAY7m4J3i4MWdKvIHVntXoY19wek2aWQizdtE 2H2tev56MSTtIY/GENqvSzO/2iCTqw9Ofovp1blwDTqJN4Q132OXwu+wZAWPfA17v9UA tLQZ9QZLEXZjxhriyD5b8gj/Ael0+0/nOz3TOjUhFl8QdyOHRxubuEYPIdr+ydLChoJ/ +yNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QjlnPd48sl1+3JCPnbga36CM99PsIZY1yldEsKZ9V/s=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.54 Subject: [Qemu-devel] [PULL 37/46] target/arm: Move CPU state dumping routines to cpu.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-11-philmd@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 - target/arm/translate.h | 5 - target/arm/cpu.c | 226 +++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 128 --------------------- target/arm/translate.c | 88 --------------- 5 files changed, 226 insertions(+), 223 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f9da672be57..a9be18660fd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -929,8 +929,6 @@ void arm_cpu_do_interrupt(CPUState *cpu); void arm_v7m_cpu_do_interrupt(CPUState *cpu); bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); =20 -void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags); - hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); =20 diff --git a/target/arm/translate.h b/target/arm/translate.h index bc1617809da..a20f6e20568 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -169,7 +169,6 @@ static inline void disas_set_insn_syndrome(DisasContext= *s, uint32_t syn) #ifdef TARGET_AARCH64 void a64_translate_init(void); void gen_a64_set_pc_im(uint64_t val); -void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags); extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) @@ -179,10 +178,6 @@ static inline void a64_translate_init(void) static inline void gen_a64_set_pc_im(uint64_t val) { } - -static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ -} #endif =20 void arm_test_cc(DisasCompare *cmp, int cc); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 376db154f00..1f73631bac0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -19,6 +19,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/qemu-print.h" #include "qemu-common.h" #include "target/arm/idau.h" #include "qemu/module.h" @@ -676,6 +677,231 @@ static void arm_disas_set_info(CPUState *cpu, disasse= mble_info *info) #endif } =20 +#ifdef TARGET_AARCH64 + +static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint32_t psr =3D pstate_read(env); + int i; + int el =3D arm_current_el(env); + const char *ns_status; + + qemu_fprintf(f, " PC=3D%016" PRIx64 " ", env->pc); + for (i =3D 0; i < 32; i++) { + if (i =3D=3D 31) { + qemu_fprintf(f, " SP=3D%016" PRIx64 "\n", env->xregs[i]); + } else { + qemu_fprintf(f, "X%02d=3D%016" PRIx64 "%s", i, env->xregs[i], + (i + 2) % 3 ? " " : "\n"); + } + } + + if (arm_feature(env, ARM_FEATURE_EL3) && el !=3D 3) { + ns_status =3D env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + } else { + ns_status =3D ""; + } + qemu_fprintf(f, "PSTATE=3D%08x %c%c%c%c %sEL%d%c", + psr, + psr & PSTATE_N ? 'N' : '-', + psr & PSTATE_Z ? 'Z' : '-', + psr & PSTATE_C ? 'C' : '-', + psr & PSTATE_V ? 'V' : '-', + ns_status, + el, + psr & PSTATE_SP ? 'h' : 't'); + + if (cpu_isar_feature(aa64_bti, cpu)) { + qemu_fprintf(f, " BTYPE=3D%d", (psr & PSTATE_BTYPE) >> 10); + } + if (!(flags & CPU_DUMP_FPU)) { + qemu_fprintf(f, "\n"); + return; + } + if (fp_exception_el(env, el) !=3D 0) { + qemu_fprintf(f, " FPU disabled\n"); + return; + } + qemu_fprintf(f, " FPCR=3D%08x FPSR=3D%08x\n", + vfp_get_fpcr(env), vfp_get_fpsr(env)); + + if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) =3D= =3D 0) { + int j, zcr_len =3D sve_zcr_len_for_el(env, el); + + for (i =3D 0; i <=3D FFR_PRED_NUM; i++) { + bool eol; + if (i =3D=3D FFR_PRED_NUM) { + qemu_fprintf(f, "FFR=3D"); + /* It's last, so end the line. */ + eol =3D true; + } else { + qemu_fprintf(f, "P%02d=3D", i); + switch (zcr_len) { + case 0: + eol =3D i % 8 =3D=3D 7; + break; + case 1: + eol =3D i % 6 =3D=3D 5; + break; + case 2: + case 3: + eol =3D i % 3 =3D=3D 2; + break; + default: + /* More than one quadword per predicate. */ + eol =3D true; + break; + } + } + for (j =3D zcr_len / 4; j >=3D 0; j--) { + int digits; + if (j * 4 + 4 <=3D zcr_len + 1) { + digits =3D 16; + } else { + digits =3D (zcr_len % 4 + 1) * 4; + } + qemu_fprintf(f, "%0*" PRIx64 "%s", digits, + env->vfp.pregs[i].p[j], + j ? ":" : eol ? "\n" : " "); + } + } + + for (i =3D 0; i < 32; i++) { + if (zcr_len =3D=3D 0) { + qemu_fprintf(f, "Z%02d=3D%016" PRIx64 ":%016" PRIx64 "%s", + i, env->vfp.zregs[i].d[1], + env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); + } else if (zcr_len =3D=3D 1) { + qemu_fprintf(f, "Z%02d=3D%016" PRIx64 ":%016" PRIx64 + ":%016" PRIx64 ":%016" PRIx64 "\n", + i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].= d[2], + env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0= ]); + } else { + for (j =3D zcr_len; j >=3D 0; j--) { + bool odd =3D (zcr_len - j) % 2 !=3D 0; + if (j =3D=3D zcr_len) { + qemu_fprintf(f, "Z%02d[%x-%x]=3D", i, j, j - 1); + } else if (!odd) { + if (j > 0) { + qemu_fprintf(f, " [%x-%x]=3D", j, j - 1); + } else { + qemu_fprintf(f, " [%x]=3D", j); + } + } + qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", + env->vfp.zregs[i].d[j * 2 + 1], + env->vfp.zregs[i].d[j * 2], + odd || j =3D=3D 0 ? "\n" : ":"); + } + } + } + } else { + for (i =3D 0; i < 32; i++) { + uint64_t *q =3D aa64_vfp_qreg(env, i); + qemu_fprintf(f, "Q%02d=3D%016" PRIx64 ":%016" PRIx64 "%s", + i, q[1], q[0], (i & 1 ? "\n" : " ")); + } + } +} + +#else + +static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + g_assert_not_reached(); +} + +#endif + +static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + int i; + + if (is_a64(env)) { + aarch64_cpu_dump_state(cs, f, flags); + return; + } + + for (i =3D 0; i < 16; i++) { + qemu_fprintf(f, "R%02d=3D%08x", i, env->regs[i]); + if ((i % 4) =3D=3D 3) { + qemu_fprintf(f, "\n"); + } else { + qemu_fprintf(f, " "); + } + } + + if (arm_feature(env, ARM_FEATURE_M)) { + uint32_t xpsr =3D xpsr_read(env); + const char *mode; + const char *ns_status =3D ""; + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + ns_status =3D env->v7m.secure ? "S " : "NS "; + } + + if (xpsr & XPSR_EXCP) { + mode =3D "handler"; + } else { + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MA= SK) { + mode =3D "unpriv-thread"; + } else { + mode =3D "priv-thread"; + } + } + + qemu_fprintf(f, "XPSR=3D%08x %c%c%c%c %c %s%s\n", + xpsr, + xpsr & XPSR_N ? 'N' : '-', + xpsr & XPSR_Z ? 'Z' : '-', + xpsr & XPSR_C ? 'C' : '-', + xpsr & XPSR_V ? 'V' : '-', + xpsr & XPSR_T ? 'T' : 'A', + ns_status, + mode); + } else { + uint32_t psr =3D cpsr_read(env); + const char *ns_status =3D ""; + + if (arm_feature(env, ARM_FEATURE_EL3) && + (psr & CPSR_M) !=3D ARM_CPU_MODE_MON) { + ns_status =3D env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + } + + qemu_fprintf(f, "PSR=3D%08x %c%c%c%c %c %s%s%d\n", + psr, + psr & CPSR_N ? 'N' : '-', + psr & CPSR_Z ? 'Z' : '-', + psr & CPSR_C ? 'C' : '-', + psr & CPSR_V ? 'V' : '-', + psr & CPSR_T ? 'T' : 'A', + ns_status, + aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); + } + + if (flags & CPU_DUMP_FPU) { + int numvfpregs =3D 0; + if (arm_feature(env, ARM_FEATURE_VFP)) { + numvfpregs +=3D 16; + } + if (arm_feature(env, ARM_FEATURE_VFP3)) { + numvfpregs +=3D 16; + } + for (i =3D 0; i < numvfpregs; i++) { + uint64_t v =3D *aa32_vfp_dreg(env, i); + qemu_fprintf(f, "s%02d=3D%08x s%02d=3D%08x d%02d=3D%016" PRIx6= 4 "\n", + i * 2, (uint32_t)v, + i * 2 + 1, (uint32_t)(v >> 32), + i, v); + } + qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); + } +} + uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) { uint32_t Aff1 =3D idx / clustersz; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 97f4164fbbc..d3231477a27 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -27,7 +27,6 @@ #include "translate.h" #include "internals.h" #include "qemu/host-utils.h" -#include "qemu/qemu-print.h" =20 #include "hw/semihosting/semihost.h" #include "exec/gen-icount.h" @@ -152,133 +151,6 @@ static void set_btype(DisasContext *s, int val) s->btype =3D -1; } =20 -void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - uint32_t psr =3D pstate_read(env); - int i; - int el =3D arm_current_el(env); - const char *ns_status; - - qemu_fprintf(f, " PC=3D%016" PRIx64 " ", env->pc); - for (i =3D 0; i < 32; i++) { - if (i =3D=3D 31) { - qemu_fprintf(f, " SP=3D%016" PRIx64 "\n", env->xregs[i]); - } else { - qemu_fprintf(f, "X%02d=3D%016" PRIx64 "%s", i, env->xregs[i], - (i + 2) % 3 ? " " : "\n"); - } - } - - if (arm_feature(env, ARM_FEATURE_EL3) && el !=3D 3) { - ns_status =3D env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; - } else { - ns_status =3D ""; - } - qemu_fprintf(f, "PSTATE=3D%08x %c%c%c%c %sEL%d%c", - psr, - psr & PSTATE_N ? 'N' : '-', - psr & PSTATE_Z ? 'Z' : '-', - psr & PSTATE_C ? 'C' : '-', - psr & PSTATE_V ? 'V' : '-', - ns_status, - el, - psr & PSTATE_SP ? 'h' : 't'); - - if (cpu_isar_feature(aa64_bti, cpu)) { - qemu_fprintf(f, " BTYPE=3D%d", (psr & PSTATE_BTYPE) >> 10); - } - if (!(flags & CPU_DUMP_FPU)) { - qemu_fprintf(f, "\n"); - return; - } - if (fp_exception_el(env, el) !=3D 0) { - qemu_fprintf(f, " FPU disabled\n"); - return; - } - qemu_fprintf(f, " FPCR=3D%08x FPSR=3D%08x\n", - vfp_get_fpcr(env), vfp_get_fpsr(env)); - - if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) =3D= =3D 0) { - int j, zcr_len =3D sve_zcr_len_for_el(env, el); - - for (i =3D 0; i <=3D FFR_PRED_NUM; i++) { - bool eol; - if (i =3D=3D FFR_PRED_NUM) { - qemu_fprintf(f, "FFR=3D"); - /* It's last, so end the line. */ - eol =3D true; - } else { - qemu_fprintf(f, "P%02d=3D", i); - switch (zcr_len) { - case 0: - eol =3D i % 8 =3D=3D 7; - break; - case 1: - eol =3D i % 6 =3D=3D 5; - break; - case 2: - case 3: - eol =3D i % 3 =3D=3D 2; - break; - default: - /* More than one quadword per predicate. */ - eol =3D true; - break; - } - } - for (j =3D zcr_len / 4; j >=3D 0; j--) { - int digits; - if (j * 4 + 4 <=3D zcr_len + 1) { - digits =3D 16; - } else { - digits =3D (zcr_len % 4 + 1) * 4; - } - qemu_fprintf(f, "%0*" PRIx64 "%s", digits, - env->vfp.pregs[i].p[j], - j ? ":" : eol ? "\n" : " "); - } - } - - for (i =3D 0; i < 32; i++) { - if (zcr_len =3D=3D 0) { - qemu_fprintf(f, "Z%02d=3D%016" PRIx64 ":%016" PRIx64 "%s", - i, env->vfp.zregs[i].d[1], - env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); - } else if (zcr_len =3D=3D 1) { - qemu_fprintf(f, "Z%02d=3D%016" PRIx64 ":%016" PRIx64 - ":%016" PRIx64 ":%016" PRIx64 "\n", - i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].= d[2], - env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0= ]); - } else { - for (j =3D zcr_len; j >=3D 0; j--) { - bool odd =3D (zcr_len - j) % 2 !=3D 0; - if (j =3D=3D zcr_len) { - qemu_fprintf(f, "Z%02d[%x-%x]=3D", i, j, j - 1); - } else if (!odd) { - if (j > 0) { - qemu_fprintf(f, " [%x-%x]=3D", j, j - 1); - } else { - qemu_fprintf(f, " [%x]=3D", j); - } - } - qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", - env->vfp.zregs[i].d[j * 2 + 1], - env->vfp.zregs[i].d[j * 2], - odd || j =3D=3D 0 ? "\n" : ":"); - } - } - } - } else { - for (i =3D 0; i < 32; i++) { - uint64_t *q =3D aa64_vfp_qreg(env, i); - qemu_fprintf(f, "Q%02d=3D%016" PRIx64 ":%016" PRIx64 "%s", - i, q[1], q[0], (i & 1 ? "\n" : " ")); - } - } -} - void gen_a64_set_pc_im(uint64_t val) { tcg_gen_movi_i64(cpu_pc, val); diff --git a/target/arm/translate.c b/target/arm/translate.c index c6bdf026b45..a5d77234232 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -28,7 +28,6 @@ #include "tcg-op-gvec.h" #include "qemu/log.h" #include "qemu/bitops.h" -#include "qemu/qemu-print.h" #include "arm_ldst.h" #include "hw/semihosting/semihost.h" =20 @@ -12342,93 +12341,6 @@ void gen_intermediate_code(CPUState *cpu, Translat= ionBlock *tb, int max_insns) translator_loop(ops, &dc.base, cpu, tb, max_insns); } =20 -void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - int i; - - if (is_a64(env)) { - aarch64_cpu_dump_state(cs, f, flags); - return; - } - - for (i =3D 0; i < 16; i++) { - qemu_fprintf(f, "R%02d=3D%08x", i, env->regs[i]); - if ((i % 4) =3D=3D 3) { - qemu_fprintf(f, "\n"); - } else { - qemu_fprintf(f, " "); - } - } - - if (arm_feature(env, ARM_FEATURE_M)) { - uint32_t xpsr =3D xpsr_read(env); - const char *mode; - const char *ns_status =3D ""; - - if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - ns_status =3D env->v7m.secure ? "S " : "NS "; - } - - if (xpsr & XPSR_EXCP) { - mode =3D "handler"; - } else { - if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MA= SK) { - mode =3D "unpriv-thread"; - } else { - mode =3D "priv-thread"; - } - } - - qemu_fprintf(f, "XPSR=3D%08x %c%c%c%c %c %s%s\n", - xpsr, - xpsr & XPSR_N ? 'N' : '-', - xpsr & XPSR_Z ? 'Z' : '-', - xpsr & XPSR_C ? 'C' : '-', - xpsr & XPSR_V ? 'V' : '-', - xpsr & XPSR_T ? 'T' : 'A', - ns_status, - mode); - } else { - uint32_t psr =3D cpsr_read(env); - const char *ns_status =3D ""; - - if (arm_feature(env, ARM_FEATURE_EL3) && - (psr & CPSR_M) !=3D ARM_CPU_MODE_MON) { - ns_status =3D env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; - } - - qemu_fprintf(f, "PSR=3D%08x %c%c%c%c %c %s%s%d\n", - psr, - psr & CPSR_N ? 'N' : '-', - psr & CPSR_Z ? 'Z' : '-', - psr & CPSR_C ? 'C' : '-', - psr & CPSR_V ? 'V' : '-', - psr & CPSR_T ? 'T' : 'A', - ns_status, - aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); - } - - if (flags & CPU_DUMP_FPU) { - int numvfpregs =3D 0; - if (arm_feature(env, ARM_FEATURE_VFP)) { - numvfpregs +=3D 16; - } - if (arm_feature(env, ARM_FEATURE_VFP3)) { - numvfpregs +=3D 16; - } - for (i =3D 0; i < numvfpregs; i++) { - uint64_t v =3D *aa32_vfp_dreg(env, i); - qemu_fprintf(f, "s%02d=3D%08x s%02d=3D%08x d%02d=3D%016" PRIx6= 4 "\n", - i * 2, (uint32_t)v, - i * 2 + 1, (uint32_t)(v >> 32), - i, v); - } - qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); - } -} - void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, target_ulong *data) { --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562031626; cv=none; d=zoho.com; s=zohoarc; b=Jeq+ZjAEtdJXVIumhjJqhic6wTHu8beWMFe29cYq1B2DgMPRJB73Hx+/02RpJqVB9taPNEIKTBBk/juqwbM03lUq44/OJBsURVDCaspx3m6BWWoSRAtahq3JxT81QhHPCwSpT4E+KcW/KlsWMenqVQQpSn186s2LnBL1Hhytag8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562031626; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=xrdtLDaUXsZEoNM0lxPRwqv5cfPxmVrBimeKTadrMYw=; b=ivAmaOIJLAgxvbrTR00PPVmmxzB3VMnHx6AKL/VxO4yCSX/RwLSgB+35SlmWH/5pCRT7hEpr1WbOh3syvFURFTXjAXHBlHB5kwrthK/HqAE/bo2mgD31vI/+pBSDKDvmMLJY2kwSvCaaEvJ8JxPpqm7u/btn5i4xLmXGC8WxvEk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562031626890770.4297327267137; Mon, 1 Jul 2019 18:40:26 -0700 (PDT) Received: from localhost ([::1]:46954 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi7mM-0002XR-Oj for importer@patchew.org; Mon, 01 Jul 2019 21:40:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46993) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3xE-0000N7-AF for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:35:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3xC-0002CR-Bh for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:35:16 -0400 Received: from mail-wr1-f44.google.com ([209.85.221.44]:39806) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3xB-0001ud-Vk for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:35:14 -0400 Received: by mail-wr1-f44.google.com with SMTP id x4so15381532wrt.6 for ; Mon, 01 Jul 2019 14:34:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.27 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xrdtLDaUXsZEoNM0lxPRwqv5cfPxmVrBimeKTadrMYw=; b=djeXwqZEQVv8z9nIyOZo04/p+tStRMiTYhs1Yclq/nqPQNFbky0dukE2VILEWn+vog 5hKPhInK5Jd8k/NTnSQyJIVBq4u+v0wFnwwKXQPzshUVS8xjzkkTsMEB6M08q8HRRvfn 8aGC3dNuIwp+J95jjM5cWBZnQ/7+MO7vK0SIJdDiU5guKbvJO9tTxJH3I9OhjdYO6MGe 7AUkJSz6Wn+JDUhuscqCOasGAPyYULdAe8DlCcq5HEmgL8dj4RciWZL4NEMbHOLWUsAP NUShKVGCdjui+muUlAgyP71RW30CxzI4Okpix21ZKT9e6dPeLt31E+8lUl5DKusIIVRA SEFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xrdtLDaUXsZEoNM0lxPRwqv5cfPxmVrBimeKTadrMYw=; b=M43AYaqgQadmQDeQvawhKp42M3J6G59P1r0a7dzp9J+qJCM0t6JNkKDu863wdIMp7Y oaINYorWfeOCYO7IGy5uh52Uq6essTp+xB1Wv0Wj2/2LB3UDcim0kSoLrNDhW3BTaWyt z9X9Q+Gq0rwB/TgFNAjNHI/azu8j9Ka3p4uxrG3u3QmQlZN+BNy/J7YJnqT/3OPQLPaw 1/xsOKfgaR7ZAmNHacqJp9CFBLT2w4CfE2A7p/6ECTbuINWMkcepqm2JI21yGv9Xre9H ofCDSAw2uccXs2RCIc09zaNTy5OxoW7kymYc/aIxGhk4z+B91Fk4OM6XD5hiU073yvvF K7mA== X-Gm-Message-State: APjAAAWJd2XOutprC1Ji5CZyIfYKilhF8VGeARDWdGv50/KWyv+9DCUP QdB/mdv58wywGhA4Z5X7y+mpUOjjr1sZCA== X-Google-Smtp-Source: APXvYqyQtivOVjwgWQWt0iPRN1tzAVHEk54hlL1Y6uFuMP0PKQ8ZQOZmvWlLZrQKS2YisNF9ICXqnA== X-Received: by 2002:adf:d4c1:: with SMTP id w1mr13032251wrk.229.1561999228119; Mon, 01 Jul 2019 09:40:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:35 +0100 Message-Id: <20190701163943.22313-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.44 Subject: [Qemu-devel] [PULL 38/46] target/arm: Declare get_phys_addr() function publicly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 In the next commit we will split the TLB related routines of this file, and this function will also be called in the new file. Declare it in the "internals.h" header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-12-philmd@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/internals.h | 16 ++++++++++++++++ target/arm/helper.c | 21 +++++---------------- 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 5a02f458f39..ff5ab0328e8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -985,4 +985,20 @@ static inline int exception_target_el(CPUARMState *env) return target_el; } =20 +#ifndef CONFIG_USER_ONLY + +/* Cacheability and shareability attributes for a memory access */ +typedef struct ARMCacheAttrs { + unsigned int attrs:8; /* as in the MAIR register encoding */ + unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PT= Es */ +} ARMCacheAttrs; + +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); + +#endif /* !CONFIG_USER_ONLY */ + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index a87fda91914..063f4778e0a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -33,17 +33,6 @@ #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ =20 #ifndef CONFIG_USER_ONLY -/* Cacheability and shareability attributes for a memory access */ -typedef struct ARMCacheAttrs { - unsigned int attrs:8; /* as in the MAIR register encoding */ - unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PT= Es */ -} ARMCacheAttrs; - -static bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); =20 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, @@ -12639,11 +12628,11 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheA= ttrs s1, ARMCacheAttrs s2) * @fi: set to fault info if the translation fails * @cacheattrs: (if non-NULL) set to the cacheability/shareability attribu= tes */ -static bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS= E1) { /* Call ourselves recursively to do the stage 1 and then stage 2 --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.28 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Yg5Vx+HL92u3RjZhwa/JrTs4lVp0MXgbzgCuIPXTEJA=; b=lgwylm3h7UNq3fo3wlBmzBiyP+kL1F6Tyqk2qXYEP/4I1HfRMaM2mjpMBLHocjwKeS liTjBfIaCBEtYPMSOhzxGLYDZI8sdMzHtUnNd9xu8oFaOmDJ7kb6ukLm80LBqymLck8I zboXqBPyW2GXCPpQfGKC2kLum3yceaAVoEB2y9aZk+xQ/h8Njk3p3EeZfejvf1VoFERL nEjaQWKIwwekmnyxhARddcuLar48WqPfGex/KPP1cnSTm7slIyaf194lyFxuUFeMRQWP vHvOO7hdP9O/j4vGMzyDtqSLdBapG1g963p/V+uvEnQEeEPN4Q43ATyT4DsGF1Zu/XO4 bUlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Yg5Vx+HL92u3RjZhwa/JrTs4lVp0MXgbzgCuIPXTEJA=; b=ihzk15pORXBgtoBTwM489pEWmy3PgPsGrjXSSFu9MYRcGF4aWmcdoIeh64dvE9wbXa Pt3kpowMPNGX8aBlWJygAsgersLUu7mUie/ksXVTa5kBywPzgfvrRMFWx5f3Kza1lQj8 /gEXQY5b2/Lr52uaPPa3ipPN6PjDCa9gU77mzUXNC1+FwIJhdiCRLla2szzK5/wfdOTd bDdfDmiOt/IL8QmQ39taiNEhnJUr+KsRfjcvBRpxIcXe2ITswI5OX3qrL7lavA8zlQHv AdML05JDnTF3k46lH9SvRDT3mdYphDvNBTKnIP7kNfeiDe/iJjDEwKGBkktXF8IaK1af G02w== X-Gm-Message-State: APjAAAVUXjX7d9bKs93YDNQqVfYAbaaJeC9yCW/PRqOU8RF/l+h7LYa1 slolTjY1pCQ10bDiS/MFgb9+u8zbhTReKA== X-Google-Smtp-Source: APXvYqxXvlU4Lml+RgWEsGhLIpp1R5DGGSLLtwebfSiF9z6A7VTieayFOjyjWwq82ep0C1f+qz3SbQ== X-Received: by 2002:a1c:1f06:: with SMTP id f6mr147412wmf.60.1561999229372; Mon, 01 Jul 2019 09:40:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:36 +0100 Message-Id: <20190701163943.22313-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.53 Subject: [Qemu-devel] [PULL 39/46] target/arm: Move TLB related routines to tlb_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 These routines are TCG specific. The arm_deliver_fault() function is only used within the new helper. Make it static. Suggested-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-13-philmd@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/Makefile.objs | 1 + target/arm/internals.h | 3 - target/arm/cpu.c | 6 +- target/arm/helper.c | 53 ----------- target/arm/op_helper.c | 135 -------------------------- target/arm/tlb_helper.c | 200 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 205 insertions(+), 193 deletions(-) create mode 100644 target/arm/tlb_helper.c diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 3fcda66132a..5c154f01c58 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -32,6 +32,7 @@ target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c =20 +obj-y +=3D tlb_helper.o obj-y +=3D translate.o op_helper.o obj-y +=3D crypto_helper.o obj-y +=3D iwmmxt_helper.o vec_helper.o neon_helper.o diff --git a/target/arm/internals.h b/target/arm/internals.h index ff5ab0328e8..46a1313d69d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -765,9 +765,6 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 -void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, - int mmu_idx, ARMMMUFaultInfo *fi) QEMU_NORETURN; - /* Return true if the stage 1 translation regime is using LPAE format page * tables */ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1f73631bac0..f21261c8ff8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2566,8 +2566,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->do_interrupt =3D arm_cpu_do_interrupt; - cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; - cc->do_transaction_failed =3D arm_cpu_do_transaction_failed; cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->vmsd =3D &vmstate_arm_cpu; @@ -2590,6 +2588,10 @@ static void arm_cpu_class_init(ObjectClass *oc, void= *data) #ifdef CONFIG_TCG cc->tcg_initialize =3D arm_translate_init; cc->tlb_fill =3D arm_cpu_tlb_fill; +#if !defined(CONFIG_USER_ONLY) + cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; + cc->do_transaction_failed =3D arm_cpu_do_transaction_failed; +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ #endif } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 063f4778e0a..4ef908c611e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13244,59 +13244,6 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t= addr, uint32_t op) =20 #endif =20 -bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - -#ifdef CONFIG_USER_ONLY - cpu->env.exception.vaddress =3D address; - if (access_type =3D=3D MMU_INST_FETCH) { - cs->exception_index =3D EXCP_PREFETCH_ABORT; - } else { - cs->exception_index =3D EXCP_DATA_ABORT; - } - cpu_loop_exit_restore(cs, retaddr); -#else - hwaddr phys_addr; - target_ulong page_size; - int prot, ret; - MemTxAttrs attrs =3D {}; - ARMMMUFaultInfo fi =3D {}; - - /* - * Walk the page table and (if the mapping exists) add the page - * to the TLB. On success, return true. Otherwise, if probing, - * return false. Otherwise populate fsr with ARM DFSR/IFSR fault - * register format, and signal the fault. - */ - ret =3D get_phys_addr(&cpu->env, address, access_type, - core_to_arm_mmu_idx(&cpu->env, mmu_idx), - &phys_addr, &attrs, &prot, &page_size, &fi, NULL); - if (likely(!ret)) { - /* - * Map a single [sub]page. Regions smaller than our declared - * target page size are handled specially, so for those we - * pass in the exact addresses. - */ - if (page_size >=3D TARGET_PAGE_SIZE) { - phys_addr &=3D TARGET_PAGE_MASK; - address &=3D TARGET_PAGE_MASK; - } - tlb_set_page_with_attrs(cs, address, phys_addr, attrs, - prot, mmu_idx, page_size); - return true; - } else if (probe) { - return false; - } else { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); - } -#endif -} - /* Note that signed overflow is undefined in C. The following routines are careful to use unsigned types where modulo arithmetic is required. Failure to do so _will_ break on newer gcc. */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 7c835d3ce77..9850993c114 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -88,141 +88,6 @@ uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, = void *vn, return val; } =20 -#if !defined(CONFIG_USER_ONLY) - -static inline uint32_t merge_syn_data_abort(uint32_t template_syn, - unsigned int target_el, - bool same_el, bool ea, - bool s1ptw, bool is_write, - int fsc) -{ - uint32_t syn; - - /* - * ISV is only set for data aborts routed to EL2 and - * never for stage-1 page table walks faulting on stage 2. - * - * Furthermore, ISV is only set for certain kinds of load/stores. - * If the template syndrome does not have ISV set, we should leave - * it cleared. - * - * See ARMv8 specs, D7-1974: - * ISS encoding for an exception from a Data Abort, the - * ISV field. - */ - if (!(template_syn & ARM_EL_ISV) || target_el !=3D 2 || s1ptw) { - syn =3D syn_data_abort_no_iss(same_el, - ea, 0, s1ptw, is_write, fsc); - } else { - /* - * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template - * syndrome created at translation time. - * Now we create the runtime syndrome with the remaining fields. - */ - syn =3D syn_data_abort_with_iss(same_el, - 0, 0, 0, 0, 0, - ea, 0, s1ptw, is_write, fsc, - false); - /* Merge the runtime syndrome with the template syndrome. */ - syn |=3D template_syn; - } - return syn; -} - -void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, - int mmu_idx, ARMMMUFaultInfo *fi) -{ - CPUARMState *env =3D &cpu->env; - int target_el; - bool same_el; - uint32_t syn, exc, fsr, fsc; - ARMMMUIdx arm_mmu_idx =3D core_to_arm_mmu_idx(env, mmu_idx); - - target_el =3D exception_target_el(env); - if (fi->stage2) { - target_el =3D 2; - env->cp15.hpfar_el2 =3D extract64(fi->s2addr, 12, 47) << 4; - } - same_el =3D (arm_current_el(env) =3D=3D target_el); - - if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el) || - arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { - /* - * LPAE format fault status register : bottom 6 bits are - * status code in the same form as needed for syndrome - */ - fsr =3D arm_fi_to_lfsc(fi); - fsc =3D extract32(fsr, 0, 6); - } else { - fsr =3D arm_fi_to_sfsc(fi); - /* - * Short format FSR : this fault will never actually be reported - * to an EL that uses a syndrome register. Use a (currently) - * reserved FSR code in case the constructed syndrome does leak - * into the guest somehow. - */ - fsc =3D 0x3f; - } - - if (access_type =3D=3D MMU_INST_FETCH) { - syn =3D syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); - exc =3D EXCP_PREFETCH_ABORT; - } else { - syn =3D merge_syn_data_abort(env->exception.syndrome, target_el, - same_el, fi->ea, fi->s1ptw, - access_type =3D=3D MMU_DATA_STORE, - fsc); - if (access_type =3D=3D MMU_DATA_STORE - && arm_feature(env, ARM_FEATURE_V6)) { - fsr |=3D (1 << 11); - } - exc =3D EXCP_DATA_ABORT; - } - - env->exception.vaddress =3D addr; - env->exception.fsr =3D fsr; - raise_exception(env, exc, syn, target_el); -} - -/* Raise a data fault alignment exception for the specified virtual addres= s */ -void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - ARMMMUFaultInfo fi =3D {}; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - - fi.type =3D ARMFault_Alignment; - arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); -} - -/* - * arm_cpu_do_transaction_failed: handle a memory system error response - * (eg "no device/memory present at address") by raising an external abort - * exception - */ -void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retaddr) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - ARMMMUFaultInfo fi =3D {}; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - - fi.ea =3D arm_extabort_type(response); - fi.type =3D ARMFault_SyncExternal; - arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); -} - -#endif /* !defined(CONFIG_USER_ONLY) */ - void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue) { /* diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c new file mode 100644 index 00000000000..5feb3129417 --- /dev/null +++ b/target/arm/tlb_helper.c @@ -0,0 +1,200 @@ +/* + * ARM TLB (Translation lookaside buffer) helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" + +#if !defined(CONFIG_USER_ONLY) + +static inline uint32_t merge_syn_data_abort(uint32_t template_syn, + unsigned int target_el, + bool same_el, bool ea, + bool s1ptw, bool is_write, + int fsc) +{ + uint32_t syn; + + /* + * ISV is only set for data aborts routed to EL2 and + * never for stage-1 page table walks faulting on stage 2. + * + * Furthermore, ISV is only set for certain kinds of load/stores. + * If the template syndrome does not have ISV set, we should leave + * it cleared. + * + * See ARMv8 specs, D7-1974: + * ISS encoding for an exception from a Data Abort, the + * ISV field. + */ + if (!(template_syn & ARM_EL_ISV) || target_el !=3D 2 || s1ptw) { + syn =3D syn_data_abort_no_iss(same_el, + ea, 0, s1ptw, is_write, fsc); + } else { + /* + * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template + * syndrome created at translation time. + * Now we create the runtime syndrome with the remaining fields. + */ + syn =3D syn_data_abort_with_iss(same_el, + 0, 0, 0, 0, 0, + ea, 0, s1ptw, is_write, fsc, + false); + /* Merge the runtime syndrome with the template syndrome. */ + syn |=3D template_syn; + } + return syn; +} + +static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *= fi) +{ + CPUARMState *env =3D &cpu->env; + int target_el; + bool same_el; + uint32_t syn, exc, fsr, fsc; + ARMMMUIdx arm_mmu_idx =3D core_to_arm_mmu_idx(env, mmu_idx); + + target_el =3D exception_target_el(env); + if (fi->stage2) { + target_el =3D 2; + env->cp15.hpfar_el2 =3D extract64(fi->s2addr, 12, 47) << 4; + } + same_el =3D (arm_current_el(env) =3D=3D target_el); + + if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el) || + arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { + /* + * LPAE format fault status register : bottom 6 bits are + * status code in the same form as needed for syndrome + */ + fsr =3D arm_fi_to_lfsc(fi); + fsc =3D extract32(fsr, 0, 6); + } else { + fsr =3D arm_fi_to_sfsc(fi); + /* + * Short format FSR : this fault will never actually be reported + * to an EL that uses a syndrome register. Use a (currently) + * reserved FSR code in case the constructed syndrome does leak + * into the guest somehow. + */ + fsc =3D 0x3f; + } + + if (access_type =3D=3D MMU_INST_FETCH) { + syn =3D syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); + exc =3D EXCP_PREFETCH_ABORT; + } else { + syn =3D merge_syn_data_abort(env->exception.syndrome, target_el, + same_el, fi->ea, fi->s1ptw, + access_type =3D=3D MMU_DATA_STORE, + fsc); + if (access_type =3D=3D MMU_DATA_STORE + && arm_feature(env, ARM_FEATURE_V6)) { + fsr |=3D (1 << 11); + } + exc =3D EXCP_DATA_ABORT; + } + + env->exception.vaddress =3D addr; + env->exception.fsr =3D fsr; + raise_exception(env, exc, syn, target_el); +} + +/* Raise a data fault alignment exception for the specified virtual addres= s */ +void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + ARMMMUFaultInfo fi =3D {}; + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + + fi.type =3D ARMFault_Alignment; + arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); +} + +/* + * arm_cpu_do_transaction_failed: handle a memory system error response + * (eg "no device/memory present at address") by raising an external abort + * exception + */ +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + ARMMMUFaultInfo fi =3D {}; + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + + fi.ea =3D arm_extabort_type(response); + fi.type =3D ARMFault_SyncExternal; + arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); +} + +#endif /* !defined(CONFIG_USER_ONLY) */ + +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + +#ifdef CONFIG_USER_ONLY + cpu->env.exception.vaddress =3D address; + if (access_type =3D=3D MMU_INST_FETCH) { + cs->exception_index =3D EXCP_PREFETCH_ABORT; + } else { + cs->exception_index =3D EXCP_DATA_ABORT; + } + cpu_loop_exit_restore(cs, retaddr); +#else + hwaddr phys_addr; + target_ulong page_size; + int prot, ret; + MemTxAttrs attrs =3D {}; + ARMMMUFaultInfo fi =3D {}; + + /* + * Walk the page table and (if the mapping exists) add the page + * to the TLB. On success, return true. Otherwise, if probing, + * return false. Otherwise populate fsr with ARM DFSR/IFSR fault + * register format, and signal the fault. + */ + ret =3D get_phys_addr(&cpu->env, address, access_type, + core_to_arm_mmu_idx(&cpu->env, mmu_idx), + &phys_addr, &attrs, &prot, &page_size, &fi, NULL); + if (likely(!ret)) { + /* + * Map a single [sub]page. Regions smaller than our declared + * target page size are handled specially, so for those we + * pass in the exact addresses. + */ + if (page_size >=3D TARGET_PAGE_SIZE) { + phys_addr &=3D TARGET_PAGE_MASK; + address &=3D TARGET_PAGE_MASK; + } + tlb_set_page_with_attrs(cs, address, phys_addr, attrs, + prot, mmu_idx, page_size); + return true; + } else if (probe) { + return false; + } else { + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); + } +#endif +} --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562033440; cv=none; d=zoho.com; s=zohoarc; b=DLXoITFRnQyTrqjoJoUfl5XB+mLnYbOhO05kaYM64PiQsJfdG8VDdyWuGClAJQC79JOFqRAHwyza5HUSjjrX5F3KPXIz+EO5GJusct+/UxKbN00JbMTxzlg70AMq508hlvcOj+5a0dM8zw2bVUT18fzXmRfL3ENOobW3iMVCy5U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562033440; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=WdrDS78k3n12ZSXX1AYlSfN84PXvZ6CqEJ/pNp8N1Lo=; b=REUdIG/Exb4g9ni9k9DODsBqeo4vOB9p9SamdLfAqjrVa/KGJb9AP+kKLNuVUAaDm+AkR9hSvyN/Rk52psWLg8Q6dJFHoPl4bQTtjR8TUI9XvCC+A41rGG9NEhRONG1styBNlcLYZ8keR4/t9VivXusqYL8FgIqpQa57xQrnPfQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562033440474733.148929280195; Mon, 1 Jul 2019 19:10:40 -0700 (PDT) Received: from localhost ([::1]:47132 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi8Fh-0000ql-Fv for importer@patchew.org; Mon, 01 Jul 2019 22:10:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56964) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4RQ-0008PJ-Mt for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:06:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi4RP-0001kI-Gf for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:06:28 -0400 Received: from mail-wm1-f41.google.com ([209.85.128.41]:36806) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi4RJ-0001is-R3 for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:06:24 -0400 Received: by mail-wm1-f41.google.com with SMTP id u8so1110767wmm.1 for ; Mon, 01 Jul 2019 15:06:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.29 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WdrDS78k3n12ZSXX1AYlSfN84PXvZ6CqEJ/pNp8N1Lo=; b=xATTY6qFMeTxMqbBSLMEYuA9m2aRkKBCe89ww9WotIcH6/VDfYhg3LThhEGqWqcmXf Fy/rnfodvLDO0rb8WMdkkFBLo3AHD1HmihvRwgHUWEThMxbtDobGzNlPjxLzkMzm+csb nyv92t26wbaiZCpbCq7GHr1zguYVhzsiuaOdJmoA2VytC1iS7pTNMB7x0TjTv3IlGn4T f2OPh7O8+JN9MBgfh/tv5pw0x6Hhkih+Lruv3FFoCpDa3tD28D+5Fies72xgM01lZ1rl l2Du04elFue/gvn8C1+7wGEqWAwC3R0ZbDOkwGYcIsmqvml4fZpWecH2WevO+aJ+t1Km RYcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WdrDS78k3n12ZSXX1AYlSfN84PXvZ6CqEJ/pNp8N1Lo=; b=NRRemThgPbYEsTTwnvd2HBGFwqRCZD6hec+y2V/vOcWUiGXnXUVb4Jxtp+kpTjLdp3 XMDccSKxoMFRXVQJI9ZxKHLrZcLYbUmrdqcVv76C65Ba3PbKnn9wquJpuHtSkzefbMCt MmQNbFSJb6pwfA6EFBX+ejKxJ+oTLVqgbF40n1vbw0woKhP2YX4FQ1NluuUeYwUZmBt4 wUS9V4eS3dBwYQyYbQC0t6HWZi+SnPmA7gZ+70SU1pDFeeGSwdnbebg4LrQyQX2VU6W9 Pw6hKX/dQSgUKG/HIONFkNq6ZoI+5c6m8K3gXkJ8rZ5jfhpf30N3QyZUJIzTgSeonSM7 ku3Q== X-Gm-Message-State: APjAAAVCycRmNvePRFhN1tgbvMuVKxn2b4q4wCi4IPSpoYNehpCP4fEc L3JhW0E5JQ8i72aAxVLg1A+Hcbn8KPU3Hg== X-Google-Smtp-Source: APXvYqzjwVc5DWrrHizc9O3RjJHKZSyeQ+n/oxtgmPcP64AAC+7FXXT4dGpKuEAY70ml5GbJIrYjZw== X-Received: by 2002:a7b:ce01:: with SMTP id m1mr123227wmc.1.1561999230410; Mon, 01 Jul 2019 09:40:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:37 +0100 Message-Id: <20190701163943.22313-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.41 Subject: [Qemu-devel] [PULL 40/46] target/arm/vfp_helper: Move code around X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 To ease the review of the next commit, move the vfp_exceptbits_to_host() function directly after vfp_exceptbits_from_host(). Amusingly the diff shows we are moving vfp_get_fpscr(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-15-philmd@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/vfp_helper.c | 52 ++++++++++++++++++++--------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 121bdbd3aff..d54e3253240 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -55,32 +55,6 @@ static inline int vfp_exceptbits_from_host(int host_bits) return target_bits; } =20 -uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) -{ - uint32_t i, fpscr; - - fpscr =3D env->vfp.xregs[ARM_VFP_FPSCR] - | (env->vfp.vec_len << 16) - | (env->vfp.vec_stride << 20); - - i =3D get_float_exception_flags(&env->vfp.fp_status); - i |=3D get_float_exception_flags(&env->vfp.standard_fp_status); - /* FZ16 does not generate an input denormal exception. */ - i |=3D (get_float_exception_flags(&env->vfp.fp_status_f16) - & ~float_flag_input_denormal); - fpscr |=3D vfp_exceptbits_from_host(i); - - i =3D env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3= ]; - fpscr |=3D i ? FPCR_QC : 0; - - return fpscr; -} - -uint32_t vfp_get_fpscr(CPUARMState *env) -{ - return HELPER(vfp_get_fpscr)(env); -} - /* Convert vfp exception flags to target form. */ static inline int vfp_exceptbits_to_host(int target_bits) { @@ -107,6 +81,32 @@ static inline int vfp_exceptbits_to_host(int target_bit= s) return host_bits; } =20 +uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) +{ + uint32_t i, fpscr; + + fpscr =3D env->vfp.xregs[ARM_VFP_FPSCR] + | (env->vfp.vec_len << 16) + | (env->vfp.vec_stride << 20); + + i =3D get_float_exception_flags(&env->vfp.fp_status); + i |=3D get_float_exception_flags(&env->vfp.standard_fp_status); + /* FZ16 does not generate an input denormal exception. */ + i |=3D (get_float_exception_flags(&env->vfp.fp_status_f16) + & ~float_flag_input_denormal); + fpscr |=3D vfp_exceptbits_from_host(i); + + i =3D env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3= ]; + fpscr |=3D i ? FPCR_QC : 0; + + return fpscr; +} + +uint32_t vfp_get_fpscr(CPUARMState *env) +{ + return HELPER(vfp_get_fpscr)(env); +} + void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { int i; --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562034050; cv=none; d=zoho.com; s=zohoarc; b=AL9jmxYJ7+lZN1SuZKYfGPMbqleRZ5W2MMW8YV+XSWnRG4kniOhtSgJ125uaWD7NEXH3y4Ia3HuBhXVVyDRzosZ56YZgh6Q0BcBsHdbL6m31LztUJ38EaQj2KiN41Etfve8syQHIlBEZpeuE1ozyW1umxfgrHYlWw6r1jOOnhTs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562034050; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ZMrqkHkBcxi0ttxgCOY8UHzzFSmivWvG6v3OYeb/MfM=; b=X3Zis9eSsQ/jXsC5nuHL+xsRxLcmoX+z1wmM1BJaIuwPOAyLM77XOSJbujODLPbKN0F52MiQ+PkbWbyYYlsCbHSsl0w+4EMLuPAvcKWV94XLuyC5ww5BIOXEfmyF7vunB7xRM05oJvv/jm+nVRhuLudF24iJaXeR/yxyVPMPSU4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562034050221357.0999371314575; Mon, 1 Jul 2019 19:20:50 -0700 (PDT) Received: from localhost ([::1]:47188 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi8PW-0006eG-4Q for importer@patchew.org; Mon, 01 Jul 2019 22:20:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60212) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4fA-0001jQ-KX for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:20:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi4f6-0005ah-RF for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:20:38 -0400 Received: from mail-wm1-f41.google.com ([209.85.128.41]:36713) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi4f5-0005Oj-9C for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:20:36 -0400 Received: by mail-wm1-f41.google.com with SMTP id u8so1136707wmm.1 for ; Mon, 01 Jul 2019 15:20:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.30 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZMrqkHkBcxi0ttxgCOY8UHzzFSmivWvG6v3OYeb/MfM=; b=psNUuIlaJiNnRjrcJvR6FYbx9Q+lXkqw9w60Qr2zvsK/kpaaljXSX2uKaW+lWHai/v 1LlyBTmYCH53gjVituGG204mtGiSiG05QEGWHULVZcLOY5hYQTOzhU/StnY1z1OAg1/K lKOpMSB7xOhr02TZp/2FDNmU8kE8YVgCbjvAQm894KqoobgpoGed53qS8OpxSP74jEmU PT/Cot+jUY8I7oyKBF/b3L0Dzn4L3ILFHFiAzaZpBSVn4arHjPz59HUaOuDnyoLj1CzT DO+8tMh4G2L1mpTnLvbiHKMbzU+/FQMrewBN5yA8Dh7U1xq5Eq5M8U8G6srkOIsHl7az osSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZMrqkHkBcxi0ttxgCOY8UHzzFSmivWvG6v3OYeb/MfM=; b=cwF2dAMW/UCOM0/601k0HrC27hQ05rbD01WEu9gf5giZcEZWeKgd+lqYgWmtF3bsE9 nfc62o9rudQ9UXx2Da0scAGPHz5NxjwqFyN8+4dSVPNfmRXba1orCgmd+Y8Dhb8cgPkK xylsKSBBaA+h3SLszgASXQe35TqLpoDR5fU2KOkEnatW2xIdS4hk/ENsz+4JWSYZP03v huE7NRg0AXwS3KzgEqKJcYaFnOPav9Zy6MCr2fjvbEf/oxLmbSWmjuQb+L3C5GzU34Di nyJI2VroiB/G46GetrJIAg5K+vTGC4hPGe5buB4FNzF51z/ErVRwfmUlqsrqXiPPz3Jl 8mpg== X-Gm-Message-State: APjAAAVTUVbZG6/NuqCJAjSyzvIhmUJoZKJ0AJdpPPsPLv1tJHqu//xq CBVZgT9cT4TUGLx6GArweCX3Y7b24wk8Ag== X-Google-Smtp-Source: APXvYqx23JurnM+ro/0QqE+Fix2mx14PhNMapJnEhNTEbXDFEkfIcz8Fq93eyUBKtDByF9QRP/xAeA== X-Received: by 2002:a1c:e108:: with SMTP id y8mr114068wmg.65.1561999231515; Mon, 01 Jul 2019 09:40:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:38 +0100 Message-Id: <20190701163943.22313-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.41 Subject: [Qemu-devel] [PULL 41/46] target/arm/vfp_helper: Extract vfp_set_fpscr_to_host() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 The vfp_set_fpscr() helper contains code specific to the host floating point implementation (here the SoftFloat library). Extract this code to vfp_set_fpscr_to_host(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-16-philmd@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/vfp_helper.c | 127 +++++++++++++++++++++------------------- 1 file changed, 66 insertions(+), 61 deletions(-) diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index d54e3253240..b19a395b67d 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -81,71 +81,11 @@ static inline int vfp_exceptbits_to_host(int target_bit= s) return host_bits; } =20 -uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) -{ - uint32_t i, fpscr; - - fpscr =3D env->vfp.xregs[ARM_VFP_FPSCR] - | (env->vfp.vec_len << 16) - | (env->vfp.vec_stride << 20); - - i =3D get_float_exception_flags(&env->vfp.fp_status); - i |=3D get_float_exception_flags(&env->vfp.standard_fp_status); - /* FZ16 does not generate an input denormal exception. */ - i |=3D (get_float_exception_flags(&env->vfp.fp_status_f16) - & ~float_flag_input_denormal); - fpscr |=3D vfp_exceptbits_from_host(i); - - i =3D env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3= ]; - fpscr |=3D i ? FPCR_QC : 0; - - return fpscr; -} - -uint32_t vfp_get_fpscr(CPUARMState *env) -{ - return HELPER(vfp_get_fpscr)(env); -} - -void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) +static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val) { int i; uint32_t changed =3D env->vfp.xregs[ARM_VFP_FPSCR]; =20 - /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) { - val &=3D ~FPCR_FZ16; - } - - if (arm_feature(env, ARM_FEATURE_M)) { - /* - * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits - * and also for the trapped-exception-handling bits IxE. - */ - val &=3D 0xf7c0009f; - } - - /* - * We don't implement trapped exception handling, so the - * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) - * - * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC - * (which are stored in fp_status), and the other RES0 bits - * in between, then we clear all of the low 16 bits. - */ - env->vfp.xregs[ARM_VFP_FPSCR] =3D val & 0xf7c80000; - env->vfp.vec_len =3D (val >> 16) & 7; - env->vfp.vec_stride =3D (val >> 20) & 3; - - /* - * The bit we set within fpscr_q is arbitrary; the register as a - * whole being zero/non-zero is what counts. - */ - env->vfp.qc[0] =3D val & FPCR_QC; - env->vfp.qc[1] =3D 0; - env->vfp.qc[2] =3D 0; - env->vfp.qc[3] =3D 0; - changed ^=3D val; if (changed & (3 << 22)) { i =3D (val >> 22) & 3; @@ -193,6 +133,71 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t = val) set_float_exception_flags(0, &env->vfp.standard_fp_status); } =20 +uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) +{ + uint32_t i, fpscr; + + fpscr =3D env->vfp.xregs[ARM_VFP_FPSCR] + | (env->vfp.vec_len << 16) + | (env->vfp.vec_stride << 20); + + i =3D get_float_exception_flags(&env->vfp.fp_status); + i |=3D get_float_exception_flags(&env->vfp.standard_fp_status); + /* FZ16 does not generate an input denormal exception. */ + i |=3D (get_float_exception_flags(&env->vfp.fp_status_f16) + & ~float_flag_input_denormal); + fpscr |=3D vfp_exceptbits_from_host(i); + + i =3D env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3= ]; + fpscr |=3D i ? FPCR_QC : 0; + + return fpscr; +} + +uint32_t vfp_get_fpscr(CPUARMState *env) +{ + return HELPER(vfp_get_fpscr)(env); +} + +void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) +{ + /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ + if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) { + val &=3D ~FPCR_FZ16; + } + + if (arm_feature(env, ARM_FEATURE_M)) { + /* + * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits + * and also for the trapped-exception-handling bits IxE. + */ + val &=3D 0xf7c0009f; + } + + /* + * We don't implement trapped exception handling, so the + * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) + * + * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC + * (which are stored in fp_status), and the other RES0 bits + * in between, then we clear all of the low 16 bits. + */ + env->vfp.xregs[ARM_VFP_FPSCR] =3D val & 0xf7c80000; + env->vfp.vec_len =3D (val >> 16) & 7; + env->vfp.vec_stride =3D (val >> 20) & 3; + + /* + * The bit we set within fpscr_q is arbitrary; the register as a + * whole being zero/non-zero is what counts. + */ + env->vfp.qc[0] =3D val & FPCR_QC; + env->vfp.qc[1] =3D 0; + env->vfp.qc[2] =3D 0; + env->vfp.qc[3] =3D 0; + + vfp_set_fpscr_to_host(env, val); +} + void vfp_set_fpscr(CPUARMState *env, uint32_t val) { HELPER(vfp_set_fpscr)(env, val); --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562034299; cv=none; d=zoho.com; s=zohoarc; b=jwjBsfegtuilAuU1o0gZD16tDTelHYAUCIf+TKgDj864CDEemAJ4gR8XYFYmIdkQhnTCnOaVsrHYonv9P5cSEjIUywaPF3TkE3lKnnPszCMnMUvCBCHVatntBe14zN5Wbq0hDv73pbGtGbxQbRoxQPYnijdFx0KSssslAfaeF5o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562034299; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=sPbsb4f0JFD9WjkRWgwBp1rhSrFIRCwYdPeLnHu8nlU=; b=aojCbHEps/rPz4wa5qU0/lFdfHQGN2MG2uK6888ESH2iyGOkA6t6P8QrlFlIA8LJuMYOHzyIaUY4JNlVPrbDHJEOMS2xi219SsuNn7661yU/SYiincNdUIJyCcFL87K0peWcCqMSVod9WjXLDfcKwvJgO8MRqv7E13+lDqvBPxI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562034299879269.4540374901551; Mon, 1 Jul 2019 19:24:59 -0700 (PDT) Received: from localhost ([::1]:47234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi8TY-0002b2-Rs for importer@patchew.org; Mon, 01 Jul 2019 22:24:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56447) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4PM-0006p1-0W for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:04:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi4PI-00017j-1d for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:04:18 -0400 Received: from mail-wr1-f49.google.com ([209.85.221.49]:44121) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi4PE-00014B-8I for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:04:14 -0400 Received: by mail-wr1-f49.google.com with SMTP id e3so5903288wrs.11 for ; Mon, 01 Jul 2019 15:04:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.31 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sPbsb4f0JFD9WjkRWgwBp1rhSrFIRCwYdPeLnHu8nlU=; b=fQG36OmneOJ9jlAXGyPQbqVNcTTRlBazSOwtcCEZUf5RMrbY84c0kYPdTYmDpduFsd TA+0NMURBn0RHKtIgTnRRVHbqQG+3edeYPSnQiOIZKR/DazbD5vpKJQQBuk86o2r186r mZc9Kx+PeS7m9B4DujbjeybhpvfF9QfO78Pj9t6CkHZchQ7jiwSIm+xf+OgH/95fCglu 67OkMiKOEdLT+Vmqt+d9ANhemHbUg5A+YDWXvzY1BenenVSwu4dUoqjVCzd43HKhx6vw beNpuM+Z5eD/5k8OFxzef1PREkkj64BlprWbOihz8PYNYRzYCVnfzdmtXOmNdxIBLodd MAYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sPbsb4f0JFD9WjkRWgwBp1rhSrFIRCwYdPeLnHu8nlU=; b=IUbtGFafgJyQ/gA9A/YqOJ82+MFxxavs8X6835FmBvjfM22rmzTqe1SYYm+ZiJUqI+ FVFBHXnAd25LUt6r+FS5bwRsAwFRL77Ubk7POxfw1i8s09omRHvMosdB7kq6kmI3M9um 28N3BTl4RKaGRaSQLwapYobKujN27+vcz5u6D+AyoL3JJHhsXgHSNGnA4efOpPd0xDKm JnFz5VrlrfeIhtWvyX8Yu0JSwHorLFOaayCpBdOAIbJaZVmSrrJLjT4pi9i1W2wUudHi Om91xN4lr93dR019edr2agthWWFruZyed7Sub2065RuJNX1rS4Is8pwBXDFez7fzOXtl gGag== X-Gm-Message-State: APjAAAUcN7Jwov+WpPrKA/qRqkLqFvx1gip4io2t2L7naVz3sh5AraSl 9fEOZLsj58OSnfbA+lXuTD6iT/C4+PTBXg== X-Google-Smtp-Source: APXvYqzVYyDLS7q1BUpVlT1//XpSKpV1y5lIlzA7o0sV2Yh001mjPLCSCCyKIS0CPn/a7mBehSHPDg== X-Received: by 2002:adf:de90:: with SMTP id w16mr19401268wrl.217.1561999232428; Mon, 01 Jul 2019 09:40:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:39 +0100 Message-Id: <20190701163943.22313-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.49 Subject: [Qemu-devel] [PULL 42/46] target/arm/vfp_helper: Extract vfp_set_fpscr_from_host() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 The vfp_set_fpscr() helper contains code specific to the host floating point implementation (here the SoftFloat library). Extract this code to vfp_set_fpscr_from_host(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-17-philmd@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/vfp_helper.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index b19a395b67d..838f7d25fd1 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -81,6 +81,18 @@ static inline int vfp_exceptbits_to_host(int target_bits) return host_bits; } =20 +static uint32_t vfp_get_fpscr_from_host(CPUARMState *env) +{ + uint32_t i; + + i =3D get_float_exception_flags(&env->vfp.fp_status); + i |=3D get_float_exception_flags(&env->vfp.standard_fp_status); + /* FZ16 does not generate an input denormal exception. */ + i |=3D (get_float_exception_flags(&env->vfp.fp_status_f16) + & ~float_flag_input_denormal); + return vfp_exceptbits_from_host(i); +} + static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val) { int i; @@ -141,12 +153,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) | (env->vfp.vec_len << 16) | (env->vfp.vec_stride << 20); =20 - i =3D get_float_exception_flags(&env->vfp.fp_status); - i |=3D get_float_exception_flags(&env->vfp.standard_fp_status); - /* FZ16 does not generate an input denormal exception. */ - i |=3D (get_float_exception_flags(&env->vfp.fp_status_f16) - & ~float_flag_input_denormal); - fpscr |=3D vfp_exceptbits_from_host(i); + fpscr |=3D vfp_get_fpscr_from_host(env); =20 i =3D env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3= ]; fpscr |=3D i ? FPCR_QC : 0; --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562031866; cv=none; d=zoho.com; s=zohoarc; b=cD2r4raKfZ7WlDSqir5jhXUQ5ZdfX+Aw6ZqEaRPw9RyGRto1rYeK+X/mcga7VTM4DDfc2msBMqh6tzzbzs17dOE0aEAdzrElepTXMwgsKhSBVUInoPuAxZQ0fTegFqIENVU8C2kh/uyrGLpLCge9NQJAR/P8J7nKUcAX6dZqc1c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562031866; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=yx5elbyAko/ok2mgqRgnOYZgmbIkaCHz6sv2gkqMUnQ=; b=lwk1TNrd0JTPBVPXc0RLGL9pZIhHOp+fCa9jrcS87I4B3b+UiFRyJGH6jb3EfFzz+ibu/Bu6JZGXoTmOSTIfgJfJrSwJevTSnRtaMXfkzlu8KB8t0AAo01yhbeR9ybwq4D+a9dk7xCGZRW5qQFh/f6KFY4TESppwr9wudSs2CIU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562031866574772.110587857473; Mon, 1 Jul 2019 18:44:26 -0700 (PDT) Received: from localhost ([::1]:47000 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi7qL-00075p-K0 for importer@patchew.org; Mon, 01 Jul 2019 21:44:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60156) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4em-0001Ue-5V for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:20:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi4ek-0005MP-Cf for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:20:16 -0400 Received: from mail-wm1-f53.google.com ([209.85.128.53]:37001) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi4ei-0005Hf-JU for qemu-devel@nongnu.org; Mon, 01 Jul 2019 18:20:13 -0400 Received: by mail-wm1-f53.google.com with SMTP id f17so1129183wme.2 for ; Mon, 01 Jul 2019 15:20:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.32 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=yx5elbyAko/ok2mgqRgnOYZgmbIkaCHz6sv2gkqMUnQ=; b=DwQ7cjEvuwHzPLz1S92z+87NLUwZx1ditwsqjHRgP6HcTU0dP1YdTc0t2ECKQyE2i+ auFdO4j8TEtHAvBdBGk8qldaxCNsX15/2fPCzRL3rAn5aPWFhTp4RzPEpWu06266ArMs 9LJFq1h1pxZ6+NE/Tm/apm32iS5tWg1OqEYllUp7iW4QDFrV8CsGf6+h/nWUXIVaVlvz cP0Zt8wsKvHM4ZBUoqZJ0SjXMxHtfplAuvmHc2BJKKPaWeeQee6j7IqJUonSphX6ETXg PjoTnHRq9iwa2/11SyeRmmYfLEEJF1BL43YTs7tNkvNLIBeX4UzqbDm2ebpdB4CVdQzO Rmzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yx5elbyAko/ok2mgqRgnOYZgmbIkaCHz6sv2gkqMUnQ=; b=CTSwKdaZOhJV5u7x+aEZ46ijCt5Ub7f+ZSUmKQ2bOK43hq2FbGb/IUTrtBdZm5ahrn +EbOAhgbrx9YiFihfMLOeM7g2CNvAUFhCSdow+iwdTXXszvHSLP4BiRGiMHQIUhL52An KpUnJBaUCJlEYyCfnrNQ9dr/YzUVeTY4Uou0Rw1V0mgbWIQ6IUW0G2L7I1IehT1/kE2P cXLcPoVUq5LngJEwdcBbviPXLD4DrIYhvsIZ3V+rXVsgfu3it7Ly5keq9wnCtwEsqm3a LSi/ZW9ceuGidPEScPoFKY+gVC6TszH9XtAuvzgy5EbM331L/JcytjMVGAJGR6wAx/w+ MKHg== X-Gm-Message-State: APjAAAVNRwyhpMvVGA06N91WpVzyoKSTcdNDMfzazv40PrpyXjrIokU7 Ag2EuFi1S8pufhxl7hcRl9Lf5SGMFZkrtg== X-Google-Smtp-Source: APXvYqww1E6PINnRZDFmi0gd2QADyGUzZ3omjPmQUnKNtWvws9nNE+UXHnrxl8pibeDGqmlrfAqkEQ== X-Received: by 2002:a1c:1a06:: with SMTP id a6mr130999wma.128.1561999233407; Mon, 01 Jul 2019 09:40:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:40 +0100 Message-Id: <20190701163943.22313-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.53 Subject: [Qemu-devel] [PULL 43/46] target/arm/vfp_helper: Restrict the SoftFloat use to TCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 This code is specific to the SoftFloat floating-point implementation, which is only used by TCG. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-18-philmd@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/vfp_helper.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 838f7d25fd1..46041e32949 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -18,17 +18,20 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "fpu/softfloat.h" #include "internals.h" - +#ifdef CONFIG_TCG +#include "qemu/log.h" +#include "fpu/softfloat.h" +#endif =20 /* VFP support. We follow the convention used for VFP instructions: Single precision routines have a "s" suffix, double precision a "d" suffix. */ =20 +#ifdef CONFIG_TCG + /* Convert host exception flags to vfp form. */ static inline int vfp_exceptbits_from_host(int host_bits) { @@ -145,6 +148,19 @@ static void vfp_set_fpscr_to_host(CPUARMState *env, ui= nt32_t val) set_float_exception_flags(0, &env->vfp.standard_fp_status); } =20 +#else + +static uint32_t vfp_get_fpscr_from_host(CPUARMState *env) +{ + return 0; +} + +static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val) +{ +} + +#endif + uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) { uint32_t i, fpscr; @@ -210,6 +226,8 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val) HELPER(vfp_set_fpscr)(env, val); } =20 +#ifdef CONFIG_TCG + #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) =20 #define VFP_BINOP(name) \ @@ -1303,3 +1321,5 @@ float64 HELPER(frint64_d)(float64 f, void *fpst) { return frint_d(f, fpst, 64); } + +#endif --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562021031; cv=none; d=zoho.com; s=zohoarc; b=eHQNYCigaBOtbcFTXiKGu/oLFEmAy87kDwLt1MmuOv3NIr/VMxNkxYFRh5B41lf8SBhPU5TDhXYnrl0IJby+oCGbQph7M12EK8tOazQJVUXTUyeZ41NekggruDVYGJCuVEM4pA1PSroL049sGAph9ppRLkntG7zPTGjqWrPmzWo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562021031; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=XcLWFdKkB/rUAkrzuf/RQAaPaI22ZL/bi/Hf38//vjk=; b=HxG+NqDKAJz6UHKjdCzBrVZrN85UKXPmM1+cgNyy6rMcDhmUOw1FmFW62fa2Wskac+heblsxGwYvDjNiobR/BDnSguRZC3HE7d7Ndw64KMkY8uD8uGd8TG5lfvMEsh2tf3W9EcRpNBw7qlyc/1mO0nGy+lbR8HCO9WoD/RW6PAk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562021031589933.3604735841539; Mon, 1 Jul 2019 15:43:51 -0700 (PDT) Received: from localhost ([::1]:46090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi51V-0006tf-9N for importer@patchew.org; Mon, 01 Jul 2019 18:43:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45879) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3P3-0001H0-IT for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:00:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3Oz-00086X-7O for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:59:54 -0400 Received: from mail-wm1-f52.google.com ([209.85.128.52]:51543) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3Ox-000728-Ve for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:59:52 -0400 Received: by mail-wm1-f52.google.com with SMTP id 207so847871wma.1 for ; Mon, 01 Jul 2019 13:58:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.33 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XcLWFdKkB/rUAkrzuf/RQAaPaI22ZL/bi/Hf38//vjk=; b=xfg4lYenWKCBHy7ePukdANVAbk1D+y8auxwxywxKbpsI6Zfn478I6fhU3RUYEjGEVZ cwcZEZPZJoMbnSalfkeL6GSYfX8B7RIs1jnLLpwZluXo7jXhqPOV1UmzO4pi/+03YqG/ lFO+0x5ltpJeYt9QHG7yq0BbDaLvvafbsdOY1JAXRI1UIrY4q2du3oAIIhxl+HKlE7Px +Cclxd+VtXVMxeYprcozfPNek8LY7MYcbbUC0vcGOHesMc0aSGMd4eIKAlt/5hzvWW0k BF7zPpgb10z59V/zvUQW2zY1k9a3Wf3toB+xMnS/pS6QeRhfQrPiZ5EQdLWy6Mb+cD+n rpkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XcLWFdKkB/rUAkrzuf/RQAaPaI22ZL/bi/Hf38//vjk=; b=B1lnuJ/4lFhT3cLcEKVNVj36vfXrPj9jmic+qPrgrkyZqIm476iqhxzQMf8JfeZN7b W1A18uYngyZ8kmma0mtwyhUsmnR+cutb5EGTGRHCFxIzoQIOot0K3AHcF5HHyez2DhkT 5LCDGQfEOWiIm/BAWQOrBzrfA03gYNANDeKUe5BWMs1ddWDtD9yyMd19LG9aoC+0rO/7 fssNcXEQL8O+c+AZ10f2NkFxS1dZtwBKIwq2L5Hq50q9UxaemnJF2Cy982eeDW+zmQeX NIuDPBJ4HWT7ly4cUner7KAsSOcQcPvBVI87a/xf6XXblHOtM4/TfEmL1RKAE7cuxCY4 pqug== X-Gm-Message-State: APjAAAVmt0N1V+PLPGzxjhY4ImG74XXhZICPDABDfD0IOaGz3PhH6MFB jq7BO2H0yQ7oXr/bkCc46AHAeIm6+dD95A== X-Google-Smtp-Source: APXvYqxnJwHbdfzH4lrHoepapVEo340M4TINf2VSH610Un69v+f5ePiplg7Ko8dJ75XZkgJUqKZT0Q== X-Received: by 2002:a7b:c774:: with SMTP id x20mr145125wmk.30.1561999234274; Mon, 01 Jul 2019 09:40:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:41 +0100 Message-Id: <20190701163943.22313-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.52 Subject: [Qemu-devel] [PULL 44/46] target/arm: Restrict PSCI to TCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Under KVM, the kernel gets the HVC call and handle the PSCI requests. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-20-philmd@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/internals.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 46a1313d69d..57e0253ef48 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -529,11 +529,15 @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vad= dr addr, int len); /* Callback function for when a watchpoint or breakpoint triggers. */ void arm_debug_excp_handler(CPUState *cs); =20 -#ifdef CONFIG_USER_ONLY +#if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG) static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) { return false; } +static inline void arm_handle_psci_call(ARMCPU *cpu) +{ + g_assert_not_reached(); +} #else /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI ca= ll. */ bool arm_is_psci_call(ARMCPU *cpu, int excp_type); --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562017825; cv=none; d=zoho.com; s=zohoarc; b=kdJGYN7bAntC0iDJuYqIKq2KxfuwmvUisfwwjD1XFsrFapwU5Ap36EjmIjYwcVhawHoakP6giu1yeL9K1iB8VcwPyGyUR5wmJYEL+U/azefMJFemYeB3FnlwcKKvPg+4o2wziI+gPNQTuBX/hVHJmSbYC54bQeI1fArKh7+gAiE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562017825; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=hbpFTS+wT4M13YQ/zISzNiEibHqtCKZT/nQxMRw1Pcg=; b=Pwhl2ojGtQkvwsEPCKtdYE5/uUeiUnX4aPq5qN0E2Jt8aISpCRuAuBs73SlttOFYjMgoaM/fP651BZjMk5haOXD2mNZqCTRyyjSO86OiFr4JZ9ZELUad7kt7qaeaC4CHGugYJ2TqI7HxZEyqjccwV+3KNSDQi66arHm8Awr6WE4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562017825050447.3559966116444; Mon, 1 Jul 2019 14:50:25 -0700 (PDT) Received: from localhost ([::1]:45796 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi4Br-0005VJ-K1 for importer@patchew.org; Mon, 01 Jul 2019 17:50:24 -0400 Received: from eggs.gnu.org ([209.51.188.92]:46823) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3HL-00044k-G9 for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:52:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3HH-00034y-Ic for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:51:57 -0400 Received: from mail-wr1-f44.google.com ([209.85.221.44]:34376) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hi3HF-000321-Sb for qemu-devel@nongnu.org; Mon, 01 Jul 2019 16:51:55 -0400 Received: by mail-wr1-f44.google.com with SMTP id u18so7121749wru.1 for ; Mon, 01 Jul 2019 13:51:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.34 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hbpFTS+wT4M13YQ/zISzNiEibHqtCKZT/nQxMRw1Pcg=; b=E1d+/6sSdVBAYdDzUpYiMSy4yFSMjeioFYXnlXj2QIRHJhhbw/Qo0o3g63tBGSnA0h vh+xpd4t0RUXpfD+63fEPEgEqgeSTeI/spqeYbBdSdx+DrgDlQnhbYiEscFpkWsOeDUn xp6h5HII2rvNIZdy9vFvndd4RkjGQHPNpRoWU8FZOt1DlZ+4UL2gC8b2xyv9enTs+oNv 4Dln8R3/wIeiSolYgYhDUlbNcyMUyZ+9+yTDne0tUeE96wpoxQw7G9NHZpcT8qiraqI9 Y4p6VmQ/VPba6mUDGjUoBT3nK5XyH5HyvDjj38BosLKwdZNIYSbYW8rI+Fqt8J0E5GSV 2UiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hbpFTS+wT4M13YQ/zISzNiEibHqtCKZT/nQxMRw1Pcg=; b=QZZ6nTIeqxRL3EJV7FXmkxdWzH8eE1YTbFu7tPcqIBXdpV1t/MbwcOKKqtMDxOFgl/ oJvZkgs+jODqvbUMOGZwywxb71r5oj1uVRwJxTmsVLTQM3PMGxAxD7A9CJ/Pp7fZqxUl VHr4glrh5SkXos92wewAzufeu9eLW7J8+IodWcFpr7vboE8kXKWQt3fVjzCLVrh7rS96 pLQaJj9FzUszRozMmBu30y9sDiSFSuOewRp0YIKfA+zn3mCY0vmAklBnIY4PROD7t5Lu O3tXKrtEBI/sycyvh5rBlFk5EmPBazVvIsqSzXKyqRJOv99iZEYI6zr0VBf9jknYPN2y SoVg== X-Gm-Message-State: APjAAAX8EwpDxrDhxvOMnGyfsjcDlsGm/b7MOC2UCM3KekdxuoWmVaYF HJCJgCZF4Bu7AjOUynuc5pIEWQHzh0UxTA== X-Google-Smtp-Source: APXvYqyjUQQAnp4H1fJsYyRMoCFKChwcphDr9xBcvLmRk9pamCIOzHeAbAaa08UTqylS+mS3y93qCg== X-Received: by 2002:adf:e947:: with SMTP id m7mr8962187wrn.123.1561999235176; Mon, 01 Jul 2019 09:40:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:42 +0100 Message-Id: <20190701163943.22313-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.44 Subject: [Qemu-devel] [PULL 45/46] target/arm: Declare arm_log_exception() function publicly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 In few commits we will split the M-profile functions from this file, and this function will also be called in the new file. Declare it in the "internals.h" header. Since it is in the middle of a block of M profile functions, move it previous to this block to ease the later refactor. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-21-philmd@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/internals.h | 2 ++ target/arm/helper.c | 76 +++++++++++++++++++++--------------------- 2 files changed, 40 insertions(+), 38 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 57e0253ef48..11bfdba5129 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1000,6 +1000,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); =20 +void arm_log_exception(int idx); + #endif /* !CONFIG_USER_ONLY */ =20 #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 4ef908c611e..dc880b4dabc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7695,6 +7695,44 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint3= 2_t excp_idx, return target_el; } =20 +void arm_log_exception(int idx) +{ + if (qemu_loglevel_mask(CPU_LOG_INT)) { + const char *exc =3D NULL; + static const char * const excnames[] =3D { + [EXCP_UDEF] =3D "Undefined Instruction", + [EXCP_SWI] =3D "SVC", + [EXCP_PREFETCH_ABORT] =3D "Prefetch Abort", + [EXCP_DATA_ABORT] =3D "Data Abort", + [EXCP_IRQ] =3D "IRQ", + [EXCP_FIQ] =3D "FIQ", + [EXCP_BKPT] =3D "Breakpoint", + [EXCP_EXCEPTION_EXIT] =3D "QEMU v7M exception exit", + [EXCP_KERNEL_TRAP] =3D "QEMU intercept of kernel commpage", + [EXCP_HVC] =3D "Hypervisor Call", + [EXCP_HYP_TRAP] =3D "Hypervisor Trap", + [EXCP_SMC] =3D "Secure Monitor Call", + [EXCP_VIRQ] =3D "Virtual IRQ", + [EXCP_VFIQ] =3D "Virtual FIQ", + [EXCP_SEMIHOST] =3D "Semihosting call", + [EXCP_NOCP] =3D "v7M NOCP UsageFault", + [EXCP_INVSTATE] =3D "v7M INVSTATE UsageFault", + [EXCP_STKOF] =3D "v8M STKOF UsageFault", + [EXCP_LAZYFP] =3D "v7M exception during lazy FP stacking", + [EXCP_LSERR] =3D "v8M LSERR UsageFault", + [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", + }; + + if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { + exc =3D excnames[idx]; + } + if (!exc) { + exc =3D "unknown"; + } + qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); + } +} + /* * Return true if the v7M CPACR permits access to the FPU for the specified * security state and privilege level. @@ -9434,44 +9472,6 @@ static bool do_v7m_function_return(ARMCPU *cpu) return true; } =20 -static void arm_log_exception(int idx) -{ - if (qemu_loglevel_mask(CPU_LOG_INT)) { - const char *exc =3D NULL; - static const char * const excnames[] =3D { - [EXCP_UDEF] =3D "Undefined Instruction", - [EXCP_SWI] =3D "SVC", - [EXCP_PREFETCH_ABORT] =3D "Prefetch Abort", - [EXCP_DATA_ABORT] =3D "Data Abort", - [EXCP_IRQ] =3D "IRQ", - [EXCP_FIQ] =3D "FIQ", - [EXCP_BKPT] =3D "Breakpoint", - [EXCP_EXCEPTION_EXIT] =3D "QEMU v7M exception exit", - [EXCP_KERNEL_TRAP] =3D "QEMU intercept of kernel commpage", - [EXCP_HVC] =3D "Hypervisor Call", - [EXCP_HYP_TRAP] =3D "Hypervisor Trap", - [EXCP_SMC] =3D "Secure Monitor Call", - [EXCP_VIRQ] =3D "Virtual IRQ", - [EXCP_VFIQ] =3D "Virtual FIQ", - [EXCP_SEMIHOST] =3D "Semihosting call", - [EXCP_NOCP] =3D "v7M NOCP UsageFault", - [EXCP_INVSTATE] =3D "v7M INVSTATE UsageFault", - [EXCP_STKOF] =3D "v8M STKOF UsageFault", - [EXCP_LAZYFP] =3D "v7M exception during lazy FP stacking", - [EXCP_LSERR] =3D "v8M LSERR UsageFault", - [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", - }; - - if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { - exc =3D excnames[idx]; - } - if (!exc) { - exc =3D "unknown"; - } - qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); - } -} - static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, uint32_t addr, uint16_t *insn) { --=20 2.20.1 From nobody Sat May 11 06:25:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1562025542; cv=none; d=zoho.com; s=zohoarc; b=SGc4N2dAz/ZG9qwwUL6NfxdV7Y60OzGumcNr3waYpUYirg1Rcqg4iyfJrvsfWzkF2ZLi+6KoS0NTq3y4UQeTFf8TrohzOI89SiWQEJn28Ho6C1CCJUVHdC9AwB8n4fasiQd3SoOEIAm8bv/fvYPRikuR87WbE/L0TcEqpPIf/10= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o6sm26573508wra.27.2019.07.01.09.40.35 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 01 Jul 2019 09:40:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wcyxWSQr6ooIWGi3dHkpFWTd3ZA08bJNcEU2ip3p0QI=; b=JC08Fcdg3eZTwjCYyfjtE3GavaJ3dS2BdvXaZzJrkF/iqC3figEKtZ96K6USXRdNMf 3/7ZfxZdRvPuBgKRoJCTpecN5j/jETcA/n27f1RRcmvyxirtUIOb7B+jOzJVtmJs9dgn uJS4fkpkcvjGZoQ2NgAoAPdZtghBIdBWHQwKLfEd68hBX8x1UjiB4yES1FmdrythHmnh /Z6AkdI/OHL5uG4+FuaV246MIqbtFhiADSjD7WwbazHd5mMgrf0CvxNzwZC1NcFgMmXz EDBabw3tD4K7G+BKOv4Y2G2Cr5ybUH2iNJOOYxAooDcv5wOEIAUWmsfuZcLCQY4x0/tg 7/lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wcyxWSQr6ooIWGi3dHkpFWTd3ZA08bJNcEU2ip3p0QI=; b=WWZW3+Oz29EjMZ9jcsZPfKRGiB3ccH7ZXMU7nJY5wEldQEBF6e6XmZ9YdaBNZyYnar n903LhlOc25Vww/HrcrMLPGRVP+sGOLjccir7gb9e8/J+7BIb7X8yLSI+Fg8zbqOQpMA 2FyId/nqDzD5JmaFzT3cE37/c3qTvYwWV1OmDvPRkgD+8p91WHsA3wMhPaaoh1ztYk4h E6irJPcyYVGXMuk07SO4sUlopywmq/E5pu+BHzVBZavF/y7bGGPXuxcQi4lf4EAx5MYS tcHXx7KnZJ6Wu6QL0pf8NyLNBSM2/C8cbW3noT7W9exeoUXGK6lpTTQdb3LLKqXnR68j ldrA== X-Gm-Message-State: APjAAAW7i6uf/nIz0AInoGemMleop7iLPVOjnFr53JdD+HLi0x9O+y/a zg4m4wJmKcTwWDfTMcD+BZhXN2MDeq8Q+Q== X-Google-Smtp-Source: APXvYqyb8VnCF27PPxhc4ig/XxX0Zw7GGo8IW0pr9bg+HaBuiohmfQW5hZsZQHozRmVx8H46FnTUjA== X-Received: by 2002:adf:dd8c:: with SMTP id x12mr19881836wrl.212.1561999236096; Mon, 01 Jul 2019 09:40:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 17:39:43 +0100 Message-Id: <20190701163943.22313-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190701163943.22313-1-peter.maydell@linaro.org> References: <20190701163943.22313-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.49 Subject: [Qemu-devel] [PULL 46/46] target/arm: Declare some M-profile functions publicly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 In the next commit we will split the M-profile functions from this file. Some function will be called out of helper.c. Declare them in the "internals.h" header. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190701132516.26392-22-philmd@redhat.com Signed-off-by: Peter Maydell --- target/arm/internals.h | 42 ++++++++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 38 ++------------------------------------ 2 files changed, 44 insertions(+), 36 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 11bfdba5129..232d9638753 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -892,6 +892,27 @@ static inline uint32_t v7m_sp_limit(CPUARMState *env) } } =20 +/** + * v7m_cpacr_pass: + * Return true if the v7M CPACR permits access to the FPU for the specified + * security state and privilege level. + */ +static inline bool v7m_cpacr_pass(CPUARMState *env, + bool is_secure, bool is_priv) +{ + switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { + case 0: + case 2: /* UNPREDICTABLE: we treat like 0 */ + return false; + case 1: + return is_priv; + case 3: + return true; + default: + g_assert_not_reached(); + } +} + /** * aarch32_mode_name(): Return name of the AArch32 CPU mode * @psr: Program Status Register indicating CPU mode @@ -988,6 +1009,27 @@ static inline int exception_target_el(CPUARMState *en= v) =20 #ifndef CONFIG_USER_ONLY =20 +/* Security attributes for an address, as returned by v8m_security_lookup.= */ +typedef struct V8M_SAttributes { + bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE= */ + bool ns; + bool nsc; + uint8_t sregion; + bool srvalid; + uint8_t iregion; + bool irvalid; +} V8M_SAttributes; + +void v8m_security_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + V8M_SAttributes *sattrs); + +bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, + int *prot, bool *is_subpage, + ARMMMUFaultInfo *fi, uint32_t *mregion); + /* Cacheability and shareability attributes for a memory access */ typedef struct ARMCacheAttrs { unsigned int attrs:8; /* as in the MAIR register encoding */ diff --git a/target/arm/helper.c b/target/arm/helper.c index dc880b4dabc..38b73430cbb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -39,21 +39,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_= ulong address, hwaddr *phys_ptr, MemTxAttrs *txattrs, int = *prot, target_ulong *page_size_ptr, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs); - -/* Security attributes for an address, as returned by v8m_security_lookup.= */ -typedef struct V8M_SAttributes { - bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE= */ - bool ns; - bool nsc; - uint8_t sregion; - bool srvalid; - uint8_t iregion; - bool irvalid; -} V8M_SAttributes; - -static void v8m_security_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_i= dx, - V8M_SAttributes *sattrs); #endif =20 static void switch_mode(CPUARMState *env, int mode); @@ -7733,25 +7718,6 @@ void arm_log_exception(int idx) } } =20 -/* - * Return true if the v7M CPACR permits access to the FPU for the specified - * security state and privilege level. - */ -static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_priv) -{ - switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { - case 0: - case 2: /* UNPREDICTABLE: we treat like 0 */ - return false; - case 1: - return is_priv; - case 3: - return true; - default: - g_assert_not_reached(); - } -} - /* * What kind of stack write are we doing? This affects how exceptions * generated during the stacking are treated. @@ -12117,7 +12083,7 @@ static bool v8m_is_sau_exempt(CPUARMState *env, (address >=3D 0xe00ff000 && address <=3D 0xe00fffff); } =20 -static void v8m_security_lookup(CPUARMState *env, uint32_t address, +void v8m_security_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_i= dx, V8M_SAttributes *sattrs) { @@ -12224,7 +12190,7 @@ static void v8m_security_lookup(CPUARMState *env, u= int32_t address, } } =20 -static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, +bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, bool *is_subpage, --=20 2.20.1