From nobody Sat May 11 21:52:03 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561927746; cv=none; d=zoho.com; s=zohoarc; b=SmrpdYpU4DSdcKcVzRCA393a4YOnjVTlTO0p77i6Kh/whfULzHR2ZT3mgs6TJrdrKDt+Y1BRkZGE2EVxOognTtCYNhq2jpULwEzRtbCveIAn9AJkb0xOXwrUxO31qatxB6SELNX2BGUdXiJgOjh4gh8Jj70ZD38DX4KmogJP/GA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561927746; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=0evCzm84A39Ef7OI9TRv+sXqstrn+beUOgYAA//LZh8=; b=AF3Vlcwn0WNx2L5y1d7j1137oZQezo6oP5NRtg3+StH/mfJDxGEvaKChOW33KGiRI8Lul9c+UCDH+BX5lMz/7a18T1y9mhRcOpi1DY/M63Hq06MPxek40JWPWRxnoH3TiLwyOYjQPL/Xl/SXOdRjm1YF4dczkMmbS/eIZ/lA3rg= ARC-Authentication-Results: i=1; mx.zoho.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561927745935270.81377703952114; Sun, 30 Jun 2019 13:49:05 -0700 (PDT) Received: from localhost ([::1]:46452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hhgkk-0001X5-Jk for importer@patchew.org; Sun, 30 Jun 2019 16:48:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35882) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hhgiS-0008Eh-LY for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:46:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hhgiR-0001sj-IA for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:46:28 -0400 Received: from 5.mo68.mail-out.ovh.net ([46.105.62.179]:49846) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hhgiR-0001ns-BF for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:46:27 -0400 Received: from player157.ha.ovh.net (unknown [10.108.57.153]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 7B6161358FE for ; Sun, 30 Jun 2019 22:46:21 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player157.ha.ovh.net (Postfix) with ESMTPSA id 38D7E7575A22; Sun, 30 Jun 2019 20:46:14 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Sun, 30 Jun 2019 22:45:52 +0200 Message-Id: <20190630204601.30574-2-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190630204601.30574-1-clg@kaod.org> References: <20190630204601.30574-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2277976986789776358 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrvdeggdduheegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.62.179 Subject: [Qemu-devel] [PATCH 01/10] ppc/xive: Force the Physical CAM line value to group mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , Suraj Jitindar Singh , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When an interrupt needs to be delivered, the XIVE interrupt controller presenter scans the CAM lines of the thread interrupt contexts of the HW threads of the chip to find a matching vCPU. The interrupt context is composed of 4 different sets of registers: Physical, HV, OS and User. The encoding of the Physical CAM line depends on the mode in which the interrupt controller is operating: CAM mode or block group mode. Block group mode being the default configuration today on POWER9 and the only one available on the next POWER10 generation, enforce this encoding in the Physical CAM line : chip << 19 | 0000000 0 0001 thread (7Bit) It fits the overall encoding of the NVT ids and simplifies the matching algorithm in the presenter. Fixes: d514c48d41fb ("ppc/xive: hardwire the Physical CAM line of the threa= d context") Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 6250c0414de8..3b1f9520ae9f 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1229,27 +1229,16 @@ XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CP= UState *cs) } =20 /* - * By default on P9, the HW CAM line (23bits) is hardwired to : + * Encode the HW CAM line in the block group mode format : * - * 0x000||0b1||4Bit chip number||7Bit Thread number. - * - * When the block grouping is enabled, the CAM line is changed to : - * - * 4Bit chip number||0x001||7Bit Thread number. + * chip << 19 | 0000000 0 0001 thread (7Bit) */ -static uint32_t hw_cam_line(uint8_t chip_id, uint8_t tid) -{ - return 1 << 11 | (chip_id & 0xf) << 7 | (tid & 0x7f); -} - -static bool xive_presenter_tctx_match_hw(XiveTCTX *tctx, - uint8_t nvt_blk, uint32_t nvt_idx) +static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) { CPUPPCState *env =3D &POWERPC_CPU(tctx->cs)->env; uint32_t pir =3D env->spr_cb[SPR_PIR].default_value; =20 - return hw_cam_line((pir >> 8) & 0xf, pir & 0x7f) =3D=3D - hw_cam_line(nvt_blk, nvt_idx); + return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f)); } =20 /* @@ -1285,7 +1274,7 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, = uint8_t format, =20 /* PHYS ring */ if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && - xive_presenter_tctx_match_hw(tctx, nvt_blk, nvt_idx)) { + cam =3D=3D xive_tctx_hw_cam_line(tctx)) { return TM_QW3_HV_PHYS; } =20 --=20 2.21.0 From nobody Sat May 11 21:52:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Sun, 30 Jun 2019 20:46:21 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Sun, 30 Jun 2019 22:45:53 +0200 Message-Id: <20190630204601.30574-3-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190630204601.30574-1-clg@kaod.org> References: <20190630204601.30574-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2279947311805008870 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrvdeggdduheegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.57.129 Subject: [Qemu-devel] [PATCH 02/10] ppc/xive: Make the PIPR register readonly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , Suraj Jitindar Singh , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When the hypervisor (KVM) dispatches a vCPU on a HW thread, it restores its thread interrupt context. The Pending Interrupt Priority Register (PIPR) is computed from the Interrupt Pending Buffer (IPB) and stores should not be allowed to change its value. Fixes: 207d9fe98510 ("ppc/xive: introduce the XIVE interrupt thread context= ") Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 3b1f9520ae9f..534f56f86bd5 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -182,31 +182,31 @@ static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwadd= r offset, unsigned size) */ =20 static const uint8_t xive_tm_hw_view[] =3D { - /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, - /* QW-1 OS */ 3, 3, 3, 3, 3, 3, 0, 3, 3, 3, 3, 3, 0, 0, 0, 0, - /* QW-2 POOL */ 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, - /* QW-3 PHYS */ 3, 3, 3, 3, 0, 3, 0, 3, 3, 0, 0, 3, 3, 3, 3, 0, + 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ + 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ + 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ + 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ }; =20 static const uint8_t xive_tm_hv_view[] =3D { - /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, - /* QW-1 OS */ 3, 3, 3, 3, 3, 3, 0, 3, 3, 3, 3, 3, 0, 0, 0, 0, - /* QW-2 POOL */ 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, - /* QW-3 PHYS */ 3, 3, 3, 3, 0, 3, 0, 3, 3, 0, 0, 3, 0, 0, 0, 0, + 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ + 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ + 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ + 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ }; =20 static const uint8_t xive_tm_os_view[] =3D { - /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, - /* QW-1 OS */ 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, - /* QW-2 POOL */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* QW-3 PHYS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ + 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ }; =20 static const uint8_t xive_tm_user_view[] =3D { - /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* QW-1 OS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* QW-2 POOL */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* QW-3 PHYS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ }; =20 /* --=20 2.21.0 From nobody Sat May 11 21:52:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Sun, 30 Jun 2019 20:46:28 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Sun, 30 Jun 2019 22:45:54 +0200 Message-Id: <20190630204601.30574-4-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190630204601.30574-1-clg@kaod.org> References: <20190630204601.30574-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2281636163921611750 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrvdeggdduheegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.248.196 Subject: [Qemu-devel] [PATCH 03/10] ppc/pnv: Rework cache watch model of PnvXIVE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , Suraj Jitindar Singh , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When the software modifies the XIVE internal structures, ESB, EAS, END, NVT, it also must update the caches of the different XIVE sub-engines. HW offers a set of common interface for such purpose. The CWATCH_SPEC register defines the block/index of the target and a set of flags to perform a full update and to watch for update conflicts. The cache watch CWATCH_DATAX registers are then loaded with the target data with a first read on CWATCH_DATA0. Writing back is done in the opposit order, CWATCH_DATA0 triggering the update. The SCRUB_TRIG registers are used to flush the cache in RAM, and to possibly invalidate it. Cache disablement is also an option but as we do not model the cache, these registers are no-ops Today, the modeling of these registers is incorrect but it did not impact the set up of a baremetal system. However, running KVM requires a rework. Fixes: 2dfa91a2aa5a ("ppc/pnv: add a XIVE interrupt controller model for PO= WER9") Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 142 +++++++++++++++++++++++++++++++++------------ 1 file changed, 106 insertions(+), 36 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 9ab77feee9d8..4dc92ef1e372 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -169,7 +169,7 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xiv= e, uint32_t type, vsd =3D ldq_be_dma(&address_space_memory, vsd_addr); =20 if (!(vsd & VSD_ADDRESS_MASK)) { - xive_error(xive, "VST: invalid %s entry %x !?", info->name, 0); + xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); return 0; } =20 @@ -190,7 +190,7 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xiv= e, uint32_t type, vsd =3D ldq_be_dma(&address_space_memory, vsd_addr); =20 if (!(vsd & VSD_ADDRESS_MASK)) { - xive_error(xive, "VST: invalid %s entry %x !?", info->name, 0); + xive_error(xive, "VST: invalid %s entry %x !?", info->name, id= x); return 0; } =20 @@ -294,8 +294,12 @@ static int pnv_xive_write_end(XiveRouter *xrtr, uint8_= t blk, uint32_t idx, word_number); } =20 -static int pnv_xive_end_update(PnvXive *xive, uint8_t blk, uint32_t idx) +static int pnv_xive_end_update(PnvXive *xive) { + uint8_t blk =3D GETFIELD(VC_EQC_CWATCH_BLOCKID, + xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); + uint32_t idx =3D GETFIELD(VC_EQC_CWATCH_OFFSET, + xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); int i; uint64_t eqc_watch[4]; =20 @@ -307,6 +311,24 @@ static int pnv_xive_end_update(PnvXive *xive, uint8_t = blk, uint32_t idx) XIVE_VST_WORD_ALL); } =20 +static void pnv_xive_end_cache_load(PnvXive *xive) +{ + uint8_t blk =3D GETFIELD(VC_EQC_CWATCH_BLOCKID, + xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); + uint32_t idx =3D GETFIELD(VC_EQC_CWATCH_OFFSET, + xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); + uint64_t eqc_watch[4] =3D { 0 }; + int i; + + if (pnv_xive_vst_read(xive, VST_TSEL_EQDT, blk, idx, eqc_watch)) { + xive_error(xive, "VST: no END entry %x/%x !?", blk, idx); + } + + for (i =3D 0; i < ARRAY_SIZE(eqc_watch); i++) { + xive->regs[(VC_EQC_CWATCH_DAT0 >> 3) + i] =3D be64_to_cpu(eqc_watc= h[i]); + } +} + static int pnv_xive_get_nvt(XiveRouter *xrtr, uint8_t blk, uint32_t idx, XiveNVT *nvt) { @@ -320,8 +342,12 @@ static int pnv_xive_write_nvt(XiveRouter *xrtr, uint8_= t blk, uint32_t idx, word_number); } =20 -static int pnv_xive_nvt_update(PnvXive *xive, uint8_t blk, uint32_t idx) +static int pnv_xive_nvt_update(PnvXive *xive) { + uint8_t blk =3D GETFIELD(PC_VPC_CWATCH_BLOCKID, + xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); + uint32_t idx =3D GETFIELD(PC_VPC_CWATCH_OFFSET, + xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); int i; uint64_t vpc_watch[8]; =20 @@ -333,6 +359,24 @@ static int pnv_xive_nvt_update(PnvXive *xive, uint8_t = blk, uint32_t idx) XIVE_VST_WORD_ALL); } =20 +static void pnv_xive_nvt_cache_load(PnvXive *xive) +{ + uint8_t blk =3D GETFIELD(PC_VPC_CWATCH_BLOCKID, + xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); + uint32_t idx =3D GETFIELD(PC_VPC_CWATCH_OFFSET, + xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); + uint64_t vpc_watch[8] =3D { 0 }; + int i; + + if (pnv_xive_vst_read(xive, VST_TSEL_VPDT, blk, idx, vpc_watch)) { + xive_error(xive, "VST: no NVT entry %x/%x !?", blk, idx); + } + + for (i =3D 0; i < ARRAY_SIZE(vpc_watch); i++) { + xive->regs[(PC_VPC_CWATCH_DAT0 >> 3) + i] =3D be64_to_cpu(vpc_watc= h[i]); + } +} + static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx, XiveEAS *eas) { @@ -346,12 +390,6 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t = blk, uint32_t idx, return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas); } =20 -static int pnv_xive_eas_update(PnvXive *xive, uint8_t blk, uint32_t idx) -{ - /* All done. */ - return 0; -} - static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -950,28 +988,43 @@ static void pnv_xive_ic_reg_write(void *opaque, hwadd= r offset, * XIVE PC & VC cache updates for EAS, NVT and END */ case VC_IVC_SCRUB_MASK: - break; case VC_IVC_SCRUB_TRIG: - pnv_xive_eas_update(xive, GETFIELD(PC_SCRUB_BLOCK_ID, val), - GETFIELD(VC_SCRUB_OFFSET, val)); break; =20 - case VC_EQC_SCRUB_MASK: case VC_EQC_CWATCH_SPEC: - case VC_EQC_CWATCH_DAT0 ... VC_EQC_CWATCH_DAT3: + val &=3D ~VC_EQC_CWATCH_CONFLICT; /* HW resets this bit */ + break; + case VC_EQC_CWATCH_DAT1 ... VC_EQC_CWATCH_DAT3: break; + case VC_EQC_CWATCH_DAT0: + /* writing to DATA0 triggers the cache write */ + xive->regs[reg] =3D val; + pnv_xive_end_update(xive); + break; + case VC_EQC_SCRUB_MASK: case VC_EQC_SCRUB_TRIG: - pnv_xive_end_update(xive, GETFIELD(VC_SCRUB_BLOCK_ID, val), - GETFIELD(VC_SCRUB_OFFSET, val)); + /* + * The scrubbing registers flush the cache in RAM and can also + * invalidate. + */ break; =20 - case PC_VPC_SCRUB_MASK: case PC_VPC_CWATCH_SPEC: - case PC_VPC_CWATCH_DAT0 ... PC_VPC_CWATCH_DAT7: + val &=3D ~PC_VPC_CWATCH_CONFLICT; /* HW resets this bit */ + break; + case PC_VPC_CWATCH_DAT1 ... PC_VPC_CWATCH_DAT7: break; + case PC_VPC_CWATCH_DAT0: + /* writing to DATA0 triggers the cache write */ + xive->regs[reg] =3D val; + pnv_xive_nvt_update(xive); + break; + case PC_VPC_SCRUB_MASK: case PC_VPC_SCRUB_TRIG: - pnv_xive_nvt_update(xive, GETFIELD(PC_SCRUB_BLOCK_ID, val), - GETFIELD(PC_SCRUB_OFFSET, val)); + /* + * The scrubbing registers flush the cache in RAM and can also + * invalidate. + */ break; =20 =20 @@ -1022,15 +1075,6 @@ static uint64_t pnv_xive_ic_reg_read(void *opaque, h= waddr offset, unsigned size) case PC_GLOBAL_CONFIG: =20 case PC_VPC_SCRUB_MASK: - case PC_VPC_CWATCH_SPEC: - case PC_VPC_CWATCH_DAT0: - case PC_VPC_CWATCH_DAT1: - case PC_VPC_CWATCH_DAT2: - case PC_VPC_CWATCH_DAT3: - case PC_VPC_CWATCH_DAT4: - case PC_VPC_CWATCH_DAT5: - case PC_VPC_CWATCH_DAT6: - case PC_VPC_CWATCH_DAT7: =20 case VC_GLOBAL_CONFIG: case VC_AIB_TX_ORDER_TAG2: @@ -1043,12 +1087,6 @@ static uint64_t pnv_xive_ic_reg_read(void *opaque, h= waddr offset, unsigned size) case VC_IRQ_CONFIG_IPI_CASC: =20 case VC_EQC_SCRUB_MASK: - case VC_EQC_CWATCH_DAT0: - case VC_EQC_CWATCH_DAT1: - case VC_EQC_CWATCH_DAT2: - case VC_EQC_CWATCH_DAT3: - - case VC_EQC_CWATCH_SPEC: case VC_IVC_SCRUB_MASK: case VC_SBC_CONFIG: case VC_AT_MACRO_KILL_MASK: @@ -1080,6 +1118,38 @@ static uint64_t pnv_xive_ic_reg_read(void *opaque, h= waddr offset, unsigned size) /* * XIVE PC & VC cache updates for EAS, NVT and END */ + case VC_EQC_CWATCH_SPEC: + xive->regs[reg] =3D ~(VC_EQC_CWATCH_FULL | VC_EQC_CWATCH_CONFLICT); + val =3D xive->regs[reg]; + break; + case VC_EQC_CWATCH_DAT0: + /* + * Load DATA registers from cache with data requested by the + * SPEC register + */ + pnv_xive_end_cache_load(xive); + val =3D xive->regs[reg]; + break; + case VC_EQC_CWATCH_DAT1 ... VC_EQC_CWATCH_DAT3: + val =3D xive->regs[reg]; + break; + + case PC_VPC_CWATCH_SPEC: + xive->regs[reg] =3D ~(PC_VPC_CWATCH_FULL | PC_VPC_CWATCH_CONFLICT); + val =3D xive->regs[reg]; + break; + case PC_VPC_CWATCH_DAT0: + /* + * Load DATA registers from cache with data requested by the + * SPEC register + */ + pnv_xive_nvt_cache_load(xive); + val =3D xive->regs[reg]; + break; + case PC_VPC_CWATCH_DAT1 ... PC_VPC_CWATCH_DAT7: + val =3D xive->regs[reg]; + break; + case PC_VPC_SCRUB_TRIG: case VC_IVC_SCRUB_TRIG: case VC_EQC_SCRUB_TRIG: --=20 2.21.0 From nobody Sat May 11 21:52:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561928028; cv=none; d=zoho.com; s=zohoarc; b=JxXJW9RfnL6gCsbHeuAZG2Y9H0hZ4iEo5w/UWJRa8iDRCG2bj7fDV9wBgZ7Cn3hPtP4/gtw9G0SWs0I4FCS4nZi8l/MxeLepCOf0mrOw+xGfOCoOP1oQKPS4JBwSkAg0dyXLDFQK/ep9s8+9Q8iaIL6znmHUXXtb4WBAlpFI4aE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561928028; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=27mrs5WykniLWSckhR2abKI25TBSsXhcmSF5Hwm44DU=; b=kOJK9eQkFK6//b5pvgj+QRvDjvcYU167ko1ZQmS2i4akzk9zto4KycdrZpRI039v9u7np7SpgXNVLLzJzAocOErkSzq0VMS9Xwf+awuc7fIDnCxC3wTreSFPU8ra5mWrZZLVGoYC4GSdaFARbDIfepHVPoVjtSZiXW7UaWaVAuY= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561928028856960.3732929935933; Sun, 30 Jun 2019 13:53:48 -0700 (PDT) Received: from localhost ([::1]:46506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hhgpX-0008Hc-RR for importer@patchew.org; Sun, 30 Jun 2019 16:53:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36006) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hhgis-0008RZ-Lg for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:46:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hhgir-0002DW-Gt for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:46:54 -0400 Received: from 11.mo7.mail-out.ovh.net ([87.98.173.157]:56125) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hhgir-00025x-4S for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:46:53 -0400 Received: from player157.ha.ovh.net (unknown [10.108.54.87]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 912E911EC66 for ; Sun, 30 Jun 2019 22:46:41 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player157.ha.ovh.net (Postfix) with ESMTPSA id B226D7575A87; Sun, 30 Jun 2019 20:46:34 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Sun, 30 Jun 2019 22:45:55 +0200 Message-Id: <20190630204601.30574-5-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190630204601.30574-1-clg@kaod.org> References: <20190630204601.30574-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2283606489384782822 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrvdeggdduheegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.173.157 Subject: [Qemu-devel] [PATCH 04/10] ppc/xive: Fix TM_PULL_POOL_CTX special operation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , Suraj Jitindar Singh , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When a CPU is reseted, the hypervisor (Linux or OPAL) invalidates the POOL interrupt context of a CPU with this special command. It returns the POOL CAM line value and resets the VP bit. Fixes: 4836b45510aa ("ppc/xive: activate HV support") Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 534f56f86bd5..cf77bdb7d34a 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -132,6 +132,11 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t= ring, uint8_t cppr) xive_tctx_notify(tctx, ring); } =20 +static inline uint32_t xive_tctx_word2(uint8_t *ring) +{ + return *((uint32_t *) &ring[TM_WORD2]); +} + /* * XIVE Thread Interrupt Management Area (TIMA) */ @@ -150,11 +155,12 @@ static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hw= addr offset, unsigned size) static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, unsigned size) { - uint64_t ret; + uint32_t qw2w2_prev =3D xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); + uint32_t qw2w2; =20 - ret =3D tctx->regs[TM_QW2_HV_POOL + TM_WORD2] & TM_QW2W2_POOL_CAM; - tctx->regs[TM_QW2_HV_POOL + TM_WORD2] &=3D ~TM_QW2W2_POOL_CAM; - return ret; + qw2w2 =3D xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); + memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); + return qw2w2; } =20 static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, @@ -484,11 +490,6 @@ const MemoryRegionOps xive_tm_ops =3D { }, }; =20 -static inline uint32_t xive_tctx_word2(uint8_t *ring) -{ - return *((uint32_t *) &ring[TM_WORD2]); -} - static char *xive_tctx_ring_print(uint8_t *ring) { uint32_t w2 =3D xive_tctx_word2(ring); --=20 2.21.0 From nobody Sat May 11 21:52:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561927921; 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Sun, 30 Jun 2019 20:46:41 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Sun, 30 Jun 2019 22:45:56 +0200 Message-Id: <20190630204601.30574-6-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190630204601.30574-1-clg@kaod.org> References: <20190630204601.30574-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2285295336376208358 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrvdeggdduheegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.172.162 Subject: [Qemu-devel] [PATCH 05/10] ppc/xive: Implement TM_PULL_OS_CTX special command X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , Suraj Jitindar Singh , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When a vCPU is not dispatched anymore on a HW thread, the Hypervisor (KVM) invalidates the OS interrupt context of a vCPU with this special command. It returns the OS CAM line value and resets the VO bit. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index cf77bdb7d34a..592c0b70f197 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -334,6 +334,17 @@ static void xive_tm_set_os_pending(XiveTCTX *tctx, hwa= ddr offset, xive_tctx_notify(tctx, TM_QW1_OS); } =20 +static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset, + unsigned size) +{ + uint32_t qw1w2_prev =3D xive_tctx_word2(&tctx->regs[TM_QW1_OS]); + uint32_t qw1w2; + + qw1w2 =3D xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0); + memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); + return qw1w2; +} + /* * Define a mapping of "special" operations depending on the TIMA page * offset and the size of the operation. @@ -360,6 +371,8 @@ static const XiveTmOp xive_tm_operations[] =3D { /* MMIOs above 2K : special operations with side effects */ { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg = }, { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, N= ULL }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx= }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx= }, { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg = }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_c= tx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_c= tx }, @@ -403,7 +416,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, = uint64_t value, if (offset & 0x800) { xto =3D xive_tm_find_op(offset, size, true); if (!xto) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at = TIMA" + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at = TIMA " "@%"HWADDR_PRIx"\n", offset); } else { xto->write_handler(tctx, offset, value, size); --=20 2.21.0 From nobody Sat May 11 21:52:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561928167; cv=none; d=zoho.com; s=zohoarc; b=ByU6THjRz8fRLf6WTt62M6j1/A4FIRwQAKuOMtRQLoaMGuEgGKc1cYqyLLrd+PRor1lIP1zQOg5fkY/iDejE29nEBe2hDowZe3zBPWB/u5I/dNjsCJKeR+zfFRsOClHqIEk8xLX8dhkiU05//9LjmpSsMV35UaDsqDEzAQDSKxk= ARC-Message-Signature: i=1; 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Sun, 30 Jun 2019 16:56:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36069) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hhgj5-00006M-TY for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hhgj2-0002Mg-BN for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:06 -0400 Received: from 1.mo68.mail-out.ovh.net ([46.105.41.146]:60776) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hhgix-0002GZ-6p for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:00 -0400 Received: from player157.ha.ovh.net (unknown [10.108.57.141]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id B8F2312CFF2 for ; Sun, 30 Jun 2019 22:46:54 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player157.ha.ovh.net (Postfix) with ESMTPSA id DA4067575AC1; Sun, 30 Jun 2019 20:46:47 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Sun, 30 Jun 2019 22:45:57 +0200 Message-Id: <20190630204601.30574-7-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190630204601.30574-1-clg@kaod.org> References: <20190630204601.30574-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2287265664829524966 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrvdeggdduheegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.41.146 Subject: [Qemu-devel] [PATCH 06/10] ppc/xive: Provide escalation support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , Suraj Jitindar Singh , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" If the XIVE presenter can not find the NVT dispatched on any of the HW threads, it can not deliver the interrupt. XIVE offers a mechanism to handle such scenarios and inform the hypervisor that an action should be taken. The first action is to keep track of the pending priority of the missed event. It is recorded in the IPB field of the NVT for a later resend if backlog is activated ('b' bit) on the END. An END can also escalate if configured: 'e' bit and setting of the EAS in word 4 & 5 to let the HW look for the escalation END on which to trigger a new event. Escalation has its own options to program different behaviors : - unconditional escalation ('u' bit) with which the ESe PQ bits are not used. - silent/gather escalation ('s' bit), the sequence skips the notification process and jumps directly to the escalation. KVM uses a combination of these. The first level END is configured to enqueue, unconditionally notify, backlog and escalate and points to an escalation END which is configured to escalate silently. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive_regs.h | 4 ++ hw/intc/xive.c | 130 +++++++++++++++++++++++++++++++------ 2 files changed, 115 insertions(+), 19 deletions(-) diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 1a8c5b5e64f0..69af326ebf2c 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -207,6 +207,10 @@ typedef struct XiveEND { #define xive_end_is_notify(end) (be32_to_cpu((end)->w0) & END_W0_UCOND_N= OTIFY) #define xive_end_is_backlog(end) (be32_to_cpu((end)->w0) & END_W0_BACKLOG) #define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALAT= E_CTL) +#define xive_end_is_uncond_escalation(end) \ + (be32_to_cpu((end)->w0) & END_W0_UNCOND_ESCALATE) +#define xive_end_is_silent_escalation(end) \ + (be32_to_cpu((end)->w0) & END_W0_SILENT_ESCALATE) =20 static inline uint64_t xive_end_qaddr(XiveEND *end) { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 592c0b70f197..3970999f4837 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1389,7 +1389,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, ui= nt8_t format, * * The parameters represent what is sent on the PowerBus */ -static void xive_presenter_notify(XiveRouter *xrtr, uint8_t format, +static bool xive_presenter_notify(XiveRouter *xrtr, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, uint32_t logic_serv) @@ -1402,13 +1402,13 @@ static void xive_presenter_notify(XiveRouter *xrtr,= uint8_t format, if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", nvt_blk, nvt_idx); - return; + return false; } =20 if (!xive_nvt_is_valid(&nvt)) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", nvt_blk, nvt_idx); - return; + return false; } =20 found =3D xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ign= ore, @@ -1416,19 +1416,55 @@ static void xive_presenter_notify(XiveRouter *xrtr,= uint8_t format, if (found) { ipb_update(&match.tctx->regs[match.ring], priority); xive_tctx_notify(match.tctx, match.ring); + } + + return found; +} + +static void xive_router_end_backlog(XiveRouter *xrtr, + uint8_t nvt_blk, uint32_t nvt_idx, + uint8_t priority) +{ + XiveNVT nvt; + + /* NVT cache lookup */ + if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", + nvt_blk, nvt_idx); + return; + } + + if (!xive_nvt_is_valid(&nvt)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", + nvt_blk, nvt_idx); return; } =20 /* Record the IPB in the associated NVT structure */ ipb_update((uint8_t *) &nvt.w4, priority); xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); +} =20 - /* - * If no matching NVT is dispatched on a HW thread : - * - update the NVT structure if backlog is activated - * - escalate (ESe PQ bits and EAS in w4-5) if escalation is - * activated - */ + +/* + * Notification using the END ESe/ESn bit (Event State Buffer for + * escalation and notification). Profide futher coalescing in the + * Router. + */ +static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, + uint32_t end_idx, XiveEND *end, + uint32_t end_esmask) +{ + uint8_t pq =3D xive_get_field32(end_esmask, end->w1); + bool notify =3D xive_esb_trigger(&pq); + + if (pq !=3D xive_get_field32(end_esmask, end->w1)) { + end->w1 =3D xive_set_field32(end_esmask, end->w1, pq); + xive_router_write_end(xrtr, end_blk, end_idx, end, 1); + } + + /* ESe/n[Q]=3D1 : end of notification */ + return notify; } =20 /* @@ -1442,6 +1478,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, = uint8_t end_blk, XiveEND end; uint8_t priority; uint8_t format; + bool found; =20 /* END cache lookup */ if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { @@ -1462,6 +1499,13 @@ static void xive_router_end_notify(XiveRouter *xrtr,= uint8_t end_blk, xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); } =20 + /* + * When the END is silent, we skip the notification part. + */ + if (xive_end_is_silent_escalation(&end)) { + goto do_escalation; + } + /* * The W7 format depends on the F bit in W6. It defines the type * of the notification : @@ -1483,16 +1527,9 @@ static void xive_router_end_notify(XiveRouter *xrtr,= uint8_t end_blk, * even futher coalescing in the Router */ if (!xive_end_is_notify(&end)) { - uint8_t pq =3D xive_get_field32(END_W1_ESn, end.w1); - bool notify =3D xive_esb_trigger(&pq); - - if (pq !=3D xive_get_field32(END_W1_ESn, end.w1)) { - end.w1 =3D xive_set_field32(END_W1_ESn, end.w1, pq); - xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); - } - /* ESn[Q]=3D1 : end of notification */ - if (!notify) { + if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, + &end, END_W1_ESn)) { return; } } @@ -1500,7 +1537,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, = uint8_t end_blk, /* * Follows IVPE notification */ - xive_presenter_notify(xrtr, format, + found =3D xive_presenter_notify(xrtr, format, xive_get_field32(END_W6_NVT_BLOCK, end.w6), xive_get_field32(END_W6_NVT_INDEX, end.w6), xive_get_field32(END_W7_F0_IGNORE, end.w7), @@ -1508,6 +1545,61 @@ static void xive_router_end_notify(XiveRouter *xrtr,= uint8_t end_blk, xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7= )); =20 /* TODO: Auto EOI. */ + + if (found) { + return; + } + + /* + * If no matching NVT is dispatched on a HW thread : + * - specific VP: update the NVT structure if backlog is activated + * - logical server : forward request to IVPE (not supported) + */ + if (xive_end_is_backlog(&end)) { + if (format =3D=3D 1) { + qemu_log_mask(LOG_GUEST_ERROR, + "XIVE: END %x/%x invalid config: F1 & backlog\n", + end_blk, end_idx); + return; + } + xive_router_end_backlog(xrtr, + xive_get_field32(END_W6_NVT_BLOCK, end.w6), + xive_get_field32(END_W6_NVT_INDEX, end.w6), + priority); + + /* + * On HW, follows a "Broadcast Backlog" to IVPEs + */ + } + +do_escalation: + /* + * If activated, escalate notification using the ESe PQ bits and + * the EAS in w4-5 + */ + if (!xive_end_is_escalate(&end)) { + return; + } + + /* + * Check the END ESe (Event State Buffer for escalation) for even + * futher coalescing in the Router + */ + if (!xive_end_is_uncond_escalation(&end)) { + /* ESe[Q]=3D1 : end of notification */ + if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, + &end, END_W1_ESe)) { + return; + } + } + + /* + * The END trigger becomes an Escalation trigger + */ + xive_router_end_notify(xrtr, + xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), + xive_get_field32(END_W4_ESC_END_INDEX, end.w4), + xive_get_field32(END_W5_ESC_END_DATA, end.w5)); } =20 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) --=20 2.21.0 From nobody Sat May 11 21:52:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561928025; cv=none; d=zoho.com; s=zohoarc; b=Ui6S14FsHMyAeWPdi7SScl0ugK5OkRVMAk7XRtDWLUu/C8qQUHb4rCyxRjy9iVK3iKyzXqsdMnpdwMjBhMCrr5jNm/bf9+dOeqw+gehhlV5qnMYWBZztC7Vg0M0pVGAfUoavp3B5OnCcNQb/WE04hJr1nXvXDYpHXGYvCllGVEk= ARC-Message-Signature: i=1; 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Sun, 30 Jun 2019 16:53:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36085) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hhgjA-00007b-0G for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hhgj5-0002PK-Ag for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:09 -0400 Received: from 9.mo178.mail-out.ovh.net ([46.105.75.45]:34593) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hhgj2-0002LN-AW for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:05 -0400 Received: from player157.ha.ovh.net (unknown [10.109.143.145]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id AF0CA6E500 for ; Sun, 30 Jun 2019 22:47:01 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player157.ha.ovh.net (Postfix) with ESMTPSA id 9CA2C7575AD1; Sun, 30 Jun 2019 20:46:54 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Sun, 30 Jun 2019 22:45:58 +0200 Message-Id: <20190630204601.30574-8-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190630204601.30574-1-clg@kaod.org> References: <20190630204601.30574-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2289235986895440870 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrvdeggdduheegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.75.45 Subject: [Qemu-devel] [PATCH 07/10] ppc/xive: Improve 'info pic' support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , Suraj Jitindar Singh , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Provide a better output of the XIVE END structures including the escalation information and extend the PowerNV machine 'info pic' command with a dump of the END EAS table used for escalations. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 5 ---- include/hw/ppc/xive_regs.h | 6 +++++ hw/intc/pnv_xive.c | 9 +++++++ hw/intc/spapr_xive.c | 1 - hw/intc/xive.c | 48 +++++++++++++++++++++++++++++++++----- 5 files changed, 57 insertions(+), 12 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index a6ee7e831d8b..d922524982d3 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -356,8 +356,6 @@ typedef struct XiveRouterClass { XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs); } XiveRouterClass; =20 -void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon); - int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_id= x, XiveEAS *eas); int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_id= x, @@ -399,9 +397,6 @@ typedef struct XiveENDSource { */ #define XIVE_PRIORITY_MAX 7 =20 -void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon); -void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *= mon); - /* * XIVE Thread Interrupt Management Aera (TIMA) * diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 69af326ebf2c..3fdf1a83b9b6 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -128,6 +128,8 @@ typedef struct XiveEAS { #define xive_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS_VALID) #define xive_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS_MASKED) =20 +void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon); + static inline uint64_t xive_get_field64(uint64_t mask, uint64_t word) { return (be64_to_cpu(word) & mask) >> ctz64(mask); @@ -218,6 +220,10 @@ static inline uint64_t xive_end_qaddr(XiveEND *end) be32_to_cpu(end->w3); } =20 +void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon); +void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *= mon); +void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *= mon); + /* Notification Virtual Target (NVT) */ typedef struct XiveNVT { uint32_t w0; diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 4dc92ef1e372..ff1226485983 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1593,6 +1593,15 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor = *mon) } xive_end_pic_print_info(&end, i, mon); } + + monitor_printf(mon, "XIVE[%x] END Escalation %08x .. %08x\n", blk, 0, + nr_ends - 1); + for (i =3D 0; i < nr_ends; i++) { + if (xive_router_get_end(xrtr, blk, i, &end)) { + break; + } + xive_end_eas_pic_print_info(&end, i, mon); + } } =20 static void pnv_xive_reset(void *dev) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 58c2e5d890bd..48cd50192f61 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -143,7 +143,6 @@ static void spapr_xive_end_pic_print_info(SpaprXive *xi= ve, XiveEND *end, priority, qindex, qentries, qaddr_base, qgen); =20 xive_end_queue_pic_print_info(end, 6, mon); - monitor_printf(mon, "]"); } =20 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 3970999f4837..f7ba1c3b622f 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1136,6 +1136,7 @@ void xive_end_queue_pic_print_info(XiveEND *end, uint= 32_t width, Monitor *mon) be32_to_cpu(qdata)); qindex =3D (qindex + 1) & (qentries - 1); } + monitor_printf(mon, "]"); } =20 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) @@ -1146,24 +1147,36 @@ void xive_end_pic_print_info(XiveEND *end, uint32_t= end_idx, Monitor *mon) uint32_t qsize =3D xive_get_field32(END_W0_QSIZE, end->w0); uint32_t qentries =3D 1 << (qsize + 10); =20 - uint32_t nvt =3D xive_get_field32(END_W6_NVT_INDEX, end->w6); + uint32_t nvt_blk =3D xive_get_field32(END_W6_NVT_BLOCK, end->w6); + uint32_t nvt_idx =3D xive_get_field32(END_W6_NVT_INDEX, end->w6); uint8_t priority =3D xive_get_field32(END_W7_F0_PRIORITY, end->w7); + uint8_t pq; =20 if (!xive_end_is_valid(end)) { return; } =20 - monitor_printf(mon, " %08x %c%c%c%c%c prio:%d nvt:%04x eq:@%08"PRIx64 - "% 6d/%5d ^%d", end_idx, + pq =3D xive_get_field32(END_W1_ESn, end->w1); + + monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", + end_idx, + pq & XIVE_ESB_VAL_P ? 'P' : '-', + pq & XIVE_ESB_VAL_Q ? 'Q' : '-', xive_end_is_valid(end) ? 'v' : '-', xive_end_is_enqueue(end) ? 'q' : '-', xive_end_is_notify(end) ? 'n' : '-', xive_end_is_backlog(end) ? 'b' : '-', xive_end_is_escalate(end) ? 'e' : '-', - priority, nvt, qaddr_base, qindex, qentries, qgen); + xive_end_is_uncond_escalation(end) ? 'u' : '-', + xive_end_is_silent_escalation(end) ? 's' : '-', + priority, nvt_blk, nvt_idx); =20 - xive_end_queue_pic_print_info(end, 6, mon); - monitor_printf(mon, "]\n"); + if (qaddr_base) { + monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", + qaddr_base, qindex, qentries, qgen); + xive_end_queue_pic_print_info(end, 6, mon); + } + monitor_printf(mon, "\n"); } =20 static void xive_end_enqueue(XiveEND *end, uint32_t data) @@ -1191,6 +1204,29 @@ static void xive_end_enqueue(XiveEND *end, uint32_t = data) end->w1 =3D xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); } =20 +void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, + Monitor *mon) +{ + XiveEAS *eas =3D (XiveEAS *) &end->w4; + uint8_t pq; + + if (!xive_end_is_escalate(end)) { + return; + } + + pq =3D xive_get_field32(END_W1_ESe, end->w1); + + monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", + end_idx, + pq & XIVE_ESB_VAL_P ? 'P' : '-', + pq & XIVE_ESB_VAL_Q ? 'Q' : '-', + xive_eas_is_valid(eas) ? 'V' : ' ', + xive_eas_is_masked(eas) ? 'M' : ' ', + (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), + (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), + (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); +} + /* * XIVE Router (aka. Virtualization Controller or IVRE) */ --=20 2.21.0 From nobody Sat May 11 21:52:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561928032; cv=none; d=zoho.com; s=zohoarc; b=N07S17l3gw00icZ+BT0i23rMIx13IrGLOj7vh/mPm2Ir8wNy/1lcY+d2Aa+v9cMhn4MjzG8nSxMaVscBI0UoW/fJ4ivcUGFo6SIbGzC8bm6qU1UMPA8JCcHo8PD1UOv0j4lf36ncmGe8r0VF5oOmK/MRvyl4Xn8nulyy4LZ093Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561928032; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=tzUgGWf43Trb45ni4C8eMbxyg42UoGzATdCAtUud3xw=; b=A18/PufYMG3RsYTftJaDZJJV8D2djHPAPEBZb15E7LnhG8su5n+jUOAD8SnXdBzG0SdY41esx8zzhNrUCNxfsJyG/qAfwqOdxD5oXK7Bv/wiLTH+IXVy/TqzXM0QD+9x0Zbz97aS83U2LyenjQTK7YbLl+X3GZCC7o9lTYWMQm8= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15619280327261016.389097654891; Sun, 30 Jun 2019 13:53:52 -0700 (PDT) Received: from localhost ([::1]:46508 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hhgpb-0008Or-Me for importer@patchew.org; Sun, 30 Jun 2019 16:53:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36220) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hhgjT-0000GP-IE for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hhgjR-0002ho-65 for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:31 -0400 Received: from 7.mo7.mail-out.ovh.net ([46.105.43.131]:37844) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hhgjM-0002T3-58 for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:26 -0400 Received: from player157.ha.ovh.net (unknown [10.108.42.5]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 1604A121DEF for ; Sun, 30 Jun 2019 22:47:08 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player157.ha.ovh.net (Postfix) with ESMTPSA id A5FFC7575AD9; Sun, 30 Jun 2019 20:47:01 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Sun, 30 Jun 2019 22:45:59 +0200 Message-Id: <20190630204601.30574-9-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190630204601.30574-1-clg@kaod.org> References: <20190630204601.30574-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2290924837335370726 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrvdeggdduheegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.43.131 Subject: [Qemu-devel] [PATCH 08/10] ppc/xive: Extend XiveTCTX with an router object pointer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , Suraj Jitindar Singh , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This is to perform lookups in the NVT table when a vCPU is dispatched and possibly resend interrupts. Future XIVE chip will use a different class for the model of the interrupt controller. So use an 'Object *' instead of a 'XiveRouter *'. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 4 +++- hw/intc/xive.c | 11 ++++++++++- hw/ppc/pnv.c | 2 +- hw/ppc/spapr_irq.c | 2 +- 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index d922524982d3..b764e1e4e6d4 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -321,6 +321,8 @@ typedef struct XiveTCTX { qemu_irq os_output; =20 uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE]; + + Object *xrtr; } XiveTCTX; =20 /* @@ -416,7 +418,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, = uint64_t value, uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size); =20 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); -Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); +Object *xive_tctx_create(Object *cpu, Object *xrtr, Error **errp); =20 static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index f7ba1c3b622f..56700681884f 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -573,6 +573,14 @@ static void xive_tctx_realize(DeviceState *dev, Error = **errp) Object *obj; Error *local_err =3D NULL; =20 + obj =3D object_property_get_link(OBJECT(dev), "xrtr", &local_err); + if (!obj) { + error_propagate(errp, local_err); + error_prepend(errp, "required link 'xrtr' not found: "); + return; + } + tctx->xrtr =3D obj; + obj =3D object_property_get_link(OBJECT(dev), "cpu", &local_err); if (!obj) { error_propagate(errp, local_err); @@ -657,7 +665,7 @@ static const TypeInfo xive_tctx_info =3D { .class_init =3D xive_tctx_class_init, }; =20 -Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) +Object *xive_tctx_create(Object *cpu, Object *xrtr, Error **errp) { Error *local_err =3D NULL; Object *obj; @@ -666,6 +674,7 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr,= Error **errp) object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); object_unref(obj); object_property_add_const_link(obj, "cpu", cpu, &error_abort); + object_property_add_const_link(obj, "xrtr", xrtr, &error_abort); object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { goto error; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index b87e01e5b925..11916dc273c2 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -765,7 +765,7 @@ static void pnv_chip_power9_intc_create(PnvChip *chip, = PowerPCCPU *cpu, * controller object is initialized afterwards. Hopefully, it's * only used at runtime. */ - obj =3D xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &loca= l_err); + obj =3D xive_tctx_create(OBJECT(cpu), OBJECT(&chip9->xive), &local_err= ); if (local_err) { error_propagate(errp, local_err); return; diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index b2b01e850de8..5b3c3c50967b 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -353,7 +353,7 @@ static void spapr_irq_cpu_intc_create_xive(SpaprMachine= State *spapr, Object *obj; SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); =20 - obj =3D xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local= _err); + obj =3D xive_tctx_create(OBJECT(cpu), OBJECT(spapr->xive), &local_err); if (local_err) { error_propagate(errp, local_err); return; --=20 2.21.0 From nobody Sat May 11 21:52:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561927848; cv=none; d=zoho.com; s=zohoarc; b=N/JFI/RoQFwmnxE+5J9j3RhAIHjpghsEhGw+piX5tJhIL5RZRcExbK4AgLJBOAKr/nFAiZ//gghSQNH8UIWYlCF/gPhfXeMoEpbwKrCCfhlUMBEQ0hTYCJ5FThjBZBoYG7ewe0DMEy4ks4b/aFyXj8IFb8VBddL7sVt4z4GaDEg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561927848; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=p56lq+Ws56HTQva9Hwee8WuXB5g/o9DhLvNiQsu6VPA=; b=SJGJWrKTRJIGt1EMGmGoo1BahfS2/PmfmZjXOHd6S2QP0sBACKkFLsKxay3it9RY+aPObNJz8pBgMoAhGGkmVIJDroXekpGzBi5NiJLXid4tlf4V93eGswkEEWLx05wnXI4mNkYgxyn67iUekaJSgjU03vSPLm5nIEBTOMuNIjM= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561927848011497.0509744206099; Sun, 30 Jun 2019 13:50:48 -0700 (PDT) Received: from localhost ([::1]:46478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hhgmb-0004Ih-2x for importer@patchew.org; Sun, 30 Jun 2019 16:50:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36247) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hhgjV-0000H4-Dz for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hhgjT-0002kj-GW for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:33 -0400 Received: from 10.mo68.mail-out.ovh.net ([46.105.79.203]:56358) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hhgjR-0002dZ-Is for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:30 -0400 Received: from player157.ha.ovh.net (unknown [10.109.159.20]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id C004C13095F for ; Sun, 30 Jun 2019 22:47:14 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player157.ha.ovh.net (Postfix) with ESMTPSA id 0E2BE7575B0C; Sun, 30 Jun 2019 20:47:08 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Sun, 30 Jun 2019 22:46:00 +0200 Message-Id: <20190630204601.30574-10-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190630204601.30574-1-clg@kaod.org> References: <20190630204601.30574-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2292895164358233062 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrvdeggdduheegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.79.203 Subject: [Qemu-devel] [PATCH 09/10] ppc/xive: Synthesize interrupt from the saved IPB in the NVT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , Suraj Jitindar Singh , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" When an interrupt can not be presented to a vCPU, the XIVE presenter updates the Interrupt Pending Buffer of the XIVE NVT if backlog is activated in the END. Later, when the same vCPU is dispatched, its context is pushed in the thread context registers and the VO bit is set in the CAM line word. The HW grabs the associated NVT to pull the pending bits, and merge them with the IPB of the TIMA. If interrupts were missed while the vCPU was not dispatched, these are synthesized in this sequence. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive.h | 14 ++++++++ include/hw/ppc/xive_regs.h | 1 + hw/intc/xive.c | 67 ++++++++++++++++++++++++++++++++++++-- 3 files changed, 80 insertions(+), 2 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index b764e1e4e6d4..e4dcaa7a10e9 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -420,11 +420,25 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr off= set, unsigned size); void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); Object *xive_tctx_create(Object *cpu, Object *xrtr, Error **errp); =20 +/* + * The VP number space in a block is defined by the END_W6_NVT_INDEX + * field of the XIVE END + */ static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) { return (nvt_blk << 19) | nvt_idx; } =20 +static inline uint32_t xive_nvt_idx(uint32_t cam_line) +{ + return cam_line & 0x7ffff; +} + +static inline uint32_t xive_nvt_blk(uint32_t cam_line) +{ + return (cam_line >> 19) & 0xf; +} + /* * KVM XIVE device helpers */ diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 3fdf1a83b9b6..7ba0fb055174 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -232,6 +232,7 @@ typedef struct XiveNVT { uint32_t w2; uint32_t w3; uint32_t w4; +#define NVT_W4_IPB PPC_BITMASK32(16, 23) uint32_t w5; uint32_t w6; uint32_t w7; diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 56700681884f..2225183e0e16 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -345,6 +345,62 @@ static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hw= addr offset, return qw1w2; } =20 +static void xive_tctx_need_resend(XiveTCTX *tctx, uint8_t nvt_blk, + uint32_t nvt_idx) +{ + XiveNVT nvt; + uint8_t ipb; + XiveRouter *xrtr =3D XIVE_ROUTER(tctx->xrtr); + + /* + * Grab the associated NVT to pull the pending bits, and merge + * them with the IPB of the thread interrupt context registers + */ + if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", + nvt_blk, nvt_idx); + return; + } + + ipb =3D xive_get_field32(NVT_W4_IPB, nvt.w4); + + if (ipb) { + uint8_t *regs =3D &tctx->regs[TM_QW1_OS]; + + /* Reset the NVT value */ + nvt.w4 =3D xive_set_field32(NVT_W4_IPB, nvt.w4, 0); + xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); + + /* Merge in current context */ + regs[TM_IPB] |=3D ipb; + regs[TM_PIPR] =3D ipb_to_pipr(regs[TM_IPB]); + + /* Possibly resend */ + xive_tctx_notify(tctx, TM_QW1_OS); + } +} + +/* + * Updating the OS CAM line can trigger a resend of interrupt + */ +static void xive_tm_push_os_cam(XiveTCTX *tctx, hwaddr offset, + uint64_t value, unsigned size) +{ + uint32_t qw1w2 =3D value; + uint8_t nvt_blk =3D xive_nvt_blk(qw1w2); + uint32_t nvt_idx =3D xive_nvt_idx(qw1w2); + bool vo =3D !!(qw1w2 & TM_QW1W2_VO); + + /* First update the registers */ + qw1w2 =3D cpu_to_be32(qw1w2); + memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); + + /* Check the interrupt pending bits */ + if (vo) { + xive_tctx_need_resend(tctx, nvt_blk, nvt_idx); + } +} + /* * Define a mapping of "special" operations depending on the TIMA page * offset and the size of the operation. @@ -364,6 +420,7 @@ static const XiveTmOp xive_tm_operations[] =3D { * effects */ { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL= }, + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_cam, N= ULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, N= ULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL= }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll= }, @@ -1471,6 +1528,7 @@ static void xive_router_end_backlog(XiveRouter *xrtr, uint8_t priority) { XiveNVT nvt; + uint8_t ipb; =20 /* NVT cache lookup */ if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { @@ -1485,8 +1543,13 @@ static void xive_router_end_backlog(XiveRouter *xrtr, return; } =20 - /* Record the IPB in the associated NVT structure */ - ipb_update((uint8_t *) &nvt.w4, priority); + /* + * Record the IPB in the associated NVT structure for later + * use. The presenter will resend the interrupt when the vCPU is + * dispatched again on a HW thread. + */ + ipb =3D xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priorit= y); + nvt.w4 =3D xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); } =20 --=20 2.21.0 From nobody Sat May 11 21:52:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561927923; cv=none; d=zoho.com; s=zohoarc; b=Ifsn824d1Cgs1ZfP8SZBsq6bnQqCTCvKyrpGZ28CJY64YGrZKdKmSOIl9eoGfP41eBjM3SOn0MDnlVv/lMYsbSJIJ/HcIBfWiUd0dqYIWwlDsaklK7jVcqs+magmPekyEiKH3aABCwMs/aXr7Mve4M7GOwNoqbqBHNi5wwpX2q4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561927923; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=r2ARuqGldJQI9ZGldvmqFdaWMs5712Sqlgf9va6vwC4=; b=IANBOdDFtdX8fKdXZCUe3BJrBpk26boQVfROoh4xTlarUqSACDtJkjZCjWU1LX/I496yWYuMMgUxq7nH2HNuo9WwQQ6DbccOBVvY209pElhQR7qrhm3Cp7C9NInfhJmtzsQVYBMD9Kl/hJTJfH3vlSW7s5Shfl6D/Qb8D+23+/o= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561927923269428.3099877264342; Sun, 30 Jun 2019 13:52:03 -0700 (PDT) Received: from localhost ([::1]:46484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hhgnp-0005cF-U9 for importer@patchew.org; Sun, 30 Jun 2019 16:52:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36176) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hhgjR-0000Fc-Js for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hhgjO-0002eR-2h for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:29 -0400 Received: from 8.mo179.mail-out.ovh.net ([46.105.75.26]:53705) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hhgjM-0002Zx-00 for qemu-devel@nongnu.org; Sun, 30 Jun 2019 16:47:24 -0400 Received: from player157.ha.ovh.net (unknown [10.109.160.143]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id 222D2137712 for ; Sun, 30 Jun 2019 22:47:21 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player157.ha.ovh.net (Postfix) with ESMTPSA id C245E7575B1C; Sun, 30 Jun 2019 20:47:14 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Sun, 30 Jun 2019 22:46:01 +0200 Message-Id: <20190630204601.30574-11-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190630204601.30574-1-clg@kaod.org> References: <20190630204601.30574-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2294865489247046630 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrvdeggdduheegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.75.26 Subject: [Qemu-devel] [PATCH 10/10] ppc/pnv: Dump the XIVE NVT table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , Suraj Jitindar Singh , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This is to track the configuration of the base END index of the vCPU and the Interrupt Pending Buffer. The NVT IPB is updated when an interrupt can not be presented to a vCPU. We try to loop on the full table skipping empty indirect pages which are not necessarily allocated. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive_regs.h | 2 ++ hw/intc/pnv_xive.c | 60 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 7ba0fb055174..50802bbdaab0 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -229,6 +229,8 @@ typedef struct XiveNVT { uint32_t w0; #define NVT_W0_VALID PPC_BIT32(0) uint32_t w1; +#define NVT_W1_EQ_BLOCK PPC_BITMASK32(0, 3) +#define NVT_W1_EQ_INDEX PPC_BITMASK32(4, 31) uint32_t w2; uint32_t w3; uint32_t w4; diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index ff1226485983..8778c11623dc 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -121,6 +121,20 @@ static uint64_t pnv_xive_vst_page_size_allowed(uint32_= t page_shift) page_shift =3D=3D 21 || page_shift =3D=3D 24; } =20 +static uint64_t pnv_xive_vst_indirect_page_shift(uint64_t vsd) +{ + uint32_t page_shift; + + vsd =3D ldq_be_dma(&address_space_memory, vsd & VSD_ADDRESS_MASK); + page_shift =3D GETFIELD(VSD_TSIZE, vsd) + 12; + + if (!pnv_xive_vst_page_size_allowed(page_shift)) { + return 0; + } + + return page_shift; +} + static uint64_t pnv_xive_vst_size(uint64_t vsd) { uint64_t vst_tsize =3D 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); @@ -466,6 +480,24 @@ static uint32_t pnv_xive_nr_ends(PnvXive *xive) / vst_infos[VST_TSEL_EQDT].size; } =20 +static uint32_t pnv_xive_nr_indirect(PnvXive *xive, uint32_t type) +{ + const XiveVstInfo *info =3D &vst_infos[type]; + uint8_t blk =3D xive->chip->chip_id; + uint32_t page_shift =3D + pnv_xive_vst_indirect_page_shift(xive->vsds[type][blk]); + + return (1ull << page_shift) / info->size; +} + +static uint32_t pnv_xive_nr_nvts(PnvXive *xive) +{ + uint8_t blk =3D xive->chip->chip_id; + + return pnv_xive_vst_size(xive->vsds[VST_TSEL_VPDT][blk]) + / vst_infos[VST_TSEL_VPDT].size; +} + /* * EDT Table * @@ -1560,6 +1592,21 @@ static const MemoryRegionOps pnv_xive_pc_ops =3D { }, }; =20 +static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx, + Monitor *mon) +{ + uint8_t eq_blk =3D xive_get_field32(NVT_W1_EQ_BLOCK, nvt->w1); + uint32_t eq_idx =3D xive_get_field32(NVT_W1_EQ_INDEX, nvt->w1); + + if (!xive_nvt_is_valid(nvt)) { + return; + } + + monitor_printf(mon, " %08x end:%02x/%04x ipb:%02x\n", nvt_idx, + eq_blk, eq_idx, + xive_get_field32(NVT_W4_IPB, nvt->w4)); +} + void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) { XiveRouter *xrtr =3D XIVE_ROUTER(xive); @@ -1567,8 +1614,11 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor = *mon) uint32_t srcno0 =3D XIVE_SRCNO(blk, 0); uint32_t nr_ipis =3D pnv_xive_nr_ipis(xive); uint32_t nr_ends =3D pnv_xive_nr_ends(xive); + uint32_t nr_nvts =3D pnv_xive_nr_nvts(xive); + uint32_t nr_indirect_nvts =3D pnv_xive_nr_indirect(xive, VST_TSEL_VPDT= ); XiveEAS eas; XiveEND end; + XiveNVT nvt; int i; =20 monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, @@ -1602,6 +1652,16 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor = *mon) } xive_end_eas_pic_print_info(&end, i, mon); } + + monitor_printf(mon, "XIVE[%x] NVTT %08x .. %08x\n", blk, 0, nr_nvts - = 1); + for (i =3D 0; i < nr_nvts; i++) { + if (xive_router_get_nvt(xrtr, blk, i, &nvt)) { + /* skip an indirect page */ + i +=3D nr_indirect_nvts - 1; + continue; + } + xive_nvt_pic_print_info(&nvt, i, mon); + } } =20 static void pnv_xive_reset(void *dev) --=20 2.21.0